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1/*
2 * MUSB OTG driver register defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_REGS_H__
36#define __MUSB_REGS_H__
37
38#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
39
40/*
41 * MUSB Register bits
42 */
43
44/* POWER */
45#define MUSB_POWER_ISOUPDATE 0x80
46#define MUSB_POWER_SOFTCONN 0x40
47#define MUSB_POWER_HSENAB 0x20
48#define MUSB_POWER_HSMODE 0x10
49#define MUSB_POWER_RESET 0x08
50#define MUSB_POWER_RESUME 0x04
51#define MUSB_POWER_SUSPENDM 0x02
52#define MUSB_POWER_ENSUSPEND 0x01
53
54/* INTRUSB */
55#define MUSB_INTR_SUSPEND 0x01
56#define MUSB_INTR_RESUME 0x02
57#define MUSB_INTR_RESET 0x04
58#define MUSB_INTR_BABBLE 0x04
59#define MUSB_INTR_SOF 0x08
60#define MUSB_INTR_CONNECT 0x10
61#define MUSB_INTR_DISCONNECT 0x20
62#define MUSB_INTR_SESSREQ 0x40
63#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
64
65/* DEVCTL */
66#define MUSB_DEVCTL_BDEVICE 0x80
67#define MUSB_DEVCTL_FSDEV 0x40
68#define MUSB_DEVCTL_LSDEV 0x20
69#define MUSB_DEVCTL_VBUS 0x18
70#define MUSB_DEVCTL_VBUS_SHIFT 3
71#define MUSB_DEVCTL_HM 0x04
72#define MUSB_DEVCTL_HR 0x02
73#define MUSB_DEVCTL_SESSION 0x01
74
75/* BABBLE_CTL */
76#define MUSB_BABBLE_FORCE_TXIDLE 0x80
77#define MUSB_BABBLE_SW_SESSION_CTRL 0x40
78#define MUSB_BABBLE_STUCK_J 0x20
79#define MUSB_BABBLE_RCV_DISABLE 0x04
80
81/* MUSB ULPI VBUSCONTROL */
82#define MUSB_ULPI_USE_EXTVBUS 0x01
83#define MUSB_ULPI_USE_EXTVBUSIND 0x02
84/* ULPI_REG_CONTROL */
85#define MUSB_ULPI_REG_REQ (1 << 0)
86#define MUSB_ULPI_REG_CMPLT (1 << 1)
87#define MUSB_ULPI_RDN_WR (1 << 2)
88
89/* TESTMODE */
90#define MUSB_TEST_FORCE_HOST 0x80
91#define MUSB_TEST_FIFO_ACCESS 0x40
92#define MUSB_TEST_FORCE_FS 0x20
93#define MUSB_TEST_FORCE_HS 0x10
94#define MUSB_TEST_PACKET 0x08
95#define MUSB_TEST_K 0x04
96#define MUSB_TEST_J 0x02
97#define MUSB_TEST_SE0_NAK 0x01
98
99/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
100#define MUSB_FIFOSZ_DPB 0x10
101/* Allocation size (8, 16, 32, ... 4096) */
102#define MUSB_FIFOSZ_SIZE 0x0f
103
104/* CSR0 */
105#define MUSB_CSR0_FLUSHFIFO 0x0100
106#define MUSB_CSR0_TXPKTRDY 0x0002
107#define MUSB_CSR0_RXPKTRDY 0x0001
108
109/* CSR0 in Peripheral mode */
110#define MUSB_CSR0_P_SVDSETUPEND 0x0080
111#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
112#define MUSB_CSR0_P_SENDSTALL 0x0020
113#define MUSB_CSR0_P_SETUPEND 0x0010
114#define MUSB_CSR0_P_DATAEND 0x0008
115#define MUSB_CSR0_P_SENTSTALL 0x0004
116
117/* CSR0 in Host mode */
118#define MUSB_CSR0_H_DIS_PING 0x0800
119#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
120#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
121#define MUSB_CSR0_H_NAKTIMEOUT 0x0080
122#define MUSB_CSR0_H_STATUSPKT 0x0040
123#define MUSB_CSR0_H_REQPKT 0x0020
124#define MUSB_CSR0_H_ERROR 0x0010
125#define MUSB_CSR0_H_SETUPPKT 0x0008
126#define MUSB_CSR0_H_RXSTALL 0x0004
127
128/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
129#define MUSB_CSR0_P_WZC_BITS \
130 (MUSB_CSR0_P_SENTSTALL)
131#define MUSB_CSR0_H_WZC_BITS \
132 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
133 | MUSB_CSR0_RXPKTRDY)
134
135/* TxType/RxType */
136#define MUSB_TYPE_SPEED 0xc0
137#define MUSB_TYPE_SPEED_SHIFT 6
138#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
139#define MUSB_TYPE_PROTO_SHIFT 4
140#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
141
142/* CONFIGDATA */
143#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
144#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
145#define MUSB_CONFIGDATA_BIGENDIAN 0x20
146#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
147#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
148#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
149#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
150#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
151
152/* TXCSR in Peripheral and Host mode */
153#define MUSB_TXCSR_AUTOSET 0x8000
154#define MUSB_TXCSR_DMAENAB 0x1000
155#define MUSB_TXCSR_FRCDATATOG 0x0800
156#define MUSB_TXCSR_DMAMODE 0x0400
157#define MUSB_TXCSR_CLRDATATOG 0x0040
158#define MUSB_TXCSR_FLUSHFIFO 0x0008
159#define MUSB_TXCSR_FIFONOTEMPTY 0x0002
160#define MUSB_TXCSR_TXPKTRDY 0x0001
161
162/* TXCSR in Peripheral mode */
163#define MUSB_TXCSR_P_ISO 0x4000
164#define MUSB_TXCSR_P_INCOMPTX 0x0080
165#define MUSB_TXCSR_P_SENTSTALL 0x0020
166#define MUSB_TXCSR_P_SENDSTALL 0x0010
167#define MUSB_TXCSR_P_UNDERRUN 0x0004
168
169/* TXCSR in Host mode */
170#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
171#define MUSB_TXCSR_H_DATATOGGLE 0x0100
172#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
173#define MUSB_TXCSR_H_RXSTALL 0x0020
174#define MUSB_TXCSR_H_ERROR 0x0004
175
176/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
177#define MUSB_TXCSR_P_WZC_BITS \
178 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
179 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
180#define MUSB_TXCSR_H_WZC_BITS \
181 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
182 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
183
184/* RXCSR in Peripheral and Host mode */
185#define MUSB_RXCSR_AUTOCLEAR 0x8000
186#define MUSB_RXCSR_DMAENAB 0x2000
187#define MUSB_RXCSR_DISNYET 0x1000
188#define MUSB_RXCSR_PID_ERR 0x1000
189#define MUSB_RXCSR_DMAMODE 0x0800
190#define MUSB_RXCSR_INCOMPRX 0x0100
191#define MUSB_RXCSR_CLRDATATOG 0x0080
192#define MUSB_RXCSR_FLUSHFIFO 0x0010
193#define MUSB_RXCSR_DATAERROR 0x0008
194#define MUSB_RXCSR_FIFOFULL 0x0002
195#define MUSB_RXCSR_RXPKTRDY 0x0001
196
197/* RXCSR in Peripheral mode */
198#define MUSB_RXCSR_P_ISO 0x4000
199#define MUSB_RXCSR_P_SENTSTALL 0x0040
200#define MUSB_RXCSR_P_SENDSTALL 0x0020
201#define MUSB_RXCSR_P_OVERRUN 0x0004
202
203/* RXCSR in Host mode */
204#define MUSB_RXCSR_H_AUTOREQ 0x4000
205#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
206#define MUSB_RXCSR_H_DATATOGGLE 0x0200
207#define MUSB_RXCSR_H_RXSTALL 0x0040
208#define MUSB_RXCSR_H_REQPKT 0x0020
209#define MUSB_RXCSR_H_ERROR 0x0004
210
211/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
212#define MUSB_RXCSR_P_WZC_BITS \
213 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
214 | MUSB_RXCSR_RXPKTRDY)
215#define MUSB_RXCSR_H_WZC_BITS \
216 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
217 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
218
219/* HUBADDR */
220#define MUSB_HUBADDR_MULTI_TT 0x80
221
222
223#ifndef CONFIG_BLACKFIN
224
225/*
226 * Common USB registers
227 */
228
229#define MUSB_FADDR 0x00 /* 8-bit */
230#define MUSB_POWER 0x01 /* 8-bit */
231
232#define MUSB_INTRTX 0x02 /* 16-bit */
233#define MUSB_INTRRX 0x04
234#define MUSB_INTRTXE 0x06
235#define MUSB_INTRRXE 0x08
236#define MUSB_INTRUSB 0x0A /* 8 bit */
237#define MUSB_INTRUSBE 0x0B /* 8 bit */
238#define MUSB_FRAME 0x0C
239#define MUSB_INDEX 0x0E /* 8 bit */
240#define MUSB_TESTMODE 0x0F /* 8 bit */
241
242/*
243 * Additional Control Registers
244 */
245
246#define MUSB_DEVCTL 0x60 /* 8 bit */
247#define MUSB_BABBLE_CTL 0x61 /* 8 bit */
248
249/* These are always controlled through the INDEX register */
250#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
251#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
252#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
253#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
254
255/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
256#define MUSB_HWVERS 0x6C /* 8 bit */
257#define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
258#define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
259#define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
260#define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
261#define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
262#define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
263#define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
264
265#define MUSB_EPINFO 0x78 /* 8 bit */
266#define MUSB_RAMINFO 0x79 /* 8 bit */
267#define MUSB_LINKINFO 0x7a /* 8 bit */
268#define MUSB_VPLEN 0x7b /* 8 bit */
269#define MUSB_HS_EOF1 0x7c /* 8 bit */
270#define MUSB_FS_EOF1 0x7d /* 8 bit */
271#define MUSB_LS_EOF1 0x7e /* 8 bit */
272
273/* Offsets to endpoint registers */
274#define MUSB_TXMAXP 0x00
275#define MUSB_TXCSR 0x02
276#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
277#define MUSB_RXMAXP 0x04
278#define MUSB_RXCSR 0x06
279#define MUSB_RXCOUNT 0x08
280#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
281#define MUSB_TXTYPE 0x0A
282#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
283#define MUSB_TXINTERVAL 0x0B
284#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
285#define MUSB_RXTYPE 0x0C
286#define MUSB_RXINTERVAL 0x0D
287#define MUSB_FIFOSIZE 0x0F
288#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
289
290#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
291
292#define MUSB_TXCSR_MODE 0x2000
293
294/* "bus control"/target registers, for host side multipoint (external hubs) */
295#define MUSB_TXFUNCADDR 0x00
296#define MUSB_TXHUBADDR 0x02
297#define MUSB_TXHUBPORT 0x03
298
299#define MUSB_RXFUNCADDR 0x04
300#define MUSB_RXHUBADDR 0x06
301#define MUSB_RXHUBPORT 0x07
302
303static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
304{
305 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
306}
307
308static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
309{
310 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
311}
312
313static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
314{
315 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
316}
317
318static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
319{
320 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
321}
322
323static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
324{
325 musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
326}
327
328static inline u8 musb_read_txfifosz(void __iomem *mbase)
329{
330 return musb_readb(mbase, MUSB_TXFIFOSZ);
331}
332
333static inline u16 musb_read_txfifoadd(void __iomem *mbase)
334{
335 return musb_readw(mbase, MUSB_TXFIFOADD);
336}
337
338static inline u8 musb_read_rxfifosz(void __iomem *mbase)
339{
340 return musb_readb(mbase, MUSB_RXFIFOSZ);
341}
342
343static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
344{
345 return musb_readw(mbase, MUSB_RXFIFOADD);
346}
347
348static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
349{
350 return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
351}
352
353static inline u8 musb_read_configdata(void __iomem *mbase)
354{
355 musb_writeb(mbase, MUSB_INDEX, 0);
356 return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
357}
358
359static inline u16 musb_read_hwvers(void __iomem *mbase)
360{
361 return musb_readw(mbase, MUSB_HWVERS);
362}
363
364static inline void musb_write_rxfunaddr(struct musb *musb, u8 epnum,
365 u8 qh_addr_reg)
366{
367 musb_writeb(musb->mregs,
368 musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR),
369 qh_addr_reg);
370}
371
372static inline void musb_write_rxhubaddr(struct musb *musb, u8 epnum,
373 u8 qh_h_addr_reg)
374{
375 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBADDR),
376 qh_h_addr_reg);
377}
378
379static inline void musb_write_rxhubport(struct musb *musb, u8 epnum,
380 u8 qh_h_port_reg)
381{
382 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBPORT),
383 qh_h_port_reg);
384}
385
386static inline void musb_write_txfunaddr(struct musb *musb, u8 epnum,
387 u8 qh_addr_reg)
388{
389 musb_writeb(musb->mregs,
390 musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR),
391 qh_addr_reg);
392}
393
394static inline void musb_write_txhubaddr(struct musb *musb, u8 epnum,
395 u8 qh_addr_reg)
396{
397 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBADDR),
398 qh_addr_reg);
399}
400
401static inline void musb_write_txhubport(struct musb *musb, u8 epnum,
402 u8 qh_h_port_reg)
403{
404 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBPORT),
405 qh_h_port_reg);
406}
407
408static inline u8 musb_read_rxfunaddr(struct musb *musb, u8 epnum)
409{
410 return musb_readb(musb->mregs,
411 musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR));
412}
413
414static inline u8 musb_read_rxhubaddr(struct musb *musb, u8 epnum)
415{
416 return musb_readb(musb->mregs,
417 musb->io.busctl_offset(epnum, MUSB_RXHUBADDR));
418}
419
420static inline u8 musb_read_rxhubport(struct musb *musb, u8 epnum)
421{
422 return musb_readb(musb->mregs,
423 musb->io.busctl_offset(epnum, MUSB_RXHUBPORT));
424}
425
426static inline u8 musb_read_txfunaddr(struct musb *musb, u8 epnum)
427{
428 return musb_readb(musb->mregs,
429 musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR));
430}
431
432static inline u8 musb_read_txhubaddr(struct musb *musb, u8 epnum)
433{
434 return musb_readb(musb->mregs,
435 musb->io.busctl_offset(epnum, MUSB_TXHUBADDR));
436}
437
438static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum)
439{
440 return musb_readb(musb->mregs,
441 musb->io.busctl_offset(epnum, MUSB_TXHUBPORT));
442}
443
444#else /* CONFIG_BLACKFIN */
445
446#define USB_BASE USB_FADDR
447#define USB_OFFSET(reg) (reg - USB_BASE)
448
449/*
450 * Common USB registers
451 */
452#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
453#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
454#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
455#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
456#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
457#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
458#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
459#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
460#define MUSB_FRAME USB_OFFSET(USB_FRAME)
461#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
462#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
463
464/*
465 * Additional Control Registers
466 */
467
468#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
469
470#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
471#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
472#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
473#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
474#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
475
476/* Offsets to endpoint registers */
477#define MUSB_TXMAXP 0x00
478#define MUSB_TXCSR 0x04
479#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
480#define MUSB_RXMAXP 0x08
481#define MUSB_RXCSR 0x0C
482#define MUSB_RXCOUNT 0x10
483#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
484#define MUSB_TXTYPE 0x14
485#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
486#define MUSB_TXINTERVAL 0x18
487#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
488#define MUSB_RXTYPE 0x1C
489#define MUSB_RXINTERVAL 0x20
490#define MUSB_TXCOUNT 0x28
491
492/* Offsets to endpoint registers in indexed model (using INDEX register) */
493#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
494 (0x40 + (_offset))
495
496/* Offsets to endpoint registers in flat models */
497#define MUSB_FLAT_OFFSET(_epnum, _offset) \
498 (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
499
500/* Not implemented - HW has separate Tx/Rx FIFO */
501#define MUSB_TXCSR_MODE 0x0000
502
503static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
504{
505}
506
507static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
508{
509}
510
511static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
512{
513}
514
515static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
516{
517}
518
519static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
520{
521}
522
523static inline u8 musb_read_txfifosz(void __iomem *mbase)
524{
525 return 0;
526}
527
528static inline u16 musb_read_txfifoadd(void __iomem *mbase)
529{
530 return 0;
531}
532
533static inline u8 musb_read_rxfifosz(void __iomem *mbase)
534{
535 return 0;
536}
537
538static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
539{
540 return 0;
541}
542
543static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
544{
545 return 0;
546}
547
548static inline u8 musb_read_configdata(void __iomem *mbase)
549{
550 return 0;
551}
552
553static inline u16 musb_read_hwvers(void __iomem *mbase)
554{
555 /*
556 * This register is invisible on Blackfin, actually the MUSB
557 * RTL version of Blackfin is 1.9, so just hardcode its value.
558 */
559 return MUSB_HWVERS_1900;
560}
561
562static inline void musb_write_rxfunaddr(void __iomem *mbase, u8 epnum,
563 u8 qh_addr_req)
564{
565}
566
567static inline void musb_write_rxhubaddr(void __iomem *mbase, u8 epnum,
568 u8 qh_h_addr_reg)
569{
570}
571
572static inline void musb_write_rxhubport(void __iomem *mbase, u8 epnum,
573 u8 qh_h_port_reg)
574{
575}
576
577static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
578 u8 qh_addr_reg)
579{
580}
581
582static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
583 u8 qh_addr_reg)
584{
585}
586
587static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
588 u8 qh_h_port_reg)
589{
590}
591
592static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
593{
594 return 0;
595}
596
597static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
598{
599 return 0;
600}
601
602static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
603{
604 return 0;
605}
606
607static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
608{
609 return 0;
610}
611
612static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
613{
614 return 0;
615}
616
617static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
618{
619 return 0;
620}
621
622#endif /* CONFIG_BLACKFIN */
623
624#endif /* __MUSB_REGS_H__ */
1/*
2 * MUSB OTG driver register defines
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_REGS_H__
36#define __MUSB_REGS_H__
37
38#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
39
40/*
41 * MUSB Register bits
42 */
43
44/* POWER */
45#define MUSB_POWER_ISOUPDATE 0x80
46#define MUSB_POWER_SOFTCONN 0x40
47#define MUSB_POWER_HSENAB 0x20
48#define MUSB_POWER_HSMODE 0x10
49#define MUSB_POWER_RESET 0x08
50#define MUSB_POWER_RESUME 0x04
51#define MUSB_POWER_SUSPENDM 0x02
52#define MUSB_POWER_ENSUSPEND 0x01
53
54/* INTRUSB */
55#define MUSB_INTR_SUSPEND 0x01
56#define MUSB_INTR_RESUME 0x02
57#define MUSB_INTR_RESET 0x04
58#define MUSB_INTR_BABBLE 0x04
59#define MUSB_INTR_SOF 0x08
60#define MUSB_INTR_CONNECT 0x10
61#define MUSB_INTR_DISCONNECT 0x20
62#define MUSB_INTR_SESSREQ 0x40
63#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
64
65/* DEVCTL */
66#define MUSB_DEVCTL_BDEVICE 0x80
67#define MUSB_DEVCTL_FSDEV 0x40
68#define MUSB_DEVCTL_LSDEV 0x20
69#define MUSB_DEVCTL_VBUS 0x18
70#define MUSB_DEVCTL_VBUS_SHIFT 3
71#define MUSB_DEVCTL_HM 0x04
72#define MUSB_DEVCTL_HR 0x02
73#define MUSB_DEVCTL_SESSION 0x01
74
75/* BABBLE_CTL */
76#define MUSB_BABBLE_FORCE_TXIDLE 0x80
77#define MUSB_BABBLE_SW_SESSION_CTRL 0x40
78#define MUSB_BABBLE_STUCK_J 0x20
79#define MUSB_BABBLE_RCV_DISABLE 0x04
80
81/* MUSB ULPI VBUSCONTROL */
82#define MUSB_ULPI_USE_EXTVBUS 0x01
83#define MUSB_ULPI_USE_EXTVBUSIND 0x02
84/* ULPI_REG_CONTROL */
85#define MUSB_ULPI_REG_REQ (1 << 0)
86#define MUSB_ULPI_REG_CMPLT (1 << 1)
87#define MUSB_ULPI_RDN_WR (1 << 2)
88
89/* TESTMODE */
90#define MUSB_TEST_FORCE_HOST 0x80
91#define MUSB_TEST_FIFO_ACCESS 0x40
92#define MUSB_TEST_FORCE_FS 0x20
93#define MUSB_TEST_FORCE_HS 0x10
94#define MUSB_TEST_PACKET 0x08
95#define MUSB_TEST_K 0x04
96#define MUSB_TEST_J 0x02
97#define MUSB_TEST_SE0_NAK 0x01
98
99/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
100#define MUSB_FIFOSZ_DPB 0x10
101/* Allocation size (8, 16, 32, ... 4096) */
102#define MUSB_FIFOSZ_SIZE 0x0f
103
104/* CSR0 */
105#define MUSB_CSR0_FLUSHFIFO 0x0100
106#define MUSB_CSR0_TXPKTRDY 0x0002
107#define MUSB_CSR0_RXPKTRDY 0x0001
108
109/* CSR0 in Peripheral mode */
110#define MUSB_CSR0_P_SVDSETUPEND 0x0080
111#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
112#define MUSB_CSR0_P_SENDSTALL 0x0020
113#define MUSB_CSR0_P_SETUPEND 0x0010
114#define MUSB_CSR0_P_DATAEND 0x0008
115#define MUSB_CSR0_P_SENTSTALL 0x0004
116
117/* CSR0 in Host mode */
118#define MUSB_CSR0_H_DIS_PING 0x0800
119#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
120#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
121#define MUSB_CSR0_H_NAKTIMEOUT 0x0080
122#define MUSB_CSR0_H_STATUSPKT 0x0040
123#define MUSB_CSR0_H_REQPKT 0x0020
124#define MUSB_CSR0_H_ERROR 0x0010
125#define MUSB_CSR0_H_SETUPPKT 0x0008
126#define MUSB_CSR0_H_RXSTALL 0x0004
127
128/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
129#define MUSB_CSR0_P_WZC_BITS \
130 (MUSB_CSR0_P_SENTSTALL)
131#define MUSB_CSR0_H_WZC_BITS \
132 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
133 | MUSB_CSR0_RXPKTRDY)
134
135/* TxType/RxType */
136#define MUSB_TYPE_SPEED 0xc0
137#define MUSB_TYPE_SPEED_SHIFT 6
138#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
139#define MUSB_TYPE_PROTO_SHIFT 4
140#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
141
142/* CONFIGDATA */
143#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
144#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
145#define MUSB_CONFIGDATA_BIGENDIAN 0x20
146#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
147#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
148#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
149#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
150#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
151
152/* TXCSR in Peripheral and Host mode */
153#define MUSB_TXCSR_AUTOSET 0x8000
154#define MUSB_TXCSR_DMAENAB 0x1000
155#define MUSB_TXCSR_FRCDATATOG 0x0800
156#define MUSB_TXCSR_DMAMODE 0x0400
157#define MUSB_TXCSR_CLRDATATOG 0x0040
158#define MUSB_TXCSR_FLUSHFIFO 0x0008
159#define MUSB_TXCSR_FIFONOTEMPTY 0x0002
160#define MUSB_TXCSR_TXPKTRDY 0x0001
161
162/* TXCSR in Peripheral mode */
163#define MUSB_TXCSR_P_ISO 0x4000
164#define MUSB_TXCSR_P_INCOMPTX 0x0080
165#define MUSB_TXCSR_P_SENTSTALL 0x0020
166#define MUSB_TXCSR_P_SENDSTALL 0x0010
167#define MUSB_TXCSR_P_UNDERRUN 0x0004
168
169/* TXCSR in Host mode */
170#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
171#define MUSB_TXCSR_H_DATATOGGLE 0x0100
172#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
173#define MUSB_TXCSR_H_RXSTALL 0x0020
174#define MUSB_TXCSR_H_ERROR 0x0004
175
176/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
177#define MUSB_TXCSR_P_WZC_BITS \
178 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
179 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
180#define MUSB_TXCSR_H_WZC_BITS \
181 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
182 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
183
184/* RXCSR in Peripheral and Host mode */
185#define MUSB_RXCSR_AUTOCLEAR 0x8000
186#define MUSB_RXCSR_DMAENAB 0x2000
187#define MUSB_RXCSR_DISNYET 0x1000
188#define MUSB_RXCSR_PID_ERR 0x1000
189#define MUSB_RXCSR_DMAMODE 0x0800
190#define MUSB_RXCSR_INCOMPRX 0x0100
191#define MUSB_RXCSR_CLRDATATOG 0x0080
192#define MUSB_RXCSR_FLUSHFIFO 0x0010
193#define MUSB_RXCSR_DATAERROR 0x0008
194#define MUSB_RXCSR_FIFOFULL 0x0002
195#define MUSB_RXCSR_RXPKTRDY 0x0001
196
197/* RXCSR in Peripheral mode */
198#define MUSB_RXCSR_P_ISO 0x4000
199#define MUSB_RXCSR_P_SENTSTALL 0x0040
200#define MUSB_RXCSR_P_SENDSTALL 0x0020
201#define MUSB_RXCSR_P_OVERRUN 0x0004
202
203/* RXCSR in Host mode */
204#define MUSB_RXCSR_H_AUTOREQ 0x4000
205#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
206#define MUSB_RXCSR_H_DATATOGGLE 0x0200
207#define MUSB_RXCSR_H_RXSTALL 0x0040
208#define MUSB_RXCSR_H_REQPKT 0x0020
209#define MUSB_RXCSR_H_ERROR 0x0004
210
211/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
212#define MUSB_RXCSR_P_WZC_BITS \
213 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
214 | MUSB_RXCSR_RXPKTRDY)
215#define MUSB_RXCSR_H_WZC_BITS \
216 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
217 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
218
219/* HUBADDR */
220#define MUSB_HUBADDR_MULTI_TT 0x80
221
222
223#ifndef CONFIG_BLACKFIN
224
225/*
226 * Common USB registers
227 */
228
229#define MUSB_FADDR 0x00 /* 8-bit */
230#define MUSB_POWER 0x01 /* 8-bit */
231
232#define MUSB_INTRTX 0x02 /* 16-bit */
233#define MUSB_INTRRX 0x04
234#define MUSB_INTRTXE 0x06
235#define MUSB_INTRRXE 0x08
236#define MUSB_INTRUSB 0x0A /* 8 bit */
237#define MUSB_INTRUSBE 0x0B /* 8 bit */
238#define MUSB_FRAME 0x0C
239#define MUSB_INDEX 0x0E /* 8 bit */
240#define MUSB_TESTMODE 0x0F /* 8 bit */
241
242/*
243 * Additional Control Registers
244 */
245
246#define MUSB_DEVCTL 0x60 /* 8 bit */
247#define MUSB_BABBLE_CTL 0x61 /* 8 bit */
248
249/* These are always controlled through the INDEX register */
250#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
251#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
252#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
253#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
254
255/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
256#define MUSB_HWVERS 0x6C /* 8 bit */
257#define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
258#define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
259#define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
260#define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
261#define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
262#define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
263#define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
264
265#define MUSB_EPINFO 0x78 /* 8 bit */
266#define MUSB_RAMINFO 0x79 /* 8 bit */
267#define MUSB_LINKINFO 0x7a /* 8 bit */
268#define MUSB_VPLEN 0x7b /* 8 bit */
269#define MUSB_HS_EOF1 0x7c /* 8 bit */
270#define MUSB_FS_EOF1 0x7d /* 8 bit */
271#define MUSB_LS_EOF1 0x7e /* 8 bit */
272
273/* Offsets to endpoint registers */
274#define MUSB_TXMAXP 0x00
275#define MUSB_TXCSR 0x02
276#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
277#define MUSB_RXMAXP 0x04
278#define MUSB_RXCSR 0x06
279#define MUSB_RXCOUNT 0x08
280#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
281#define MUSB_TXTYPE 0x0A
282#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
283#define MUSB_TXINTERVAL 0x0B
284#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
285#define MUSB_RXTYPE 0x0C
286#define MUSB_RXINTERVAL 0x0D
287#define MUSB_FIFOSIZE 0x0F
288#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
289
290#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
291
292#define MUSB_TXCSR_MODE 0x2000
293
294/* "bus control"/target registers, for host side multipoint (external hubs) */
295#define MUSB_TXFUNCADDR 0x00
296#define MUSB_TXHUBADDR 0x02
297#define MUSB_TXHUBPORT 0x03
298
299#define MUSB_RXFUNCADDR 0x04
300#define MUSB_RXHUBADDR 0x06
301#define MUSB_RXHUBPORT 0x07
302
303static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
304{
305 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
306}
307
308static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
309{
310 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
311}
312
313static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
314{
315 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
316}
317
318static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
319{
320 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
321}
322
323static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
324{
325 musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
326}
327
328static inline u8 musb_read_txfifosz(void __iomem *mbase)
329{
330 return musb_readb(mbase, MUSB_TXFIFOSZ);
331}
332
333static inline u16 musb_read_txfifoadd(void __iomem *mbase)
334{
335 return musb_readw(mbase, MUSB_TXFIFOADD);
336}
337
338static inline u8 musb_read_rxfifosz(void __iomem *mbase)
339{
340 return musb_readb(mbase, MUSB_RXFIFOSZ);
341}
342
343static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
344{
345 return musb_readw(mbase, MUSB_RXFIFOADD);
346}
347
348static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
349{
350 return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
351}
352
353static inline u8 musb_read_configdata(void __iomem *mbase)
354{
355 musb_writeb(mbase, MUSB_INDEX, 0);
356 return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
357}
358
359static inline u16 musb_read_hwvers(void __iomem *mbase)
360{
361 return musb_readw(mbase, MUSB_HWVERS);
362}
363
364static inline void musb_write_rxfunaddr(struct musb *musb, u8 epnum,
365 u8 qh_addr_reg)
366{
367 musb_writeb(musb->mregs,
368 musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR),
369 qh_addr_reg);
370}
371
372static inline void musb_write_rxhubaddr(struct musb *musb, u8 epnum,
373 u8 qh_h_addr_reg)
374{
375 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBADDR),
376 qh_h_addr_reg);
377}
378
379static inline void musb_write_rxhubport(struct musb *musb, u8 epnum,
380 u8 qh_h_port_reg)
381{
382 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_RXHUBPORT),
383 qh_h_port_reg);
384}
385
386static inline void musb_write_txfunaddr(struct musb *musb, u8 epnum,
387 u8 qh_addr_reg)
388{
389 musb_writeb(musb->mregs,
390 musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR),
391 qh_addr_reg);
392}
393
394static inline void musb_write_txhubaddr(struct musb *musb, u8 epnum,
395 u8 qh_addr_reg)
396{
397 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBADDR),
398 qh_addr_reg);
399}
400
401static inline void musb_write_txhubport(struct musb *musb, u8 epnum,
402 u8 qh_h_port_reg)
403{
404 musb_writeb(musb->mregs, musb->io.busctl_offset(epnum, MUSB_TXHUBPORT),
405 qh_h_port_reg);
406}
407
408static inline u8 musb_read_rxfunaddr(struct musb *musb, u8 epnum)
409{
410 return musb_readb(musb->mregs,
411 musb->io.busctl_offset(epnum, MUSB_RXFUNCADDR));
412}
413
414static inline u8 musb_read_rxhubaddr(struct musb *musb, u8 epnum)
415{
416 return musb_readb(musb->mregs,
417 musb->io.busctl_offset(epnum, MUSB_RXHUBADDR));
418}
419
420static inline u8 musb_read_rxhubport(struct musb *musb, u8 epnum)
421{
422 return musb_readb(musb->mregs,
423 musb->io.busctl_offset(epnum, MUSB_RXHUBPORT));
424}
425
426static inline u8 musb_read_txfunaddr(struct musb *musb, u8 epnum)
427{
428 return musb_readb(musb->mregs,
429 musb->io.busctl_offset(epnum, MUSB_TXFUNCADDR));
430}
431
432static inline u8 musb_read_txhubaddr(struct musb *musb, u8 epnum)
433{
434 return musb_readb(musb->mregs,
435 musb->io.busctl_offset(epnum, MUSB_TXHUBADDR));
436}
437
438static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum)
439{
440 return musb_readb(musb->mregs,
441 musb->io.busctl_offset(epnum, MUSB_TXHUBPORT));
442}
443
444#else /* CONFIG_BLACKFIN */
445
446#define USB_BASE USB_FADDR
447#define USB_OFFSET(reg) (reg - USB_BASE)
448
449/*
450 * Common USB registers
451 */
452#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
453#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
454#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
455#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
456#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
457#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
458#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
459#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
460#define MUSB_FRAME USB_OFFSET(USB_FRAME)
461#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
462#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
463
464/*
465 * Additional Control Registers
466 */
467
468#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
469
470#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
471#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
472#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
473#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
474#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
475
476/* Offsets to endpoint registers */
477#define MUSB_TXMAXP 0x00
478#define MUSB_TXCSR 0x04
479#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
480#define MUSB_RXMAXP 0x08
481#define MUSB_RXCSR 0x0C
482#define MUSB_RXCOUNT 0x10
483#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
484#define MUSB_TXTYPE 0x14
485#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
486#define MUSB_TXINTERVAL 0x18
487#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
488#define MUSB_RXTYPE 0x1C
489#define MUSB_RXINTERVAL 0x20
490#define MUSB_TXCOUNT 0x28
491
492/* Offsets to endpoint registers in indexed model (using INDEX register) */
493#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
494 (0x40 + (_offset))
495
496/* Offsets to endpoint registers in flat models */
497#define MUSB_FLAT_OFFSET(_epnum, _offset) \
498 (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
499
500/* Not implemented - HW has separate Tx/Rx FIFO */
501#define MUSB_TXCSR_MODE 0x0000
502
503static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
504{
505}
506
507static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
508{
509}
510
511static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
512{
513}
514
515static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
516{
517}
518
519static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
520{
521}
522
523static inline u8 musb_read_txfifosz(void __iomem *mbase)
524{
525 return 0;
526}
527
528static inline u16 musb_read_txfifoadd(void __iomem *mbase)
529{
530 return 0;
531}
532
533static inline u8 musb_read_rxfifosz(void __iomem *mbase)
534{
535 return 0;
536}
537
538static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
539{
540 return 0;
541}
542
543static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
544{
545 return 0;
546}
547
548static inline u8 musb_read_configdata(void __iomem *mbase)
549{
550 return 0;
551}
552
553static inline u16 musb_read_hwvers(void __iomem *mbase)
554{
555 /*
556 * This register is invisible on Blackfin, actually the MUSB
557 * RTL version of Blackfin is 1.9, so just hardcode its value.
558 */
559 return MUSB_HWVERS_1900;
560}
561
562static inline void musb_write_rxfunaddr(void __iomem *mbase, u8 epnum,
563 u8 qh_addr_req)
564{
565}
566
567static inline void musb_write_rxhubaddr(void __iomem *mbase, u8 epnum,
568 u8 qh_h_addr_reg)
569{
570}
571
572static inline void musb_write_rxhubport(void __iomem *mbase, u8 epnum,
573 u8 qh_h_port_reg)
574{
575}
576
577static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
578 u8 qh_addr_reg)
579{
580}
581
582static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
583 u8 qh_addr_reg)
584{
585}
586
587static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
588 u8 qh_h_port_reg)
589{
590}
591
592static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
593{
594 return 0;
595}
596
597static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
598{
599 return 0;
600}
601
602static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
603{
604 return 0;
605}
606
607static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
608{
609 return 0;
610}
611
612static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
613{
614 return 0;
615}
616
617static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
618{
619 return 0;
620}
621
622#endif /* CONFIG_BLACKFIN */
623
624#endif /* __MUSB_REGS_H__ */