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1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef SPI_PXA2XX_H
11#define SPI_PXA2XX_H
12
13#include <linux/atomic.h>
14#include <linux/dmaengine.h>
15#include <linux/errno.h>
16#include <linux/io.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/pxa2xx_ssp.h>
20#include <linux/scatterlist.h>
21#include <linux/sizes.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/pxa2xx_spi.h>
24
25struct driver_data {
26 /* Driver model hookup */
27 struct platform_device *pdev;
28
29 /* SSP Info */
30 struct ssp_device *ssp;
31
32 /* SPI framework hookup */
33 enum pxa_ssp_type ssp_type;
34 struct spi_master *master;
35
36 /* PXA hookup */
37 struct pxa2xx_spi_master *master_info;
38
39 /* SSP register addresses */
40 void __iomem *ioaddr;
41 u32 ssdr_physical;
42
43 /* SSP masks*/
44 u32 dma_cr1;
45 u32 int_cr1;
46 u32 clear_sr;
47 u32 mask_sr;
48
49 /* Message Transfer pump */
50 struct tasklet_struct pump_transfers;
51
52 /* DMA engine support */
53 struct dma_chan *rx_chan;
54 struct dma_chan *tx_chan;
55 struct sg_table rx_sgt;
56 struct sg_table tx_sgt;
57 int rx_nents;
58 int tx_nents;
59 void *dummy;
60 atomic_t dma_running;
61
62 /* Current message transfer state info */
63 struct spi_message *cur_msg;
64 struct spi_transfer *cur_transfer;
65 struct chip_data *cur_chip;
66 size_t len;
67 void *tx;
68 void *tx_end;
69 void *rx;
70 void *rx_end;
71 int dma_mapped;
72 size_t rx_map_len;
73 size_t tx_map_len;
74 u8 n_bytes;
75 int (*write)(struct driver_data *drv_data);
76 int (*read)(struct driver_data *drv_data);
77 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
78 void (*cs_control)(u32 command);
79
80 void __iomem *lpss_base;
81};
82
83struct chip_data {
84 u32 cr1;
85 u32 dds_rate;
86 u32 timeout;
87 u8 n_bytes;
88 u32 dma_burst_size;
89 u32 threshold;
90 u32 dma_threshold;
91 u16 lpss_rx_threshold;
92 u16 lpss_tx_threshold;
93 u8 enable_dma;
94 union {
95 int gpio_cs;
96 unsigned int frm;
97 };
98 int gpio_cs_inverted;
99 int (*write)(struct driver_data *drv_data);
100 int (*read)(struct driver_data *drv_data);
101 void (*cs_control)(u32 command);
102};
103
104static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
105 unsigned reg)
106{
107 return __raw_readl(drv_data->ioaddr + reg);
108}
109
110static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
111 unsigned reg, u32 val)
112{
113 __raw_writel(val, drv_data->ioaddr + reg);
114}
115
116#define START_STATE ((void *)0)
117#define RUNNING_STATE ((void *)1)
118#define DONE_STATE ((void *)2)
119#define ERROR_STATE ((void *)-1)
120
121#define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
122#define DMA_ALIGNMENT 8
123
124static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
125{
126 switch (drv_data->ssp_type) {
127 case PXA25x_SSP:
128 case CE4100_SSP:
129 case QUARK_X1000_SSP:
130 return 1;
131 default:
132 return 0;
133 }
134}
135
136static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
137{
138 if (drv_data->ssp_type == CE4100_SSP ||
139 drv_data->ssp_type == QUARK_X1000_SSP)
140 val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
141
142 pxa2xx_spi_write(drv_data, SSSR, val);
143}
144
145extern int pxa2xx_spi_flush(struct driver_data *drv_data);
146extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
147
148#define MAX_DMA_LEN SZ_64K
149#define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
150
151extern bool pxa2xx_spi_dma_is_possible(size_t len);
152extern int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data);
153extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
154extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
155extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
156extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
157extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
158extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
159 struct spi_device *spi,
160 u8 bits_per_word,
161 u32 *burst_code,
162 u32 *threshold);
163
164#endif /* SPI_PXA2XX_H */
1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef SPI_PXA2XX_H
11#define SPI_PXA2XX_H
12
13#include <linux/atomic.h>
14#include <linux/dmaengine.h>
15#include <linux/errno.h>
16#include <linux/io.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/pxa2xx_ssp.h>
20#include <linux/scatterlist.h>
21#include <linux/sizes.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/pxa2xx_spi.h>
24
25struct driver_data {
26 /* Driver model hookup */
27 struct platform_device *pdev;
28
29 /* SSP Info */
30 struct ssp_device *ssp;
31
32 /* SPI framework hookup */
33 enum pxa_ssp_type ssp_type;
34 struct spi_master *master;
35
36 /* PXA hookup */
37 struct pxa2xx_spi_master *master_info;
38
39 /* SSP register addresses */
40 void __iomem *ioaddr;
41 u32 ssdr_physical;
42
43 /* SSP masks*/
44 u32 dma_cr1;
45 u32 int_cr1;
46 u32 clear_sr;
47 u32 mask_sr;
48
49 /* Message Transfer pump */
50 struct tasklet_struct pump_transfers;
51
52 /* DMA engine support */
53 atomic_t dma_running;
54
55 /* Current message transfer state info */
56 struct spi_transfer *cur_transfer;
57 size_t len;
58 void *tx;
59 void *tx_end;
60 void *rx;
61 void *rx_end;
62 u8 n_bytes;
63 int (*write)(struct driver_data *drv_data);
64 int (*read)(struct driver_data *drv_data);
65 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
66 void (*cs_control)(u32 command);
67
68 void __iomem *lpss_base;
69
70 /* GPIOs for chip selects */
71 struct gpio_desc **cs_gpiods;
72};
73
74struct chip_data {
75 u32 cr1;
76 u32 dds_rate;
77 u32 timeout;
78 u8 n_bytes;
79 u32 dma_burst_size;
80 u32 threshold;
81 u32 dma_threshold;
82 u16 lpss_rx_threshold;
83 u16 lpss_tx_threshold;
84 u8 enable_dma;
85 union {
86 int gpio_cs;
87 unsigned int frm;
88 };
89 int gpio_cs_inverted;
90 int (*write)(struct driver_data *drv_data);
91 int (*read)(struct driver_data *drv_data);
92 void (*cs_control)(u32 command);
93};
94
95static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
96 unsigned reg)
97{
98 return __raw_readl(drv_data->ioaddr + reg);
99}
100
101static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
102 unsigned reg, u32 val)
103{
104 __raw_writel(val, drv_data->ioaddr + reg);
105}
106
107#define START_STATE ((void *)0)
108#define RUNNING_STATE ((void *)1)
109#define DONE_STATE ((void *)2)
110#define ERROR_STATE ((void *)-1)
111
112#define DMA_ALIGNMENT 8
113
114static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
115{
116 switch (drv_data->ssp_type) {
117 case PXA25x_SSP:
118 case CE4100_SSP:
119 case QUARK_X1000_SSP:
120 return 1;
121 default:
122 return 0;
123 }
124}
125
126static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
127{
128 if (drv_data->ssp_type == CE4100_SSP ||
129 drv_data->ssp_type == QUARK_X1000_SSP)
130 val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
131
132 pxa2xx_spi_write(drv_data, SSSR, val);
133}
134
135extern int pxa2xx_spi_flush(struct driver_data *drv_data);
136extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
137
138#define MAX_DMA_LEN SZ_64K
139#define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
140
141extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
142extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
143extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
144extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
145extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
146extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
147 struct spi_device *spi,
148 u8 bits_per_word,
149 u32 *burst_code,
150 u32 *threshold);
151
152#endif /* SPI_PXA2XX_H */