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1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/fsl_devices.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/module.h>
17#include <linux/mm.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/of_platform.h>
22#include <linux/platform_device.h>
23#include <linux/spi/spi.h>
24#include <linux/pm_runtime.h>
25#include <sysdev/fsl_soc.h>
26
27#include "spi-fsl-lib.h"
28
29/* eSPI Controller registers */
30struct fsl_espi_reg {
31 __be32 mode; /* 0x000 - eSPI mode register */
32 __be32 event; /* 0x004 - eSPI event register */
33 __be32 mask; /* 0x008 - eSPI mask register */
34 __be32 command; /* 0x00c - eSPI command register */
35 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
36 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
37 u8 res[8]; /* 0x018 - 0x01c reserved */
38 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
39};
40
41struct fsl_espi_transfer {
42 const void *tx_buf;
43 void *rx_buf;
44 unsigned len;
45 unsigned n_tx;
46 unsigned n_rx;
47 unsigned actual_length;
48 int status;
49};
50
51/* eSPI Controller mode register definitions */
52#define SPMODE_ENABLE (1 << 31)
53#define SPMODE_LOOP (1 << 30)
54#define SPMODE_TXTHR(x) ((x) << 8)
55#define SPMODE_RXTHR(x) ((x) << 0)
56
57/* eSPI Controller CS mode register definitions */
58#define CSMODE_CI_INACTIVEHIGH (1 << 31)
59#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
60#define CSMODE_REV (1 << 29)
61#define CSMODE_DIV16 (1 << 28)
62#define CSMODE_PM(x) ((x) << 24)
63#define CSMODE_POL_1 (1 << 20)
64#define CSMODE_LEN(x) ((x) << 16)
65#define CSMODE_BEF(x) ((x) << 12)
66#define CSMODE_AFT(x) ((x) << 8)
67#define CSMODE_CG(x) ((x) << 3)
68
69/* Default mode/csmode for eSPI controller */
70#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
71#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
72 | CSMODE_AFT(0) | CSMODE_CG(1))
73
74/* SPIE register values */
75#define SPIE_NE 0x00000200 /* Not empty */
76#define SPIE_NF 0x00000100 /* Not full */
77
78/* SPIM register values */
79#define SPIM_NE 0x00000200 /* Not empty */
80#define SPIM_NF 0x00000100 /* Not full */
81#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
82#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
83
84/* SPCOM register values */
85#define SPCOM_CS(x) ((x) << 30)
86#define SPCOM_TRANLEN(x) ((x) << 0)
87#define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
88
89#define AUTOSUSPEND_TIMEOUT 2000
90
91static void fsl_espi_change_mode(struct spi_device *spi)
92{
93 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
94 struct spi_mpc8xxx_cs *cs = spi->controller_state;
95 struct fsl_espi_reg *reg_base = mspi->reg_base;
96 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
97 __be32 __iomem *espi_mode = ®_base->mode;
98 u32 tmp;
99 unsigned long flags;
100
101 /* Turn off IRQs locally to minimize time that SPI is disabled. */
102 local_irq_save(flags);
103
104 /* Turn off SPI unit prior changing mode */
105 tmp = mpc8xxx_spi_read_reg(espi_mode);
106 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
107 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
108 mpc8xxx_spi_write_reg(espi_mode, tmp);
109
110 local_irq_restore(flags);
111}
112
113static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
114{
115 u32 data;
116 u16 data_h;
117 u16 data_l;
118 const u32 *tx = mpc8xxx_spi->tx;
119
120 if (!tx)
121 return 0;
122
123 data = *tx++ << mpc8xxx_spi->tx_shift;
124 data_l = data & 0xffff;
125 data_h = (data >> 16) & 0xffff;
126 swab16s(&data_l);
127 swab16s(&data_h);
128 data = data_h | data_l;
129
130 mpc8xxx_spi->tx = tx;
131 return data;
132}
133
134static int fsl_espi_setup_transfer(struct spi_device *spi,
135 struct spi_transfer *t)
136{
137 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
138 int bits_per_word = 0;
139 u8 pm;
140 u32 hz = 0;
141 struct spi_mpc8xxx_cs *cs = spi->controller_state;
142
143 if (t) {
144 bits_per_word = t->bits_per_word;
145 hz = t->speed_hz;
146 }
147
148 /* spi_transfer level calls that work per-word */
149 if (!bits_per_word)
150 bits_per_word = spi->bits_per_word;
151
152 if (!hz)
153 hz = spi->max_speed_hz;
154
155 cs->rx_shift = 0;
156 cs->tx_shift = 0;
157 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
158 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
159 if (bits_per_word <= 8) {
160 cs->rx_shift = 8 - bits_per_word;
161 } else {
162 cs->rx_shift = 16 - bits_per_word;
163 if (spi->mode & SPI_LSB_FIRST)
164 cs->get_tx = fsl_espi_tx_buf_lsb;
165 }
166
167 mpc8xxx_spi->rx_shift = cs->rx_shift;
168 mpc8xxx_spi->tx_shift = cs->tx_shift;
169 mpc8xxx_spi->get_rx = cs->get_rx;
170 mpc8xxx_spi->get_tx = cs->get_tx;
171
172 bits_per_word = bits_per_word - 1;
173
174 /* mask out bits we are going to set */
175 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
176
177 cs->hw_mode |= CSMODE_LEN(bits_per_word);
178
179 if ((mpc8xxx_spi->spibrg / hz) > 64) {
180 cs->hw_mode |= CSMODE_DIV16;
181 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
182
183 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
184 "Will use %d Hz instead.\n", dev_name(&spi->dev),
185 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
186 if (pm > 33)
187 pm = 33;
188 } else {
189 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
190 }
191 if (pm)
192 pm--;
193 if (pm < 2)
194 pm = 2;
195
196 cs->hw_mode |= CSMODE_PM(pm);
197
198 fsl_espi_change_mode(spi);
199 return 0;
200}
201
202static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
203 unsigned int len)
204{
205 u32 word;
206 struct fsl_espi_reg *reg_base = mspi->reg_base;
207
208 mspi->count = len;
209
210 /* enable rx ints */
211 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
212
213 /* transmit word */
214 word = mspi->get_tx(mspi);
215 mpc8xxx_spi_write_reg(®_base->transmit, word);
216
217 return 0;
218}
219
220static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
221{
222 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
223 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
224 unsigned int len = t->len;
225 int ret;
226
227 mpc8xxx_spi->len = t->len;
228 len = roundup(len, 4) / 4;
229
230 mpc8xxx_spi->tx = t->tx_buf;
231 mpc8xxx_spi->rx = t->rx_buf;
232
233 reinit_completion(&mpc8xxx_spi->done);
234
235 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
236 if (t->len > SPCOM_TRANLEN_MAX) {
237 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
238 " beyond the SPCOM[TRANLEN] field\n", t->len);
239 return -EINVAL;
240 }
241 mpc8xxx_spi_write_reg(®_base->command,
242 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
243
244 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
245 if (ret)
246 return ret;
247
248 wait_for_completion(&mpc8xxx_spi->done);
249
250 /* disable rx ints */
251 mpc8xxx_spi_write_reg(®_base->mask, 0);
252
253 return mpc8xxx_spi->count;
254}
255
256static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
257{
258 if (cmd) {
259 cmd[1] = (u8)(addr >> 16);
260 cmd[2] = (u8)(addr >> 8);
261 cmd[3] = (u8)(addr >> 0);
262 }
263}
264
265static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
266{
267 if (cmd)
268 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
269
270 return 0;
271}
272
273static void fsl_espi_do_trans(struct spi_message *m,
274 struct fsl_espi_transfer *tr)
275{
276 struct spi_device *spi = m->spi;
277 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
278 struct fsl_espi_transfer *espi_trans = tr;
279 struct spi_message message;
280 struct spi_transfer *t, *first, trans;
281 int status = 0;
282
283 spi_message_init(&message);
284 memset(&trans, 0, sizeof(trans));
285
286 first = list_first_entry(&m->transfers, struct spi_transfer,
287 transfer_list);
288 list_for_each_entry(t, &m->transfers, transfer_list) {
289 if ((first->bits_per_word != t->bits_per_word) ||
290 (first->speed_hz != t->speed_hz)) {
291 espi_trans->status = -EINVAL;
292 dev_err(mspi->dev,
293 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
294 return;
295 }
296
297 trans.speed_hz = t->speed_hz;
298 trans.bits_per_word = t->bits_per_word;
299 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
300 }
301
302 trans.len = espi_trans->len;
303 trans.tx_buf = espi_trans->tx_buf;
304 trans.rx_buf = espi_trans->rx_buf;
305 spi_message_add_tail(&trans, &message);
306
307 list_for_each_entry(t, &message.transfers, transfer_list) {
308 if (t->bits_per_word || t->speed_hz) {
309 status = -EINVAL;
310
311 status = fsl_espi_setup_transfer(spi, t);
312 if (status < 0)
313 break;
314 }
315
316 if (t->len)
317 status = fsl_espi_bufs(spi, t);
318
319 if (status) {
320 status = -EMSGSIZE;
321 break;
322 }
323
324 if (t->delay_usecs)
325 udelay(t->delay_usecs);
326 }
327
328 espi_trans->status = status;
329 fsl_espi_setup_transfer(spi, NULL);
330}
331
332static void fsl_espi_cmd_trans(struct spi_message *m,
333 struct fsl_espi_transfer *trans, u8 *rx_buff)
334{
335 struct spi_transfer *t;
336 u8 *local_buf;
337 int i = 0;
338 struct fsl_espi_transfer *espi_trans = trans;
339
340 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
341 if (!local_buf) {
342 espi_trans->status = -ENOMEM;
343 return;
344 }
345
346 list_for_each_entry(t, &m->transfers, transfer_list) {
347 if (t->tx_buf) {
348 memcpy(local_buf + i, t->tx_buf, t->len);
349 i += t->len;
350 }
351 }
352
353 espi_trans->tx_buf = local_buf;
354 espi_trans->rx_buf = local_buf;
355 fsl_espi_do_trans(m, espi_trans);
356
357 espi_trans->actual_length = espi_trans->len;
358 kfree(local_buf);
359}
360
361static void fsl_espi_rw_trans(struct spi_message *m,
362 struct fsl_espi_transfer *trans, u8 *rx_buff)
363{
364 struct fsl_espi_transfer *espi_trans = trans;
365 unsigned int total_len = espi_trans->len;
366 struct spi_transfer *t;
367 u8 *local_buf;
368 u8 *rx_buf = rx_buff;
369 unsigned int trans_len;
370 unsigned int addr;
371 unsigned int tx_only;
372 unsigned int rx_pos = 0;
373 unsigned int pos;
374 int i, loop;
375
376 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
377 if (!local_buf) {
378 espi_trans->status = -ENOMEM;
379 return;
380 }
381
382 for (pos = 0, loop = 0; pos < total_len; pos += trans_len, loop++) {
383 trans_len = total_len - pos;
384
385 i = 0;
386 tx_only = 0;
387 list_for_each_entry(t, &m->transfers, transfer_list) {
388 if (t->tx_buf) {
389 memcpy(local_buf + i, t->tx_buf, t->len);
390 i += t->len;
391 if (!t->rx_buf)
392 tx_only += t->len;
393 }
394 }
395
396 /* Add additional TX bytes to compensate SPCOM_TRANLEN_MAX */
397 if (loop > 0)
398 trans_len += tx_only;
399
400 if (trans_len > SPCOM_TRANLEN_MAX)
401 trans_len = SPCOM_TRANLEN_MAX;
402
403 /* Update device offset */
404 if (pos > 0) {
405 addr = fsl_espi_cmd2addr(local_buf);
406 addr += rx_pos;
407 fsl_espi_addr2cmd(addr, local_buf);
408 }
409
410 espi_trans->len = trans_len;
411 espi_trans->tx_buf = local_buf;
412 espi_trans->rx_buf = local_buf;
413 fsl_espi_do_trans(m, espi_trans);
414
415 /* If there is at least one RX byte then copy it to rx_buf */
416 if (tx_only < SPCOM_TRANLEN_MAX)
417 memcpy(rx_buf + rx_pos, espi_trans->rx_buf + tx_only,
418 trans_len - tx_only);
419
420 rx_pos += trans_len - tx_only;
421
422 if (loop > 0)
423 espi_trans->actual_length += espi_trans->len - tx_only;
424 else
425 espi_trans->actual_length += espi_trans->len;
426 }
427
428 kfree(local_buf);
429}
430
431static int fsl_espi_do_one_msg(struct spi_master *master,
432 struct spi_message *m)
433{
434 struct spi_transfer *t;
435 u8 *rx_buf = NULL;
436 unsigned int n_tx = 0;
437 unsigned int n_rx = 0;
438 unsigned int xfer_len = 0;
439 struct fsl_espi_transfer espi_trans;
440
441 list_for_each_entry(t, &m->transfers, transfer_list) {
442 if (t->tx_buf)
443 n_tx += t->len;
444 if (t->rx_buf) {
445 n_rx += t->len;
446 rx_buf = t->rx_buf;
447 }
448 if ((t->tx_buf) || (t->rx_buf))
449 xfer_len += t->len;
450 }
451
452 espi_trans.n_tx = n_tx;
453 espi_trans.n_rx = n_rx;
454 espi_trans.len = xfer_len;
455 espi_trans.actual_length = 0;
456 espi_trans.status = 0;
457
458 if (!rx_buf)
459 fsl_espi_cmd_trans(m, &espi_trans, NULL);
460 else
461 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
462
463 m->actual_length = espi_trans.actual_length;
464 m->status = espi_trans.status;
465 spi_finalize_current_message(master);
466 return 0;
467}
468
469static int fsl_espi_setup(struct spi_device *spi)
470{
471 struct mpc8xxx_spi *mpc8xxx_spi;
472 struct fsl_espi_reg *reg_base;
473 int retval;
474 u32 hw_mode;
475 u32 loop_mode;
476 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
477
478 if (!spi->max_speed_hz)
479 return -EINVAL;
480
481 if (!cs) {
482 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
483 if (!cs)
484 return -ENOMEM;
485 spi_set_ctldata(spi, cs);
486 }
487
488 mpc8xxx_spi = spi_master_get_devdata(spi->master);
489 reg_base = mpc8xxx_spi->reg_base;
490
491 pm_runtime_get_sync(mpc8xxx_spi->dev);
492
493 hw_mode = cs->hw_mode; /* Save original settings */
494 cs->hw_mode = mpc8xxx_spi_read_reg(
495 ®_base->csmode[spi->chip_select]);
496 /* mask out bits we are going to set */
497 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
498 | CSMODE_REV);
499
500 if (spi->mode & SPI_CPHA)
501 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
502 if (spi->mode & SPI_CPOL)
503 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
504 if (!(spi->mode & SPI_LSB_FIRST))
505 cs->hw_mode |= CSMODE_REV;
506
507 /* Handle the loop mode */
508 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
509 loop_mode &= ~SPMODE_LOOP;
510 if (spi->mode & SPI_LOOP)
511 loop_mode |= SPMODE_LOOP;
512 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
513
514 retval = fsl_espi_setup_transfer(spi, NULL);
515
516 pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
517 pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
518
519 if (retval < 0) {
520 cs->hw_mode = hw_mode; /* Restore settings */
521 return retval;
522 }
523 return 0;
524}
525
526static void fsl_espi_cleanup(struct spi_device *spi)
527{
528 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
529
530 kfree(cs);
531 spi_set_ctldata(spi, NULL);
532}
533
534void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
535{
536 struct fsl_espi_reg *reg_base = mspi->reg_base;
537
538 /* We need handle RX first */
539 if (events & SPIE_NE) {
540 u32 rx_data, tmp;
541 u8 rx_data_8;
542
543 /* Spin until RX is done */
544 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
545 cpu_relax();
546 events = mpc8xxx_spi_read_reg(®_base->event);
547 }
548
549 if (mspi->len >= 4) {
550 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
551 } else {
552 tmp = mspi->len;
553 rx_data = 0;
554 while (tmp--) {
555 rx_data_8 = in_8((u8 *)®_base->receive);
556 rx_data |= (rx_data_8 << (tmp * 8));
557 }
558
559 rx_data <<= (4 - mspi->len) * 8;
560 }
561
562 mspi->len -= 4;
563
564 if (mspi->rx)
565 mspi->get_rx(rx_data, mspi);
566 }
567
568 if (!(events & SPIE_NF)) {
569 int ret;
570
571 /* spin until TX is done */
572 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
573 ®_base->event)) & SPIE_NF), 1000, 0);
574 if (!ret) {
575 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
576
577 /* Clear the SPIE bits */
578 mpc8xxx_spi_write_reg(®_base->event, events);
579 complete(&mspi->done);
580 return;
581 }
582 }
583
584 /* Clear the events */
585 mpc8xxx_spi_write_reg(®_base->event, events);
586
587 mspi->count -= 1;
588 if (mspi->count) {
589 u32 word = mspi->get_tx(mspi);
590
591 mpc8xxx_spi_write_reg(®_base->transmit, word);
592 } else {
593 complete(&mspi->done);
594 }
595}
596
597static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
598{
599 struct mpc8xxx_spi *mspi = context_data;
600 struct fsl_espi_reg *reg_base = mspi->reg_base;
601 irqreturn_t ret = IRQ_NONE;
602 u32 events;
603
604 /* Get interrupt events(tx/rx) */
605 events = mpc8xxx_spi_read_reg(®_base->event);
606 if (events)
607 ret = IRQ_HANDLED;
608
609 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
610
611 fsl_espi_cpu_irq(mspi, events);
612
613 return ret;
614}
615
616#ifdef CONFIG_PM
617static int fsl_espi_runtime_suspend(struct device *dev)
618{
619 struct spi_master *master = dev_get_drvdata(dev);
620 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
621 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
622 u32 regval;
623
624 regval = mpc8xxx_spi_read_reg(®_base->mode);
625 regval &= ~SPMODE_ENABLE;
626 mpc8xxx_spi_write_reg(®_base->mode, regval);
627
628 return 0;
629}
630
631static int fsl_espi_runtime_resume(struct device *dev)
632{
633 struct spi_master *master = dev_get_drvdata(dev);
634 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
635 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
636 u32 regval;
637
638 regval = mpc8xxx_spi_read_reg(®_base->mode);
639 regval |= SPMODE_ENABLE;
640 mpc8xxx_spi_write_reg(®_base->mode, regval);
641
642 return 0;
643}
644#endif
645
646static size_t fsl_espi_max_transfer_size(struct spi_device *spi)
647{
648 return SPCOM_TRANLEN_MAX;
649}
650
651static struct spi_master * fsl_espi_probe(struct device *dev,
652 struct resource *mem, unsigned int irq)
653{
654 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
655 struct spi_master *master;
656 struct mpc8xxx_spi *mpc8xxx_spi;
657 struct fsl_espi_reg *reg_base;
658 struct device_node *nc;
659 const __be32 *prop;
660 u32 regval, csmode;
661 int i, len, ret = 0;
662
663 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
664 if (!master) {
665 ret = -ENOMEM;
666 goto err;
667 }
668
669 dev_set_drvdata(dev, master);
670
671 mpc8xxx_spi_probe(dev, mem, irq);
672
673 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
674 master->setup = fsl_espi_setup;
675 master->cleanup = fsl_espi_cleanup;
676 master->transfer_one_message = fsl_espi_do_one_msg;
677 master->auto_runtime_pm = true;
678 master->max_transfer_size = fsl_espi_max_transfer_size;
679
680 mpc8xxx_spi = spi_master_get_devdata(master);
681
682 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
683 if (IS_ERR(mpc8xxx_spi->reg_base)) {
684 ret = PTR_ERR(mpc8xxx_spi->reg_base);
685 goto err_probe;
686 }
687
688 reg_base = mpc8xxx_spi->reg_base;
689
690 /* Register for SPI Interrupt */
691 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
692 0, "fsl_espi", mpc8xxx_spi);
693 if (ret)
694 goto err_probe;
695
696 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
697 mpc8xxx_spi->rx_shift = 16;
698 mpc8xxx_spi->tx_shift = 24;
699 }
700
701 /* SPI controller initializations */
702 mpc8xxx_spi_write_reg(®_base->mode, 0);
703 mpc8xxx_spi_write_reg(®_base->mask, 0);
704 mpc8xxx_spi_write_reg(®_base->command, 0);
705 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
706
707 /* Init eSPI CS mode register */
708 for_each_available_child_of_node(master->dev.of_node, nc) {
709 /* get chip select */
710 prop = of_get_property(nc, "reg", &len);
711 if (!prop || len < sizeof(*prop))
712 continue;
713 i = be32_to_cpup(prop);
714 if (i < 0 || i >= pdata->max_chipselect)
715 continue;
716
717 csmode = CSMODE_INIT_VAL;
718 /* check if CSBEF is set in device tree */
719 prop = of_get_property(nc, "fsl,csbef", &len);
720 if (prop && len >= sizeof(*prop)) {
721 csmode &= ~(CSMODE_BEF(0xf));
722 csmode |= CSMODE_BEF(be32_to_cpup(prop));
723 }
724 /* check if CSAFT is set in device tree */
725 prop = of_get_property(nc, "fsl,csaft", &len);
726 if (prop && len >= sizeof(*prop)) {
727 csmode &= ~(CSMODE_AFT(0xf));
728 csmode |= CSMODE_AFT(be32_to_cpup(prop));
729 }
730 mpc8xxx_spi_write_reg(®_base->csmode[i], csmode);
731
732 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
733 }
734
735 /* Enable SPI interface */
736 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
737
738 mpc8xxx_spi_write_reg(®_base->mode, regval);
739
740 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
741 pm_runtime_use_autosuspend(dev);
742 pm_runtime_set_active(dev);
743 pm_runtime_enable(dev);
744 pm_runtime_get_sync(dev);
745
746 ret = devm_spi_register_master(dev, master);
747 if (ret < 0)
748 goto err_pm;
749
750 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
751
752 pm_runtime_mark_last_busy(dev);
753 pm_runtime_put_autosuspend(dev);
754
755 return master;
756
757err_pm:
758 pm_runtime_put_noidle(dev);
759 pm_runtime_disable(dev);
760 pm_runtime_set_suspended(dev);
761err_probe:
762 spi_master_put(master);
763err:
764 return ERR_PTR(ret);
765}
766
767static int of_fsl_espi_get_chipselects(struct device *dev)
768{
769 struct device_node *np = dev->of_node;
770 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
771 const u32 *prop;
772 int len;
773
774 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
775 if (!prop || len < sizeof(*prop)) {
776 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
777 return -EINVAL;
778 }
779
780 pdata->max_chipselect = *prop;
781 pdata->cs_control = NULL;
782
783 return 0;
784}
785
786static int of_fsl_espi_probe(struct platform_device *ofdev)
787{
788 struct device *dev = &ofdev->dev;
789 struct device_node *np = ofdev->dev.of_node;
790 struct spi_master *master;
791 struct resource mem;
792 unsigned int irq;
793 int ret = -ENOMEM;
794
795 ret = of_mpc8xxx_spi_probe(ofdev);
796 if (ret)
797 return ret;
798
799 ret = of_fsl_espi_get_chipselects(dev);
800 if (ret)
801 goto err;
802
803 ret = of_address_to_resource(np, 0, &mem);
804 if (ret)
805 goto err;
806
807 irq = irq_of_parse_and_map(np, 0);
808 if (!irq) {
809 ret = -EINVAL;
810 goto err;
811 }
812
813 master = fsl_espi_probe(dev, &mem, irq);
814 if (IS_ERR(master)) {
815 ret = PTR_ERR(master);
816 goto err;
817 }
818
819 return 0;
820
821err:
822 return ret;
823}
824
825static int of_fsl_espi_remove(struct platform_device *dev)
826{
827 pm_runtime_disable(&dev->dev);
828
829 return 0;
830}
831
832#ifdef CONFIG_PM_SLEEP
833static int of_fsl_espi_suspend(struct device *dev)
834{
835 struct spi_master *master = dev_get_drvdata(dev);
836 int ret;
837
838 ret = spi_master_suspend(master);
839 if (ret) {
840 dev_warn(dev, "cannot suspend master\n");
841 return ret;
842 }
843
844 ret = pm_runtime_force_suspend(dev);
845 if (ret < 0)
846 return ret;
847
848 return 0;
849}
850
851static int of_fsl_espi_resume(struct device *dev)
852{
853 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
854 struct spi_master *master = dev_get_drvdata(dev);
855 struct mpc8xxx_spi *mpc8xxx_spi;
856 struct fsl_espi_reg *reg_base;
857 u32 regval;
858 int i, ret;
859
860 mpc8xxx_spi = spi_master_get_devdata(master);
861 reg_base = mpc8xxx_spi->reg_base;
862
863 /* SPI controller initializations */
864 mpc8xxx_spi_write_reg(®_base->mode, 0);
865 mpc8xxx_spi_write_reg(®_base->mask, 0);
866 mpc8xxx_spi_write_reg(®_base->command, 0);
867 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
868
869 /* Init eSPI CS mode register */
870 for (i = 0; i < pdata->max_chipselect; i++)
871 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
872
873 /* Enable SPI interface */
874 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
875
876 mpc8xxx_spi_write_reg(®_base->mode, regval);
877
878 ret = pm_runtime_force_resume(dev);
879 if (ret < 0)
880 return ret;
881
882 return spi_master_resume(master);
883}
884#endif /* CONFIG_PM_SLEEP */
885
886static const struct dev_pm_ops espi_pm = {
887 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
888 fsl_espi_runtime_resume, NULL)
889 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
890};
891
892static const struct of_device_id of_fsl_espi_match[] = {
893 { .compatible = "fsl,mpc8536-espi" },
894 {}
895};
896MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
897
898static struct platform_driver fsl_espi_driver = {
899 .driver = {
900 .name = "fsl_espi",
901 .of_match_table = of_fsl_espi_match,
902 .pm = &espi_pm,
903 },
904 .probe = of_fsl_espi_probe,
905 .remove = of_fsl_espi_remove,
906};
907module_platform_driver(fsl_espi_driver);
908
909MODULE_AUTHOR("Mingkai Hu");
910MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
911MODULE_LICENSE("GPL");
1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/fsl_devices.h>
14#include <linux/interrupt.h>
15#include <linux/module.h>
16#include <linux/mm.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
23#include <linux/pm_runtime.h>
24#include <sysdev/fsl_soc.h>
25
26/* eSPI Controller registers */
27#define ESPI_SPMODE 0x00 /* eSPI mode register */
28#define ESPI_SPIE 0x04 /* eSPI event register */
29#define ESPI_SPIM 0x08 /* eSPI mask register */
30#define ESPI_SPCOM 0x0c /* eSPI command register */
31#define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
32#define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
33#define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
34
35#define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
36
37/* eSPI Controller mode register definitions */
38#define SPMODE_ENABLE BIT(31)
39#define SPMODE_LOOP BIT(30)
40#define SPMODE_TXTHR(x) ((x) << 8)
41#define SPMODE_RXTHR(x) ((x) << 0)
42
43/* eSPI Controller CS mode register definitions */
44#define CSMODE_CI_INACTIVEHIGH BIT(31)
45#define CSMODE_CP_BEGIN_EDGECLK BIT(30)
46#define CSMODE_REV BIT(29)
47#define CSMODE_DIV16 BIT(28)
48#define CSMODE_PM(x) ((x) << 24)
49#define CSMODE_POL_1 BIT(20)
50#define CSMODE_LEN(x) ((x) << 16)
51#define CSMODE_BEF(x) ((x) << 12)
52#define CSMODE_AFT(x) ((x) << 8)
53#define CSMODE_CG(x) ((x) << 3)
54
55#define FSL_ESPI_FIFO_SIZE 32
56#define FSL_ESPI_RXTHR 15
57
58/* Default mode/csmode for eSPI controller */
59#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR))
60#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
61 | CSMODE_AFT(0) | CSMODE_CG(1))
62
63/* SPIE register values */
64#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
65#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
66#define SPIE_TXE BIT(15) /* TX FIFO empty */
67#define SPIE_DON BIT(14) /* TX done */
68#define SPIE_RXT BIT(13) /* RX FIFO threshold */
69#define SPIE_RXF BIT(12) /* RX FIFO full */
70#define SPIE_TXT BIT(11) /* TX FIFO threshold*/
71#define SPIE_RNE BIT(9) /* RX FIFO not empty */
72#define SPIE_TNF BIT(8) /* TX FIFO not full */
73
74/* SPIM register values */
75#define SPIM_TXE BIT(15) /* TX FIFO empty */
76#define SPIM_DON BIT(14) /* TX done */
77#define SPIM_RXT BIT(13) /* RX FIFO threshold */
78#define SPIM_RXF BIT(12) /* RX FIFO full */
79#define SPIM_TXT BIT(11) /* TX FIFO threshold*/
80#define SPIM_RNE BIT(9) /* RX FIFO not empty */
81#define SPIM_TNF BIT(8) /* TX FIFO not full */
82
83/* SPCOM register values */
84#define SPCOM_CS(x) ((x) << 30)
85#define SPCOM_DO BIT(28) /* Dual output */
86#define SPCOM_TO BIT(27) /* TX only */
87#define SPCOM_RXSKIP(x) ((x) << 16)
88#define SPCOM_TRANLEN(x) ((x) << 0)
89
90#define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
91
92#define AUTOSUSPEND_TIMEOUT 2000
93
94struct fsl_espi {
95 struct device *dev;
96 void __iomem *reg_base;
97
98 struct list_head *m_transfers;
99 struct spi_transfer *tx_t;
100 unsigned int tx_pos;
101 bool tx_done;
102 struct spi_transfer *rx_t;
103 unsigned int rx_pos;
104 bool rx_done;
105
106 bool swab;
107 unsigned int rxskip;
108
109 spinlock_t lock;
110
111 u32 spibrg; /* SPIBRG input clock */
112
113 struct completion done;
114};
115
116struct fsl_espi_cs {
117 u32 hw_mode;
118};
119
120static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset)
121{
122 return ioread32be(espi->reg_base + offset);
123}
124
125static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset)
126{
127 return ioread16be(espi->reg_base + offset);
128}
129
130static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset)
131{
132 return ioread8(espi->reg_base + offset);
133}
134
135static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset,
136 u32 val)
137{
138 iowrite32be(val, espi->reg_base + offset);
139}
140
141static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset,
142 u16 val)
143{
144 iowrite16be(val, espi->reg_base + offset);
145}
146
147static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset,
148 u8 val)
149{
150 iowrite8(val, espi->reg_base + offset);
151}
152
153static int fsl_espi_check_message(struct spi_message *m)
154{
155 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
156 struct spi_transfer *t, *first;
157
158 if (m->frame_length > SPCOM_TRANLEN_MAX) {
159 dev_err(espi->dev, "message too long, size is %u bytes\n",
160 m->frame_length);
161 return -EMSGSIZE;
162 }
163
164 first = list_first_entry(&m->transfers, struct spi_transfer,
165 transfer_list);
166
167 list_for_each_entry(t, &m->transfers, transfer_list) {
168 if (first->bits_per_word != t->bits_per_word ||
169 first->speed_hz != t->speed_hz) {
170 dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
171 return -EINVAL;
172 }
173 }
174
175 /* ESPI supports MSB-first transfers for word size 8 / 16 only */
176 if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 &&
177 first->bits_per_word != 16) {
178 dev_err(espi->dev,
179 "MSB-first transfer not supported for wordsize %u\n",
180 first->bits_per_word);
181 return -EINVAL;
182 }
183
184 return 0;
185}
186
187static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m)
188{
189 struct spi_transfer *t;
190 unsigned int i = 0, rxskip = 0;
191
192 /*
193 * prerequisites for ESPI rxskip mode:
194 * - message has two transfers
195 * - first transfer is a write and second is a read
196 *
197 * In addition the current low-level transfer mechanism requires
198 * that the rxskip bytes fit into the TX FIFO. Else the transfer
199 * would hang because after the first FSL_ESPI_FIFO_SIZE bytes
200 * the TX FIFO isn't re-filled.
201 */
202 list_for_each_entry(t, &m->transfers, transfer_list) {
203 if (i == 0) {
204 if (!t->tx_buf || t->rx_buf ||
205 t->len > FSL_ESPI_FIFO_SIZE)
206 return 0;
207 rxskip = t->len;
208 } else if (i == 1) {
209 if (t->tx_buf || !t->rx_buf)
210 return 0;
211 }
212 i++;
213 }
214
215 return i == 2 ? rxskip : 0;
216}
217
218static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)
219{
220 u32 tx_fifo_avail;
221 unsigned int tx_left;
222 const void *tx_buf;
223
224 /* if events is zero transfer has not started and tx fifo is empty */
225 tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE;
226start:
227 tx_left = espi->tx_t->len - espi->tx_pos;
228 tx_buf = espi->tx_t->tx_buf;
229 while (tx_fifo_avail >= min(4U, tx_left) && tx_left) {
230 if (tx_left >= 4) {
231 if (!tx_buf)
232 fsl_espi_write_reg(espi, ESPI_SPITF, 0);
233 else if (espi->swab)
234 fsl_espi_write_reg(espi, ESPI_SPITF,
235 swahb32p(tx_buf + espi->tx_pos));
236 else
237 fsl_espi_write_reg(espi, ESPI_SPITF,
238 *(u32 *)(tx_buf + espi->tx_pos));
239 espi->tx_pos += 4;
240 tx_left -= 4;
241 tx_fifo_avail -= 4;
242 } else if (tx_left >= 2 && tx_buf && espi->swab) {
243 fsl_espi_write_reg16(espi, ESPI_SPITF,
244 swab16p(tx_buf + espi->tx_pos));
245 espi->tx_pos += 2;
246 tx_left -= 2;
247 tx_fifo_avail -= 2;
248 } else {
249 if (!tx_buf)
250 fsl_espi_write_reg8(espi, ESPI_SPITF, 0);
251 else
252 fsl_espi_write_reg8(espi, ESPI_SPITF,
253 *(u8 *)(tx_buf + espi->tx_pos));
254 espi->tx_pos += 1;
255 tx_left -= 1;
256 tx_fifo_avail -= 1;
257 }
258 }
259
260 if (!tx_left) {
261 /* Last transfer finished, in rxskip mode only one is needed */
262 if (list_is_last(&espi->tx_t->transfer_list,
263 espi->m_transfers) || espi->rxskip) {
264 espi->tx_done = true;
265 return;
266 }
267 espi->tx_t = list_next_entry(espi->tx_t, transfer_list);
268 espi->tx_pos = 0;
269 /* continue with next transfer if tx fifo is not full */
270 if (tx_fifo_avail)
271 goto start;
272 }
273}
274
275static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events)
276{
277 u32 rx_fifo_avail = SPIE_RXCNT(events);
278 unsigned int rx_left;
279 void *rx_buf;
280
281start:
282 rx_left = espi->rx_t->len - espi->rx_pos;
283 rx_buf = espi->rx_t->rx_buf;
284 while (rx_fifo_avail >= min(4U, rx_left) && rx_left) {
285 if (rx_left >= 4) {
286 u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF);
287
288 if (rx_buf && espi->swab)
289 *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val);
290 else if (rx_buf)
291 *(u32 *)(rx_buf + espi->rx_pos) = val;
292 espi->rx_pos += 4;
293 rx_left -= 4;
294 rx_fifo_avail -= 4;
295 } else if (rx_left >= 2 && rx_buf && espi->swab) {
296 u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF);
297
298 *(u16 *)(rx_buf + espi->rx_pos) = swab16(val);
299 espi->rx_pos += 2;
300 rx_left -= 2;
301 rx_fifo_avail -= 2;
302 } else {
303 u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF);
304
305 if (rx_buf)
306 *(u8 *)(rx_buf + espi->rx_pos) = val;
307 espi->rx_pos += 1;
308 rx_left -= 1;
309 rx_fifo_avail -= 1;
310 }
311 }
312
313 if (!rx_left) {
314 if (list_is_last(&espi->rx_t->transfer_list,
315 espi->m_transfers)) {
316 espi->rx_done = true;
317 return;
318 }
319 espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
320 espi->rx_pos = 0;
321 /* continue with next transfer if rx fifo is not empty */
322 if (rx_fifo_avail)
323 goto start;
324 }
325}
326
327static void fsl_espi_setup_transfer(struct spi_device *spi,
328 struct spi_transfer *t)
329{
330 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
331 int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
332 u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
333 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
334 u32 hw_mode_old = cs->hw_mode;
335
336 /* mask out bits we are going to set */
337 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
338
339 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
340
341 pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1;
342
343 if (pm > 15) {
344 cs->hw_mode |= CSMODE_DIV16;
345 pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1;
346 }
347
348 cs->hw_mode |= CSMODE_PM(pm);
349
350 /* don't write the mode register if the mode doesn't change */
351 if (cs->hw_mode != hw_mode_old)
352 fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
353 cs->hw_mode);
354}
355
356static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
357{
358 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
359 unsigned int rx_len = t->len;
360 u32 mask, spcom;
361 int ret;
362
363 reinit_completion(&espi->done);
364
365 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
366 spcom = SPCOM_CS(spi->chip_select);
367 spcom |= SPCOM_TRANLEN(t->len - 1);
368
369 /* configure RXSKIP mode */
370 if (espi->rxskip) {
371 spcom |= SPCOM_RXSKIP(espi->rxskip);
372 rx_len = t->len - espi->rxskip;
373 if (t->rx_nbits == SPI_NBITS_DUAL)
374 spcom |= SPCOM_DO;
375 }
376
377 fsl_espi_write_reg(espi, ESPI_SPCOM, spcom);
378
379 /* enable interrupts */
380 mask = SPIM_DON;
381 if (rx_len > FSL_ESPI_FIFO_SIZE)
382 mask |= SPIM_RXT;
383 fsl_espi_write_reg(espi, ESPI_SPIM, mask);
384
385 /* Prevent filling the fifo from getting interrupted */
386 spin_lock_irq(&espi->lock);
387 fsl_espi_fill_tx_fifo(espi, 0);
388 spin_unlock_irq(&espi->lock);
389
390 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
391 ret = wait_for_completion_timeout(&espi->done, 2 * HZ);
392 if (ret == 0)
393 dev_err(espi->dev, "Transfer timed out!\n");
394
395 /* disable rx ints */
396 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
397
398 return ret == 0 ? -ETIMEDOUT : 0;
399}
400
401static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
402{
403 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
404 struct spi_device *spi = m->spi;
405 int ret;
406
407 /* In case of LSB-first and bits_per_word > 8 byte-swap all words */
408 espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8;
409
410 espi->m_transfers = &m->transfers;
411 espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer,
412 transfer_list);
413 espi->tx_pos = 0;
414 espi->tx_done = false;
415 espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer,
416 transfer_list);
417 espi->rx_pos = 0;
418 espi->rx_done = false;
419
420 espi->rxskip = fsl_espi_check_rxskip_mode(m);
421 if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) {
422 dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n");
423 return -EINVAL;
424 }
425
426 /* In RXSKIP mode skip first transfer for reads */
427 if (espi->rxskip)
428 espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
429
430 fsl_espi_setup_transfer(spi, trans);
431
432 ret = fsl_espi_bufs(spi, trans);
433
434 if (trans->delay_usecs)
435 udelay(trans->delay_usecs);
436
437 return ret;
438}
439
440static int fsl_espi_do_one_msg(struct spi_master *master,
441 struct spi_message *m)
442{
443 unsigned int delay_usecs = 0, rx_nbits = 0;
444 struct spi_transfer *t, trans = {};
445 int ret;
446
447 ret = fsl_espi_check_message(m);
448 if (ret)
449 goto out;
450
451 list_for_each_entry(t, &m->transfers, transfer_list) {
452 if (t->delay_usecs > delay_usecs)
453 delay_usecs = t->delay_usecs;
454 if (t->rx_nbits > rx_nbits)
455 rx_nbits = t->rx_nbits;
456 }
457
458 t = list_first_entry(&m->transfers, struct spi_transfer,
459 transfer_list);
460
461 trans.len = m->frame_length;
462 trans.speed_hz = t->speed_hz;
463 trans.bits_per_word = t->bits_per_word;
464 trans.delay_usecs = delay_usecs;
465 trans.rx_nbits = rx_nbits;
466
467 if (trans.len)
468 ret = fsl_espi_trans(m, &trans);
469
470 m->actual_length = ret ? 0 : trans.len;
471out:
472 if (m->status == -EINPROGRESS)
473 m->status = ret;
474
475 spi_finalize_current_message(master);
476
477 return ret;
478}
479
480static int fsl_espi_setup(struct spi_device *spi)
481{
482 struct fsl_espi *espi;
483 u32 loop_mode;
484 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
485
486 if (!cs) {
487 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
488 if (!cs)
489 return -ENOMEM;
490 spi_set_ctldata(spi, cs);
491 }
492
493 espi = spi_master_get_devdata(spi->master);
494
495 pm_runtime_get_sync(espi->dev);
496
497 cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
498 /* mask out bits we are going to set */
499 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
500 | CSMODE_REV);
501
502 if (spi->mode & SPI_CPHA)
503 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
504 if (spi->mode & SPI_CPOL)
505 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
506 if (!(spi->mode & SPI_LSB_FIRST))
507 cs->hw_mode |= CSMODE_REV;
508
509 /* Handle the loop mode */
510 loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE);
511 loop_mode &= ~SPMODE_LOOP;
512 if (spi->mode & SPI_LOOP)
513 loop_mode |= SPMODE_LOOP;
514 fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode);
515
516 fsl_espi_setup_transfer(spi, NULL);
517
518 pm_runtime_mark_last_busy(espi->dev);
519 pm_runtime_put_autosuspend(espi->dev);
520
521 return 0;
522}
523
524static void fsl_espi_cleanup(struct spi_device *spi)
525{
526 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
527
528 kfree(cs);
529 spi_set_ctldata(spi, NULL);
530}
531
532static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
533{
534 if (!espi->rx_done)
535 fsl_espi_read_rx_fifo(espi, events);
536
537 if (!espi->tx_done)
538 fsl_espi_fill_tx_fifo(espi, events);
539
540 if (!espi->tx_done || !espi->rx_done)
541 return;
542
543 /* we're done, but check for errors before returning */
544 events = fsl_espi_read_reg(espi, ESPI_SPIE);
545
546 if (!(events & SPIE_DON))
547 dev_err(espi->dev,
548 "Transfer done but SPIE_DON isn't set!\n");
549
550 if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE)
551 dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
552
553 complete(&espi->done);
554}
555
556static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
557{
558 struct fsl_espi *espi = context_data;
559 u32 events;
560
561 spin_lock(&espi->lock);
562
563 /* Get interrupt events(tx/rx) */
564 events = fsl_espi_read_reg(espi, ESPI_SPIE);
565 if (!events) {
566 spin_unlock(&espi->lock);
567 return IRQ_NONE;
568 }
569
570 dev_vdbg(espi->dev, "%s: events %x\n", __func__, events);
571
572 fsl_espi_cpu_irq(espi, events);
573
574 /* Clear the events */
575 fsl_espi_write_reg(espi, ESPI_SPIE, events);
576
577 spin_unlock(&espi->lock);
578
579 return IRQ_HANDLED;
580}
581
582#ifdef CONFIG_PM
583static int fsl_espi_runtime_suspend(struct device *dev)
584{
585 struct spi_master *master = dev_get_drvdata(dev);
586 struct fsl_espi *espi = spi_master_get_devdata(master);
587 u32 regval;
588
589 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
590 regval &= ~SPMODE_ENABLE;
591 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
592
593 return 0;
594}
595
596static int fsl_espi_runtime_resume(struct device *dev)
597{
598 struct spi_master *master = dev_get_drvdata(dev);
599 struct fsl_espi *espi = spi_master_get_devdata(master);
600 u32 regval;
601
602 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
603 regval |= SPMODE_ENABLE;
604 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
605
606 return 0;
607}
608#endif
609
610static size_t fsl_espi_max_message_size(struct spi_device *spi)
611{
612 return SPCOM_TRANLEN_MAX;
613}
614
615static void fsl_espi_init_regs(struct device *dev, bool initial)
616{
617 struct spi_master *master = dev_get_drvdata(dev);
618 struct fsl_espi *espi = spi_master_get_devdata(master);
619 struct device_node *nc;
620 u32 csmode, cs, prop;
621 int ret;
622
623 /* SPI controller initializations */
624 fsl_espi_write_reg(espi, ESPI_SPMODE, 0);
625 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
626 fsl_espi_write_reg(espi, ESPI_SPCOM, 0);
627 fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff);
628
629 /* Init eSPI CS mode register */
630 for_each_available_child_of_node(master->dev.of_node, nc) {
631 /* get chip select */
632 ret = of_property_read_u32(nc, "reg", &cs);
633 if (ret || cs >= master->num_chipselect)
634 continue;
635
636 csmode = CSMODE_INIT_VAL;
637
638 /* check if CSBEF is set in device tree */
639 ret = of_property_read_u32(nc, "fsl,csbef", &prop);
640 if (!ret) {
641 csmode &= ~(CSMODE_BEF(0xf));
642 csmode |= CSMODE_BEF(prop);
643 }
644
645 /* check if CSAFT is set in device tree */
646 ret = of_property_read_u32(nc, "fsl,csaft", &prop);
647 if (!ret) {
648 csmode &= ~(CSMODE_AFT(0xf));
649 csmode |= CSMODE_AFT(prop);
650 }
651
652 fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode);
653
654 if (initial)
655 dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode);
656 }
657
658 /* Enable SPI interface */
659 fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE);
660}
661
662static int fsl_espi_probe(struct device *dev, struct resource *mem,
663 unsigned int irq, unsigned int num_cs)
664{
665 struct spi_master *master;
666 struct fsl_espi *espi;
667 int ret;
668
669 master = spi_alloc_master(dev, sizeof(struct fsl_espi));
670 if (!master)
671 return -ENOMEM;
672
673 dev_set_drvdata(dev, master);
674
675 master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
676 SPI_LSB_FIRST | SPI_LOOP;
677 master->dev.of_node = dev->of_node;
678 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
679 master->setup = fsl_espi_setup;
680 master->cleanup = fsl_espi_cleanup;
681 master->transfer_one_message = fsl_espi_do_one_msg;
682 master->auto_runtime_pm = true;
683 master->max_message_size = fsl_espi_max_message_size;
684 master->num_chipselect = num_cs;
685
686 espi = spi_master_get_devdata(master);
687 spin_lock_init(&espi->lock);
688
689 espi->dev = dev;
690 espi->spibrg = fsl_get_sys_freq();
691 if (espi->spibrg == -1) {
692 dev_err(dev, "Can't get sys frequency!\n");
693 ret = -EINVAL;
694 goto err_probe;
695 }
696 /* determined by clock divider fields DIV16/PM in register SPMODEx */
697 master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16);
698 master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4);
699
700 init_completion(&espi->done);
701
702 espi->reg_base = devm_ioremap_resource(dev, mem);
703 if (IS_ERR(espi->reg_base)) {
704 ret = PTR_ERR(espi->reg_base);
705 goto err_probe;
706 }
707
708 /* Register for SPI Interrupt */
709 ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi);
710 if (ret)
711 goto err_probe;
712
713 fsl_espi_init_regs(dev, true);
714
715 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
716 pm_runtime_use_autosuspend(dev);
717 pm_runtime_set_active(dev);
718 pm_runtime_enable(dev);
719 pm_runtime_get_sync(dev);
720
721 ret = devm_spi_register_master(dev, master);
722 if (ret < 0)
723 goto err_pm;
724
725 dev_info(dev, "at 0x%p (irq = %u)\n", espi->reg_base, irq);
726
727 pm_runtime_mark_last_busy(dev);
728 pm_runtime_put_autosuspend(dev);
729
730 return 0;
731
732err_pm:
733 pm_runtime_put_noidle(dev);
734 pm_runtime_disable(dev);
735 pm_runtime_set_suspended(dev);
736err_probe:
737 spi_master_put(master);
738 return ret;
739}
740
741static int of_fsl_espi_get_chipselects(struct device *dev)
742{
743 struct device_node *np = dev->of_node;
744 u32 num_cs;
745 int ret;
746
747 ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs);
748 if (ret) {
749 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
750 return 0;
751 }
752
753 return num_cs;
754}
755
756static int of_fsl_espi_probe(struct platform_device *ofdev)
757{
758 struct device *dev = &ofdev->dev;
759 struct device_node *np = ofdev->dev.of_node;
760 struct resource mem;
761 unsigned int irq, num_cs;
762 int ret;
763
764 if (of_property_read_bool(np, "mode")) {
765 dev_err(dev, "mode property is not supported on ESPI!\n");
766 return -EINVAL;
767 }
768
769 num_cs = of_fsl_espi_get_chipselects(dev);
770 if (!num_cs)
771 return -EINVAL;
772
773 ret = of_address_to_resource(np, 0, &mem);
774 if (ret)
775 return ret;
776
777 irq = irq_of_parse_and_map(np, 0);
778 if (!irq)
779 return -EINVAL;
780
781 return fsl_espi_probe(dev, &mem, irq, num_cs);
782}
783
784static int of_fsl_espi_remove(struct platform_device *dev)
785{
786 pm_runtime_disable(&dev->dev);
787
788 return 0;
789}
790
791#ifdef CONFIG_PM_SLEEP
792static int of_fsl_espi_suspend(struct device *dev)
793{
794 struct spi_master *master = dev_get_drvdata(dev);
795 int ret;
796
797 ret = spi_master_suspend(master);
798 if (ret) {
799 dev_warn(dev, "cannot suspend master\n");
800 return ret;
801 }
802
803 return pm_runtime_force_suspend(dev);
804}
805
806static int of_fsl_espi_resume(struct device *dev)
807{
808 struct spi_master *master = dev_get_drvdata(dev);
809 int ret;
810
811 fsl_espi_init_regs(dev, false);
812
813 ret = pm_runtime_force_resume(dev);
814 if (ret < 0)
815 return ret;
816
817 return spi_master_resume(master);
818}
819#endif /* CONFIG_PM_SLEEP */
820
821static const struct dev_pm_ops espi_pm = {
822 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
823 fsl_espi_runtime_resume, NULL)
824 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
825};
826
827static const struct of_device_id of_fsl_espi_match[] = {
828 { .compatible = "fsl,mpc8536-espi" },
829 {}
830};
831MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
832
833static struct platform_driver fsl_espi_driver = {
834 .driver = {
835 .name = "fsl_espi",
836 .of_match_table = of_fsl_espi_match,
837 .pm = &espi_pm,
838 },
839 .probe = of_fsl_espi_probe,
840 .remove = of_fsl_espi_remove,
841};
842module_platform_driver(fsl_espi_driver);
843
844MODULE_AUTHOR("Mingkai Hu");
845MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
846MODULE_LICENSE("GPL");