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1/*
2 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
3 *
4 * Copyright (c) 2010, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/delay.h>
27#include <linux/rtc.h>
28#include <linux/platform_device.h>
29#include <linux/pm.h>
30
31/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
32#define TEGRA_RTC_REG_BUSY 0x004
33#define TEGRA_RTC_REG_SECONDS 0x008
34/* when msec is read, the seconds are buffered into shadow seconds. */
35#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
36#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
37#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
38#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
39#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
40#define TEGRA_RTC_REG_INTR_MASK 0x028
41/* write 1 bits to clear status bits */
42#define TEGRA_RTC_REG_INTR_STATUS 0x02c
43
44/* bits in INTR_MASK */
45#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
46#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
47#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
48#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
49#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
50
51/* bits in INTR_STATUS */
52#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
53#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
54#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
55#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
56#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
57
58struct tegra_rtc_info {
59 struct platform_device *pdev;
60 struct rtc_device *rtc_dev;
61 void __iomem *rtc_base; /* NULL if not initialized. */
62 int tegra_rtc_irq; /* alarm and periodic irq */
63 spinlock_t tegra_rtc_lock;
64};
65
66/* RTC hardware is busy when it is updating its values over AHB once
67 * every eight 32kHz clocks (~250uS).
68 * outside of these updates the CPU is free to write.
69 * CPU is always free to read.
70 */
71static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
72{
73 return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
74}
75
76/* Wait for hardware to be ready for writing.
77 * This function tries to maximize the amount of time before the next update.
78 * It does this by waiting for the RTC to become busy with its periodic update,
79 * then returning once the RTC first becomes not busy.
80 * This periodic update (where the seconds and milliseconds are copied to the
81 * AHB side) occurs every eight 32kHz clocks (~250uS).
82 * The behavior of this function allows us to make some assumptions without
83 * introducing a race, because 250uS is plenty of time to read/write a value.
84 */
85static int tegra_rtc_wait_while_busy(struct device *dev)
86{
87 struct tegra_rtc_info *info = dev_get_drvdata(dev);
88
89 int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
90
91 /* first wait for the RTC to become busy. this is when it
92 * posts its updated seconds+msec registers to AHB side. */
93 while (tegra_rtc_check_busy(info)) {
94 if (!retries--)
95 goto retry_failed;
96 udelay(1);
97 }
98
99 /* now we have about 250 us to manipulate registers */
100 return 0;
101
102retry_failed:
103 dev_err(dev, "write failed:retry count exceeded.\n");
104 return -ETIMEDOUT;
105}
106
107static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
108{
109 struct tegra_rtc_info *info = dev_get_drvdata(dev);
110 unsigned long sec, msec;
111 unsigned long sl_irq_flags;
112
113 /* RTC hardware copies seconds to shadow seconds when a read
114 * of milliseconds occurs. use a lock to keep other threads out. */
115 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
116
117 msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
118 sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
119
120 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
121
122 rtc_time_to_tm(sec, tm);
123
124 dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
125 sec,
126 tm->tm_mon + 1,
127 tm->tm_mday,
128 tm->tm_year + 1900,
129 tm->tm_hour,
130 tm->tm_min,
131 tm->tm_sec
132 );
133
134 return 0;
135}
136
137static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
138{
139 struct tegra_rtc_info *info = dev_get_drvdata(dev);
140 unsigned long sec;
141 int ret;
142
143 /* convert tm to seconds. */
144 ret = rtc_valid_tm(tm);
145 if (ret)
146 return ret;
147
148 rtc_tm_to_time(tm, &sec);
149
150 dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
151 sec,
152 tm->tm_mon+1,
153 tm->tm_mday,
154 tm->tm_year+1900,
155 tm->tm_hour,
156 tm->tm_min,
157 tm->tm_sec
158 );
159
160 /* seconds only written if wait succeeded. */
161 ret = tegra_rtc_wait_while_busy(dev);
162 if (!ret)
163 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
164
165 dev_vdbg(dev, "time read back as %d\n",
166 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
167
168 return ret;
169}
170
171static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
172{
173 struct tegra_rtc_info *info = dev_get_drvdata(dev);
174 unsigned long sec;
175 unsigned tmp;
176
177 sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
178
179 if (sec == 0) {
180 /* alarm is disabled. */
181 alarm->enabled = 0;
182 alarm->time.tm_mon = -1;
183 alarm->time.tm_mday = -1;
184 alarm->time.tm_year = -1;
185 alarm->time.tm_hour = -1;
186 alarm->time.tm_min = -1;
187 alarm->time.tm_sec = -1;
188 } else {
189 /* alarm is enabled. */
190 alarm->enabled = 1;
191 rtc_time_to_tm(sec, &alarm->time);
192 }
193
194 tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
195 alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
196
197 return 0;
198}
199
200static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
201{
202 struct tegra_rtc_info *info = dev_get_drvdata(dev);
203 unsigned status;
204 unsigned long sl_irq_flags;
205
206 tegra_rtc_wait_while_busy(dev);
207 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
208
209 /* read the original value, and OR in the flag. */
210 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
211 if (enabled)
212 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
213 else
214 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
215
216 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
217
218 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
219
220 return 0;
221}
222
223static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
224{
225 struct tegra_rtc_info *info = dev_get_drvdata(dev);
226 unsigned long sec;
227
228 if (alarm->enabled)
229 rtc_tm_to_time(&alarm->time, &sec);
230 else
231 sec = 0;
232
233 tegra_rtc_wait_while_busy(dev);
234 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
235 dev_vdbg(dev, "alarm read back as %d\n",
236 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
237
238 /* if successfully written and alarm is enabled ... */
239 if (sec) {
240 tegra_rtc_alarm_irq_enable(dev, 1);
241
242 dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
243 sec,
244 alarm->time.tm_mon+1,
245 alarm->time.tm_mday,
246 alarm->time.tm_year+1900,
247 alarm->time.tm_hour,
248 alarm->time.tm_min,
249 alarm->time.tm_sec);
250 } else {
251 /* disable alarm if 0 or write error. */
252 dev_vdbg(dev, "alarm disabled\n");
253 tegra_rtc_alarm_irq_enable(dev, 0);
254 }
255
256 return 0;
257}
258
259static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
260{
261 if (!dev || !dev->driver)
262 return 0;
263
264 seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
265
266 return 0;
267}
268
269static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
270{
271 struct device *dev = data;
272 struct tegra_rtc_info *info = dev_get_drvdata(dev);
273 unsigned long events = 0;
274 unsigned status;
275 unsigned long sl_irq_flags;
276
277 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
278 if (status) {
279 /* clear the interrupt masks and status on any irq. */
280 tegra_rtc_wait_while_busy(dev);
281 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
282 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
283 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
284 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
285 }
286
287 /* check if Alarm */
288 if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
289 events |= RTC_IRQF | RTC_AF;
290
291 /* check if Periodic */
292 if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
293 events |= RTC_IRQF | RTC_PF;
294
295 rtc_update_irq(info->rtc_dev, 1, events);
296
297 return IRQ_HANDLED;
298}
299
300static struct rtc_class_ops tegra_rtc_ops = {
301 .read_time = tegra_rtc_read_time,
302 .set_time = tegra_rtc_set_time,
303 .read_alarm = tegra_rtc_read_alarm,
304 .set_alarm = tegra_rtc_set_alarm,
305 .proc = tegra_rtc_proc,
306 .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
307};
308
309static const struct of_device_id tegra_rtc_dt_match[] = {
310 { .compatible = "nvidia,tegra20-rtc", },
311 {}
312};
313MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
314
315static int __init tegra_rtc_probe(struct platform_device *pdev)
316{
317 struct tegra_rtc_info *info;
318 struct resource *res;
319 int ret;
320
321 info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
322 GFP_KERNEL);
323 if (!info)
324 return -ENOMEM;
325
326 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
327 info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
328 if (IS_ERR(info->rtc_base))
329 return PTR_ERR(info->rtc_base);
330
331 info->tegra_rtc_irq = platform_get_irq(pdev, 0);
332 if (info->tegra_rtc_irq <= 0)
333 return -EBUSY;
334
335 /* set context info. */
336 info->pdev = pdev;
337 spin_lock_init(&info->tegra_rtc_lock);
338
339 platform_set_drvdata(pdev, info);
340
341 /* clear out the hardware. */
342 writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
343 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
344 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
345
346 device_init_wakeup(&pdev->dev, 1);
347
348 info->rtc_dev = devm_rtc_device_register(&pdev->dev,
349 dev_name(&pdev->dev), &tegra_rtc_ops,
350 THIS_MODULE);
351 if (IS_ERR(info->rtc_dev)) {
352 ret = PTR_ERR(info->rtc_dev);
353 dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
354 ret);
355 return ret;
356 }
357
358 ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
359 tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
360 dev_name(&pdev->dev), &pdev->dev);
361 if (ret) {
362 dev_err(&pdev->dev,
363 "Unable to request interrupt for device (err=%d).\n",
364 ret);
365 return ret;
366 }
367
368 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
369
370 return 0;
371}
372
373#ifdef CONFIG_PM_SLEEP
374static int tegra_rtc_suspend(struct device *dev)
375{
376 struct tegra_rtc_info *info = dev_get_drvdata(dev);
377
378 tegra_rtc_wait_while_busy(dev);
379
380 /* only use ALARM0 as a wake source. */
381 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
382 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
383 info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
384
385 dev_vdbg(dev, "alarm sec = %d\n",
386 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
387
388 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
389 device_may_wakeup(dev), info->tegra_rtc_irq);
390
391 /* leave the alarms on as a wake source. */
392 if (device_may_wakeup(dev))
393 enable_irq_wake(info->tegra_rtc_irq);
394
395 return 0;
396}
397
398static int tegra_rtc_resume(struct device *dev)
399{
400 struct tegra_rtc_info *info = dev_get_drvdata(dev);
401
402 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
403 device_may_wakeup(dev));
404 /* alarms were left on as a wake source, turn them off. */
405 if (device_may_wakeup(dev))
406 disable_irq_wake(info->tegra_rtc_irq);
407
408 return 0;
409}
410#endif
411
412static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
413
414static void tegra_rtc_shutdown(struct platform_device *pdev)
415{
416 dev_vdbg(&pdev->dev, "disabling interrupts.\n");
417 tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
418}
419
420MODULE_ALIAS("platform:tegra_rtc");
421static struct platform_driver tegra_rtc_driver = {
422 .shutdown = tegra_rtc_shutdown,
423 .driver = {
424 .name = "tegra_rtc",
425 .of_match_table = tegra_rtc_dt_match,
426 .pm = &tegra_rtc_pm_ops,
427 },
428};
429
430module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
431
432MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
433MODULE_DESCRIPTION("driver for Tegra internal RTC");
434MODULE_LICENSE("GPL");
1/*
2 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
3 *
4 * Copyright (c) 2010, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/delay.h>
27#include <linux/rtc.h>
28#include <linux/platform_device.h>
29#include <linux/pm.h>
30
31/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
32#define TEGRA_RTC_REG_BUSY 0x004
33#define TEGRA_RTC_REG_SECONDS 0x008
34/* when msec is read, the seconds are buffered into shadow seconds. */
35#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
36#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
37#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
38#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
39#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
40#define TEGRA_RTC_REG_INTR_MASK 0x028
41/* write 1 bits to clear status bits */
42#define TEGRA_RTC_REG_INTR_STATUS 0x02c
43
44/* bits in INTR_MASK */
45#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
46#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
47#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
48#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
49#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
50
51/* bits in INTR_STATUS */
52#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
53#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
54#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
55#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
56#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
57
58struct tegra_rtc_info {
59 struct platform_device *pdev;
60 struct rtc_device *rtc_dev;
61 void __iomem *rtc_base; /* NULL if not initialized. */
62 int tegra_rtc_irq; /* alarm and periodic irq */
63 spinlock_t tegra_rtc_lock;
64};
65
66/* RTC hardware is busy when it is updating its values over AHB once
67 * every eight 32kHz clocks (~250uS).
68 * outside of these updates the CPU is free to write.
69 * CPU is always free to read.
70 */
71static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
72{
73 return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
74}
75
76/* Wait for hardware to be ready for writing.
77 * This function tries to maximize the amount of time before the next update.
78 * It does this by waiting for the RTC to become busy with its periodic update,
79 * then returning once the RTC first becomes not busy.
80 * This periodic update (where the seconds and milliseconds are copied to the
81 * AHB side) occurs every eight 32kHz clocks (~250uS).
82 * The behavior of this function allows us to make some assumptions without
83 * introducing a race, because 250uS is plenty of time to read/write a value.
84 */
85static int tegra_rtc_wait_while_busy(struct device *dev)
86{
87 struct tegra_rtc_info *info = dev_get_drvdata(dev);
88
89 int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
90
91 /* first wait for the RTC to become busy. this is when it
92 * posts its updated seconds+msec registers to AHB side. */
93 while (tegra_rtc_check_busy(info)) {
94 if (!retries--)
95 goto retry_failed;
96 udelay(1);
97 }
98
99 /* now we have about 250 us to manipulate registers */
100 return 0;
101
102retry_failed:
103 dev_err(dev, "write failed:retry count exceeded.\n");
104 return -ETIMEDOUT;
105}
106
107static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
108{
109 struct tegra_rtc_info *info = dev_get_drvdata(dev);
110 unsigned long sec, msec;
111 unsigned long sl_irq_flags;
112
113 /* RTC hardware copies seconds to shadow seconds when a read
114 * of milliseconds occurs. use a lock to keep other threads out. */
115 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
116
117 msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
118 sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
119
120 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
121
122 rtc_time_to_tm(sec, tm);
123
124 dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
125 sec,
126 tm->tm_mon + 1,
127 tm->tm_mday,
128 tm->tm_year + 1900,
129 tm->tm_hour,
130 tm->tm_min,
131 tm->tm_sec
132 );
133
134 return 0;
135}
136
137static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
138{
139 struct tegra_rtc_info *info = dev_get_drvdata(dev);
140 unsigned long sec;
141 int ret;
142
143 /* convert tm to seconds. */
144 ret = rtc_valid_tm(tm);
145 if (ret)
146 return ret;
147
148 rtc_tm_to_time(tm, &sec);
149
150 dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
151 sec,
152 tm->tm_mon+1,
153 tm->tm_mday,
154 tm->tm_year+1900,
155 tm->tm_hour,
156 tm->tm_min,
157 tm->tm_sec
158 );
159
160 /* seconds only written if wait succeeded. */
161 ret = tegra_rtc_wait_while_busy(dev);
162 if (!ret)
163 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
164
165 dev_vdbg(dev, "time read back as %d\n",
166 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
167
168 return ret;
169}
170
171static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
172{
173 struct tegra_rtc_info *info = dev_get_drvdata(dev);
174 unsigned long sec;
175 unsigned tmp;
176
177 sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
178
179 if (sec == 0) {
180 /* alarm is disabled. */
181 alarm->enabled = 0;
182 } else {
183 /* alarm is enabled. */
184 alarm->enabled = 1;
185 rtc_time_to_tm(sec, &alarm->time);
186 }
187
188 tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
189 alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
190
191 return 0;
192}
193
194static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
195{
196 struct tegra_rtc_info *info = dev_get_drvdata(dev);
197 unsigned status;
198 unsigned long sl_irq_flags;
199
200 tegra_rtc_wait_while_busy(dev);
201 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
202
203 /* read the original value, and OR in the flag. */
204 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
205 if (enabled)
206 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
207 else
208 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
209
210 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
211
212 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
213
214 return 0;
215}
216
217static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
218{
219 struct tegra_rtc_info *info = dev_get_drvdata(dev);
220 unsigned long sec;
221
222 if (alarm->enabled)
223 rtc_tm_to_time(&alarm->time, &sec);
224 else
225 sec = 0;
226
227 tegra_rtc_wait_while_busy(dev);
228 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
229 dev_vdbg(dev, "alarm read back as %d\n",
230 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
231
232 /* if successfully written and alarm is enabled ... */
233 if (sec) {
234 tegra_rtc_alarm_irq_enable(dev, 1);
235
236 dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
237 sec,
238 alarm->time.tm_mon+1,
239 alarm->time.tm_mday,
240 alarm->time.tm_year+1900,
241 alarm->time.tm_hour,
242 alarm->time.tm_min,
243 alarm->time.tm_sec);
244 } else {
245 /* disable alarm if 0 or write error. */
246 dev_vdbg(dev, "alarm disabled\n");
247 tegra_rtc_alarm_irq_enable(dev, 0);
248 }
249
250 return 0;
251}
252
253static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
254{
255 if (!dev || !dev->driver)
256 return 0;
257
258 seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
259
260 return 0;
261}
262
263static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
264{
265 struct device *dev = data;
266 struct tegra_rtc_info *info = dev_get_drvdata(dev);
267 unsigned long events = 0;
268 unsigned status;
269 unsigned long sl_irq_flags;
270
271 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
272 if (status) {
273 /* clear the interrupt masks and status on any irq. */
274 tegra_rtc_wait_while_busy(dev);
275 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
276 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
277 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
278 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
279 }
280
281 /* check if Alarm */
282 if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
283 events |= RTC_IRQF | RTC_AF;
284
285 /* check if Periodic */
286 if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
287 events |= RTC_IRQF | RTC_PF;
288
289 rtc_update_irq(info->rtc_dev, 1, events);
290
291 return IRQ_HANDLED;
292}
293
294static const struct rtc_class_ops tegra_rtc_ops = {
295 .read_time = tegra_rtc_read_time,
296 .set_time = tegra_rtc_set_time,
297 .read_alarm = tegra_rtc_read_alarm,
298 .set_alarm = tegra_rtc_set_alarm,
299 .proc = tegra_rtc_proc,
300 .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
301};
302
303static const struct of_device_id tegra_rtc_dt_match[] = {
304 { .compatible = "nvidia,tegra20-rtc", },
305 {}
306};
307MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
308
309static int __init tegra_rtc_probe(struct platform_device *pdev)
310{
311 struct tegra_rtc_info *info;
312 struct resource *res;
313 int ret;
314
315 info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
316 GFP_KERNEL);
317 if (!info)
318 return -ENOMEM;
319
320 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
321 info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
322 if (IS_ERR(info->rtc_base))
323 return PTR_ERR(info->rtc_base);
324
325 info->tegra_rtc_irq = platform_get_irq(pdev, 0);
326 if (info->tegra_rtc_irq <= 0)
327 return -EBUSY;
328
329 /* set context info. */
330 info->pdev = pdev;
331 spin_lock_init(&info->tegra_rtc_lock);
332
333 platform_set_drvdata(pdev, info);
334
335 /* clear out the hardware. */
336 writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
337 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
338 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
339
340 device_init_wakeup(&pdev->dev, 1);
341
342 info->rtc_dev = devm_rtc_device_register(&pdev->dev,
343 dev_name(&pdev->dev), &tegra_rtc_ops,
344 THIS_MODULE);
345 if (IS_ERR(info->rtc_dev)) {
346 ret = PTR_ERR(info->rtc_dev);
347 dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
348 ret);
349 return ret;
350 }
351
352 ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
353 tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
354 dev_name(&pdev->dev), &pdev->dev);
355 if (ret) {
356 dev_err(&pdev->dev,
357 "Unable to request interrupt for device (err=%d).\n",
358 ret);
359 return ret;
360 }
361
362 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
363
364 return 0;
365}
366
367#ifdef CONFIG_PM_SLEEP
368static int tegra_rtc_suspend(struct device *dev)
369{
370 struct tegra_rtc_info *info = dev_get_drvdata(dev);
371
372 tegra_rtc_wait_while_busy(dev);
373
374 /* only use ALARM0 as a wake source. */
375 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
376 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
377 info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
378
379 dev_vdbg(dev, "alarm sec = %d\n",
380 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
381
382 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
383 device_may_wakeup(dev), info->tegra_rtc_irq);
384
385 /* leave the alarms on as a wake source. */
386 if (device_may_wakeup(dev))
387 enable_irq_wake(info->tegra_rtc_irq);
388
389 return 0;
390}
391
392static int tegra_rtc_resume(struct device *dev)
393{
394 struct tegra_rtc_info *info = dev_get_drvdata(dev);
395
396 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
397 device_may_wakeup(dev));
398 /* alarms were left on as a wake source, turn them off. */
399 if (device_may_wakeup(dev))
400 disable_irq_wake(info->tegra_rtc_irq);
401
402 return 0;
403}
404#endif
405
406static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
407
408static void tegra_rtc_shutdown(struct platform_device *pdev)
409{
410 dev_vdbg(&pdev->dev, "disabling interrupts.\n");
411 tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
412}
413
414MODULE_ALIAS("platform:tegra_rtc");
415static struct platform_driver tegra_rtc_driver = {
416 .shutdown = tegra_rtc_shutdown,
417 .driver = {
418 .name = "tegra_rtc",
419 .of_match_table = tegra_rtc_dt_match,
420 .pm = &tegra_rtc_pm_ops,
421 },
422};
423
424module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
425
426MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
427MODULE_DESCRIPTION("driver for Tegra internal RTC");
428MODULE_LICENSE("GPL");