1/*
   2 *	drivers/pci/setup-bus.c
   3 *
   4 * Extruded from code written by
   5 *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6 *      David Mosberger (davidm@cs.arizona.edu)
   7 *	David Miller (davem@redhat.com)
   8 *
   9 * Support routines for initializing a PCI subsystem.
  10 */
  11
  12/*
  13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  14 *	     PCI-PCI bridges cleanup, sorted resource allocation.
  15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16 *	     Converted to allocation in 3 passes, which gives
  17 *	     tighter packing. Prefetchable range support.
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/kernel.h>
  22#include <linux/module.h>
  23#include <linux/pci.h>
  24#include <linux/errno.h>
  25#include <linux/ioport.h>
  26#include <linux/cache.h>
  27#include <linux/slab.h>
 
  28#include "pci.h"
  29
  30unsigned int pci_flags;
  31
  32struct pci_dev_resource {
  33	struct list_head list;
  34	struct resource *res;
  35	struct pci_dev *dev;
  36	resource_size_t start;
  37	resource_size_t end;
  38	resource_size_t add_size;
  39	resource_size_t min_align;
  40	unsigned long flags;
  41};
  42
  43static void free_list(struct list_head *head)
  44{
  45	struct pci_dev_resource *dev_res, *tmp;
  46
  47	list_for_each_entry_safe(dev_res, tmp, head, list) {
  48		list_del(&dev_res->list);
  49		kfree(dev_res);
  50	}
  51}
  52
  53/**
  54 * add_to_list() - add a new resource tracker to the list
  55 * @head:	Head of the list
  56 * @dev:	device corresponding to which the resource
  57 *		belongs
  58 * @res:	The resource to be tracked
  59 * @add_size:	additional size to be optionally added
  60 *              to the resource
  61 */
  62static int add_to_list(struct list_head *head,
  63		 struct pci_dev *dev, struct resource *res,
  64		 resource_size_t add_size, resource_size_t min_align)
  65{
  66	struct pci_dev_resource *tmp;
  67
  68	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  69	if (!tmp) {
  70		pr_warn("add_to_list: kmalloc() failed!\n");
  71		return -ENOMEM;
  72	}
  73
  74	tmp->res = res;
  75	tmp->dev = dev;
  76	tmp->start = res->start;
  77	tmp->end = res->end;
  78	tmp->flags = res->flags;
  79	tmp->add_size = add_size;
  80	tmp->min_align = min_align;
  81
  82	list_add(&tmp->list, head);
  83
  84	return 0;
  85}
  86
  87static void remove_from_list(struct list_head *head,
  88				 struct resource *res)
  89{
  90	struct pci_dev_resource *dev_res, *tmp;
  91
  92	list_for_each_entry_safe(dev_res, tmp, head, list) {
  93		if (dev_res->res == res) {
  94			list_del(&dev_res->list);
  95			kfree(dev_res);
  96			break;
  97		}
  98	}
  99}
 100
 101static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
 102					       struct resource *res)
 103{
 104	struct pci_dev_resource *dev_res;
 105
 106	list_for_each_entry(dev_res, head, list) {
 107		if (dev_res->res == res) {
 108			int idx = res - &dev_res->dev->resource[0];
 109
 110			dev_printk(KERN_DEBUG, &dev_res->dev->dev,
 111				 "res[%d]=%pR res_to_dev_res add_size %llx min_align %llx\n",
 112				 idx, dev_res->res,
 113				 (unsigned long long)dev_res->add_size,
 114				 (unsigned long long)dev_res->min_align);
 115
 116			return dev_res;
 117		}
 118	}
 119
 120	return NULL;
 121}
 122
 123static resource_size_t get_res_add_size(struct list_head *head,
 124					struct resource *res)
 125{
 126	struct pci_dev_resource *dev_res;
 127
 128	dev_res = res_to_dev_res(head, res);
 129	return dev_res ? dev_res->add_size : 0;
 130}
 131
 132static resource_size_t get_res_add_align(struct list_head *head,
 133					 struct resource *res)
 134{
 135	struct pci_dev_resource *dev_res;
 136
 137	dev_res = res_to_dev_res(head, res);
 138	return dev_res ? dev_res->min_align : 0;
 139}
 140
 141
 142/* Sort resources by alignment */
 143static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
 144{
 145	int i;
 146
 147	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 148		struct resource *r;
 149		struct pci_dev_resource *dev_res, *tmp;
 150		resource_size_t r_align;
 151		struct list_head *n;
 152
 153		r = &dev->resource[i];
 154
 155		if (r->flags & IORESOURCE_PCI_FIXED)
 156			continue;
 157
 158		if (!(r->flags) || r->parent)
 159			continue;
 160
 161		r_align = pci_resource_alignment(dev, r);
 162		if (!r_align) {
 163			dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
 164				 i, r);
 165			continue;
 166		}
 167
 168		tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
 169		if (!tmp)
 170			panic("pdev_sort_resources(): kmalloc() failed!\n");
 171		tmp->res = r;
 172		tmp->dev = dev;
 173
 174		/* fallback is smallest one or list is empty*/
 175		n = head;
 176		list_for_each_entry(dev_res, head, list) {
 177			resource_size_t align;
 178
 179			align = pci_resource_alignment(dev_res->dev,
 180							 dev_res->res);
 181
 182			if (r_align > align) {
 183				n = &dev_res->list;
 184				break;
 185			}
 186		}
 187		/* Insert it just before n*/
 188		list_add_tail(&tmp->list, n);
 189	}
 190}
 191
 192static void __dev_sort_resources(struct pci_dev *dev,
 193				 struct list_head *head)
 194{
 195	u16 class = dev->class >> 8;
 196
 197	/* Don't touch classless devices or host bridges or ioapics.  */
 198	if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
 199		return;
 200
 201	/* Don't touch ioapic devices already enabled by firmware */
 202	if (class == PCI_CLASS_SYSTEM_PIC) {
 203		u16 command;
 204		pci_read_config_word(dev, PCI_COMMAND, &command);
 205		if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
 206			return;
 207	}
 208
 209	pdev_sort_resources(dev, head);
 210}
 211
 212static inline void reset_resource(struct resource *res)
 213{
 214	res->start = 0;
 215	res->end = 0;
 216	res->flags = 0;
 217}
 218
 219/**
 220 * reassign_resources_sorted() - satisfy any additional resource requests
 221 *
 222 * @realloc_head : head of the list tracking requests requiring additional
 223 *             resources
 224 * @head     : head of the list tracking requests with allocated
 225 *             resources
 226 *
 227 * Walk through each element of the realloc_head and try to procure
 228 * additional resources for the element, provided the element
 229 * is in the head list.
 230 */
 231static void reassign_resources_sorted(struct list_head *realloc_head,
 232		struct list_head *head)
 233{
 234	struct resource *res;
 235	struct pci_dev_resource *add_res, *tmp;
 236	struct pci_dev_resource *dev_res;
 237	resource_size_t add_size, align;
 238	int idx;
 239
 240	list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
 241		bool found_match = false;
 242
 243		res = add_res->res;
 244		/* skip resource that has been reset */
 245		if (!res->flags)
 246			goto out;
 247
 248		/* skip this resource if not found in head list */
 249		list_for_each_entry(dev_res, head, list) {
 250			if (dev_res->res == res) {
 251				found_match = true;
 252				break;
 253			}
 254		}
 255		if (!found_match)/* just skip */
 256			continue;
 257
 258		idx = res - &add_res->dev->resource[0];
 259		add_size = add_res->add_size;
 260		align = add_res->min_align;
 261		if (!resource_size(res)) {
 262			res->start = align;
 263			res->end = res->start + add_size - 1;
 264			if (pci_assign_resource(add_res->dev, idx))
 265				reset_resource(res);
 266		} else {
 267			res->flags |= add_res->flags &
 268				 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
 269			if (pci_reassign_resource(add_res->dev, idx,
 270						  add_size, align))
 271				dev_printk(KERN_DEBUG, &add_res->dev->dev,
 272					   "failed to add %llx res[%d]=%pR\n",
 273					   (unsigned long long)add_size,
 274					   idx, res);
 275		}
 276out:
 277		list_del(&add_res->list);
 278		kfree(add_res);
 279	}
 280}
 281
 282/**
 283 * assign_requested_resources_sorted() - satisfy resource requests
 284 *
 285 * @head : head of the list tracking requests for resources
 286 * @fail_head : head of the list tracking requests that could
 287 *		not be allocated
 288 *
 289 * Satisfy resource requests of each element in the list. Add
 290 * requests that could not satisfied to the failed_list.
 291 */
 292static void assign_requested_resources_sorted(struct list_head *head,
 293				 struct list_head *fail_head)
 294{
 295	struct resource *res;
 296	struct pci_dev_resource *dev_res;
 297	int idx;
 298
 299	list_for_each_entry(dev_res, head, list) {
 300		res = dev_res->res;
 301		idx = res - &dev_res->dev->resource[0];
 302		if (resource_size(res) &&
 303		    pci_assign_resource(dev_res->dev, idx)) {
 304			if (fail_head) {
 305				/*
 306				 * if the failed res is for ROM BAR, and it will
 307				 * be enabled later, don't add it to the list
 308				 */
 309				if (!((idx == PCI_ROM_RESOURCE) &&
 310				      (!(res->flags & IORESOURCE_ROM_ENABLE))))
 311					add_to_list(fail_head,
 312						    dev_res->dev, res,
 313						    0 /* don't care */,
 314						    0 /* don't care */);
 315			}
 316			reset_resource(res);
 317		}
 318	}
 319}
 320
 321static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
 322{
 323	struct pci_dev_resource *fail_res;
 324	unsigned long mask = 0;
 325
 326	/* check failed type */
 327	list_for_each_entry(fail_res, fail_head, list)
 328		mask |= fail_res->flags;
 329
 330	/*
 331	 * one pref failed resource will set IORESOURCE_MEM,
 332	 * as we can allocate pref in non-pref range.
 333	 * Will release all assigned non-pref sibling resources
 334	 * according to that bit.
 335	 */
 336	return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
 337}
 338
 339static bool pci_need_to_release(unsigned long mask, struct resource *res)
 340{
 341	if (res->flags & IORESOURCE_IO)
 342		return !!(mask & IORESOURCE_IO);
 343
 344	/* check pref at first */
 345	if (res->flags & IORESOURCE_PREFETCH) {
 346		if (mask & IORESOURCE_PREFETCH)
 347			return true;
 348		/* count pref if its parent is non-pref */
 349		else if ((mask & IORESOURCE_MEM) &&
 350			 !(res->parent->flags & IORESOURCE_PREFETCH))
 351			return true;
 352		else
 353			return false;
 354	}
 355
 356	if (res->flags & IORESOURCE_MEM)
 357		return !!(mask & IORESOURCE_MEM);
 358
 359	return false;	/* should not get here */
 360}
 361
 362static void __assign_resources_sorted(struct list_head *head,
 363				 struct list_head *realloc_head,
 364				 struct list_head *fail_head)
 365{
 366	/*
 367	 * Should not assign requested resources at first.
 368	 *   they could be adjacent, so later reassign can not reallocate
 369	 *   them one by one in parent resource window.
 370	 * Try to assign requested + add_size at beginning
 371	 *  if could do that, could get out early.
 372	 *  if could not do that, we still try to assign requested at first,
 373	 *    then try to reassign add_size for some resources.
 374	 *
 375	 * Separate three resource type checking if we need to release
 376	 * assigned resource after requested + add_size try.
 377	 *	1. if there is io port assign fail, will release assigned
 378	 *	   io port.
 379	 *	2. if there is pref mmio assign fail, release assigned
 380	 *	   pref mmio.
 381	 *	   if assigned pref mmio's parent is non-pref mmio and there
 382	 *	   is non-pref mmio assign fail, will release that assigned
 383	 *	   pref mmio.
 384	 *	3. if there is non-pref mmio assign fail or pref mmio
 385	 *	   assigned fail, will release assigned non-pref mmio.
 386	 */
 387	LIST_HEAD(save_head);
 388	LIST_HEAD(local_fail_head);
 389	struct pci_dev_resource *save_res;
 390	struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
 391	unsigned long fail_type;
 392	resource_size_t add_align, align;
 393
 394	/* Check if optional add_size is there */
 395	if (!realloc_head || list_empty(realloc_head))
 396		goto requested_and_reassign;
 397
 398	/* Save original start, end, flags etc at first */
 399	list_for_each_entry(dev_res, head, list) {
 400		if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
 401			free_list(&save_head);
 402			goto requested_and_reassign;
 403		}
 404	}
 405
 406	/* Update res in head list with add_size in realloc_head list */
 407	list_for_each_entry_safe(dev_res, tmp_res, head, list) {
 408		dev_res->res->end += get_res_add_size(realloc_head,
 409							dev_res->res);
 410
 411		/*
 412		 * There are two kinds of additional resources in the list:
 413		 * 1. bridge resource  -- IORESOURCE_STARTALIGN
 414		 * 2. SR-IOV resource   -- IORESOURCE_SIZEALIGN
 415		 * Here just fix the additional alignment for bridge
 416		 */
 417		if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
 418			continue;
 419
 420		add_align = get_res_add_align(realloc_head, dev_res->res);
 421
 422		/*
 423		 * The "head" list is sorted by the alignment to make sure
 424		 * resources with bigger alignment will be assigned first.
 425		 * After we change the alignment of a dev_res in "head" list,
 426		 * we need to reorder the list by alignment to make it
 427		 * consistent.
 428		 */
 429		if (add_align > dev_res->res->start) {
 430			resource_size_t r_size = resource_size(dev_res->res);
 431
 432			dev_res->res->start = add_align;
 433			dev_res->res->end = add_align + r_size - 1;
 434
 435			list_for_each_entry(dev_res2, head, list) {
 436				align = pci_resource_alignment(dev_res2->dev,
 437							       dev_res2->res);
 438				if (add_align > align) {
 439					list_move_tail(&dev_res->list,
 440						       &dev_res2->list);
 441					break;
 442				}
 443			}
 444		}
 445
 446	}
 447
 448	/* Try updated head list with add_size added */
 449	assign_requested_resources_sorted(head, &local_fail_head);
 450
 451	/* all assigned with add_size ? */
 452	if (list_empty(&local_fail_head)) {
 453		/* Remove head list from realloc_head list */
 454		list_for_each_entry(dev_res, head, list)
 455			remove_from_list(realloc_head, dev_res->res);
 456		free_list(&save_head);
 457		free_list(head);
 458		return;
 459	}
 460
 461	/* check failed type */
 462	fail_type = pci_fail_res_type_mask(&local_fail_head);
 463	/* remove not need to be released assigned res from head list etc */
 464	list_for_each_entry_safe(dev_res, tmp_res, head, list)
 465		if (dev_res->res->parent &&
 466		    !pci_need_to_release(fail_type, dev_res->res)) {
 467			/* remove it from realloc_head list */
 468			remove_from_list(realloc_head, dev_res->res);
 469			remove_from_list(&save_head, dev_res->res);
 470			list_del(&dev_res->list);
 471			kfree(dev_res);
 472		}
 473
 474	free_list(&local_fail_head);
 475	/* Release assigned resource */
 476	list_for_each_entry(dev_res, head, list)
 477		if (dev_res->res->parent)
 478			release_resource(dev_res->res);
 479	/* Restore start/end/flags from saved list */
 480	list_for_each_entry(save_res, &save_head, list) {
 481		struct resource *res = save_res->res;
 482
 483		res->start = save_res->start;
 484		res->end = save_res->end;
 485		res->flags = save_res->flags;
 486	}
 487	free_list(&save_head);
 488
 489requested_and_reassign:
 490	/* Satisfy the must-have resource requests */
 491	assign_requested_resources_sorted(head, fail_head);
 492
 493	/* Try to satisfy any additional optional resource
 494		requests */
 495	if (realloc_head)
 496		reassign_resources_sorted(realloc_head, head);
 497	free_list(head);
 498}
 499
 500static void pdev_assign_resources_sorted(struct pci_dev *dev,
 501				 struct list_head *add_head,
 502				 struct list_head *fail_head)
 503{
 504	LIST_HEAD(head);
 505
 506	__dev_sort_resources(dev, &head);
 507	__assign_resources_sorted(&head, add_head, fail_head);
 508
 509}
 510
 511static void pbus_assign_resources_sorted(const struct pci_bus *bus,
 512					 struct list_head *realloc_head,
 513					 struct list_head *fail_head)
 514{
 515	struct pci_dev *dev;
 516	LIST_HEAD(head);
 517
 518	list_for_each_entry(dev, &bus->devices, bus_list)
 519		__dev_sort_resources(dev, &head);
 520
 521	__assign_resources_sorted(&head, realloc_head, fail_head);
 522}
 523
 524void pci_setup_cardbus(struct pci_bus *bus)
 525{
 526	struct pci_dev *bridge = bus->self;
 527	struct resource *res;
 528	struct pci_bus_region region;
 529
 530	dev_info(&bridge->dev, "CardBus bridge to %pR\n",
 531		 &bus->busn_res);
 532
 533	res = bus->resource[0];
 534	pcibios_resource_to_bus(bridge->bus, &region, res);
 535	if (res->flags & IORESOURCE_IO) {
 536		/*
 537		 * The IO resource is allocated a range twice as large as it
 538		 * would normally need.  This allows us to set both IO regs.
 539		 */
 540		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 541		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
 542					region.start);
 543		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
 544					region.end);
 545	}
 546
 547	res = bus->resource[1];
 548	pcibios_resource_to_bus(bridge->bus, &region, res);
 549	if (res->flags & IORESOURCE_IO) {
 550		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 551		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
 552					region.start);
 553		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
 554					region.end);
 555	}
 556
 557	res = bus->resource[2];
 558	pcibios_resource_to_bus(bridge->bus, &region, res);
 559	if (res->flags & IORESOURCE_MEM) {
 560		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 561		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
 562					region.start);
 563		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
 564					region.end);
 565	}
 566
 567	res = bus->resource[3];
 568	pcibios_resource_to_bus(bridge->bus, &region, res);
 569	if (res->flags & IORESOURCE_MEM) {
 570		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 571		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
 572					region.start);
 573		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
 574					region.end);
 575	}
 576}
 577EXPORT_SYMBOL(pci_setup_cardbus);
 578
 579/* Initialize bridges with base/limit values we have collected.
 580   PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
 581   requires that if there is no I/O ports or memory behind the
 582   bridge, corresponding range must be turned off by writing base
 583   value greater than limit to the bridge's base/limit registers.
 584
 585   Note: care must be taken when updating I/O base/limit registers
 586   of bridges which support 32-bit I/O. This update requires two
 587   config space writes, so it's quite possible that an I/O window of
 588   the bridge will have some undesirable address (e.g. 0) after the
 589   first write. Ditto 64-bit prefetchable MMIO.  */
 590static void pci_setup_bridge_io(struct pci_dev *bridge)
 591{
 592	struct resource *res;
 593	struct pci_bus_region region;
 594	unsigned long io_mask;
 595	u8 io_base_lo, io_limit_lo;
 596	u16 l;
 597	u32 io_upper16;
 598
 599	io_mask = PCI_IO_RANGE_MASK;
 600	if (bridge->io_window_1k)
 601		io_mask = PCI_IO_1K_RANGE_MASK;
 602
 603	/* Set up the top and bottom of the PCI I/O segment for this bus. */
 604	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
 605	pcibios_resource_to_bus(bridge->bus, &region, res);
 606	if (res->flags & IORESOURCE_IO) {
 607		pci_read_config_word(bridge, PCI_IO_BASE, &l);
 608		io_base_lo = (region.start >> 8) & io_mask;
 609		io_limit_lo = (region.end >> 8) & io_mask;
 610		l = ((u16) io_limit_lo << 8) | io_base_lo;
 611		/* Set up upper 16 bits of I/O base/limit. */
 612		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
 613		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 614	} else {
 615		/* Clear upper 16 bits of I/O base/limit. */
 616		io_upper16 = 0;
 617		l = 0x00f0;
 618	}
 619	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
 620	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
 621	/* Update lower 16 bits of I/O base/limit. */
 622	pci_write_config_word(bridge, PCI_IO_BASE, l);
 623	/* Update upper 16 bits of I/O base/limit. */
 624	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
 625}
 626
 627static void pci_setup_bridge_mmio(struct pci_dev *bridge)
 628{
 629	struct resource *res;
 630	struct pci_bus_region region;
 631	u32 l;
 632
 633	/* Set up the top and bottom of the PCI Memory segment for this bus. */
 634	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
 635	pcibios_resource_to_bus(bridge->bus, &region, res);
 636	if (res->flags & IORESOURCE_MEM) {
 637		l = (region.start >> 16) & 0xfff0;
 638		l |= region.end & 0xfff00000;
 639		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 640	} else {
 641		l = 0x0000fff0;
 642	}
 643	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
 644}
 645
 646static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
 647{
 648	struct resource *res;
 649	struct pci_bus_region region;
 650	u32 l, bu, lu;
 651
 652	/* Clear out the upper 32 bits of PREF limit.
 653	   If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
 654	   disables PREF range, which is ok. */
 655	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
 656
 657	/* Set up PREF base/limit. */
 658	bu = lu = 0;
 659	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
 660	pcibios_resource_to_bus(bridge->bus, &region, res);
 661	if (res->flags & IORESOURCE_PREFETCH) {
 662		l = (region.start >> 16) & 0xfff0;
 663		l |= region.end & 0xfff00000;
 664		if (res->flags & IORESOURCE_MEM_64) {
 665			bu = upper_32_bits(region.start);
 666			lu = upper_32_bits(region.end);
 667		}
 668		dev_info(&bridge->dev, "  bridge window %pR\n", res);
 669	} else {
 670		l = 0x0000fff0;
 671	}
 672	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
 673
 674	/* Set the upper 32 bits of PREF base & limit. */
 675	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
 676	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
 677}
 678
 679static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
 680{
 681	struct pci_dev *bridge = bus->self;
 682
 683	dev_info(&bridge->dev, "PCI bridge to %pR\n",
 684		 &bus->busn_res);
 685
 686	if (type & IORESOURCE_IO)
 687		pci_setup_bridge_io(bridge);
 688
 689	if (type & IORESOURCE_MEM)
 690		pci_setup_bridge_mmio(bridge);
 691
 692	if (type & IORESOURCE_PREFETCH)
 693		pci_setup_bridge_mmio_pref(bridge);
 694
 695	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
 696}
 697
 
 
 
 
 698void pci_setup_bridge(struct pci_bus *bus)
 699{
 700	unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
 701				  IORESOURCE_PREFETCH;
 702
 
 703	__pci_setup_bridge(bus, type);
 704}
 705
 706
 707int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
 708{
 709	if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
 710		return 0;
 711
 712	if (pci_claim_resource(bridge, i) == 0)
 713		return 0;	/* claimed the window */
 714
 715	if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 716		return 0;
 717
 718	if (!pci_bus_clip_resource(bridge, i))
 719		return -EINVAL;	/* clipping didn't change anything */
 720
 721	switch (i - PCI_BRIDGE_RESOURCES) {
 722	case 0:
 723		pci_setup_bridge_io(bridge);
 724		break;
 725	case 1:
 726		pci_setup_bridge_mmio(bridge);
 727		break;
 728	case 2:
 729		pci_setup_bridge_mmio_pref(bridge);
 730		break;
 731	default:
 732		return -EINVAL;
 733	}
 734
 735	if (pci_claim_resource(bridge, i) == 0)
 736		return 0;	/* claimed a smaller window */
 737
 738	return -EINVAL;
 739}
 740
 741/* Check whether the bridge supports optional I/O and
 742   prefetchable memory ranges. If not, the respective
 743   base/limit registers must be read-only and read as 0. */
 744static void pci_bridge_check_ranges(struct pci_bus *bus)
 745{
 746	u16 io;
 747	u32 pmem;
 748	struct pci_dev *bridge = bus->self;
 749	struct resource *b_res;
 750
 751	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
 752	b_res[1].flags |= IORESOURCE_MEM;
 753
 754	pci_read_config_word(bridge, PCI_IO_BASE, &io);
 755	if (!io) {
 756		pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
 757		pci_read_config_word(bridge, PCI_IO_BASE, &io);
 758		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
 759	}
 760	if (io)
 761		b_res[0].flags |= IORESOURCE_IO;
 762
 763	/*  DECchip 21050 pass 2 errata: the bridge may miss an address
 764	    disconnect boundary by one PCI data phase.
 765	    Workaround: do not use prefetching on this device. */
 766	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
 767		return;
 768
 769	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 770	if (!pmem) {
 771		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
 772					       0xffe0fff0);
 773		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 774		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
 775	}
 776	if (pmem) {
 777		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
 778		if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
 779		    PCI_PREF_RANGE_TYPE_64) {
 780			b_res[2].flags |= IORESOURCE_MEM_64;
 781			b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
 782		}
 783	}
 784
 785	/* double check if bridge does support 64 bit pref */
 786	if (b_res[2].flags & IORESOURCE_MEM_64) {
 787		u32 mem_base_hi, tmp;
 788		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
 789					 &mem_base_hi);
 790		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
 791					       0xffffffff);
 792		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
 793		if (!tmp)
 794			b_res[2].flags &= ~IORESOURCE_MEM_64;
 795		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
 796				       mem_base_hi);
 797	}
 798}
 799
 800/* Helper function for sizing routines: find first available
 801   bus resource of a given type. Note: we intentionally skip
 802   the bus resources which have already been assigned (that is,
 803   have non-NULL parent resource). */
 804static struct resource *find_free_bus_resource(struct pci_bus *bus,
 805			 unsigned long type_mask, unsigned long type)
 806{
 807	int i;
 808	struct resource *r;
 809
 810	pci_bus_for_each_resource(bus, r, i) {
 811		if (r == &ioport_resource || r == &iomem_resource)
 812			continue;
 813		if (r && (r->flags & type_mask) == type && !r->parent)
 814			return r;
 815	}
 816	return NULL;
 817}
 818
 819static resource_size_t calculate_iosize(resource_size_t size,
 820		resource_size_t min_size,
 821		resource_size_t size1,
 822		resource_size_t old_size,
 823		resource_size_t align)
 824{
 825	if (size < min_size)
 826		size = min_size;
 827	if (old_size == 1)
 828		old_size = 0;
 829	/* To be fixed in 2.5: we should have sort of HAVE_ISA
 830	   flag in the struct pci_bus. */
 831#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
 832	size = (size & 0xff) + ((size & ~0xffUL) << 2);
 833#endif
 834	size = ALIGN(size + size1, align);
 835	if (size < old_size)
 836		size = old_size;
 837	return size;
 838}
 839
 840static resource_size_t calculate_memsize(resource_size_t size,
 841		resource_size_t min_size,
 842		resource_size_t size1,
 843		resource_size_t old_size,
 844		resource_size_t align)
 845{
 846	if (size < min_size)
 847		size = min_size;
 848	if (old_size == 1)
 849		old_size = 0;
 850	if (size < old_size)
 851		size = old_size;
 852	size = ALIGN(size + size1, align);
 853	return size;
 854}
 855
 856resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
 857						unsigned long type)
 858{
 859	return 1;
 860}
 861
 862#define PCI_P2P_DEFAULT_MEM_ALIGN	0x100000	/* 1MiB */
 863#define PCI_P2P_DEFAULT_IO_ALIGN	0x1000		/* 4KiB */
 864#define PCI_P2P_DEFAULT_IO_ALIGN_1K	0x400		/* 1KiB */
 865
 866static resource_size_t window_alignment(struct pci_bus *bus,
 867					unsigned long type)
 868{
 869	resource_size_t align = 1, arch_align;
 870
 871	if (type & IORESOURCE_MEM)
 872		align = PCI_P2P_DEFAULT_MEM_ALIGN;
 873	else if (type & IORESOURCE_IO) {
 874		/*
 875		 * Per spec, I/O windows are 4K-aligned, but some
 876		 * bridges have an extension to support 1K alignment.
 877		 */
 878		if (bus->self->io_window_1k)
 879			align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
 880		else
 881			align = PCI_P2P_DEFAULT_IO_ALIGN;
 882	}
 883
 884	arch_align = pcibios_window_alignment(bus, type);
 885	return max(align, arch_align);
 886}
 887
 888/**
 889 * pbus_size_io() - size the io window of a given bus
 890 *
 891 * @bus : the bus
 892 * @min_size : the minimum io window that must to be allocated
 893 * @add_size : additional optional io window
 894 * @realloc_head : track the additional io window on this list
 895 *
 896 * Sizing the IO windows of the PCI-PCI bridge is trivial,
 897 * since these windows have 1K or 4K granularity and the IO ranges
 898 * of non-bridge PCI devices are limited to 256 bytes.
 899 * We must be careful with the ISA aliasing though.
 900 */
 901static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
 902		resource_size_t add_size, struct list_head *realloc_head)
 903{
 904	struct pci_dev *dev;
 905	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
 906							IORESOURCE_IO);
 907	resource_size_t size = 0, size0 = 0, size1 = 0;
 908	resource_size_t children_add_size = 0;
 909	resource_size_t min_align, align;
 910
 911	if (!b_res)
 912		return;
 913
 914	min_align = window_alignment(bus, IORESOURCE_IO);
 915	list_for_each_entry(dev, &bus->devices, bus_list) {
 916		int i;
 917
 918		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 919			struct resource *r = &dev->resource[i];
 920			unsigned long r_size;
 921
 922			if (r->parent || !(r->flags & IORESOURCE_IO))
 923				continue;
 924			r_size = resource_size(r);
 925
 926			if (r_size < 0x400)
 927				/* Might be re-aligned for ISA */
 928				size += r_size;
 929			else
 930				size1 += r_size;
 931
 932			align = pci_resource_alignment(dev, r);
 933			if (align > min_align)
 934				min_align = align;
 935
 936			if (realloc_head)
 937				children_add_size += get_res_add_size(realloc_head, r);
 938		}
 939	}
 940
 941	size0 = calculate_iosize(size, min_size, size1,
 942			resource_size(b_res), min_align);
 943	if (children_add_size > add_size)
 944		add_size = children_add_size;
 945	size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
 946		calculate_iosize(size, min_size, add_size + size1,
 947			resource_size(b_res), min_align);
 948	if (!size0 && !size1) {
 949		if (b_res->start || b_res->end)
 950			dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
 951				 b_res, &bus->busn_res);
 952		b_res->flags = 0;
 953		return;
 954	}
 955
 956	b_res->start = min_align;
 957	b_res->end = b_res->start + size0 - 1;
 958	b_res->flags |= IORESOURCE_STARTALIGN;
 959	if (size1 > size0 && realloc_head) {
 960		add_to_list(realloc_head, bus->self, b_res, size1-size0,
 961			    min_align);
 962		dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n",
 963			   b_res, &bus->busn_res,
 964			   (unsigned long long)size1-size0);
 965	}
 966}
 967
 968static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
 969						  int max_order)
 970{
 971	resource_size_t align = 0;
 972	resource_size_t min_align = 0;
 973	int order;
 974
 975	for (order = 0; order <= max_order; order++) {
 976		resource_size_t align1 = 1;
 977
 978		align1 <<= (order + 20);
 979
 980		if (!align)
 981			min_align = align1;
 982		else if (ALIGN(align + min_align, min_align) < align1)
 983			min_align = align1 >> 1;
 984		align += aligns[order];
 985	}
 986
 987	return min_align;
 988}
 989
 990/**
 991 * pbus_size_mem() - size the memory window of a given bus
 992 *
 993 * @bus : the bus
 994 * @mask: mask the resource flag, then compare it with type
 995 * @type: the type of free resource from bridge
 996 * @type2: second match type
 997 * @type3: third match type
 998 * @min_size : the minimum memory window that must to be allocated
 999 * @add_size : additional optional memory window
1000 * @realloc_head : track the additional memory window on this list
1001 *
1002 * Calculate the size of the bus and minimal alignment which
1003 * guarantees that all child resources fit in this size.
1004 *
1005 * Returns -ENOSPC if there's no available bus resource of the desired type.
1006 * Otherwise, sets the bus resource start/end to indicate the required
1007 * size, adds things to realloc_head (if supplied), and returns 0.
1008 */
1009static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1010			 unsigned long type, unsigned long type2,
1011			 unsigned long type3,
1012			 resource_size_t min_size, resource_size_t add_size,
1013			 struct list_head *realloc_head)
1014{
1015	struct pci_dev *dev;
1016	resource_size_t min_align, align, size, size0, size1;
1017	resource_size_t aligns[18];	/* Alignments from 1Mb to 128Gb */
1018	int order, max_order;
1019	struct resource *b_res = find_free_bus_resource(bus,
1020					mask | IORESOURCE_PREFETCH, type);
1021	resource_size_t children_add_size = 0;
1022	resource_size_t children_add_align = 0;
1023	resource_size_t add_align = 0;
1024
1025	if (!b_res)
1026		return -ENOSPC;
1027
1028	memset(aligns, 0, sizeof(aligns));
1029	max_order = 0;
1030	size = 0;
1031
1032	list_for_each_entry(dev, &bus->devices, bus_list) {
1033		int i;
1034
1035		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1036			struct resource *r = &dev->resource[i];
1037			resource_size_t r_size;
1038
1039			if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1040			    ((r->flags & mask) != type &&
1041			     (r->flags & mask) != type2 &&
1042			     (r->flags & mask) != type3))
1043				continue;
1044			r_size = resource_size(r);
1045#ifdef CONFIG_PCI_IOV
1046			/* put SRIOV requested res to the optional list */
1047			if (realloc_head && i >= PCI_IOV_RESOURCES &&
1048					i <= PCI_IOV_RESOURCE_END) {
1049				add_align = max(pci_resource_alignment(dev, r), add_align);
1050				r->end = r->start - 1;
1051				add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
1052				children_add_size += r_size;
1053				continue;
1054			}
1055#endif
1056			/*
1057			 * aligns[0] is for 1MB (since bridge memory
1058			 * windows are always at least 1MB aligned), so
1059			 * keep "order" from being negative for smaller
1060			 * resources.
1061			 */
1062			align = pci_resource_alignment(dev, r);
1063			order = __ffs(align) - 20;
1064			if (order < 0)
1065				order = 0;
1066			if (order >= ARRAY_SIZE(aligns)) {
1067				dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1068					 i, r, (unsigned long long) align);
1069				r->flags = 0;
1070				continue;
1071			}
1072			size += r_size;
1073			/* Exclude ranges with size > align from
1074			   calculation of the alignment. */
1075			if (r_size == align)
1076				aligns[order] += align;
1077			if (order > max_order)
1078				max_order = order;
1079
1080			if (realloc_head) {
1081				children_add_size += get_res_add_size(realloc_head, r);
1082				children_add_align = get_res_add_align(realloc_head, r);
1083				add_align = max(add_align, children_add_align);
1084			}
1085		}
1086	}
1087
1088	min_align = calculate_mem_align(aligns, max_order);
1089	min_align = max(min_align, window_alignment(bus, b_res->flags));
1090	size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
1091	add_align = max(min_align, add_align);
1092	if (children_add_size > add_size)
1093		add_size = children_add_size;
1094	size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
1095		calculate_memsize(size, min_size, add_size,
1096				resource_size(b_res), add_align);
1097	if (!size0 && !size1) {
1098		if (b_res->start || b_res->end)
1099			dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
1100				 b_res, &bus->busn_res);
1101		b_res->flags = 0;
1102		return 0;
1103	}
1104	b_res->start = min_align;
1105	b_res->end = size0 + min_align - 1;
1106	b_res->flags |= IORESOURCE_STARTALIGN;
1107	if (size1 > size0 && realloc_head) {
1108		add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1109		dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1110			   b_res, &bus->busn_res,
1111			   (unsigned long long) (size1 - size0),
1112			   (unsigned long long) add_align);
1113	}
1114	return 0;
1115}
1116
1117unsigned long pci_cardbus_resource_alignment(struct resource *res)
1118{
1119	if (res->flags & IORESOURCE_IO)
1120		return pci_cardbus_io_size;
1121	if (res->flags & IORESOURCE_MEM)
1122		return pci_cardbus_mem_size;
1123	return 0;
1124}
1125
1126static void pci_bus_size_cardbus(struct pci_bus *bus,
1127			struct list_head *realloc_head)
1128{
1129	struct pci_dev *bridge = bus->self;
1130	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1131	resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1132	u16 ctrl;
1133
1134	if (b_res[0].parent)
1135		goto handle_b_res_1;
1136	/*
1137	 * Reserve some resources for CardBus.  We reserve
1138	 * a fixed amount of bus space for CardBus bridges.
1139	 */
1140	b_res[0].start = pci_cardbus_io_size;
1141	b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1142	b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1143	if (realloc_head) {
1144		b_res[0].end -= pci_cardbus_io_size;
1145		add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1146				pci_cardbus_io_size);
1147	}
1148
1149handle_b_res_1:
1150	if (b_res[1].parent)
1151		goto handle_b_res_2;
1152	b_res[1].start = pci_cardbus_io_size;
1153	b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1154	b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1155	if (realloc_head) {
1156		b_res[1].end -= pci_cardbus_io_size;
1157		add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1158				 pci_cardbus_io_size);
1159	}
1160
1161handle_b_res_2:
1162	/* MEM1 must not be pref mmio */
1163	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1164	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1165		ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1166		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1167		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1168	}
1169
1170	/*
1171	 * Check whether prefetchable memory is supported
1172	 * by this bridge.
1173	 */
1174	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1175	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1176		ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1177		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1178		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1179	}
1180
1181	if (b_res[2].parent)
1182		goto handle_b_res_3;
1183	/*
1184	 * If we have prefetchable memory support, allocate
1185	 * two regions.  Otherwise, allocate one region of
1186	 * twice the size.
1187	 */
1188	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1189		b_res[2].start = pci_cardbus_mem_size;
1190		b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1191		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1192				  IORESOURCE_STARTALIGN;
1193		if (realloc_head) {
1194			b_res[2].end -= pci_cardbus_mem_size;
1195			add_to_list(realloc_head, bridge, b_res+2,
1196				 pci_cardbus_mem_size, pci_cardbus_mem_size);
1197		}
1198
1199		/* reduce that to half */
1200		b_res_3_size = pci_cardbus_mem_size;
1201	}
1202
1203handle_b_res_3:
1204	if (b_res[3].parent)
1205		goto handle_done;
1206	b_res[3].start = pci_cardbus_mem_size;
1207	b_res[3].end = b_res[3].start + b_res_3_size - 1;
1208	b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1209	if (realloc_head) {
1210		b_res[3].end -= b_res_3_size;
1211		add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1212				 pci_cardbus_mem_size);
1213	}
1214
1215handle_done:
1216	;
1217}
1218
1219void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1220{
1221	struct pci_dev *dev;
1222	unsigned long mask, prefmask, type2 = 0, type3 = 0;
1223	resource_size_t additional_mem_size = 0, additional_io_size = 0;
1224	struct resource *b_res;
1225	int ret;
1226
1227	list_for_each_entry(dev, &bus->devices, bus_list) {
1228		struct pci_bus *b = dev->subordinate;
1229		if (!b)
1230			continue;
1231
1232		switch (dev->class >> 8) {
1233		case PCI_CLASS_BRIDGE_CARDBUS:
1234			pci_bus_size_cardbus(b, realloc_head);
1235			break;
1236
1237		case PCI_CLASS_BRIDGE_PCI:
1238		default:
1239			__pci_bus_size_bridges(b, realloc_head);
1240			break;
1241		}
1242	}
1243
1244	/* The root bus? */
1245	if (pci_is_root_bus(bus))
1246		return;
1247
1248	switch (bus->self->class >> 8) {
1249	case PCI_CLASS_BRIDGE_CARDBUS:
1250		/* don't size cardbuses yet. */
1251		break;
1252
1253	case PCI_CLASS_BRIDGE_PCI:
1254		pci_bridge_check_ranges(bus);
1255		if (bus->self->is_hotplug_bridge) {
1256			additional_io_size  = pci_hotplug_io_size;
1257			additional_mem_size = pci_hotplug_mem_size;
1258		}
1259		/* Fall through */
1260	default:
1261		pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1262			     additional_io_size, realloc_head);
1263
1264		/*
1265		 * If there's a 64-bit prefetchable MMIO window, compute
1266		 * the size required to put all 64-bit prefetchable
1267		 * resources in it.
1268		 */
1269		b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1270		mask = IORESOURCE_MEM;
1271		prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1272		if (b_res[2].flags & IORESOURCE_MEM_64) {
1273			prefmask |= IORESOURCE_MEM_64;
1274			ret = pbus_size_mem(bus, prefmask, prefmask,
1275				  prefmask, prefmask,
1276				  realloc_head ? 0 : additional_mem_size,
1277				  additional_mem_size, realloc_head);
1278
1279			/*
1280			 * If successful, all non-prefetchable resources
1281			 * and any 32-bit prefetchable resources will go in
1282			 * the non-prefetchable window.
1283			 */
1284			if (ret == 0) {
1285				mask = prefmask;
1286				type2 = prefmask & ~IORESOURCE_MEM_64;
1287				type3 = prefmask & ~IORESOURCE_PREFETCH;
1288			}
1289		}
1290
1291		/*
1292		 * If there is no 64-bit prefetchable window, compute the
1293		 * size required to put all prefetchable resources in the
1294		 * 32-bit prefetchable window (if there is one).
1295		 */
1296		if (!type2) {
1297			prefmask &= ~IORESOURCE_MEM_64;
1298			ret = pbus_size_mem(bus, prefmask, prefmask,
1299					 prefmask, prefmask,
1300					 realloc_head ? 0 : additional_mem_size,
1301					 additional_mem_size, realloc_head);
1302
1303			/*
1304			 * If successful, only non-prefetchable resources
1305			 * will go in the non-prefetchable window.
1306			 */
1307			if (ret == 0)
1308				mask = prefmask;
1309			else
1310				additional_mem_size += additional_mem_size;
1311
1312			type2 = type3 = IORESOURCE_MEM;
1313		}
1314
1315		/*
1316		 * Compute the size required to put everything else in the
1317		 * non-prefetchable window.  This includes:
1318		 *
1319		 *   - all non-prefetchable resources
1320		 *   - 32-bit prefetchable resources if there's a 64-bit
1321		 *     prefetchable window or no prefetchable window at all
1322		 *   - 64-bit prefetchable resources if there's no
1323		 *     prefetchable window at all
1324		 *
1325		 * Note that the strategy in __pci_assign_resource() must
1326		 * match that used here.  Specifically, we cannot put a
1327		 * 32-bit prefetchable resource in a 64-bit prefetchable
1328		 * window.
1329		 */
1330		pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1331				realloc_head ? 0 : additional_mem_size,
1332				additional_mem_size, realloc_head);
1333		break;
1334	}
1335}
1336
1337void pci_bus_size_bridges(struct pci_bus *bus)
1338{
1339	__pci_bus_size_bridges(bus, NULL);
1340}
1341EXPORT_SYMBOL(pci_bus_size_bridges);
1342
1343static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1344{
1345	int i;
1346	struct resource *parent_r;
1347	unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1348			     IORESOURCE_PREFETCH;
1349
1350	pci_bus_for_each_resource(b, parent_r, i) {
1351		if (!parent_r)
1352			continue;
1353
1354		if ((r->flags & mask) == (parent_r->flags & mask) &&
1355		    resource_contains(parent_r, r))
1356			request_resource(parent_r, r);
1357	}
1358}
1359
1360/*
1361 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they
1362 * are skipped by pbus_assign_resources_sorted().
1363 */
1364static void pdev_assign_fixed_resources(struct pci_dev *dev)
1365{
1366	int i;
1367
1368	for (i = 0; i <  PCI_NUM_RESOURCES; i++) {
1369		struct pci_bus *b;
1370		struct resource *r = &dev->resource[i];
1371
1372		if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1373		    !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1374			continue;
1375
1376		b = dev->bus;
1377		while (b && !r->parent) {
1378			assign_fixed_resource_on_bus(b, r);
1379			b = b->parent;
1380		}
1381	}
1382}
1383
1384void __pci_bus_assign_resources(const struct pci_bus *bus,
1385				struct list_head *realloc_head,
1386				struct list_head *fail_head)
1387{
1388	struct pci_bus *b;
1389	struct pci_dev *dev;
1390
1391	pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1392
1393	list_for_each_entry(dev, &bus->devices, bus_list) {
1394		pdev_assign_fixed_resources(dev);
1395
1396		b = dev->subordinate;
1397		if (!b)
1398			continue;
1399
1400		__pci_bus_assign_resources(b, realloc_head, fail_head);
1401
1402		switch (dev->class >> 8) {
1403		case PCI_CLASS_BRIDGE_PCI:
1404			if (!pci_is_enabled(dev))
1405				pci_setup_bridge(b);
1406			break;
1407
1408		case PCI_CLASS_BRIDGE_CARDBUS:
1409			pci_setup_cardbus(b);
1410			break;
1411
1412		default:
1413			dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n",
1414				 pci_domain_nr(b), b->number);
1415			break;
1416		}
1417	}
1418}
1419
1420void pci_bus_assign_resources(const struct pci_bus *bus)
1421{
1422	__pci_bus_assign_resources(bus, NULL, NULL);
1423}
1424EXPORT_SYMBOL(pci_bus_assign_resources);
1425
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1426static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1427					  struct list_head *add_head,
1428					  struct list_head *fail_head)
1429{
1430	struct pci_bus *b;
1431
1432	pdev_assign_resources_sorted((struct pci_dev *)bridge,
1433					 add_head, fail_head);
1434
1435	b = bridge->subordinate;
1436	if (!b)
1437		return;
1438
1439	__pci_bus_assign_resources(b, add_head, fail_head);
1440
1441	switch (bridge->class >> 8) {
1442	case PCI_CLASS_BRIDGE_PCI:
1443		pci_setup_bridge(b);
1444		break;
1445
1446	case PCI_CLASS_BRIDGE_CARDBUS:
1447		pci_setup_cardbus(b);
1448		break;
1449
1450	default:
1451		dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n",
1452			 pci_domain_nr(b), b->number);
1453		break;
1454	}
1455}
1456static void pci_bridge_release_resources(struct pci_bus *bus,
1457					  unsigned long type)
1458{
1459	struct pci_dev *dev = bus->self;
1460	struct resource *r;
1461	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1462				  IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1463	unsigned old_flags = 0;
1464	struct resource *b_res;
1465	int idx = 1;
1466
1467	b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1468
1469	/*
1470	 *     1. if there is io port assign fail, will release bridge
1471	 *	  io port.
1472	 *     2. if there is non pref mmio assign fail, release bridge
1473	 *	  nonpref mmio.
1474	 *     3. if there is 64bit pref mmio assign fail, and bridge pref
1475	 *	  is 64bit, release bridge pref mmio.
1476	 *     4. if there is pref mmio assign fail, and bridge pref is
1477	 *	  32bit mmio, release bridge pref mmio
1478	 *     5. if there is pref mmio assign fail, and bridge pref is not
1479	 *	  assigned, release bridge nonpref mmio.
1480	 */
1481	if (type & IORESOURCE_IO)
1482		idx = 0;
1483	else if (!(type & IORESOURCE_PREFETCH))
1484		idx = 1;
1485	else if ((type & IORESOURCE_MEM_64) &&
1486		 (b_res[2].flags & IORESOURCE_MEM_64))
1487		idx = 2;
1488	else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1489		 (b_res[2].flags & IORESOURCE_PREFETCH))
1490		idx = 2;
1491	else
1492		idx = 1;
1493
1494	r = &b_res[idx];
1495
1496	if (!r->parent)
1497		return;
1498
1499	/*
1500	 * if there are children under that, we should release them
1501	 *  all
1502	 */
1503	release_child_resources(r);
1504	if (!release_resource(r)) {
1505		type = old_flags = r->flags & type_mask;
1506		dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
1507					PCI_BRIDGE_RESOURCES + idx, r);
1508		/* keep the old size */
1509		r->end = resource_size(r) - 1;
1510		r->start = 0;
1511		r->flags = 0;
1512
1513		/* avoiding touch the one without PREF */
1514		if (type & IORESOURCE_PREFETCH)
1515			type = IORESOURCE_PREFETCH;
1516		__pci_setup_bridge(bus, type);
1517		/* for next child res under same bridge */
1518		r->flags = old_flags;
1519	}
1520}
1521
1522enum release_type {
1523	leaf_only,
1524	whole_subtree,
1525};
1526/*
1527 * try to release pci bridge resources that is from leaf bridge,
1528 * so we can allocate big new one later
1529 */
1530static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1531					     unsigned long type,
1532					     enum release_type rel_type)
1533{
1534	struct pci_dev *dev;
1535	bool is_leaf_bridge = true;
1536
1537	list_for_each_entry(dev, &bus->devices, bus_list) {
1538		struct pci_bus *b = dev->subordinate;
1539		if (!b)
1540			continue;
1541
1542		is_leaf_bridge = false;
1543
1544		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1545			continue;
1546
1547		if (rel_type == whole_subtree)
1548			pci_bus_release_bridge_resources(b, type,
1549						 whole_subtree);
1550	}
1551
1552	if (pci_is_root_bus(bus))
1553		return;
1554
1555	if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1556		return;
1557
1558	if ((rel_type == whole_subtree) || is_leaf_bridge)
1559		pci_bridge_release_resources(bus, type);
1560}
1561
1562static void pci_bus_dump_res(struct pci_bus *bus)
1563{
1564	struct resource *res;
1565	int i;
1566
1567	pci_bus_for_each_resource(bus, res, i) {
1568		if (!res || !res->end || !res->flags)
1569			continue;
1570
1571		dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1572	}
1573}
1574
1575static void pci_bus_dump_resources(struct pci_bus *bus)
1576{
1577	struct pci_bus *b;
1578	struct pci_dev *dev;
1579
1580
1581	pci_bus_dump_res(bus);
1582
1583	list_for_each_entry(dev, &bus->devices, bus_list) {
1584		b = dev->subordinate;
1585		if (!b)
1586			continue;
1587
1588		pci_bus_dump_resources(b);
1589	}
1590}
1591
1592static int pci_bus_get_depth(struct pci_bus *bus)
1593{
1594	int depth = 0;
1595	struct pci_bus *child_bus;
1596
1597	list_for_each_entry(child_bus, &bus->children, node) {
1598		int ret;
1599
1600		ret = pci_bus_get_depth(child_bus);
1601		if (ret + 1 > depth)
1602			depth = ret + 1;
1603	}
1604
1605	return depth;
1606}
1607
1608/*
1609 * -1: undefined, will auto detect later
1610 *  0: disabled by user
1611 *  1: disabled by auto detect
1612 *  2: enabled by user
1613 *  3: enabled by auto detect
1614 */
1615enum enable_type {
1616	undefined = -1,
1617	user_disabled,
1618	auto_disabled,
1619	user_enabled,
1620	auto_enabled,
1621};
1622
1623static enum enable_type pci_realloc_enable = undefined;
1624void __init pci_realloc_get_opt(char *str)
1625{
1626	if (!strncmp(str, "off", 3))
1627		pci_realloc_enable = user_disabled;
1628	else if (!strncmp(str, "on", 2))
1629		pci_realloc_enable = user_enabled;
1630}
1631static bool pci_realloc_enabled(enum enable_type enable)
1632{
1633	return enable >= user_enabled;
1634}
1635
1636#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1637static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1638{
1639	int i;
1640	bool *unassigned = data;
1641
1642	for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1643		struct resource *r = &dev->resource[i];
1644		struct pci_bus_region region;
1645
1646		/* Not assigned or rejected by kernel? */
1647		if (!r->flags)
1648			continue;
1649
1650		pcibios_resource_to_bus(dev->bus, &region, r);
1651		if (!region.start) {
1652			*unassigned = true;
1653			return 1; /* return early from pci_walk_bus() */
1654		}
1655	}
1656
1657	return 0;
1658}
1659
1660static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1661			 enum enable_type enable_local)
1662{
1663	bool unassigned = false;
1664
1665	if (enable_local != undefined)
1666		return enable_local;
1667
1668	pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1669	if (unassigned)
1670		return auto_enabled;
1671
1672	return enable_local;
1673}
1674#else
1675static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1676			 enum enable_type enable_local)
1677{
1678	return enable_local;
1679}
1680#endif
1681
1682/*
1683 * first try will not touch pci bridge res
1684 * second and later try will clear small leaf bridge res
1685 * will stop till to the max depth if can not find good one
1686 */
1687void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1688{
1689	LIST_HEAD(realloc_head); /* list of resources that
1690					want additional resources */
1691	struct list_head *add_list = NULL;
1692	int tried_times = 0;
1693	enum release_type rel_type = leaf_only;
1694	LIST_HEAD(fail_head);
1695	struct pci_dev_resource *fail_res;
1696	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1697				  IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1698	int pci_try_num = 1;
1699	enum enable_type enable_local;
1700
1701	/* don't realloc if asked to do so */
1702	enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1703	if (pci_realloc_enabled(enable_local)) {
1704		int max_depth = pci_bus_get_depth(bus);
1705
1706		pci_try_num = max_depth + 1;
1707		dev_printk(KERN_DEBUG, &bus->dev,
1708			   "max bus depth: %d pci_try_num: %d\n",
1709			   max_depth, pci_try_num);
1710	}
1711
1712again:
1713	/*
1714	 * last try will use add_list, otherwise will try good to have as
1715	 * must have, so can realloc parent bridge resource
1716	 */
1717	if (tried_times + 1 == pci_try_num)
1718		add_list = &realloc_head;
1719	/* Depth first, calculate sizes and alignments of all
1720	   subordinate buses. */
1721	__pci_bus_size_bridges(bus, add_list);
1722
1723	/* Depth last, allocate resources and update the hardware. */
1724	__pci_bus_assign_resources(bus, add_list, &fail_head);
1725	if (add_list)
1726		BUG_ON(!list_empty(add_list));
1727	tried_times++;
1728
1729	/* any device complain? */
1730	if (list_empty(&fail_head))
1731		goto dump;
1732
1733	if (tried_times >= pci_try_num) {
1734		if (enable_local == undefined)
1735			dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1736		else if (enable_local == auto_enabled)
1737			dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1738
1739		free_list(&fail_head);
1740		goto dump;
1741	}
1742
1743	dev_printk(KERN_DEBUG, &bus->dev,
1744		   "No. %d try to assign unassigned res\n", tried_times + 1);
1745
1746	/* third times and later will not check if it is leaf */
1747	if ((tried_times + 1) > 2)
1748		rel_type = whole_subtree;
1749
1750	/*
1751	 * Try to release leaf bridge's resources that doesn't fit resource of
1752	 * child device under that bridge
1753	 */
1754	list_for_each_entry(fail_res, &fail_head, list)
1755		pci_bus_release_bridge_resources(fail_res->dev->bus,
1756						 fail_res->flags & type_mask,
1757						 rel_type);
1758
1759	/* restore size and flags */
1760	list_for_each_entry(fail_res, &fail_head, list) {
1761		struct resource *res = fail_res->res;
1762
1763		res->start = fail_res->start;
1764		res->end = fail_res->end;
1765		res->flags = fail_res->flags;
1766		if (fail_res->dev->subordinate)
1767			res->flags = 0;
1768	}
1769	free_list(&fail_head);
1770
1771	goto again;
1772
1773dump:
1774	/* dump the resource on buses */
1775	pci_bus_dump_resources(bus);
1776}
1777
1778void __init pci_assign_unassigned_resources(void)
1779{
1780	struct pci_bus *root_bus;
1781
1782	list_for_each_entry(root_bus, &pci_root_buses, node)
1783		pci_assign_unassigned_root_bus_resources(root_bus);
 
 
 
 
 
1784}
1785
1786void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1787{
1788	struct pci_bus *parent = bridge->subordinate;
1789	LIST_HEAD(add_list); /* list of resources that
1790					want additional resources */
1791	int tried_times = 0;
1792	LIST_HEAD(fail_head);
1793	struct pci_dev_resource *fail_res;
1794	int retval;
1795	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1796				  IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1797
1798again:
1799	__pci_bus_size_bridges(parent, &add_list);
1800	__pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1801	BUG_ON(!list_empty(&add_list));
1802	tried_times++;
1803
1804	if (list_empty(&fail_head))
1805		goto enable_all;
1806
1807	if (tried_times >= 2) {
1808		/* still fail, don't need to try more */
1809		free_list(&fail_head);
1810		goto enable_all;
1811	}
1812
1813	printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1814			 tried_times + 1);
1815
1816	/*
1817	 * Try to release leaf bridge's resources that doesn't fit resource of
1818	 * child device under that bridge
1819	 */
1820	list_for_each_entry(fail_res, &fail_head, list)
1821		pci_bus_release_bridge_resources(fail_res->dev->bus,
1822						 fail_res->flags & type_mask,
1823						 whole_subtree);
1824
1825	/* restore size and flags */
1826	list_for_each_entry(fail_res, &fail_head, list) {
1827		struct resource *res = fail_res->res;
1828
1829		res->start = fail_res->start;
1830		res->end = fail_res->end;
1831		res->flags = fail_res->flags;
1832		if (fail_res->dev->subordinate)
1833			res->flags = 0;
1834	}
1835	free_list(&fail_head);
1836
1837	goto again;
1838
1839enable_all:
1840	retval = pci_reenable_device(bridge);
1841	if (retval)
1842		dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
1843	pci_set_master(bridge);
1844}
1845EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1846
1847void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
1848{
1849	struct pci_dev *dev;
1850	LIST_HEAD(add_list); /* list of resources that
1851					want additional resources */
1852
1853	down_read(&pci_bus_sem);
1854	list_for_each_entry(dev, &bus->devices, bus_list)
1855		if (pci_is_bridge(dev) && pci_has_subordinate(dev))
1856				__pci_bus_size_bridges(dev->subordinate,
1857							 &add_list);
1858	up_read(&pci_bus_sem);
1859	__pci_bus_assign_resources(bus, &add_list, NULL);
1860	BUG_ON(!list_empty(&add_list));
1861}
1862EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);