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1#ifndef DRIVERS_PCI_H
2#define DRIVERS_PCI_H
3
4#define PCI_CFG_SPACE_SIZE 256
5#define PCI_CFG_SPACE_EXP_SIZE 4096
6
7#define PCI_FIND_CAP_TTL 48
8
9extern const unsigned char pcie_link_speed[];
10
11bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
12
13/* Functions internal to the PCI core code */
14
15int pci_create_sysfs_dev_files(struct pci_dev *pdev);
16void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
17#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
18static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
19{ return; }
20static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
21{ return; }
22#else
23void pci_create_firmware_label_files(struct pci_dev *pdev);
24void pci_remove_firmware_label_files(struct pci_dev *pdev);
25#endif
26void pci_cleanup_rom(struct pci_dev *dev);
27#ifdef HAVE_PCI_MMAP
28enum pci_mmap_api {
29 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
30 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
31};
32int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
33 enum pci_mmap_api mmap_api);
34#endif
35int pci_probe_reset_function(struct pci_dev *dev);
36
37/**
38 * struct pci_platform_pm_ops - Firmware PM callbacks
39 *
40 * @is_manageable: returns 'true' if given device is power manageable by the
41 * platform firmware
42 *
43 * @set_state: invokes the platform firmware to set the device's power state
44 *
45 * @choose_state: returns PCI power state of given device preferred by the
46 * platform; to be used during system-wide transitions from a
47 * sleeping state to the working state and vice versa
48 *
49 * @sleep_wake: enables/disables the system wake up capability of given device
50 *
51 * @run_wake: enables/disables the platform to generate run-time wake-up events
52 * for given device (the device's wake-up capability has to be
53 * enabled by @sleep_wake for this feature to work)
54 *
55 * @need_resume: returns 'true' if the given device (which is currently
56 * suspended) needs to be resumed to be configured for system
57 * wakeup.
58 *
59 * If given platform is generally capable of power managing PCI devices, all of
60 * these callbacks are mandatory.
61 */
62struct pci_platform_pm_ops {
63 bool (*is_manageable)(struct pci_dev *dev);
64 int (*set_state)(struct pci_dev *dev, pci_power_t state);
65 pci_power_t (*choose_state)(struct pci_dev *dev);
66 int (*sleep_wake)(struct pci_dev *dev, bool enable);
67 int (*run_wake)(struct pci_dev *dev, bool enable);
68 bool (*need_resume)(struct pci_dev *dev);
69};
70
71int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
72void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
73void pci_power_up(struct pci_dev *dev);
74void pci_disable_enabled_device(struct pci_dev *dev);
75int pci_finish_runtime_suspend(struct pci_dev *dev);
76int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
77bool pci_dev_keep_suspended(struct pci_dev *dev);
78void pci_dev_complete_resume(struct pci_dev *pci_dev);
79void pci_config_pm_runtime_get(struct pci_dev *dev);
80void pci_config_pm_runtime_put(struct pci_dev *dev);
81void pci_pm_init(struct pci_dev *dev);
82void pci_ea_init(struct pci_dev *dev);
83void pci_allocate_cap_save_buffers(struct pci_dev *dev);
84void pci_free_cap_save_buffers(struct pci_dev *dev);
85
86static inline void pci_wakeup_event(struct pci_dev *dev)
87{
88 /* Wait 100 ms before the system can be put into a sleep state. */
89 pm_wakeup_event(&dev->dev, 100);
90}
91
92static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
93{
94 return !!(pci_dev->subordinate);
95}
96
97struct pci_vpd_ops {
98 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
99 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
100 int (*set_size)(struct pci_dev *dev, size_t len);
101};
102
103struct pci_vpd {
104 const struct pci_vpd_ops *ops;
105 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
106 struct mutex lock;
107 unsigned int len;
108 u16 flag;
109 u8 cap;
110 u8 busy:1;
111 u8 valid:1;
112};
113
114int pci_vpd_init(struct pci_dev *dev);
115void pci_vpd_release(struct pci_dev *dev);
116
117/* PCI /proc functions */
118#ifdef CONFIG_PROC_FS
119int pci_proc_attach_device(struct pci_dev *dev);
120int pci_proc_detach_device(struct pci_dev *dev);
121int pci_proc_detach_bus(struct pci_bus *bus);
122#else
123static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
124static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
125static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
126#endif
127
128/* Functions for PCI Hotplug drivers to use */
129int pci_hp_add_bridge(struct pci_dev *dev);
130
131#ifdef HAVE_PCI_LEGACY
132void pci_create_legacy_files(struct pci_bus *bus);
133void pci_remove_legacy_files(struct pci_bus *bus);
134#else
135static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
136static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
137#endif
138
139/* Lock for read/write access to pci device and bus lists */
140extern struct rw_semaphore pci_bus_sem;
141
142extern raw_spinlock_t pci_lock;
143
144extern unsigned int pci_pm_d3_delay;
145
146#ifdef CONFIG_PCI_MSI
147void pci_no_msi(void);
148#else
149static inline void pci_no_msi(void) { }
150#endif
151
152static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
153{
154 u16 control;
155
156 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
157 control &= ~PCI_MSI_FLAGS_ENABLE;
158 if (enable)
159 control |= PCI_MSI_FLAGS_ENABLE;
160 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
161}
162
163static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
164{
165 u16 ctrl;
166
167 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
168 ctrl &= ~clear;
169 ctrl |= set;
170 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
171}
172
173void pci_realloc_get_opt(char *);
174
175static inline int pci_no_d1d2(struct pci_dev *dev)
176{
177 unsigned int parent_dstates = 0;
178
179 if (dev->bus->self)
180 parent_dstates = dev->bus->self->no_d1d2;
181 return (dev->no_d1d2 || parent_dstates);
182
183}
184extern const struct attribute_group *pci_dev_groups[];
185extern const struct attribute_group *pcibus_groups[];
186extern struct device_type pci_dev_type;
187extern const struct attribute_group *pci_bus_groups[];
188
189
190/**
191 * pci_match_one_device - Tell if a PCI device structure has a matching
192 * PCI device id structure
193 * @id: single PCI device id structure to match
194 * @dev: the PCI device structure to match against
195 *
196 * Returns the matching pci_device_id structure or %NULL if there is no match.
197 */
198static inline const struct pci_device_id *
199pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
200{
201 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
202 (id->device == PCI_ANY_ID || id->device == dev->device) &&
203 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
204 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
205 !((id->class ^ dev->class) & id->class_mask))
206 return id;
207 return NULL;
208}
209
210/* PCI slot sysfs helper code */
211#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
212
213extern struct kset *pci_slots_kset;
214
215struct pci_slot_attribute {
216 struct attribute attr;
217 ssize_t (*show)(struct pci_slot *, char *);
218 ssize_t (*store)(struct pci_slot *, const char *, size_t);
219};
220#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
221
222enum pci_bar_type {
223 pci_bar_unknown, /* Standard PCI BAR probe */
224 pci_bar_io, /* An io port BAR */
225 pci_bar_mem32, /* A 32-bit memory BAR */
226 pci_bar_mem64, /* A 64-bit memory BAR */
227};
228
229bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
230 int crs_timeout);
231int pci_setup_device(struct pci_dev *dev);
232int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
233 struct resource *res, unsigned int reg);
234int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type);
235void pci_configure_ari(struct pci_dev *dev);
236void __pci_bus_size_bridges(struct pci_bus *bus,
237 struct list_head *realloc_head);
238void __pci_bus_assign_resources(const struct pci_bus *bus,
239 struct list_head *realloc_head,
240 struct list_head *fail_head);
241bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
242
243void pci_reassigndev_resource_alignment(struct pci_dev *dev);
244void pci_disable_bridge_window(struct pci_dev *dev);
245
246/* Single Root I/O Virtualization */
247struct pci_sriov {
248 int pos; /* capability position */
249 int nres; /* number of resources */
250 u32 cap; /* SR-IOV Capabilities */
251 u16 ctrl; /* SR-IOV Control */
252 u16 total_VFs; /* total VFs associated with the PF */
253 u16 initial_VFs; /* initial VFs associated with the PF */
254 u16 num_VFs; /* number of VFs available */
255 u16 offset; /* first VF Routing ID offset */
256 u16 stride; /* following VF stride */
257 u32 pgsz; /* page size for BAR alignment */
258 u8 link; /* Function Dependency Link */
259 u8 max_VF_buses; /* max buses consumed by VFs */
260 u16 driver_max_VFs; /* max num VFs driver supports */
261 struct pci_dev *dev; /* lowest numbered PF */
262 struct pci_dev *self; /* this PF */
263 struct mutex lock; /* lock for VF bus */
264 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
265};
266
267#ifdef CONFIG_PCI_ATS
268void pci_restore_ats_state(struct pci_dev *dev);
269#else
270static inline void pci_restore_ats_state(struct pci_dev *dev)
271{
272}
273#endif /* CONFIG_PCI_ATS */
274
275#ifdef CONFIG_PCI_IOV
276int pci_iov_init(struct pci_dev *dev);
277void pci_iov_release(struct pci_dev *dev);
278int pci_iov_resource_bar(struct pci_dev *dev, int resno);
279resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
280void pci_restore_iov_state(struct pci_dev *dev);
281int pci_iov_bus_range(struct pci_bus *bus);
282
283#else
284static inline int pci_iov_init(struct pci_dev *dev)
285{
286 return -ENODEV;
287}
288static inline void pci_iov_release(struct pci_dev *dev)
289
290{
291}
292static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno)
293{
294 return 0;
295}
296static inline void pci_restore_iov_state(struct pci_dev *dev)
297{
298}
299static inline int pci_iov_bus_range(struct pci_bus *bus)
300{
301 return 0;
302}
303
304#endif /* CONFIG_PCI_IOV */
305
306unsigned long pci_cardbus_resource_alignment(struct resource *);
307
308static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
309 struct resource *res)
310{
311#ifdef CONFIG_PCI_IOV
312 int resno = res - dev->resource;
313
314 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
315 return pci_sriov_resource_alignment(dev, resno);
316#endif
317 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
318 return pci_cardbus_resource_alignment(res);
319 return resource_alignment(res);
320}
321
322void pci_enable_acs(struct pci_dev *dev);
323
324struct pci_dev_reset_methods {
325 u16 vendor;
326 u16 device;
327 int (*reset)(struct pci_dev *dev, int probe);
328};
329
330#ifdef CONFIG_PCI_QUIRKS
331int pci_dev_specific_reset(struct pci_dev *dev, int probe);
332#else
333static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
334{
335 return -ENOTTY;
336}
337#endif
338
339#endif /* DRIVERS_PCI_H */
1#ifndef DRIVERS_PCI_H
2#define DRIVERS_PCI_H
3
4#define PCI_FIND_CAP_TTL 48
5
6extern const unsigned char pcie_link_speed[];
7
8bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
9
10/* Functions internal to the PCI core code */
11
12int pci_create_sysfs_dev_files(struct pci_dev *pdev);
13void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
14#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
15static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
16{ return; }
17static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
18{ return; }
19#else
20void pci_create_firmware_label_files(struct pci_dev *pdev);
21void pci_remove_firmware_label_files(struct pci_dev *pdev);
22#endif
23void pci_cleanup_rom(struct pci_dev *dev);
24#ifdef HAVE_PCI_MMAP
25enum pci_mmap_api {
26 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
27 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
28};
29int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
30 enum pci_mmap_api mmap_api);
31#endif
32int pci_probe_reset_function(struct pci_dev *dev);
33
34/**
35 * struct pci_platform_pm_ops - Firmware PM callbacks
36 *
37 * @is_manageable: returns 'true' if given device is power manageable by the
38 * platform firmware
39 *
40 * @set_state: invokes the platform firmware to set the device's power state
41 *
42 * @get_state: queries the platform firmware for a device's current power state
43 *
44 * @choose_state: returns PCI power state of given device preferred by the
45 * platform; to be used during system-wide transitions from a
46 * sleeping state to the working state and vice versa
47 *
48 * @sleep_wake: enables/disables the system wake up capability of given device
49 *
50 * @run_wake: enables/disables the platform to generate run-time wake-up events
51 * for given device (the device's wake-up capability has to be
52 * enabled by @sleep_wake for this feature to work)
53 *
54 * @need_resume: returns 'true' if the given device (which is currently
55 * suspended) needs to be resumed to be configured for system
56 * wakeup.
57 *
58 * If given platform is generally capable of power managing PCI devices, all of
59 * these callbacks are mandatory.
60 */
61struct pci_platform_pm_ops {
62 bool (*is_manageable)(struct pci_dev *dev);
63 int (*set_state)(struct pci_dev *dev, pci_power_t state);
64 pci_power_t (*get_state)(struct pci_dev *dev);
65 pci_power_t (*choose_state)(struct pci_dev *dev);
66 int (*sleep_wake)(struct pci_dev *dev, bool enable);
67 int (*run_wake)(struct pci_dev *dev, bool enable);
68 bool (*need_resume)(struct pci_dev *dev);
69};
70
71int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
72void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
73void pci_power_up(struct pci_dev *dev);
74void pci_disable_enabled_device(struct pci_dev *dev);
75int pci_finish_runtime_suspend(struct pci_dev *dev);
76int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
77bool pci_dev_keep_suspended(struct pci_dev *dev);
78void pci_dev_complete_resume(struct pci_dev *pci_dev);
79void pci_config_pm_runtime_get(struct pci_dev *dev);
80void pci_config_pm_runtime_put(struct pci_dev *dev);
81void pci_pm_init(struct pci_dev *dev);
82void pci_ea_init(struct pci_dev *dev);
83void pci_allocate_cap_save_buffers(struct pci_dev *dev);
84void pci_free_cap_save_buffers(struct pci_dev *dev);
85bool pci_bridge_d3_possible(struct pci_dev *dev);
86void pci_bridge_d3_update(struct pci_dev *dev);
87
88static inline void pci_wakeup_event(struct pci_dev *dev)
89{
90 /* Wait 100 ms before the system can be put into a sleep state. */
91 pm_wakeup_event(&dev->dev, 100);
92}
93
94static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
95{
96 return !!(pci_dev->subordinate);
97}
98
99static inline bool pci_power_manageable(struct pci_dev *pci_dev)
100{
101 /*
102 * Currently we allow normal PCI devices and PCI bridges transition
103 * into D3 if their bridge_d3 is set.
104 */
105 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
106}
107
108struct pci_vpd_ops {
109 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
110 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
111 int (*set_size)(struct pci_dev *dev, size_t len);
112};
113
114struct pci_vpd {
115 const struct pci_vpd_ops *ops;
116 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
117 struct mutex lock;
118 unsigned int len;
119 u16 flag;
120 u8 cap;
121 u8 busy:1;
122 u8 valid:1;
123};
124
125int pci_vpd_init(struct pci_dev *dev);
126void pci_vpd_release(struct pci_dev *dev);
127
128/* PCI /proc functions */
129#ifdef CONFIG_PROC_FS
130int pci_proc_attach_device(struct pci_dev *dev);
131int pci_proc_detach_device(struct pci_dev *dev);
132int pci_proc_detach_bus(struct pci_bus *bus);
133#else
134static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
135static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
136static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
137#endif
138
139/* Functions for PCI Hotplug drivers to use */
140int pci_hp_add_bridge(struct pci_dev *dev);
141
142#ifdef HAVE_PCI_LEGACY
143void pci_create_legacy_files(struct pci_bus *bus);
144void pci_remove_legacy_files(struct pci_bus *bus);
145#else
146static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
147static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
148#endif
149
150/* Lock for read/write access to pci device and bus lists */
151extern struct rw_semaphore pci_bus_sem;
152
153extern raw_spinlock_t pci_lock;
154
155extern unsigned int pci_pm_d3_delay;
156
157#ifdef CONFIG_PCI_MSI
158void pci_no_msi(void);
159#else
160static inline void pci_no_msi(void) { }
161#endif
162
163static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
164{
165 u16 control;
166
167 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
168 control &= ~PCI_MSI_FLAGS_ENABLE;
169 if (enable)
170 control |= PCI_MSI_FLAGS_ENABLE;
171 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
172}
173
174static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
175{
176 u16 ctrl;
177
178 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
179 ctrl &= ~clear;
180 ctrl |= set;
181 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
182}
183
184void pci_realloc_get_opt(char *);
185
186static inline int pci_no_d1d2(struct pci_dev *dev)
187{
188 unsigned int parent_dstates = 0;
189
190 if (dev->bus->self)
191 parent_dstates = dev->bus->self->no_d1d2;
192 return (dev->no_d1d2 || parent_dstates);
193
194}
195extern const struct attribute_group *pci_dev_groups[];
196extern const struct attribute_group *pcibus_groups[];
197extern struct device_type pci_dev_type;
198extern const struct attribute_group *pci_bus_groups[];
199
200
201/**
202 * pci_match_one_device - Tell if a PCI device structure has a matching
203 * PCI device id structure
204 * @id: single PCI device id structure to match
205 * @dev: the PCI device structure to match against
206 *
207 * Returns the matching pci_device_id structure or %NULL if there is no match.
208 */
209static inline const struct pci_device_id *
210pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
211{
212 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
213 (id->device == PCI_ANY_ID || id->device == dev->device) &&
214 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
215 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
216 !((id->class ^ dev->class) & id->class_mask))
217 return id;
218 return NULL;
219}
220
221/* PCI slot sysfs helper code */
222#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
223
224extern struct kset *pci_slots_kset;
225
226struct pci_slot_attribute {
227 struct attribute attr;
228 ssize_t (*show)(struct pci_slot *, char *);
229 ssize_t (*store)(struct pci_slot *, const char *, size_t);
230};
231#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
232
233enum pci_bar_type {
234 pci_bar_unknown, /* Standard PCI BAR probe */
235 pci_bar_io, /* An io port BAR */
236 pci_bar_mem32, /* A 32-bit memory BAR */
237 pci_bar_mem64, /* A 64-bit memory BAR */
238};
239
240bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
241 int crs_timeout);
242int pci_setup_device(struct pci_dev *dev);
243int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
244 struct resource *res, unsigned int reg);
245void pci_configure_ari(struct pci_dev *dev);
246void __pci_bus_size_bridges(struct pci_bus *bus,
247 struct list_head *realloc_head);
248void __pci_bus_assign_resources(const struct pci_bus *bus,
249 struct list_head *realloc_head,
250 struct list_head *fail_head);
251bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
252
253void pci_reassigndev_resource_alignment(struct pci_dev *dev);
254void pci_disable_bridge_window(struct pci_dev *dev);
255
256/* Single Root I/O Virtualization */
257struct pci_sriov {
258 int pos; /* capability position */
259 int nres; /* number of resources */
260 u32 cap; /* SR-IOV Capabilities */
261 u16 ctrl; /* SR-IOV Control */
262 u16 total_VFs; /* total VFs associated with the PF */
263 u16 initial_VFs; /* initial VFs associated with the PF */
264 u16 num_VFs; /* number of VFs available */
265 u16 offset; /* first VF Routing ID offset */
266 u16 stride; /* following VF stride */
267 u32 pgsz; /* page size for BAR alignment */
268 u8 link; /* Function Dependency Link */
269 u8 max_VF_buses; /* max buses consumed by VFs */
270 u16 driver_max_VFs; /* max num VFs driver supports */
271 struct pci_dev *dev; /* lowest numbered PF */
272 struct pci_dev *self; /* this PF */
273 struct mutex lock; /* lock for VF bus */
274 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
275};
276
277#ifdef CONFIG_PCI_ATS
278void pci_restore_ats_state(struct pci_dev *dev);
279#else
280static inline void pci_restore_ats_state(struct pci_dev *dev)
281{
282}
283#endif /* CONFIG_PCI_ATS */
284
285#ifdef CONFIG_PCI_IOV
286int pci_iov_init(struct pci_dev *dev);
287void pci_iov_release(struct pci_dev *dev);
288void pci_iov_update_resource(struct pci_dev *dev, int resno);
289resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
290void pci_restore_iov_state(struct pci_dev *dev);
291int pci_iov_bus_range(struct pci_bus *bus);
292
293#else
294static inline int pci_iov_init(struct pci_dev *dev)
295{
296 return -ENODEV;
297}
298static inline void pci_iov_release(struct pci_dev *dev)
299
300{
301}
302static inline void pci_restore_iov_state(struct pci_dev *dev)
303{
304}
305static inline int pci_iov_bus_range(struct pci_bus *bus)
306{
307 return 0;
308}
309
310#endif /* CONFIG_PCI_IOV */
311
312unsigned long pci_cardbus_resource_alignment(struct resource *);
313
314static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
315 struct resource *res)
316{
317#ifdef CONFIG_PCI_IOV
318 int resno = res - dev->resource;
319
320 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
321 return pci_sriov_resource_alignment(dev, resno);
322#endif
323 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
324 return pci_cardbus_resource_alignment(res);
325 return resource_alignment(res);
326}
327
328void pci_enable_acs(struct pci_dev *dev);
329
330#ifdef CONFIG_PCIE_PTM
331void pci_ptm_init(struct pci_dev *dev);
332#else
333static inline void pci_ptm_init(struct pci_dev *dev) { }
334#endif
335
336struct pci_dev_reset_methods {
337 u16 vendor;
338 u16 device;
339 int (*reset)(struct pci_dev *dev, int probe);
340};
341
342#ifdef CONFIG_PCI_QUIRKS
343int pci_dev_specific_reset(struct pci_dev *dev, int probe);
344#else
345static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
346{
347 return -ENOTTY;
348}
349#endif
350
351#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
352int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
353 struct resource *res);
354#endif
355
356#endif /* DRIVERS_PCI_H */