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1/*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/of.h>
14#include <linux/of_pci.h>
15#include <linux/pci.h>
16#include <linux/pm.h>
17#include <linux/slab.h>
18#include <linux/module.h>
19#include <linux/spinlock.h>
20#include <linux/string.h>
21#include <linux/log2.h>
22#include <linux/pci-aspm.h>
23#include <linux/pm_wakeup.h>
24#include <linux/interrupt.h>
25#include <linux/device.h>
26#include <linux/pm_runtime.h>
27#include <linux/pci_hotplug.h>
28#include <asm/setup.h>
29#include <linux/aer.h>
30#include "pci.h"
31
32const char *pci_power_names[] = {
33 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
34};
35EXPORT_SYMBOL_GPL(pci_power_names);
36
37int isa_dma_bridge_buggy;
38EXPORT_SYMBOL(isa_dma_bridge_buggy);
39
40int pci_pci_problems;
41EXPORT_SYMBOL(pci_pci_problems);
42
43unsigned int pci_pm_d3_delay;
44
45static void pci_pme_list_scan(struct work_struct *work);
46
47static LIST_HEAD(pci_pme_list);
48static DEFINE_MUTEX(pci_pme_list_mutex);
49static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
50
51struct pci_pme_device {
52 struct list_head list;
53 struct pci_dev *dev;
54};
55
56#define PME_TIMEOUT 1000 /* How long between PME checks */
57
58static void pci_dev_d3_sleep(struct pci_dev *dev)
59{
60 unsigned int delay = dev->d3_delay;
61
62 if (delay < pci_pm_d3_delay)
63 delay = pci_pm_d3_delay;
64
65 msleep(delay);
66}
67
68#ifdef CONFIG_PCI_DOMAINS
69int pci_domains_supported = 1;
70#endif
71
72#define DEFAULT_CARDBUS_IO_SIZE (256)
73#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
74/* pci=cbmemsize=nnM,cbiosize=nn can override this */
75unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
76unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
77
78#define DEFAULT_HOTPLUG_IO_SIZE (256)
79#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
80/* pci=hpmemsize=nnM,hpiosize=nn can override this */
81unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
82unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
83
84enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
85
86/*
87 * The default CLS is used if arch didn't set CLS explicitly and not
88 * all pci devices agree on the same value. Arch can override either
89 * the dfl or actual value as it sees fit. Don't forget this is
90 * measured in 32-bit words, not bytes.
91 */
92u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
93u8 pci_cache_line_size;
94
95/*
96 * If we set up a device for bus mastering, we need to check the latency
97 * timer as certain BIOSes forget to set it properly.
98 */
99unsigned int pcibios_max_latency = 255;
100
101/* If set, the PCIe ARI capability will not be used. */
102static bool pcie_ari_disabled;
103
104/**
105 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
106 * @bus: pointer to PCI bus structure to search
107 *
108 * Given a PCI bus, returns the highest PCI bus number present in the set
109 * including the given PCI bus and its list of child PCI buses.
110 */
111unsigned char pci_bus_max_busnr(struct pci_bus *bus)
112{
113 struct pci_bus *tmp;
114 unsigned char max, n;
115
116 max = bus->busn_res.end;
117 list_for_each_entry(tmp, &bus->children, node) {
118 n = pci_bus_max_busnr(tmp);
119 if (n > max)
120 max = n;
121 }
122 return max;
123}
124EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
125
126#ifdef CONFIG_HAS_IOMEM
127void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
128{
129 struct resource *res = &pdev->resource[bar];
130
131 /*
132 * Make sure the BAR is actually a memory resource, not an IO resource
133 */
134 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
135 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
136 return NULL;
137 }
138 return ioremap_nocache(res->start, resource_size(res));
139}
140EXPORT_SYMBOL_GPL(pci_ioremap_bar);
141
142void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
143{
144 /*
145 * Make sure the BAR is actually a memory resource, not an IO resource
146 */
147 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
148 WARN_ON(1);
149 return NULL;
150 }
151 return ioremap_wc(pci_resource_start(pdev, bar),
152 pci_resource_len(pdev, bar));
153}
154EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
155#endif
156
157
158static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
159 u8 pos, int cap, int *ttl)
160{
161 u8 id;
162 u16 ent;
163
164 pci_bus_read_config_byte(bus, devfn, pos, &pos);
165
166 while ((*ttl)--) {
167 if (pos < 0x40)
168 break;
169 pos &= ~3;
170 pci_bus_read_config_word(bus, devfn, pos, &ent);
171
172 id = ent & 0xff;
173 if (id == 0xff)
174 break;
175 if (id == cap)
176 return pos;
177 pos = (ent >> 8);
178 }
179 return 0;
180}
181
182static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
183 u8 pos, int cap)
184{
185 int ttl = PCI_FIND_CAP_TTL;
186
187 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
188}
189
190int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
191{
192 return __pci_find_next_cap(dev->bus, dev->devfn,
193 pos + PCI_CAP_LIST_NEXT, cap);
194}
195EXPORT_SYMBOL_GPL(pci_find_next_capability);
196
197static int __pci_bus_find_cap_start(struct pci_bus *bus,
198 unsigned int devfn, u8 hdr_type)
199{
200 u16 status;
201
202 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
203 if (!(status & PCI_STATUS_CAP_LIST))
204 return 0;
205
206 switch (hdr_type) {
207 case PCI_HEADER_TYPE_NORMAL:
208 case PCI_HEADER_TYPE_BRIDGE:
209 return PCI_CAPABILITY_LIST;
210 case PCI_HEADER_TYPE_CARDBUS:
211 return PCI_CB_CAPABILITY_LIST;
212 }
213
214 return 0;
215}
216
217/**
218 * pci_find_capability - query for devices' capabilities
219 * @dev: PCI device to query
220 * @cap: capability code
221 *
222 * Tell if a device supports a given PCI capability.
223 * Returns the address of the requested capability structure within the
224 * device's PCI configuration space or 0 in case the device does not
225 * support it. Possible values for @cap:
226 *
227 * %PCI_CAP_ID_PM Power Management
228 * %PCI_CAP_ID_AGP Accelerated Graphics Port
229 * %PCI_CAP_ID_VPD Vital Product Data
230 * %PCI_CAP_ID_SLOTID Slot Identification
231 * %PCI_CAP_ID_MSI Message Signalled Interrupts
232 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
233 * %PCI_CAP_ID_PCIX PCI-X
234 * %PCI_CAP_ID_EXP PCI Express
235 */
236int pci_find_capability(struct pci_dev *dev, int cap)
237{
238 int pos;
239
240 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
241 if (pos)
242 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
243
244 return pos;
245}
246EXPORT_SYMBOL(pci_find_capability);
247
248/**
249 * pci_bus_find_capability - query for devices' capabilities
250 * @bus: the PCI bus to query
251 * @devfn: PCI device to query
252 * @cap: capability code
253 *
254 * Like pci_find_capability() but works for pci devices that do not have a
255 * pci_dev structure set up yet.
256 *
257 * Returns the address of the requested capability structure within the
258 * device's PCI configuration space or 0 in case the device does not
259 * support it.
260 */
261int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
262{
263 int pos;
264 u8 hdr_type;
265
266 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
267
268 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
269 if (pos)
270 pos = __pci_find_next_cap(bus, devfn, pos, cap);
271
272 return pos;
273}
274EXPORT_SYMBOL(pci_bus_find_capability);
275
276/**
277 * pci_find_next_ext_capability - Find an extended capability
278 * @dev: PCI device to query
279 * @start: address at which to start looking (0 to start at beginning of list)
280 * @cap: capability code
281 *
282 * Returns the address of the next matching extended capability structure
283 * within the device's PCI configuration space or 0 if the device does
284 * not support it. Some capabilities can occur several times, e.g., the
285 * vendor-specific capability, and this provides a way to find them all.
286 */
287int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
288{
289 u32 header;
290 int ttl;
291 int pos = PCI_CFG_SPACE_SIZE;
292
293 /* minimum 8 bytes per capability */
294 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
295
296 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
297 return 0;
298
299 if (start)
300 pos = start;
301
302 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
303 return 0;
304
305 /*
306 * If we have no capabilities, this is indicated by cap ID,
307 * cap version and next pointer all being 0.
308 */
309 if (header == 0)
310 return 0;
311
312 while (ttl-- > 0) {
313 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
314 return pos;
315
316 pos = PCI_EXT_CAP_NEXT(header);
317 if (pos < PCI_CFG_SPACE_SIZE)
318 break;
319
320 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
321 break;
322 }
323
324 return 0;
325}
326EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
327
328/**
329 * pci_find_ext_capability - Find an extended capability
330 * @dev: PCI device to query
331 * @cap: capability code
332 *
333 * Returns the address of the requested extended capability structure
334 * within the device's PCI configuration space or 0 if the device does
335 * not support it. Possible values for @cap:
336 *
337 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
338 * %PCI_EXT_CAP_ID_VC Virtual Channel
339 * %PCI_EXT_CAP_ID_DSN Device Serial Number
340 * %PCI_EXT_CAP_ID_PWR Power Budgeting
341 */
342int pci_find_ext_capability(struct pci_dev *dev, int cap)
343{
344 return pci_find_next_ext_capability(dev, 0, cap);
345}
346EXPORT_SYMBOL_GPL(pci_find_ext_capability);
347
348static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
349{
350 int rc, ttl = PCI_FIND_CAP_TTL;
351 u8 cap, mask;
352
353 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
354 mask = HT_3BIT_CAP_MASK;
355 else
356 mask = HT_5BIT_CAP_MASK;
357
358 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
359 PCI_CAP_ID_HT, &ttl);
360 while (pos) {
361 rc = pci_read_config_byte(dev, pos + 3, &cap);
362 if (rc != PCIBIOS_SUCCESSFUL)
363 return 0;
364
365 if ((cap & mask) == ht_cap)
366 return pos;
367
368 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
369 pos + PCI_CAP_LIST_NEXT,
370 PCI_CAP_ID_HT, &ttl);
371 }
372
373 return 0;
374}
375/**
376 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @pos: Position from which to continue searching
379 * @ht_cap: Hypertransport capability code
380 *
381 * To be used in conjunction with pci_find_ht_capability() to search for
382 * all capabilities matching @ht_cap. @pos should always be a value returned
383 * from pci_find_ht_capability().
384 *
385 * NB. To be 100% safe against broken PCI devices, the caller should take
386 * steps to avoid an infinite loop.
387 */
388int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
389{
390 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
391}
392EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
393
394/**
395 * pci_find_ht_capability - query a device's Hypertransport capabilities
396 * @dev: PCI device to query
397 * @ht_cap: Hypertransport capability code
398 *
399 * Tell if a device supports a given Hypertransport capability.
400 * Returns an address within the device's PCI configuration space
401 * or 0 in case the device does not support the request capability.
402 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
403 * which has a Hypertransport capability matching @ht_cap.
404 */
405int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
406{
407 int pos;
408
409 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
410 if (pos)
411 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
412
413 return pos;
414}
415EXPORT_SYMBOL_GPL(pci_find_ht_capability);
416
417/**
418 * pci_find_parent_resource - return resource region of parent bus of given region
419 * @dev: PCI device structure contains resources to be searched
420 * @res: child resource record for which parent is sought
421 *
422 * For given resource region of given device, return the resource
423 * region of parent bus the given region is contained in.
424 */
425struct resource *pci_find_parent_resource(const struct pci_dev *dev,
426 struct resource *res)
427{
428 const struct pci_bus *bus = dev->bus;
429 struct resource *r;
430 int i;
431
432 pci_bus_for_each_resource(bus, r, i) {
433 if (!r)
434 continue;
435 if (res->start && resource_contains(r, res)) {
436
437 /*
438 * If the window is prefetchable but the BAR is
439 * not, the allocator made a mistake.
440 */
441 if (r->flags & IORESOURCE_PREFETCH &&
442 !(res->flags & IORESOURCE_PREFETCH))
443 return NULL;
444
445 /*
446 * If we're below a transparent bridge, there may
447 * be both a positively-decoded aperture and a
448 * subtractively-decoded region that contain the BAR.
449 * We want the positively-decoded one, so this depends
450 * on pci_bus_for_each_resource() giving us those
451 * first.
452 */
453 return r;
454 }
455 }
456 return NULL;
457}
458EXPORT_SYMBOL(pci_find_parent_resource);
459
460/**
461 * pci_find_pcie_root_port - return PCIe Root Port
462 * @dev: PCI device to query
463 *
464 * Traverse up the parent chain and return the PCIe Root Port PCI Device
465 * for a given PCI Device.
466 */
467struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
468{
469 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
470
471 bridge = pci_upstream_bridge(dev);
472 while (bridge && pci_is_pcie(bridge)) {
473 highest_pcie_bridge = bridge;
474 bridge = pci_upstream_bridge(bridge);
475 }
476
477 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
478 return NULL;
479
480 return highest_pcie_bridge;
481}
482EXPORT_SYMBOL(pci_find_pcie_root_port);
483
484/**
485 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
486 * @dev: the PCI device to operate on
487 * @pos: config space offset of status word
488 * @mask: mask of bit(s) to care about in status word
489 *
490 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
491 */
492int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
493{
494 int i;
495
496 /* Wait for Transaction Pending bit clean */
497 for (i = 0; i < 4; i++) {
498 u16 status;
499 if (i)
500 msleep((1 << (i - 1)) * 100);
501
502 pci_read_config_word(dev, pos, &status);
503 if (!(status & mask))
504 return 1;
505 }
506
507 return 0;
508}
509
510/**
511 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
512 * @dev: PCI device to have its BARs restored
513 *
514 * Restore the BAR values for a given device, so as to make it
515 * accessible by its driver.
516 */
517static void pci_restore_bars(struct pci_dev *dev)
518{
519 int i;
520
521 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
522 if (dev->is_virtfn)
523 return;
524
525 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
526 pci_update_resource(dev, i);
527}
528
529static const struct pci_platform_pm_ops *pci_platform_pm;
530
531int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
532{
533 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
534 || !ops->sleep_wake)
535 return -EINVAL;
536 pci_platform_pm = ops;
537 return 0;
538}
539
540static inline bool platform_pci_power_manageable(struct pci_dev *dev)
541{
542 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
543}
544
545static inline int platform_pci_set_power_state(struct pci_dev *dev,
546 pci_power_t t)
547{
548 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
549}
550
551static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
552{
553 return pci_platform_pm ?
554 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
555}
556
557static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
558{
559 return pci_platform_pm ?
560 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
561}
562
563static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
564{
565 return pci_platform_pm ?
566 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
567}
568
569static inline bool platform_pci_need_resume(struct pci_dev *dev)
570{
571 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
572}
573
574/**
575 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
576 * given PCI device
577 * @dev: PCI device to handle.
578 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
579 *
580 * RETURN VALUE:
581 * -EINVAL if the requested state is invalid.
582 * -EIO if device does not support PCI PM or its PM capabilities register has a
583 * wrong version, or device doesn't support the requested state.
584 * 0 if device already is in the requested state.
585 * 0 if device's power state has been successfully changed.
586 */
587static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
588{
589 u16 pmcsr;
590 bool need_restore = false;
591
592 /* Check if we're already there */
593 if (dev->current_state == state)
594 return 0;
595
596 if (!dev->pm_cap)
597 return -EIO;
598
599 if (state < PCI_D0 || state > PCI_D3hot)
600 return -EINVAL;
601
602 /* Validate current state:
603 * Can enter D0 from any state, but if we can only go deeper
604 * to sleep if we're already in a low power state
605 */
606 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
607 && dev->current_state > state) {
608 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
609 dev->current_state, state);
610 return -EINVAL;
611 }
612
613 /* check if this device supports the desired state */
614 if ((state == PCI_D1 && !dev->d1_support)
615 || (state == PCI_D2 && !dev->d2_support))
616 return -EIO;
617
618 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
619
620 /* If we're (effectively) in D3, force entire word to 0.
621 * This doesn't affect PME_Status, disables PME_En, and
622 * sets PowerState to 0.
623 */
624 switch (dev->current_state) {
625 case PCI_D0:
626 case PCI_D1:
627 case PCI_D2:
628 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
629 pmcsr |= state;
630 break;
631 case PCI_D3hot:
632 case PCI_D3cold:
633 case PCI_UNKNOWN: /* Boot-up */
634 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
635 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
636 need_restore = true;
637 /* Fall-through: force to D0 */
638 default:
639 pmcsr = 0;
640 break;
641 }
642
643 /* enter specified state */
644 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
645
646 /* Mandatory power management transition delays */
647 /* see PCI PM 1.1 5.6.1 table 18 */
648 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
649 pci_dev_d3_sleep(dev);
650 else if (state == PCI_D2 || dev->current_state == PCI_D2)
651 udelay(PCI_PM_D2_DELAY);
652
653 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
654 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
655 if (dev->current_state != state && printk_ratelimit())
656 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
657 dev->current_state);
658
659 /*
660 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
661 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
662 * from D3hot to D0 _may_ perform an internal reset, thereby
663 * going to "D0 Uninitialized" rather than "D0 Initialized".
664 * For example, at least some versions of the 3c905B and the
665 * 3c556B exhibit this behaviour.
666 *
667 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
668 * devices in a D3hot state at boot. Consequently, we need to
669 * restore at least the BARs so that the device will be
670 * accessible to its driver.
671 */
672 if (need_restore)
673 pci_restore_bars(dev);
674
675 if (dev->bus->self)
676 pcie_aspm_pm_state_change(dev->bus->self);
677
678 return 0;
679}
680
681/**
682 * pci_update_current_state - Read PCI power state of given device from its
683 * PCI PM registers and cache it
684 * @dev: PCI device to handle.
685 * @state: State to cache in case the device doesn't have the PM capability
686 */
687void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
688{
689 if (dev->pm_cap) {
690 u16 pmcsr;
691
692 /*
693 * Configuration space is not accessible for device in
694 * D3cold, so just keep or set D3cold for safety
695 */
696 if (dev->current_state == PCI_D3cold)
697 return;
698 if (state == PCI_D3cold) {
699 dev->current_state = PCI_D3cold;
700 return;
701 }
702 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
703 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
704 } else {
705 dev->current_state = state;
706 }
707}
708
709/**
710 * pci_power_up - Put the given device into D0 forcibly
711 * @dev: PCI device to power up
712 */
713void pci_power_up(struct pci_dev *dev)
714{
715 if (platform_pci_power_manageable(dev))
716 platform_pci_set_power_state(dev, PCI_D0);
717
718 pci_raw_set_power_state(dev, PCI_D0);
719 pci_update_current_state(dev, PCI_D0);
720}
721
722/**
723 * pci_platform_power_transition - Use platform to change device power state
724 * @dev: PCI device to handle.
725 * @state: State to put the device into.
726 */
727static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
728{
729 int error;
730
731 if (platform_pci_power_manageable(dev)) {
732 error = platform_pci_set_power_state(dev, state);
733 if (!error)
734 pci_update_current_state(dev, state);
735 } else
736 error = -ENODEV;
737
738 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
739 dev->current_state = PCI_D0;
740
741 return error;
742}
743
744/**
745 * pci_wakeup - Wake up a PCI device
746 * @pci_dev: Device to handle.
747 * @ign: ignored parameter
748 */
749static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
750{
751 pci_wakeup_event(pci_dev);
752 pm_request_resume(&pci_dev->dev);
753 return 0;
754}
755
756/**
757 * pci_wakeup_bus - Walk given bus and wake up devices on it
758 * @bus: Top bus of the subtree to walk.
759 */
760static void pci_wakeup_bus(struct pci_bus *bus)
761{
762 if (bus)
763 pci_walk_bus(bus, pci_wakeup, NULL);
764}
765
766/**
767 * __pci_start_power_transition - Start power transition of a PCI device
768 * @dev: PCI device to handle.
769 * @state: State to put the device into.
770 */
771static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
772{
773 if (state == PCI_D0) {
774 pci_platform_power_transition(dev, PCI_D0);
775 /*
776 * Mandatory power management transition delays, see
777 * PCI Express Base Specification Revision 2.0 Section
778 * 6.6.1: Conventional Reset. Do not delay for
779 * devices powered on/off by corresponding bridge,
780 * because have already delayed for the bridge.
781 */
782 if (dev->runtime_d3cold) {
783 msleep(dev->d3cold_delay);
784 /*
785 * When powering on a bridge from D3cold, the
786 * whole hierarchy may be powered on into
787 * D0uninitialized state, resume them to give
788 * them a chance to suspend again
789 */
790 pci_wakeup_bus(dev->subordinate);
791 }
792 }
793}
794
795/**
796 * __pci_dev_set_current_state - Set current state of a PCI device
797 * @dev: Device to handle
798 * @data: pointer to state to be set
799 */
800static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
801{
802 pci_power_t state = *(pci_power_t *)data;
803
804 dev->current_state = state;
805 return 0;
806}
807
808/**
809 * __pci_bus_set_current_state - Walk given bus and set current state of devices
810 * @bus: Top bus of the subtree to walk.
811 * @state: state to be set
812 */
813static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
814{
815 if (bus)
816 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
817}
818
819/**
820 * __pci_complete_power_transition - Complete power transition of a PCI device
821 * @dev: PCI device to handle.
822 * @state: State to put the device into.
823 *
824 * This function should not be called directly by device drivers.
825 */
826int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
827{
828 int ret;
829
830 if (state <= PCI_D0)
831 return -EINVAL;
832 ret = pci_platform_power_transition(dev, state);
833 /* Power off the bridge may power off the whole hierarchy */
834 if (!ret && state == PCI_D3cold)
835 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
836 return ret;
837}
838EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
839
840/**
841 * pci_set_power_state - Set the power state of a PCI device
842 * @dev: PCI device to handle.
843 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
844 *
845 * Transition a device to a new power state, using the platform firmware and/or
846 * the device's PCI PM registers.
847 *
848 * RETURN VALUE:
849 * -EINVAL if the requested state is invalid.
850 * -EIO if device does not support PCI PM or its PM capabilities register has a
851 * wrong version, or device doesn't support the requested state.
852 * 0 if device already is in the requested state.
853 * 0 if device's power state has been successfully changed.
854 */
855int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
856{
857 int error;
858
859 /* bound the state we're entering */
860 if (state > PCI_D3cold)
861 state = PCI_D3cold;
862 else if (state < PCI_D0)
863 state = PCI_D0;
864 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
865 /*
866 * If the device or the parent bridge do not support PCI PM,
867 * ignore the request if we're doing anything other than putting
868 * it into D0 (which would only happen on boot).
869 */
870 return 0;
871
872 /* Check if we're already there */
873 if (dev->current_state == state)
874 return 0;
875
876 __pci_start_power_transition(dev, state);
877
878 /* This device is quirked not to be put into D3, so
879 don't put it in D3 */
880 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
881 return 0;
882
883 /*
884 * To put device in D3cold, we put device into D3hot in native
885 * way, then put device into D3cold with platform ops
886 */
887 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
888 PCI_D3hot : state);
889
890 if (!__pci_complete_power_transition(dev, state))
891 error = 0;
892
893 return error;
894}
895EXPORT_SYMBOL(pci_set_power_state);
896
897/**
898 * pci_choose_state - Choose the power state of a PCI device
899 * @dev: PCI device to be suspended
900 * @state: target sleep state for the whole system. This is the value
901 * that is passed to suspend() function.
902 *
903 * Returns PCI power state suitable for given device and given system
904 * message.
905 */
906
907pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
908{
909 pci_power_t ret;
910
911 if (!dev->pm_cap)
912 return PCI_D0;
913
914 ret = platform_pci_choose_state(dev);
915 if (ret != PCI_POWER_ERROR)
916 return ret;
917
918 switch (state.event) {
919 case PM_EVENT_ON:
920 return PCI_D0;
921 case PM_EVENT_FREEZE:
922 case PM_EVENT_PRETHAW:
923 /* REVISIT both freeze and pre-thaw "should" use D0 */
924 case PM_EVENT_SUSPEND:
925 case PM_EVENT_HIBERNATE:
926 return PCI_D3hot;
927 default:
928 dev_info(&dev->dev, "unrecognized suspend event %d\n",
929 state.event);
930 BUG();
931 }
932 return PCI_D0;
933}
934EXPORT_SYMBOL(pci_choose_state);
935
936#define PCI_EXP_SAVE_REGS 7
937
938static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
939 u16 cap, bool extended)
940{
941 struct pci_cap_saved_state *tmp;
942
943 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
944 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
945 return tmp;
946 }
947 return NULL;
948}
949
950struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
951{
952 return _pci_find_saved_cap(dev, cap, false);
953}
954
955struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
956{
957 return _pci_find_saved_cap(dev, cap, true);
958}
959
960static int pci_save_pcie_state(struct pci_dev *dev)
961{
962 int i = 0;
963 struct pci_cap_saved_state *save_state;
964 u16 *cap;
965
966 if (!pci_is_pcie(dev))
967 return 0;
968
969 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
970 if (!save_state) {
971 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
972 return -ENOMEM;
973 }
974
975 cap = (u16 *)&save_state->cap.data[0];
976 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
977 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
978 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
979 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
980 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
981 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
982 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
983
984 return 0;
985}
986
987static void pci_restore_pcie_state(struct pci_dev *dev)
988{
989 int i = 0;
990 struct pci_cap_saved_state *save_state;
991 u16 *cap;
992
993 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
994 if (!save_state)
995 return;
996
997 cap = (u16 *)&save_state->cap.data[0];
998 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
999 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1000 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1001 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1002 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1003 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1004 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1005}
1006
1007
1008static int pci_save_pcix_state(struct pci_dev *dev)
1009{
1010 int pos;
1011 struct pci_cap_saved_state *save_state;
1012
1013 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1014 if (!pos)
1015 return 0;
1016
1017 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1018 if (!save_state) {
1019 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1020 return -ENOMEM;
1021 }
1022
1023 pci_read_config_word(dev, pos + PCI_X_CMD,
1024 (u16 *)save_state->cap.data);
1025
1026 return 0;
1027}
1028
1029static void pci_restore_pcix_state(struct pci_dev *dev)
1030{
1031 int i = 0, pos;
1032 struct pci_cap_saved_state *save_state;
1033 u16 *cap;
1034
1035 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1036 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1037 if (!save_state || !pos)
1038 return;
1039 cap = (u16 *)&save_state->cap.data[0];
1040
1041 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1042}
1043
1044
1045/**
1046 * pci_save_state - save the PCI configuration space of a device before suspending
1047 * @dev: - PCI device that we're dealing with
1048 */
1049int pci_save_state(struct pci_dev *dev)
1050{
1051 int i;
1052 /* XXX: 100% dword access ok here? */
1053 for (i = 0; i < 16; i++)
1054 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1055 dev->state_saved = true;
1056
1057 i = pci_save_pcie_state(dev);
1058 if (i != 0)
1059 return i;
1060
1061 i = pci_save_pcix_state(dev);
1062 if (i != 0)
1063 return i;
1064
1065 return pci_save_vc_state(dev);
1066}
1067EXPORT_SYMBOL(pci_save_state);
1068
1069static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1070 u32 saved_val, int retry)
1071{
1072 u32 val;
1073
1074 pci_read_config_dword(pdev, offset, &val);
1075 if (val == saved_val)
1076 return;
1077
1078 for (;;) {
1079 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1080 offset, val, saved_val);
1081 pci_write_config_dword(pdev, offset, saved_val);
1082 if (retry-- <= 0)
1083 return;
1084
1085 pci_read_config_dword(pdev, offset, &val);
1086 if (val == saved_val)
1087 return;
1088
1089 mdelay(1);
1090 }
1091}
1092
1093static void pci_restore_config_space_range(struct pci_dev *pdev,
1094 int start, int end, int retry)
1095{
1096 int index;
1097
1098 for (index = end; index >= start; index--)
1099 pci_restore_config_dword(pdev, 4 * index,
1100 pdev->saved_config_space[index],
1101 retry);
1102}
1103
1104static void pci_restore_config_space(struct pci_dev *pdev)
1105{
1106 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1107 pci_restore_config_space_range(pdev, 10, 15, 0);
1108 /* Restore BARs before the command register. */
1109 pci_restore_config_space_range(pdev, 4, 9, 10);
1110 pci_restore_config_space_range(pdev, 0, 3, 0);
1111 } else {
1112 pci_restore_config_space_range(pdev, 0, 15, 0);
1113 }
1114}
1115
1116/**
1117 * pci_restore_state - Restore the saved state of a PCI device
1118 * @dev: - PCI device that we're dealing with
1119 */
1120void pci_restore_state(struct pci_dev *dev)
1121{
1122 if (!dev->state_saved)
1123 return;
1124
1125 /* PCI Express register must be restored first */
1126 pci_restore_pcie_state(dev);
1127 pci_restore_ats_state(dev);
1128 pci_restore_vc_state(dev);
1129
1130 pci_cleanup_aer_error_status_regs(dev);
1131
1132 pci_restore_config_space(dev);
1133
1134 pci_restore_pcix_state(dev);
1135 pci_restore_msi_state(dev);
1136
1137 /* Restore ACS and IOV configuration state */
1138 pci_enable_acs(dev);
1139 pci_restore_iov_state(dev);
1140
1141 dev->state_saved = false;
1142}
1143EXPORT_SYMBOL(pci_restore_state);
1144
1145struct pci_saved_state {
1146 u32 config_space[16];
1147 struct pci_cap_saved_data cap[0];
1148};
1149
1150/**
1151 * pci_store_saved_state - Allocate and return an opaque struct containing
1152 * the device saved state.
1153 * @dev: PCI device that we're dealing with
1154 *
1155 * Return NULL if no state or error.
1156 */
1157struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1158{
1159 struct pci_saved_state *state;
1160 struct pci_cap_saved_state *tmp;
1161 struct pci_cap_saved_data *cap;
1162 size_t size;
1163
1164 if (!dev->state_saved)
1165 return NULL;
1166
1167 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1168
1169 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1170 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1171
1172 state = kzalloc(size, GFP_KERNEL);
1173 if (!state)
1174 return NULL;
1175
1176 memcpy(state->config_space, dev->saved_config_space,
1177 sizeof(state->config_space));
1178
1179 cap = state->cap;
1180 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1181 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1182 memcpy(cap, &tmp->cap, len);
1183 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1184 }
1185 /* Empty cap_save terminates list */
1186
1187 return state;
1188}
1189EXPORT_SYMBOL_GPL(pci_store_saved_state);
1190
1191/**
1192 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1193 * @dev: PCI device that we're dealing with
1194 * @state: Saved state returned from pci_store_saved_state()
1195 */
1196int pci_load_saved_state(struct pci_dev *dev,
1197 struct pci_saved_state *state)
1198{
1199 struct pci_cap_saved_data *cap;
1200
1201 dev->state_saved = false;
1202
1203 if (!state)
1204 return 0;
1205
1206 memcpy(dev->saved_config_space, state->config_space,
1207 sizeof(state->config_space));
1208
1209 cap = state->cap;
1210 while (cap->size) {
1211 struct pci_cap_saved_state *tmp;
1212
1213 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1214 if (!tmp || tmp->cap.size != cap->size)
1215 return -EINVAL;
1216
1217 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1218 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1219 sizeof(struct pci_cap_saved_data) + cap->size);
1220 }
1221
1222 dev->state_saved = true;
1223 return 0;
1224}
1225EXPORT_SYMBOL_GPL(pci_load_saved_state);
1226
1227/**
1228 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1229 * and free the memory allocated for it.
1230 * @dev: PCI device that we're dealing with
1231 * @state: Pointer to saved state returned from pci_store_saved_state()
1232 */
1233int pci_load_and_free_saved_state(struct pci_dev *dev,
1234 struct pci_saved_state **state)
1235{
1236 int ret = pci_load_saved_state(dev, *state);
1237 kfree(*state);
1238 *state = NULL;
1239 return ret;
1240}
1241EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1242
1243int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1244{
1245 return pci_enable_resources(dev, bars);
1246}
1247
1248static int do_pci_enable_device(struct pci_dev *dev, int bars)
1249{
1250 int err;
1251 struct pci_dev *bridge;
1252 u16 cmd;
1253 u8 pin;
1254
1255 err = pci_set_power_state(dev, PCI_D0);
1256 if (err < 0 && err != -EIO)
1257 return err;
1258
1259 bridge = pci_upstream_bridge(dev);
1260 if (bridge)
1261 pcie_aspm_powersave_config_link(bridge);
1262
1263 err = pcibios_enable_device(dev, bars);
1264 if (err < 0)
1265 return err;
1266 pci_fixup_device(pci_fixup_enable, dev);
1267
1268 if (dev->msi_enabled || dev->msix_enabled)
1269 return 0;
1270
1271 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1272 if (pin) {
1273 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1274 if (cmd & PCI_COMMAND_INTX_DISABLE)
1275 pci_write_config_word(dev, PCI_COMMAND,
1276 cmd & ~PCI_COMMAND_INTX_DISABLE);
1277 }
1278
1279 return 0;
1280}
1281
1282/**
1283 * pci_reenable_device - Resume abandoned device
1284 * @dev: PCI device to be resumed
1285 *
1286 * Note this function is a backend of pci_default_resume and is not supposed
1287 * to be called by normal code, write proper resume handler and use it instead.
1288 */
1289int pci_reenable_device(struct pci_dev *dev)
1290{
1291 if (pci_is_enabled(dev))
1292 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1293 return 0;
1294}
1295EXPORT_SYMBOL(pci_reenable_device);
1296
1297static void pci_enable_bridge(struct pci_dev *dev)
1298{
1299 struct pci_dev *bridge;
1300 int retval;
1301
1302 bridge = pci_upstream_bridge(dev);
1303 if (bridge)
1304 pci_enable_bridge(bridge);
1305
1306 if (pci_is_enabled(dev)) {
1307 if (!dev->is_busmaster)
1308 pci_set_master(dev);
1309 return;
1310 }
1311
1312 retval = pci_enable_device(dev);
1313 if (retval)
1314 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1315 retval);
1316 pci_set_master(dev);
1317}
1318
1319static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1320{
1321 struct pci_dev *bridge;
1322 int err;
1323 int i, bars = 0;
1324
1325 /*
1326 * Power state could be unknown at this point, either due to a fresh
1327 * boot or a device removal call. So get the current power state
1328 * so that things like MSI message writing will behave as expected
1329 * (e.g. if the device really is in D0 at enable time).
1330 */
1331 if (dev->pm_cap) {
1332 u16 pmcsr;
1333 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1334 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1335 }
1336
1337 if (atomic_inc_return(&dev->enable_cnt) > 1)
1338 return 0; /* already enabled */
1339
1340 bridge = pci_upstream_bridge(dev);
1341 if (bridge)
1342 pci_enable_bridge(bridge);
1343
1344 /* only skip sriov related */
1345 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1346 if (dev->resource[i].flags & flags)
1347 bars |= (1 << i);
1348 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1349 if (dev->resource[i].flags & flags)
1350 bars |= (1 << i);
1351
1352 err = do_pci_enable_device(dev, bars);
1353 if (err < 0)
1354 atomic_dec(&dev->enable_cnt);
1355 return err;
1356}
1357
1358/**
1359 * pci_enable_device_io - Initialize a device for use with IO space
1360 * @dev: PCI device to be initialized
1361 *
1362 * Initialize device before it's used by a driver. Ask low-level code
1363 * to enable I/O resources. Wake up the device if it was suspended.
1364 * Beware, this function can fail.
1365 */
1366int pci_enable_device_io(struct pci_dev *dev)
1367{
1368 return pci_enable_device_flags(dev, IORESOURCE_IO);
1369}
1370EXPORT_SYMBOL(pci_enable_device_io);
1371
1372/**
1373 * pci_enable_device_mem - Initialize a device for use with Memory space
1374 * @dev: PCI device to be initialized
1375 *
1376 * Initialize device before it's used by a driver. Ask low-level code
1377 * to enable Memory resources. Wake up the device if it was suspended.
1378 * Beware, this function can fail.
1379 */
1380int pci_enable_device_mem(struct pci_dev *dev)
1381{
1382 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1383}
1384EXPORT_SYMBOL(pci_enable_device_mem);
1385
1386/**
1387 * pci_enable_device - Initialize device before it's used by a driver.
1388 * @dev: PCI device to be initialized
1389 *
1390 * Initialize device before it's used by a driver. Ask low-level code
1391 * to enable I/O and memory. Wake up the device if it was suspended.
1392 * Beware, this function can fail.
1393 *
1394 * Note we don't actually enable the device many times if we call
1395 * this function repeatedly (we just increment the count).
1396 */
1397int pci_enable_device(struct pci_dev *dev)
1398{
1399 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1400}
1401EXPORT_SYMBOL(pci_enable_device);
1402
1403/*
1404 * Managed PCI resources. This manages device on/off, intx/msi/msix
1405 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1406 * there's no need to track it separately. pci_devres is initialized
1407 * when a device is enabled using managed PCI device enable interface.
1408 */
1409struct pci_devres {
1410 unsigned int enabled:1;
1411 unsigned int pinned:1;
1412 unsigned int orig_intx:1;
1413 unsigned int restore_intx:1;
1414 u32 region_mask;
1415};
1416
1417static void pcim_release(struct device *gendev, void *res)
1418{
1419 struct pci_dev *dev = to_pci_dev(gendev);
1420 struct pci_devres *this = res;
1421 int i;
1422
1423 if (dev->msi_enabled)
1424 pci_disable_msi(dev);
1425 if (dev->msix_enabled)
1426 pci_disable_msix(dev);
1427
1428 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1429 if (this->region_mask & (1 << i))
1430 pci_release_region(dev, i);
1431
1432 if (this->restore_intx)
1433 pci_intx(dev, this->orig_intx);
1434
1435 if (this->enabled && !this->pinned)
1436 pci_disable_device(dev);
1437}
1438
1439static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1440{
1441 struct pci_devres *dr, *new_dr;
1442
1443 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1444 if (dr)
1445 return dr;
1446
1447 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1448 if (!new_dr)
1449 return NULL;
1450 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1451}
1452
1453static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1454{
1455 if (pci_is_managed(pdev))
1456 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1457 return NULL;
1458}
1459
1460/**
1461 * pcim_enable_device - Managed pci_enable_device()
1462 * @pdev: PCI device to be initialized
1463 *
1464 * Managed pci_enable_device().
1465 */
1466int pcim_enable_device(struct pci_dev *pdev)
1467{
1468 struct pci_devres *dr;
1469 int rc;
1470
1471 dr = get_pci_dr(pdev);
1472 if (unlikely(!dr))
1473 return -ENOMEM;
1474 if (dr->enabled)
1475 return 0;
1476
1477 rc = pci_enable_device(pdev);
1478 if (!rc) {
1479 pdev->is_managed = 1;
1480 dr->enabled = 1;
1481 }
1482 return rc;
1483}
1484EXPORT_SYMBOL(pcim_enable_device);
1485
1486/**
1487 * pcim_pin_device - Pin managed PCI device
1488 * @pdev: PCI device to pin
1489 *
1490 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1491 * driver detach. @pdev must have been enabled with
1492 * pcim_enable_device().
1493 */
1494void pcim_pin_device(struct pci_dev *pdev)
1495{
1496 struct pci_devres *dr;
1497
1498 dr = find_pci_dr(pdev);
1499 WARN_ON(!dr || !dr->enabled);
1500 if (dr)
1501 dr->pinned = 1;
1502}
1503EXPORT_SYMBOL(pcim_pin_device);
1504
1505/*
1506 * pcibios_add_device - provide arch specific hooks when adding device dev
1507 * @dev: the PCI device being added
1508 *
1509 * Permits the platform to provide architecture specific functionality when
1510 * devices are added. This is the default implementation. Architecture
1511 * implementations can override this.
1512 */
1513int __weak pcibios_add_device(struct pci_dev *dev)
1514{
1515 return 0;
1516}
1517
1518/**
1519 * pcibios_release_device - provide arch specific hooks when releasing device dev
1520 * @dev: the PCI device being released
1521 *
1522 * Permits the platform to provide architecture specific functionality when
1523 * devices are released. This is the default implementation. Architecture
1524 * implementations can override this.
1525 */
1526void __weak pcibios_release_device(struct pci_dev *dev) {}
1527
1528/**
1529 * pcibios_disable_device - disable arch specific PCI resources for device dev
1530 * @dev: the PCI device to disable
1531 *
1532 * Disables architecture specific PCI resources for the device. This
1533 * is the default implementation. Architecture implementations can
1534 * override this.
1535 */
1536void __weak pcibios_disable_device(struct pci_dev *dev) {}
1537
1538/**
1539 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1540 * @irq: ISA IRQ to penalize
1541 * @active: IRQ active or not
1542 *
1543 * Permits the platform to provide architecture-specific functionality when
1544 * penalizing ISA IRQs. This is the default implementation. Architecture
1545 * implementations can override this.
1546 */
1547void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1548
1549static void do_pci_disable_device(struct pci_dev *dev)
1550{
1551 u16 pci_command;
1552
1553 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1554 if (pci_command & PCI_COMMAND_MASTER) {
1555 pci_command &= ~PCI_COMMAND_MASTER;
1556 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1557 }
1558
1559 pcibios_disable_device(dev);
1560}
1561
1562/**
1563 * pci_disable_enabled_device - Disable device without updating enable_cnt
1564 * @dev: PCI device to disable
1565 *
1566 * NOTE: This function is a backend of PCI power management routines and is
1567 * not supposed to be called drivers.
1568 */
1569void pci_disable_enabled_device(struct pci_dev *dev)
1570{
1571 if (pci_is_enabled(dev))
1572 do_pci_disable_device(dev);
1573}
1574
1575/**
1576 * pci_disable_device - Disable PCI device after use
1577 * @dev: PCI device to be disabled
1578 *
1579 * Signal to the system that the PCI device is not in use by the system
1580 * anymore. This only involves disabling PCI bus-mastering, if active.
1581 *
1582 * Note we don't actually disable the device until all callers of
1583 * pci_enable_device() have called pci_disable_device().
1584 */
1585void pci_disable_device(struct pci_dev *dev)
1586{
1587 struct pci_devres *dr;
1588
1589 dr = find_pci_dr(dev);
1590 if (dr)
1591 dr->enabled = 0;
1592
1593 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1594 "disabling already-disabled device");
1595
1596 if (atomic_dec_return(&dev->enable_cnt) != 0)
1597 return;
1598
1599 do_pci_disable_device(dev);
1600
1601 dev->is_busmaster = 0;
1602}
1603EXPORT_SYMBOL(pci_disable_device);
1604
1605/**
1606 * pcibios_set_pcie_reset_state - set reset state for device dev
1607 * @dev: the PCIe device reset
1608 * @state: Reset state to enter into
1609 *
1610 *
1611 * Sets the PCIe reset state for the device. This is the default
1612 * implementation. Architecture implementations can override this.
1613 */
1614int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1615 enum pcie_reset_state state)
1616{
1617 return -EINVAL;
1618}
1619
1620/**
1621 * pci_set_pcie_reset_state - set reset state for device dev
1622 * @dev: the PCIe device reset
1623 * @state: Reset state to enter into
1624 *
1625 *
1626 * Sets the PCI reset state for the device.
1627 */
1628int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1629{
1630 return pcibios_set_pcie_reset_state(dev, state);
1631}
1632EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1633
1634/**
1635 * pci_check_pme_status - Check if given device has generated PME.
1636 * @dev: Device to check.
1637 *
1638 * Check the PME status of the device and if set, clear it and clear PME enable
1639 * (if set). Return 'true' if PME status and PME enable were both set or
1640 * 'false' otherwise.
1641 */
1642bool pci_check_pme_status(struct pci_dev *dev)
1643{
1644 int pmcsr_pos;
1645 u16 pmcsr;
1646 bool ret = false;
1647
1648 if (!dev->pm_cap)
1649 return false;
1650
1651 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1652 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1653 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1654 return false;
1655
1656 /* Clear PME status. */
1657 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1658 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1659 /* Disable PME to avoid interrupt flood. */
1660 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1661 ret = true;
1662 }
1663
1664 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1665
1666 return ret;
1667}
1668
1669/**
1670 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1671 * @dev: Device to handle.
1672 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1673 *
1674 * Check if @dev has generated PME and queue a resume request for it in that
1675 * case.
1676 */
1677static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1678{
1679 if (pme_poll_reset && dev->pme_poll)
1680 dev->pme_poll = false;
1681
1682 if (pci_check_pme_status(dev)) {
1683 pci_wakeup_event(dev);
1684 pm_request_resume(&dev->dev);
1685 }
1686 return 0;
1687}
1688
1689/**
1690 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1691 * @bus: Top bus of the subtree to walk.
1692 */
1693void pci_pme_wakeup_bus(struct pci_bus *bus)
1694{
1695 if (bus)
1696 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1697}
1698
1699
1700/**
1701 * pci_pme_capable - check the capability of PCI device to generate PME#
1702 * @dev: PCI device to handle.
1703 * @state: PCI state from which device will issue PME#.
1704 */
1705bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1706{
1707 if (!dev->pm_cap)
1708 return false;
1709
1710 return !!(dev->pme_support & (1 << state));
1711}
1712EXPORT_SYMBOL(pci_pme_capable);
1713
1714static void pci_pme_list_scan(struct work_struct *work)
1715{
1716 struct pci_pme_device *pme_dev, *n;
1717
1718 mutex_lock(&pci_pme_list_mutex);
1719 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1720 if (pme_dev->dev->pme_poll) {
1721 struct pci_dev *bridge;
1722
1723 bridge = pme_dev->dev->bus->self;
1724 /*
1725 * If bridge is in low power state, the
1726 * configuration space of subordinate devices
1727 * may be not accessible
1728 */
1729 if (bridge && bridge->current_state != PCI_D0)
1730 continue;
1731 pci_pme_wakeup(pme_dev->dev, NULL);
1732 } else {
1733 list_del(&pme_dev->list);
1734 kfree(pme_dev);
1735 }
1736 }
1737 if (!list_empty(&pci_pme_list))
1738 schedule_delayed_work(&pci_pme_work,
1739 msecs_to_jiffies(PME_TIMEOUT));
1740 mutex_unlock(&pci_pme_list_mutex);
1741}
1742
1743static void __pci_pme_active(struct pci_dev *dev, bool enable)
1744{
1745 u16 pmcsr;
1746
1747 if (!dev->pme_support)
1748 return;
1749
1750 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1751 /* Clear PME_Status by writing 1 to it and enable PME# */
1752 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1753 if (!enable)
1754 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1755
1756 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1757}
1758
1759/**
1760 * pci_pme_active - enable or disable PCI device's PME# function
1761 * @dev: PCI device to handle.
1762 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1763 *
1764 * The caller must verify that the device is capable of generating PME# before
1765 * calling this function with @enable equal to 'true'.
1766 */
1767void pci_pme_active(struct pci_dev *dev, bool enable)
1768{
1769 __pci_pme_active(dev, enable);
1770
1771 /*
1772 * PCI (as opposed to PCIe) PME requires that the device have
1773 * its PME# line hooked up correctly. Not all hardware vendors
1774 * do this, so the PME never gets delivered and the device
1775 * remains asleep. The easiest way around this is to
1776 * periodically walk the list of suspended devices and check
1777 * whether any have their PME flag set. The assumption is that
1778 * we'll wake up often enough anyway that this won't be a huge
1779 * hit, and the power savings from the devices will still be a
1780 * win.
1781 *
1782 * Although PCIe uses in-band PME message instead of PME# line
1783 * to report PME, PME does not work for some PCIe devices in
1784 * reality. For example, there are devices that set their PME
1785 * status bits, but don't really bother to send a PME message;
1786 * there are PCI Express Root Ports that don't bother to
1787 * trigger interrupts when they receive PME messages from the
1788 * devices below. So PME poll is used for PCIe devices too.
1789 */
1790
1791 if (dev->pme_poll) {
1792 struct pci_pme_device *pme_dev;
1793 if (enable) {
1794 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1795 GFP_KERNEL);
1796 if (!pme_dev) {
1797 dev_warn(&dev->dev, "can't enable PME#\n");
1798 return;
1799 }
1800 pme_dev->dev = dev;
1801 mutex_lock(&pci_pme_list_mutex);
1802 list_add(&pme_dev->list, &pci_pme_list);
1803 if (list_is_singular(&pci_pme_list))
1804 schedule_delayed_work(&pci_pme_work,
1805 msecs_to_jiffies(PME_TIMEOUT));
1806 mutex_unlock(&pci_pme_list_mutex);
1807 } else {
1808 mutex_lock(&pci_pme_list_mutex);
1809 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1810 if (pme_dev->dev == dev) {
1811 list_del(&pme_dev->list);
1812 kfree(pme_dev);
1813 break;
1814 }
1815 }
1816 mutex_unlock(&pci_pme_list_mutex);
1817 }
1818 }
1819
1820 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1821}
1822EXPORT_SYMBOL(pci_pme_active);
1823
1824/**
1825 * __pci_enable_wake - enable PCI device as wakeup event source
1826 * @dev: PCI device affected
1827 * @state: PCI state from which device will issue wakeup events
1828 * @runtime: True if the events are to be generated at run time
1829 * @enable: True to enable event generation; false to disable
1830 *
1831 * This enables the device as a wakeup event source, or disables it.
1832 * When such events involves platform-specific hooks, those hooks are
1833 * called automatically by this routine.
1834 *
1835 * Devices with legacy power management (no standard PCI PM capabilities)
1836 * always require such platform hooks.
1837 *
1838 * RETURN VALUE:
1839 * 0 is returned on success
1840 * -EINVAL is returned if device is not supposed to wake up the system
1841 * Error code depending on the platform is returned if both the platform and
1842 * the native mechanism fail to enable the generation of wake-up events
1843 */
1844int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1845 bool runtime, bool enable)
1846{
1847 int ret = 0;
1848
1849 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1850 return -EINVAL;
1851
1852 /* Don't do the same thing twice in a row for one device. */
1853 if (!!enable == !!dev->wakeup_prepared)
1854 return 0;
1855
1856 /*
1857 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1858 * Anderson we should be doing PME# wake enable followed by ACPI wake
1859 * enable. To disable wake-up we call the platform first, for symmetry.
1860 */
1861
1862 if (enable) {
1863 int error;
1864
1865 if (pci_pme_capable(dev, state))
1866 pci_pme_active(dev, true);
1867 else
1868 ret = 1;
1869 error = runtime ? platform_pci_run_wake(dev, true) :
1870 platform_pci_sleep_wake(dev, true);
1871 if (ret)
1872 ret = error;
1873 if (!ret)
1874 dev->wakeup_prepared = true;
1875 } else {
1876 if (runtime)
1877 platform_pci_run_wake(dev, false);
1878 else
1879 platform_pci_sleep_wake(dev, false);
1880 pci_pme_active(dev, false);
1881 dev->wakeup_prepared = false;
1882 }
1883
1884 return ret;
1885}
1886EXPORT_SYMBOL(__pci_enable_wake);
1887
1888/**
1889 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1890 * @dev: PCI device to prepare
1891 * @enable: True to enable wake-up event generation; false to disable
1892 *
1893 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1894 * and this function allows them to set that up cleanly - pci_enable_wake()
1895 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1896 * ordering constraints.
1897 *
1898 * This function only returns error code if the device is not capable of
1899 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1900 * enable wake-up power for it.
1901 */
1902int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1903{
1904 return pci_pme_capable(dev, PCI_D3cold) ?
1905 pci_enable_wake(dev, PCI_D3cold, enable) :
1906 pci_enable_wake(dev, PCI_D3hot, enable);
1907}
1908EXPORT_SYMBOL(pci_wake_from_d3);
1909
1910/**
1911 * pci_target_state - find an appropriate low power state for a given PCI dev
1912 * @dev: PCI device
1913 *
1914 * Use underlying platform code to find a supported low power state for @dev.
1915 * If the platform can't manage @dev, return the deepest state from which it
1916 * can generate wake events, based on any available PME info.
1917 */
1918static pci_power_t pci_target_state(struct pci_dev *dev)
1919{
1920 pci_power_t target_state = PCI_D3hot;
1921
1922 if (platform_pci_power_manageable(dev)) {
1923 /*
1924 * Call the platform to choose the target state of the device
1925 * and enable wake-up from this state if supported.
1926 */
1927 pci_power_t state = platform_pci_choose_state(dev);
1928
1929 switch (state) {
1930 case PCI_POWER_ERROR:
1931 case PCI_UNKNOWN:
1932 break;
1933 case PCI_D1:
1934 case PCI_D2:
1935 if (pci_no_d1d2(dev))
1936 break;
1937 default:
1938 target_state = state;
1939 }
1940 } else if (!dev->pm_cap) {
1941 target_state = PCI_D0;
1942 } else if (device_may_wakeup(&dev->dev)) {
1943 /*
1944 * Find the deepest state from which the device can generate
1945 * wake-up events, make it the target state and enable device
1946 * to generate PME#.
1947 */
1948 if (dev->pme_support) {
1949 while (target_state
1950 && !(dev->pme_support & (1 << target_state)))
1951 target_state--;
1952 }
1953 }
1954
1955 return target_state;
1956}
1957
1958/**
1959 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1960 * @dev: Device to handle.
1961 *
1962 * Choose the power state appropriate for the device depending on whether
1963 * it can wake up the system and/or is power manageable by the platform
1964 * (PCI_D3hot is the default) and put the device into that state.
1965 */
1966int pci_prepare_to_sleep(struct pci_dev *dev)
1967{
1968 pci_power_t target_state = pci_target_state(dev);
1969 int error;
1970
1971 if (target_state == PCI_POWER_ERROR)
1972 return -EIO;
1973
1974 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1975
1976 error = pci_set_power_state(dev, target_state);
1977
1978 if (error)
1979 pci_enable_wake(dev, target_state, false);
1980
1981 return error;
1982}
1983EXPORT_SYMBOL(pci_prepare_to_sleep);
1984
1985/**
1986 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1987 * @dev: Device to handle.
1988 *
1989 * Disable device's system wake-up capability and put it into D0.
1990 */
1991int pci_back_from_sleep(struct pci_dev *dev)
1992{
1993 pci_enable_wake(dev, PCI_D0, false);
1994 return pci_set_power_state(dev, PCI_D0);
1995}
1996EXPORT_SYMBOL(pci_back_from_sleep);
1997
1998/**
1999 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2000 * @dev: PCI device being suspended.
2001 *
2002 * Prepare @dev to generate wake-up events at run time and put it into a low
2003 * power state.
2004 */
2005int pci_finish_runtime_suspend(struct pci_dev *dev)
2006{
2007 pci_power_t target_state = pci_target_state(dev);
2008 int error;
2009
2010 if (target_state == PCI_POWER_ERROR)
2011 return -EIO;
2012
2013 dev->runtime_d3cold = target_state == PCI_D3cold;
2014
2015 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
2016
2017 error = pci_set_power_state(dev, target_state);
2018
2019 if (error) {
2020 __pci_enable_wake(dev, target_state, true, false);
2021 dev->runtime_d3cold = false;
2022 }
2023
2024 return error;
2025}
2026
2027/**
2028 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2029 * @dev: Device to check.
2030 *
2031 * Return true if the device itself is capable of generating wake-up events
2032 * (through the platform or using the native PCIe PME) or if the device supports
2033 * PME and one of its upstream bridges can generate wake-up events.
2034 */
2035bool pci_dev_run_wake(struct pci_dev *dev)
2036{
2037 struct pci_bus *bus = dev->bus;
2038
2039 if (device_run_wake(&dev->dev))
2040 return true;
2041
2042 if (!dev->pme_support)
2043 return false;
2044
2045 while (bus->parent) {
2046 struct pci_dev *bridge = bus->self;
2047
2048 if (device_run_wake(&bridge->dev))
2049 return true;
2050
2051 bus = bus->parent;
2052 }
2053
2054 /* We have reached the root bus. */
2055 if (bus->bridge)
2056 return device_run_wake(bus->bridge);
2057
2058 return false;
2059}
2060EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2061
2062/**
2063 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2064 * @pci_dev: Device to check.
2065 *
2066 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2067 * reconfigured due to wakeup settings difference between system and runtime
2068 * suspend and the current power state of it is suitable for the upcoming
2069 * (system) transition.
2070 *
2071 * If the device is not configured for system wakeup, disable PME for it before
2072 * returning 'true' to prevent it from waking up the system unnecessarily.
2073 */
2074bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2075{
2076 struct device *dev = &pci_dev->dev;
2077
2078 if (!pm_runtime_suspended(dev)
2079 || pci_target_state(pci_dev) != pci_dev->current_state
2080 || platform_pci_need_resume(pci_dev))
2081 return false;
2082
2083 /*
2084 * At this point the device is good to go unless it's been configured
2085 * to generate PME at the runtime suspend time, but it is not supposed
2086 * to wake up the system. In that case, simply disable PME for it
2087 * (it will have to be re-enabled on exit from system resume).
2088 *
2089 * If the device's power state is D3cold and the platform check above
2090 * hasn't triggered, the device's configuration is suitable and we don't
2091 * need to manipulate it at all.
2092 */
2093 spin_lock_irq(&dev->power.lock);
2094
2095 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2096 !device_may_wakeup(dev))
2097 __pci_pme_active(pci_dev, false);
2098
2099 spin_unlock_irq(&dev->power.lock);
2100 return true;
2101}
2102
2103/**
2104 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2105 * @pci_dev: Device to handle.
2106 *
2107 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2108 * it might have been disabled during the prepare phase of system suspend if
2109 * the device was not configured for system wakeup.
2110 */
2111void pci_dev_complete_resume(struct pci_dev *pci_dev)
2112{
2113 struct device *dev = &pci_dev->dev;
2114
2115 if (!pci_dev_run_wake(pci_dev))
2116 return;
2117
2118 spin_lock_irq(&dev->power.lock);
2119
2120 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2121 __pci_pme_active(pci_dev, true);
2122
2123 spin_unlock_irq(&dev->power.lock);
2124}
2125
2126void pci_config_pm_runtime_get(struct pci_dev *pdev)
2127{
2128 struct device *dev = &pdev->dev;
2129 struct device *parent = dev->parent;
2130
2131 if (parent)
2132 pm_runtime_get_sync(parent);
2133 pm_runtime_get_noresume(dev);
2134 /*
2135 * pdev->current_state is set to PCI_D3cold during suspending,
2136 * so wait until suspending completes
2137 */
2138 pm_runtime_barrier(dev);
2139 /*
2140 * Only need to resume devices in D3cold, because config
2141 * registers are still accessible for devices suspended but
2142 * not in D3cold.
2143 */
2144 if (pdev->current_state == PCI_D3cold)
2145 pm_runtime_resume(dev);
2146}
2147
2148void pci_config_pm_runtime_put(struct pci_dev *pdev)
2149{
2150 struct device *dev = &pdev->dev;
2151 struct device *parent = dev->parent;
2152
2153 pm_runtime_put(dev);
2154 if (parent)
2155 pm_runtime_put_sync(parent);
2156}
2157
2158/**
2159 * pci_pm_init - Initialize PM functions of given PCI device
2160 * @dev: PCI device to handle.
2161 */
2162void pci_pm_init(struct pci_dev *dev)
2163{
2164 int pm;
2165 u16 pmc;
2166
2167 pm_runtime_forbid(&dev->dev);
2168 pm_runtime_set_active(&dev->dev);
2169 pm_runtime_enable(&dev->dev);
2170 device_enable_async_suspend(&dev->dev);
2171 dev->wakeup_prepared = false;
2172
2173 dev->pm_cap = 0;
2174 dev->pme_support = 0;
2175
2176 /* find PCI PM capability in list */
2177 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2178 if (!pm)
2179 return;
2180 /* Check device's ability to generate PME# */
2181 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2182
2183 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2184 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2185 pmc & PCI_PM_CAP_VER_MASK);
2186 return;
2187 }
2188
2189 dev->pm_cap = pm;
2190 dev->d3_delay = PCI_PM_D3_WAIT;
2191 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2192 dev->d3cold_allowed = true;
2193
2194 dev->d1_support = false;
2195 dev->d2_support = false;
2196 if (!pci_no_d1d2(dev)) {
2197 if (pmc & PCI_PM_CAP_D1)
2198 dev->d1_support = true;
2199 if (pmc & PCI_PM_CAP_D2)
2200 dev->d2_support = true;
2201
2202 if (dev->d1_support || dev->d2_support)
2203 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2204 dev->d1_support ? " D1" : "",
2205 dev->d2_support ? " D2" : "");
2206 }
2207
2208 pmc &= PCI_PM_CAP_PME_MASK;
2209 if (pmc) {
2210 dev_printk(KERN_DEBUG, &dev->dev,
2211 "PME# supported from%s%s%s%s%s\n",
2212 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2213 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2214 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2215 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2216 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2217 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2218 dev->pme_poll = true;
2219 /*
2220 * Make device's PM flags reflect the wake-up capability, but
2221 * let the user space enable it to wake up the system as needed.
2222 */
2223 device_set_wakeup_capable(&dev->dev, true);
2224 /* Disable the PME# generation functionality */
2225 pci_pme_active(dev, false);
2226 }
2227}
2228
2229static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2230{
2231 unsigned long flags = IORESOURCE_PCI_FIXED;
2232
2233 switch (prop) {
2234 case PCI_EA_P_MEM:
2235 case PCI_EA_P_VF_MEM:
2236 flags |= IORESOURCE_MEM;
2237 break;
2238 case PCI_EA_P_MEM_PREFETCH:
2239 case PCI_EA_P_VF_MEM_PREFETCH:
2240 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2241 break;
2242 case PCI_EA_P_IO:
2243 flags |= IORESOURCE_IO;
2244 break;
2245 default:
2246 return 0;
2247 }
2248
2249 return flags;
2250}
2251
2252static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2253 u8 prop)
2254{
2255 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2256 return &dev->resource[bei];
2257#ifdef CONFIG_PCI_IOV
2258 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2259 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2260 return &dev->resource[PCI_IOV_RESOURCES +
2261 bei - PCI_EA_BEI_VF_BAR0];
2262#endif
2263 else if (bei == PCI_EA_BEI_ROM)
2264 return &dev->resource[PCI_ROM_RESOURCE];
2265 else
2266 return NULL;
2267}
2268
2269/* Read an Enhanced Allocation (EA) entry */
2270static int pci_ea_read(struct pci_dev *dev, int offset)
2271{
2272 struct resource *res;
2273 int ent_size, ent_offset = offset;
2274 resource_size_t start, end;
2275 unsigned long flags;
2276 u32 dw0, bei, base, max_offset;
2277 u8 prop;
2278 bool support_64 = (sizeof(resource_size_t) >= 8);
2279
2280 pci_read_config_dword(dev, ent_offset, &dw0);
2281 ent_offset += 4;
2282
2283 /* Entry size field indicates DWORDs after 1st */
2284 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2285
2286 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2287 goto out;
2288
2289 bei = (dw0 & PCI_EA_BEI) >> 4;
2290 prop = (dw0 & PCI_EA_PP) >> 8;
2291
2292 /*
2293 * If the Property is in the reserved range, try the Secondary
2294 * Property instead.
2295 */
2296 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2297 prop = (dw0 & PCI_EA_SP) >> 16;
2298 if (prop > PCI_EA_P_BRIDGE_IO)
2299 goto out;
2300
2301 res = pci_ea_get_resource(dev, bei, prop);
2302 if (!res) {
2303 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2304 goto out;
2305 }
2306
2307 flags = pci_ea_flags(dev, prop);
2308 if (!flags) {
2309 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2310 goto out;
2311 }
2312
2313 /* Read Base */
2314 pci_read_config_dword(dev, ent_offset, &base);
2315 start = (base & PCI_EA_FIELD_MASK);
2316 ent_offset += 4;
2317
2318 /* Read MaxOffset */
2319 pci_read_config_dword(dev, ent_offset, &max_offset);
2320 ent_offset += 4;
2321
2322 /* Read Base MSBs (if 64-bit entry) */
2323 if (base & PCI_EA_IS_64) {
2324 u32 base_upper;
2325
2326 pci_read_config_dword(dev, ent_offset, &base_upper);
2327 ent_offset += 4;
2328
2329 flags |= IORESOURCE_MEM_64;
2330
2331 /* entry starts above 32-bit boundary, can't use */
2332 if (!support_64 && base_upper)
2333 goto out;
2334
2335 if (support_64)
2336 start |= ((u64)base_upper << 32);
2337 }
2338
2339 end = start + (max_offset | 0x03);
2340
2341 /* Read MaxOffset MSBs (if 64-bit entry) */
2342 if (max_offset & PCI_EA_IS_64) {
2343 u32 max_offset_upper;
2344
2345 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2346 ent_offset += 4;
2347
2348 flags |= IORESOURCE_MEM_64;
2349
2350 /* entry too big, can't use */
2351 if (!support_64 && max_offset_upper)
2352 goto out;
2353
2354 if (support_64)
2355 end += ((u64)max_offset_upper << 32);
2356 }
2357
2358 if (end < start) {
2359 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2360 goto out;
2361 }
2362
2363 if (ent_size != ent_offset - offset) {
2364 dev_err(&dev->dev,
2365 "EA Entry Size (%d) does not match length read (%d)\n",
2366 ent_size, ent_offset - offset);
2367 goto out;
2368 }
2369
2370 res->name = pci_name(dev);
2371 res->start = start;
2372 res->end = end;
2373 res->flags = flags;
2374
2375 if (bei <= PCI_EA_BEI_BAR5)
2376 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2377 bei, res, prop);
2378 else if (bei == PCI_EA_BEI_ROM)
2379 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2380 res, prop);
2381 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2382 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2383 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2384 else
2385 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2386 bei, res, prop);
2387
2388out:
2389 return offset + ent_size;
2390}
2391
2392/* Enhanced Allocation Initalization */
2393void pci_ea_init(struct pci_dev *dev)
2394{
2395 int ea;
2396 u8 num_ent;
2397 int offset;
2398 int i;
2399
2400 /* find PCI EA capability in list */
2401 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2402 if (!ea)
2403 return;
2404
2405 /* determine the number of entries */
2406 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2407 &num_ent);
2408 num_ent &= PCI_EA_NUM_ENT_MASK;
2409
2410 offset = ea + PCI_EA_FIRST_ENT;
2411
2412 /* Skip DWORD 2 for type 1 functions */
2413 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2414 offset += 4;
2415
2416 /* parse each EA entry */
2417 for (i = 0; i < num_ent; ++i)
2418 offset = pci_ea_read(dev, offset);
2419}
2420
2421static void pci_add_saved_cap(struct pci_dev *pci_dev,
2422 struct pci_cap_saved_state *new_cap)
2423{
2424 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2425}
2426
2427/**
2428 * _pci_add_cap_save_buffer - allocate buffer for saving given
2429 * capability registers
2430 * @dev: the PCI device
2431 * @cap: the capability to allocate the buffer for
2432 * @extended: Standard or Extended capability ID
2433 * @size: requested size of the buffer
2434 */
2435static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2436 bool extended, unsigned int size)
2437{
2438 int pos;
2439 struct pci_cap_saved_state *save_state;
2440
2441 if (extended)
2442 pos = pci_find_ext_capability(dev, cap);
2443 else
2444 pos = pci_find_capability(dev, cap);
2445
2446 if (!pos)
2447 return 0;
2448
2449 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2450 if (!save_state)
2451 return -ENOMEM;
2452
2453 save_state->cap.cap_nr = cap;
2454 save_state->cap.cap_extended = extended;
2455 save_state->cap.size = size;
2456 pci_add_saved_cap(dev, save_state);
2457
2458 return 0;
2459}
2460
2461int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2462{
2463 return _pci_add_cap_save_buffer(dev, cap, false, size);
2464}
2465
2466int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2467{
2468 return _pci_add_cap_save_buffer(dev, cap, true, size);
2469}
2470
2471/**
2472 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2473 * @dev: the PCI device
2474 */
2475void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2476{
2477 int error;
2478
2479 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2480 PCI_EXP_SAVE_REGS * sizeof(u16));
2481 if (error)
2482 dev_err(&dev->dev,
2483 "unable to preallocate PCI Express save buffer\n");
2484
2485 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2486 if (error)
2487 dev_err(&dev->dev,
2488 "unable to preallocate PCI-X save buffer\n");
2489
2490 pci_allocate_vc_save_buffers(dev);
2491}
2492
2493void pci_free_cap_save_buffers(struct pci_dev *dev)
2494{
2495 struct pci_cap_saved_state *tmp;
2496 struct hlist_node *n;
2497
2498 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2499 kfree(tmp);
2500}
2501
2502/**
2503 * pci_configure_ari - enable or disable ARI forwarding
2504 * @dev: the PCI device
2505 *
2506 * If @dev and its upstream bridge both support ARI, enable ARI in the
2507 * bridge. Otherwise, disable ARI in the bridge.
2508 */
2509void pci_configure_ari(struct pci_dev *dev)
2510{
2511 u32 cap;
2512 struct pci_dev *bridge;
2513
2514 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2515 return;
2516
2517 bridge = dev->bus->self;
2518 if (!bridge)
2519 return;
2520
2521 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2522 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2523 return;
2524
2525 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2526 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2527 PCI_EXP_DEVCTL2_ARI);
2528 bridge->ari_enabled = 1;
2529 } else {
2530 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2531 PCI_EXP_DEVCTL2_ARI);
2532 bridge->ari_enabled = 0;
2533 }
2534}
2535
2536static int pci_acs_enable;
2537
2538/**
2539 * pci_request_acs - ask for ACS to be enabled if supported
2540 */
2541void pci_request_acs(void)
2542{
2543 pci_acs_enable = 1;
2544}
2545
2546/**
2547 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2548 * @dev: the PCI device
2549 */
2550static int pci_std_enable_acs(struct pci_dev *dev)
2551{
2552 int pos;
2553 u16 cap;
2554 u16 ctrl;
2555
2556 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2557 if (!pos)
2558 return -ENODEV;
2559
2560 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2561 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2562
2563 /* Source Validation */
2564 ctrl |= (cap & PCI_ACS_SV);
2565
2566 /* P2P Request Redirect */
2567 ctrl |= (cap & PCI_ACS_RR);
2568
2569 /* P2P Completion Redirect */
2570 ctrl |= (cap & PCI_ACS_CR);
2571
2572 /* Upstream Forwarding */
2573 ctrl |= (cap & PCI_ACS_UF);
2574
2575 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2576
2577 return 0;
2578}
2579
2580/**
2581 * pci_enable_acs - enable ACS if hardware support it
2582 * @dev: the PCI device
2583 */
2584void pci_enable_acs(struct pci_dev *dev)
2585{
2586 if (!pci_acs_enable)
2587 return;
2588
2589 if (!pci_std_enable_acs(dev))
2590 return;
2591
2592 pci_dev_specific_enable_acs(dev);
2593}
2594
2595static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2596{
2597 int pos;
2598 u16 cap, ctrl;
2599
2600 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2601 if (!pos)
2602 return false;
2603
2604 /*
2605 * Except for egress control, capabilities are either required
2606 * or only required if controllable. Features missing from the
2607 * capability field can therefore be assumed as hard-wired enabled.
2608 */
2609 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2610 acs_flags &= (cap | PCI_ACS_EC);
2611
2612 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2613 return (ctrl & acs_flags) == acs_flags;
2614}
2615
2616/**
2617 * pci_acs_enabled - test ACS against required flags for a given device
2618 * @pdev: device to test
2619 * @acs_flags: required PCI ACS flags
2620 *
2621 * Return true if the device supports the provided flags. Automatically
2622 * filters out flags that are not implemented on multifunction devices.
2623 *
2624 * Note that this interface checks the effective ACS capabilities of the
2625 * device rather than the actual capabilities. For instance, most single
2626 * function endpoints are not required to support ACS because they have no
2627 * opportunity for peer-to-peer access. We therefore return 'true'
2628 * regardless of whether the device exposes an ACS capability. This makes
2629 * it much easier for callers of this function to ignore the actual type
2630 * or topology of the device when testing ACS support.
2631 */
2632bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2633{
2634 int ret;
2635
2636 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2637 if (ret >= 0)
2638 return ret > 0;
2639
2640 /*
2641 * Conventional PCI and PCI-X devices never support ACS, either
2642 * effectively or actually. The shared bus topology implies that
2643 * any device on the bus can receive or snoop DMA.
2644 */
2645 if (!pci_is_pcie(pdev))
2646 return false;
2647
2648 switch (pci_pcie_type(pdev)) {
2649 /*
2650 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2651 * but since their primary interface is PCI/X, we conservatively
2652 * handle them as we would a non-PCIe device.
2653 */
2654 case PCI_EXP_TYPE_PCIE_BRIDGE:
2655 /*
2656 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2657 * applicable... must never implement an ACS Extended Capability...".
2658 * This seems arbitrary, but we take a conservative interpretation
2659 * of this statement.
2660 */
2661 case PCI_EXP_TYPE_PCI_BRIDGE:
2662 case PCI_EXP_TYPE_RC_EC:
2663 return false;
2664 /*
2665 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2666 * implement ACS in order to indicate their peer-to-peer capabilities,
2667 * regardless of whether they are single- or multi-function devices.
2668 */
2669 case PCI_EXP_TYPE_DOWNSTREAM:
2670 case PCI_EXP_TYPE_ROOT_PORT:
2671 return pci_acs_flags_enabled(pdev, acs_flags);
2672 /*
2673 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2674 * implemented by the remaining PCIe types to indicate peer-to-peer
2675 * capabilities, but only when they are part of a multifunction
2676 * device. The footnote for section 6.12 indicates the specific
2677 * PCIe types included here.
2678 */
2679 case PCI_EXP_TYPE_ENDPOINT:
2680 case PCI_EXP_TYPE_UPSTREAM:
2681 case PCI_EXP_TYPE_LEG_END:
2682 case PCI_EXP_TYPE_RC_END:
2683 if (!pdev->multifunction)
2684 break;
2685
2686 return pci_acs_flags_enabled(pdev, acs_flags);
2687 }
2688
2689 /*
2690 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2691 * to single function devices with the exception of downstream ports.
2692 */
2693 return true;
2694}
2695
2696/**
2697 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2698 * @start: starting downstream device
2699 * @end: ending upstream device or NULL to search to the root bus
2700 * @acs_flags: required flags
2701 *
2702 * Walk up a device tree from start to end testing PCI ACS support. If
2703 * any step along the way does not support the required flags, return false.
2704 */
2705bool pci_acs_path_enabled(struct pci_dev *start,
2706 struct pci_dev *end, u16 acs_flags)
2707{
2708 struct pci_dev *pdev, *parent = start;
2709
2710 do {
2711 pdev = parent;
2712
2713 if (!pci_acs_enabled(pdev, acs_flags))
2714 return false;
2715
2716 if (pci_is_root_bus(pdev->bus))
2717 return (end == NULL);
2718
2719 parent = pdev->bus->self;
2720 } while (pdev != end);
2721
2722 return true;
2723}
2724
2725/**
2726 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2727 * @dev: the PCI device
2728 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2729 *
2730 * Perform INTx swizzling for a device behind one level of bridge. This is
2731 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2732 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2733 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2734 * the PCI Express Base Specification, Revision 2.1)
2735 */
2736u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2737{
2738 int slot;
2739
2740 if (pci_ari_enabled(dev->bus))
2741 slot = 0;
2742 else
2743 slot = PCI_SLOT(dev->devfn);
2744
2745 return (((pin - 1) + slot) % 4) + 1;
2746}
2747
2748int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2749{
2750 u8 pin;
2751
2752 pin = dev->pin;
2753 if (!pin)
2754 return -1;
2755
2756 while (!pci_is_root_bus(dev->bus)) {
2757 pin = pci_swizzle_interrupt_pin(dev, pin);
2758 dev = dev->bus->self;
2759 }
2760 *bridge = dev;
2761 return pin;
2762}
2763
2764/**
2765 * pci_common_swizzle - swizzle INTx all the way to root bridge
2766 * @dev: the PCI device
2767 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2768 *
2769 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2770 * bridges all the way up to a PCI root bus.
2771 */
2772u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2773{
2774 u8 pin = *pinp;
2775
2776 while (!pci_is_root_bus(dev->bus)) {
2777 pin = pci_swizzle_interrupt_pin(dev, pin);
2778 dev = dev->bus->self;
2779 }
2780 *pinp = pin;
2781 return PCI_SLOT(dev->devfn);
2782}
2783EXPORT_SYMBOL_GPL(pci_common_swizzle);
2784
2785/**
2786 * pci_release_region - Release a PCI bar
2787 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2788 * @bar: BAR to release
2789 *
2790 * Releases the PCI I/O and memory resources previously reserved by a
2791 * successful call to pci_request_region. Call this function only
2792 * after all use of the PCI regions has ceased.
2793 */
2794void pci_release_region(struct pci_dev *pdev, int bar)
2795{
2796 struct pci_devres *dr;
2797
2798 if (pci_resource_len(pdev, bar) == 0)
2799 return;
2800 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2801 release_region(pci_resource_start(pdev, bar),
2802 pci_resource_len(pdev, bar));
2803 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2804 release_mem_region(pci_resource_start(pdev, bar),
2805 pci_resource_len(pdev, bar));
2806
2807 dr = find_pci_dr(pdev);
2808 if (dr)
2809 dr->region_mask &= ~(1 << bar);
2810}
2811EXPORT_SYMBOL(pci_release_region);
2812
2813/**
2814 * __pci_request_region - Reserved PCI I/O and memory resource
2815 * @pdev: PCI device whose resources are to be reserved
2816 * @bar: BAR to be reserved
2817 * @res_name: Name to be associated with resource.
2818 * @exclusive: whether the region access is exclusive or not
2819 *
2820 * Mark the PCI region associated with PCI device @pdev BR @bar as
2821 * being reserved by owner @res_name. Do not access any
2822 * address inside the PCI regions unless this call returns
2823 * successfully.
2824 *
2825 * If @exclusive is set, then the region is marked so that userspace
2826 * is explicitly not allowed to map the resource via /dev/mem or
2827 * sysfs MMIO access.
2828 *
2829 * Returns 0 on success, or %EBUSY on error. A warning
2830 * message is also printed on failure.
2831 */
2832static int __pci_request_region(struct pci_dev *pdev, int bar,
2833 const char *res_name, int exclusive)
2834{
2835 struct pci_devres *dr;
2836
2837 if (pci_resource_len(pdev, bar) == 0)
2838 return 0;
2839
2840 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2841 if (!request_region(pci_resource_start(pdev, bar),
2842 pci_resource_len(pdev, bar), res_name))
2843 goto err_out;
2844 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2845 if (!__request_mem_region(pci_resource_start(pdev, bar),
2846 pci_resource_len(pdev, bar), res_name,
2847 exclusive))
2848 goto err_out;
2849 }
2850
2851 dr = find_pci_dr(pdev);
2852 if (dr)
2853 dr->region_mask |= 1 << bar;
2854
2855 return 0;
2856
2857err_out:
2858 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2859 &pdev->resource[bar]);
2860 return -EBUSY;
2861}
2862
2863/**
2864 * pci_request_region - Reserve PCI I/O and memory resource
2865 * @pdev: PCI device whose resources are to be reserved
2866 * @bar: BAR to be reserved
2867 * @res_name: Name to be associated with resource
2868 *
2869 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2870 * being reserved by owner @res_name. Do not access any
2871 * address inside the PCI regions unless this call returns
2872 * successfully.
2873 *
2874 * Returns 0 on success, or %EBUSY on error. A warning
2875 * message is also printed on failure.
2876 */
2877int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2878{
2879 return __pci_request_region(pdev, bar, res_name, 0);
2880}
2881EXPORT_SYMBOL(pci_request_region);
2882
2883/**
2884 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2885 * @pdev: PCI device whose resources are to be reserved
2886 * @bar: BAR to be reserved
2887 * @res_name: Name to be associated with resource.
2888 *
2889 * Mark the PCI region associated with PCI device @pdev BR @bar as
2890 * being reserved by owner @res_name. Do not access any
2891 * address inside the PCI regions unless this call returns
2892 * successfully.
2893 *
2894 * Returns 0 on success, or %EBUSY on error. A warning
2895 * message is also printed on failure.
2896 *
2897 * The key difference that _exclusive makes it that userspace is
2898 * explicitly not allowed to map the resource via /dev/mem or
2899 * sysfs.
2900 */
2901int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
2902 const char *res_name)
2903{
2904 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2905}
2906EXPORT_SYMBOL(pci_request_region_exclusive);
2907
2908/**
2909 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2910 * @pdev: PCI device whose resources were previously reserved
2911 * @bars: Bitmask of BARs to be released
2912 *
2913 * Release selected PCI I/O and memory resources previously reserved.
2914 * Call this function only after all use of the PCI regions has ceased.
2915 */
2916void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2917{
2918 int i;
2919
2920 for (i = 0; i < 6; i++)
2921 if (bars & (1 << i))
2922 pci_release_region(pdev, i);
2923}
2924EXPORT_SYMBOL(pci_release_selected_regions);
2925
2926static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2927 const char *res_name, int excl)
2928{
2929 int i;
2930
2931 for (i = 0; i < 6; i++)
2932 if (bars & (1 << i))
2933 if (__pci_request_region(pdev, i, res_name, excl))
2934 goto err_out;
2935 return 0;
2936
2937err_out:
2938 while (--i >= 0)
2939 if (bars & (1 << i))
2940 pci_release_region(pdev, i);
2941
2942 return -EBUSY;
2943}
2944
2945
2946/**
2947 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2948 * @pdev: PCI device whose resources are to be reserved
2949 * @bars: Bitmask of BARs to be requested
2950 * @res_name: Name to be associated with resource
2951 */
2952int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2953 const char *res_name)
2954{
2955 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2956}
2957EXPORT_SYMBOL(pci_request_selected_regions);
2958
2959int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
2960 const char *res_name)
2961{
2962 return __pci_request_selected_regions(pdev, bars, res_name,
2963 IORESOURCE_EXCLUSIVE);
2964}
2965EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2966
2967/**
2968 * pci_release_regions - Release reserved PCI I/O and memory resources
2969 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2970 *
2971 * Releases all PCI I/O and memory resources previously reserved by a
2972 * successful call to pci_request_regions. Call this function only
2973 * after all use of the PCI regions has ceased.
2974 */
2975
2976void pci_release_regions(struct pci_dev *pdev)
2977{
2978 pci_release_selected_regions(pdev, (1 << 6) - 1);
2979}
2980EXPORT_SYMBOL(pci_release_regions);
2981
2982/**
2983 * pci_request_regions - Reserved PCI I/O and memory resources
2984 * @pdev: PCI device whose resources are to be reserved
2985 * @res_name: Name to be associated with resource.
2986 *
2987 * Mark all PCI regions associated with PCI device @pdev as
2988 * being reserved by owner @res_name. Do not access any
2989 * address inside the PCI regions unless this call returns
2990 * successfully.
2991 *
2992 * Returns 0 on success, or %EBUSY on error. A warning
2993 * message is also printed on failure.
2994 */
2995int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2996{
2997 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2998}
2999EXPORT_SYMBOL(pci_request_regions);
3000
3001/**
3002 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3003 * @pdev: PCI device whose resources are to be reserved
3004 * @res_name: Name to be associated with resource.
3005 *
3006 * Mark all PCI regions associated with PCI device @pdev as
3007 * being reserved by owner @res_name. Do not access any
3008 * address inside the PCI regions unless this call returns
3009 * successfully.
3010 *
3011 * pci_request_regions_exclusive() will mark the region so that
3012 * /dev/mem and the sysfs MMIO access will not be allowed.
3013 *
3014 * Returns 0 on success, or %EBUSY on error. A warning
3015 * message is also printed on failure.
3016 */
3017int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3018{
3019 return pci_request_selected_regions_exclusive(pdev,
3020 ((1 << 6) - 1), res_name);
3021}
3022EXPORT_SYMBOL(pci_request_regions_exclusive);
3023
3024/**
3025 * pci_remap_iospace - Remap the memory mapped I/O space
3026 * @res: Resource describing the I/O space
3027 * @phys_addr: physical address of range to be mapped
3028 *
3029 * Remap the memory mapped I/O space described by the @res
3030 * and the CPU physical address @phys_addr into virtual address space.
3031 * Only architectures that have memory mapped IO functions defined
3032 * (and the PCI_IOBASE value defined) should call this function.
3033 */
3034int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3035{
3036#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3037 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3038
3039 if (!(res->flags & IORESOURCE_IO))
3040 return -EINVAL;
3041
3042 if (res->end > IO_SPACE_LIMIT)
3043 return -EINVAL;
3044
3045 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3046 pgprot_device(PAGE_KERNEL));
3047#else
3048 /* this architecture does not have memory mapped I/O space,
3049 so this function should never be called */
3050 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3051 return -ENODEV;
3052#endif
3053}
3054
3055static void __pci_set_master(struct pci_dev *dev, bool enable)
3056{
3057 u16 old_cmd, cmd;
3058
3059 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3060 if (enable)
3061 cmd = old_cmd | PCI_COMMAND_MASTER;
3062 else
3063 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3064 if (cmd != old_cmd) {
3065 dev_dbg(&dev->dev, "%s bus mastering\n",
3066 enable ? "enabling" : "disabling");
3067 pci_write_config_word(dev, PCI_COMMAND, cmd);
3068 }
3069 dev->is_busmaster = enable;
3070}
3071
3072/**
3073 * pcibios_setup - process "pci=" kernel boot arguments
3074 * @str: string used to pass in "pci=" kernel boot arguments
3075 *
3076 * Process kernel boot arguments. This is the default implementation.
3077 * Architecture specific implementations can override this as necessary.
3078 */
3079char * __weak __init pcibios_setup(char *str)
3080{
3081 return str;
3082}
3083
3084/**
3085 * pcibios_set_master - enable PCI bus-mastering for device dev
3086 * @dev: the PCI device to enable
3087 *
3088 * Enables PCI bus-mastering for the device. This is the default
3089 * implementation. Architecture specific implementations can override
3090 * this if necessary.
3091 */
3092void __weak pcibios_set_master(struct pci_dev *dev)
3093{
3094 u8 lat;
3095
3096 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3097 if (pci_is_pcie(dev))
3098 return;
3099
3100 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3101 if (lat < 16)
3102 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3103 else if (lat > pcibios_max_latency)
3104 lat = pcibios_max_latency;
3105 else
3106 return;
3107
3108 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3109}
3110
3111/**
3112 * pci_set_master - enables bus-mastering for device dev
3113 * @dev: the PCI device to enable
3114 *
3115 * Enables bus-mastering on the device and calls pcibios_set_master()
3116 * to do the needed arch specific settings.
3117 */
3118void pci_set_master(struct pci_dev *dev)
3119{
3120 __pci_set_master(dev, true);
3121 pcibios_set_master(dev);
3122}
3123EXPORT_SYMBOL(pci_set_master);
3124
3125/**
3126 * pci_clear_master - disables bus-mastering for device dev
3127 * @dev: the PCI device to disable
3128 */
3129void pci_clear_master(struct pci_dev *dev)
3130{
3131 __pci_set_master(dev, false);
3132}
3133EXPORT_SYMBOL(pci_clear_master);
3134
3135/**
3136 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3137 * @dev: the PCI device for which MWI is to be enabled
3138 *
3139 * Helper function for pci_set_mwi.
3140 * Originally copied from drivers/net/acenic.c.
3141 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3142 *
3143 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3144 */
3145int pci_set_cacheline_size(struct pci_dev *dev)
3146{
3147 u8 cacheline_size;
3148
3149 if (!pci_cache_line_size)
3150 return -EINVAL;
3151
3152 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3153 equal to or multiple of the right value. */
3154 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3155 if (cacheline_size >= pci_cache_line_size &&
3156 (cacheline_size % pci_cache_line_size) == 0)
3157 return 0;
3158
3159 /* Write the correct value. */
3160 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3161 /* Read it back. */
3162 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3163 if (cacheline_size == pci_cache_line_size)
3164 return 0;
3165
3166 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3167 pci_cache_line_size << 2);
3168
3169 return -EINVAL;
3170}
3171EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3172
3173/**
3174 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3175 * @dev: the PCI device for which MWI is enabled
3176 *
3177 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3178 *
3179 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3180 */
3181int pci_set_mwi(struct pci_dev *dev)
3182{
3183#ifdef PCI_DISABLE_MWI
3184 return 0;
3185#else
3186 int rc;
3187 u16 cmd;
3188
3189 rc = pci_set_cacheline_size(dev);
3190 if (rc)
3191 return rc;
3192
3193 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3194 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3195 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3196 cmd |= PCI_COMMAND_INVALIDATE;
3197 pci_write_config_word(dev, PCI_COMMAND, cmd);
3198 }
3199 return 0;
3200#endif
3201}
3202EXPORT_SYMBOL(pci_set_mwi);
3203
3204/**
3205 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3206 * @dev: the PCI device for which MWI is enabled
3207 *
3208 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3209 * Callers are not required to check the return value.
3210 *
3211 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3212 */
3213int pci_try_set_mwi(struct pci_dev *dev)
3214{
3215#ifdef PCI_DISABLE_MWI
3216 return 0;
3217#else
3218 return pci_set_mwi(dev);
3219#endif
3220}
3221EXPORT_SYMBOL(pci_try_set_mwi);
3222
3223/**
3224 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3225 * @dev: the PCI device to disable
3226 *
3227 * Disables PCI Memory-Write-Invalidate transaction on the device
3228 */
3229void pci_clear_mwi(struct pci_dev *dev)
3230{
3231#ifndef PCI_DISABLE_MWI
3232 u16 cmd;
3233
3234 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3235 if (cmd & PCI_COMMAND_INVALIDATE) {
3236 cmd &= ~PCI_COMMAND_INVALIDATE;
3237 pci_write_config_word(dev, PCI_COMMAND, cmd);
3238 }
3239#endif
3240}
3241EXPORT_SYMBOL(pci_clear_mwi);
3242
3243/**
3244 * pci_intx - enables/disables PCI INTx for device dev
3245 * @pdev: the PCI device to operate on
3246 * @enable: boolean: whether to enable or disable PCI INTx
3247 *
3248 * Enables/disables PCI INTx for device dev
3249 */
3250void pci_intx(struct pci_dev *pdev, int enable)
3251{
3252 u16 pci_command, new;
3253
3254 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3255
3256 if (enable)
3257 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3258 else
3259 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3260
3261 if (new != pci_command) {
3262 struct pci_devres *dr;
3263
3264 pci_write_config_word(pdev, PCI_COMMAND, new);
3265
3266 dr = find_pci_dr(pdev);
3267 if (dr && !dr->restore_intx) {
3268 dr->restore_intx = 1;
3269 dr->orig_intx = !enable;
3270 }
3271 }
3272}
3273EXPORT_SYMBOL_GPL(pci_intx);
3274
3275/**
3276 * pci_intx_mask_supported - probe for INTx masking support
3277 * @dev: the PCI device to operate on
3278 *
3279 * Check if the device dev support INTx masking via the config space
3280 * command word.
3281 */
3282bool pci_intx_mask_supported(struct pci_dev *dev)
3283{
3284 bool mask_supported = false;
3285 u16 orig, new;
3286
3287 if (dev->broken_intx_masking)
3288 return false;
3289
3290 pci_cfg_access_lock(dev);
3291
3292 pci_read_config_word(dev, PCI_COMMAND, &orig);
3293 pci_write_config_word(dev, PCI_COMMAND,
3294 orig ^ PCI_COMMAND_INTX_DISABLE);
3295 pci_read_config_word(dev, PCI_COMMAND, &new);
3296
3297 /*
3298 * There's no way to protect against hardware bugs or detect them
3299 * reliably, but as long as we know what the value should be, let's
3300 * go ahead and check it.
3301 */
3302 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3303 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3304 orig, new);
3305 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3306 mask_supported = true;
3307 pci_write_config_word(dev, PCI_COMMAND, orig);
3308 }
3309
3310 pci_cfg_access_unlock(dev);
3311 return mask_supported;
3312}
3313EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3314
3315static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3316{
3317 struct pci_bus *bus = dev->bus;
3318 bool mask_updated = true;
3319 u32 cmd_status_dword;
3320 u16 origcmd, newcmd;
3321 unsigned long flags;
3322 bool irq_pending;
3323
3324 /*
3325 * We do a single dword read to retrieve both command and status.
3326 * Document assumptions that make this possible.
3327 */
3328 BUILD_BUG_ON(PCI_COMMAND % 4);
3329 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3330
3331 raw_spin_lock_irqsave(&pci_lock, flags);
3332
3333 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3334
3335 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3336
3337 /*
3338 * Check interrupt status register to see whether our device
3339 * triggered the interrupt (when masking) or the next IRQ is
3340 * already pending (when unmasking).
3341 */
3342 if (mask != irq_pending) {
3343 mask_updated = false;
3344 goto done;
3345 }
3346
3347 origcmd = cmd_status_dword;
3348 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3349 if (mask)
3350 newcmd |= PCI_COMMAND_INTX_DISABLE;
3351 if (newcmd != origcmd)
3352 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3353
3354done:
3355 raw_spin_unlock_irqrestore(&pci_lock, flags);
3356
3357 return mask_updated;
3358}
3359
3360/**
3361 * pci_check_and_mask_intx - mask INTx on pending interrupt
3362 * @dev: the PCI device to operate on
3363 *
3364 * Check if the device dev has its INTx line asserted, mask it and
3365 * return true in that case. False is returned if not interrupt was
3366 * pending.
3367 */
3368bool pci_check_and_mask_intx(struct pci_dev *dev)
3369{
3370 return pci_check_and_set_intx_mask(dev, true);
3371}
3372EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3373
3374/**
3375 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3376 * @dev: the PCI device to operate on
3377 *
3378 * Check if the device dev has its INTx line asserted, unmask it if not
3379 * and return true. False is returned and the mask remains active if
3380 * there was still an interrupt pending.
3381 */
3382bool pci_check_and_unmask_intx(struct pci_dev *dev)
3383{
3384 return pci_check_and_set_intx_mask(dev, false);
3385}
3386EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3387
3388/**
3389 * pci_wait_for_pending_transaction - waits for pending transaction
3390 * @dev: the PCI device to operate on
3391 *
3392 * Return 0 if transaction is pending 1 otherwise.
3393 */
3394int pci_wait_for_pending_transaction(struct pci_dev *dev)
3395{
3396 if (!pci_is_pcie(dev))
3397 return 1;
3398
3399 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3400 PCI_EXP_DEVSTA_TRPND);
3401}
3402EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3403
3404/*
3405 * We should only need to wait 100ms after FLR, but some devices take longer.
3406 * Wait for up to 1000ms for config space to return something other than -1.
3407 * Intel IGD requires this when an LCD panel is attached. We read the 2nd
3408 * dword because VFs don't implement the 1st dword.
3409 */
3410static void pci_flr_wait(struct pci_dev *dev)
3411{
3412 int i = 0;
3413 u32 id;
3414
3415 do {
3416 msleep(100);
3417 pci_read_config_dword(dev, PCI_COMMAND, &id);
3418 } while (i++ < 10 && id == ~0);
3419
3420 if (id == ~0)
3421 dev_warn(&dev->dev, "Failed to return from FLR\n");
3422 else if (i > 1)
3423 dev_info(&dev->dev, "Required additional %dms to return from FLR\n",
3424 (i - 1) * 100);
3425}
3426
3427static int pcie_flr(struct pci_dev *dev, int probe)
3428{
3429 u32 cap;
3430
3431 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3432 if (!(cap & PCI_EXP_DEVCAP_FLR))
3433 return -ENOTTY;
3434
3435 if (probe)
3436 return 0;
3437
3438 if (!pci_wait_for_pending_transaction(dev))
3439 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3440
3441 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3442 pci_flr_wait(dev);
3443 return 0;
3444}
3445
3446static int pci_af_flr(struct pci_dev *dev, int probe)
3447{
3448 int pos;
3449 u8 cap;
3450
3451 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3452 if (!pos)
3453 return -ENOTTY;
3454
3455 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3456 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3457 return -ENOTTY;
3458
3459 if (probe)
3460 return 0;
3461
3462 /*
3463 * Wait for Transaction Pending bit to clear. A word-aligned test
3464 * is used, so we use the conrol offset rather than status and shift
3465 * the test bit to match.
3466 */
3467 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3468 PCI_AF_STATUS_TP << 8))
3469 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3470
3471 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3472 pci_flr_wait(dev);
3473 return 0;
3474}
3475
3476/**
3477 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3478 * @dev: Device to reset.
3479 * @probe: If set, only check if the device can be reset this way.
3480 *
3481 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3482 * unset, it will be reinitialized internally when going from PCI_D3hot to
3483 * PCI_D0. If that's the case and the device is not in a low-power state
3484 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3485 *
3486 * NOTE: This causes the caller to sleep for twice the device power transition
3487 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3488 * by default (i.e. unless the @dev's d3_delay field has a different value).
3489 * Moreover, only devices in D0 can be reset by this function.
3490 */
3491static int pci_pm_reset(struct pci_dev *dev, int probe)
3492{
3493 u16 csr;
3494
3495 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3496 return -ENOTTY;
3497
3498 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3499 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3500 return -ENOTTY;
3501
3502 if (probe)
3503 return 0;
3504
3505 if (dev->current_state != PCI_D0)
3506 return -EINVAL;
3507
3508 csr &= ~PCI_PM_CTRL_STATE_MASK;
3509 csr |= PCI_D3hot;
3510 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3511 pci_dev_d3_sleep(dev);
3512
3513 csr &= ~PCI_PM_CTRL_STATE_MASK;
3514 csr |= PCI_D0;
3515 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3516 pci_dev_d3_sleep(dev);
3517
3518 return 0;
3519}
3520
3521void pci_reset_secondary_bus(struct pci_dev *dev)
3522{
3523 u16 ctrl;
3524
3525 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3526 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3527 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3528 /*
3529 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3530 * this to 2ms to ensure that we meet the minimum requirement.
3531 */
3532 msleep(2);
3533
3534 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3535 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3536
3537 /*
3538 * Trhfa for conventional PCI is 2^25 clock cycles.
3539 * Assuming a minimum 33MHz clock this results in a 1s
3540 * delay before we can consider subordinate devices to
3541 * be re-initialized. PCIe has some ways to shorten this,
3542 * but we don't make use of them yet.
3543 */
3544 ssleep(1);
3545}
3546
3547void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3548{
3549 pci_reset_secondary_bus(dev);
3550}
3551
3552/**
3553 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3554 * @dev: Bridge device
3555 *
3556 * Use the bridge control register to assert reset on the secondary bus.
3557 * Devices on the secondary bus are left in power-on state.
3558 */
3559void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3560{
3561 pcibios_reset_secondary_bus(dev);
3562}
3563EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3564
3565static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3566{
3567 struct pci_dev *pdev;
3568
3569 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3570 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3571 return -ENOTTY;
3572
3573 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3574 if (pdev != dev)
3575 return -ENOTTY;
3576
3577 if (probe)
3578 return 0;
3579
3580 pci_reset_bridge_secondary_bus(dev->bus->self);
3581
3582 return 0;
3583}
3584
3585static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3586{
3587 int rc = -ENOTTY;
3588
3589 if (!hotplug || !try_module_get(hotplug->ops->owner))
3590 return rc;
3591
3592 if (hotplug->ops->reset_slot)
3593 rc = hotplug->ops->reset_slot(hotplug, probe);
3594
3595 module_put(hotplug->ops->owner);
3596
3597 return rc;
3598}
3599
3600static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3601{
3602 struct pci_dev *pdev;
3603
3604 if (dev->subordinate || !dev->slot ||
3605 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3606 return -ENOTTY;
3607
3608 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3609 if (pdev != dev && pdev->slot == dev->slot)
3610 return -ENOTTY;
3611
3612 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3613}
3614
3615static int __pci_dev_reset(struct pci_dev *dev, int probe)
3616{
3617 int rc;
3618
3619 might_sleep();
3620
3621 rc = pci_dev_specific_reset(dev, probe);
3622 if (rc != -ENOTTY)
3623 goto done;
3624
3625 rc = pcie_flr(dev, probe);
3626 if (rc != -ENOTTY)
3627 goto done;
3628
3629 rc = pci_af_flr(dev, probe);
3630 if (rc != -ENOTTY)
3631 goto done;
3632
3633 rc = pci_pm_reset(dev, probe);
3634 if (rc != -ENOTTY)
3635 goto done;
3636
3637 rc = pci_dev_reset_slot_function(dev, probe);
3638 if (rc != -ENOTTY)
3639 goto done;
3640
3641 rc = pci_parent_bus_reset(dev, probe);
3642done:
3643 return rc;
3644}
3645
3646static void pci_dev_lock(struct pci_dev *dev)
3647{
3648 pci_cfg_access_lock(dev);
3649 /* block PM suspend, driver probe, etc. */
3650 device_lock(&dev->dev);
3651}
3652
3653/* Return 1 on successful lock, 0 on contention */
3654static int pci_dev_trylock(struct pci_dev *dev)
3655{
3656 if (pci_cfg_access_trylock(dev)) {
3657 if (device_trylock(&dev->dev))
3658 return 1;
3659 pci_cfg_access_unlock(dev);
3660 }
3661
3662 return 0;
3663}
3664
3665static void pci_dev_unlock(struct pci_dev *dev)
3666{
3667 device_unlock(&dev->dev);
3668 pci_cfg_access_unlock(dev);
3669}
3670
3671/**
3672 * pci_reset_notify - notify device driver of reset
3673 * @dev: device to be notified of reset
3674 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3675 * completed
3676 *
3677 * Must be called prior to device access being disabled and after device
3678 * access is restored.
3679 */
3680static void pci_reset_notify(struct pci_dev *dev, bool prepare)
3681{
3682 const struct pci_error_handlers *err_handler =
3683 dev->driver ? dev->driver->err_handler : NULL;
3684 if (err_handler && err_handler->reset_notify)
3685 err_handler->reset_notify(dev, prepare);
3686}
3687
3688static void pci_dev_save_and_disable(struct pci_dev *dev)
3689{
3690 pci_reset_notify(dev, true);
3691
3692 /*
3693 * Wake-up device prior to save. PM registers default to D0 after
3694 * reset and a simple register restore doesn't reliably return
3695 * to a non-D0 state anyway.
3696 */
3697 pci_set_power_state(dev, PCI_D0);
3698
3699 pci_save_state(dev);
3700 /*
3701 * Disable the device by clearing the Command register, except for
3702 * INTx-disable which is set. This not only disables MMIO and I/O port
3703 * BARs, but also prevents the device from being Bus Master, preventing
3704 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3705 * compliant devices, INTx-disable prevents legacy interrupts.
3706 */
3707 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3708}
3709
3710static void pci_dev_restore(struct pci_dev *dev)
3711{
3712 pci_restore_state(dev);
3713 pci_reset_notify(dev, false);
3714}
3715
3716static int pci_dev_reset(struct pci_dev *dev, int probe)
3717{
3718 int rc;
3719
3720 if (!probe)
3721 pci_dev_lock(dev);
3722
3723 rc = __pci_dev_reset(dev, probe);
3724
3725 if (!probe)
3726 pci_dev_unlock(dev);
3727
3728 return rc;
3729}
3730
3731/**
3732 * __pci_reset_function - reset a PCI device function
3733 * @dev: PCI device to reset
3734 *
3735 * Some devices allow an individual function to be reset without affecting
3736 * other functions in the same device. The PCI device must be responsive
3737 * to PCI config space in order to use this function.
3738 *
3739 * The device function is presumed to be unused when this function is called.
3740 * Resetting the device will make the contents of PCI configuration space
3741 * random, so any caller of this must be prepared to reinitialise the
3742 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3743 * etc.
3744 *
3745 * Returns 0 if the device function was successfully reset or negative if the
3746 * device doesn't support resetting a single function.
3747 */
3748int __pci_reset_function(struct pci_dev *dev)
3749{
3750 return pci_dev_reset(dev, 0);
3751}
3752EXPORT_SYMBOL_GPL(__pci_reset_function);
3753
3754/**
3755 * __pci_reset_function_locked - reset a PCI device function while holding
3756 * the @dev mutex lock.
3757 * @dev: PCI device to reset
3758 *
3759 * Some devices allow an individual function to be reset without affecting
3760 * other functions in the same device. The PCI device must be responsive
3761 * to PCI config space in order to use this function.
3762 *
3763 * The device function is presumed to be unused and the caller is holding
3764 * the device mutex lock when this function is called.
3765 * Resetting the device will make the contents of PCI configuration space
3766 * random, so any caller of this must be prepared to reinitialise the
3767 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3768 * etc.
3769 *
3770 * Returns 0 if the device function was successfully reset or negative if the
3771 * device doesn't support resetting a single function.
3772 */
3773int __pci_reset_function_locked(struct pci_dev *dev)
3774{
3775 return __pci_dev_reset(dev, 0);
3776}
3777EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3778
3779/**
3780 * pci_probe_reset_function - check whether the device can be safely reset
3781 * @dev: PCI device to reset
3782 *
3783 * Some devices allow an individual function to be reset without affecting
3784 * other functions in the same device. The PCI device must be responsive
3785 * to PCI config space in order to use this function.
3786 *
3787 * Returns 0 if the device function can be reset or negative if the
3788 * device doesn't support resetting a single function.
3789 */
3790int pci_probe_reset_function(struct pci_dev *dev)
3791{
3792 return pci_dev_reset(dev, 1);
3793}
3794
3795/**
3796 * pci_reset_function - quiesce and reset a PCI device function
3797 * @dev: PCI device to reset
3798 *
3799 * Some devices allow an individual function to be reset without affecting
3800 * other functions in the same device. The PCI device must be responsive
3801 * to PCI config space in order to use this function.
3802 *
3803 * This function does not just reset the PCI portion of a device, but
3804 * clears all the state associated with the device. This function differs
3805 * from __pci_reset_function in that it saves and restores device state
3806 * over the reset.
3807 *
3808 * Returns 0 if the device function was successfully reset or negative if the
3809 * device doesn't support resetting a single function.
3810 */
3811int pci_reset_function(struct pci_dev *dev)
3812{
3813 int rc;
3814
3815 rc = pci_dev_reset(dev, 1);
3816 if (rc)
3817 return rc;
3818
3819 pci_dev_save_and_disable(dev);
3820
3821 rc = pci_dev_reset(dev, 0);
3822
3823 pci_dev_restore(dev);
3824
3825 return rc;
3826}
3827EXPORT_SYMBOL_GPL(pci_reset_function);
3828
3829/**
3830 * pci_try_reset_function - quiesce and reset a PCI device function
3831 * @dev: PCI device to reset
3832 *
3833 * Same as above, except return -EAGAIN if unable to lock device.
3834 */
3835int pci_try_reset_function(struct pci_dev *dev)
3836{
3837 int rc;
3838
3839 rc = pci_dev_reset(dev, 1);
3840 if (rc)
3841 return rc;
3842
3843 pci_dev_save_and_disable(dev);
3844
3845 if (pci_dev_trylock(dev)) {
3846 rc = __pci_dev_reset(dev, 0);
3847 pci_dev_unlock(dev);
3848 } else
3849 rc = -EAGAIN;
3850
3851 pci_dev_restore(dev);
3852
3853 return rc;
3854}
3855EXPORT_SYMBOL_GPL(pci_try_reset_function);
3856
3857/* Do any devices on or below this bus prevent a bus reset? */
3858static bool pci_bus_resetable(struct pci_bus *bus)
3859{
3860 struct pci_dev *dev;
3861
3862 list_for_each_entry(dev, &bus->devices, bus_list) {
3863 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3864 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3865 return false;
3866 }
3867
3868 return true;
3869}
3870
3871/* Lock devices from the top of the tree down */
3872static void pci_bus_lock(struct pci_bus *bus)
3873{
3874 struct pci_dev *dev;
3875
3876 list_for_each_entry(dev, &bus->devices, bus_list) {
3877 pci_dev_lock(dev);
3878 if (dev->subordinate)
3879 pci_bus_lock(dev->subordinate);
3880 }
3881}
3882
3883/* Unlock devices from the bottom of the tree up */
3884static void pci_bus_unlock(struct pci_bus *bus)
3885{
3886 struct pci_dev *dev;
3887
3888 list_for_each_entry(dev, &bus->devices, bus_list) {
3889 if (dev->subordinate)
3890 pci_bus_unlock(dev->subordinate);
3891 pci_dev_unlock(dev);
3892 }
3893}
3894
3895/* Return 1 on successful lock, 0 on contention */
3896static int pci_bus_trylock(struct pci_bus *bus)
3897{
3898 struct pci_dev *dev;
3899
3900 list_for_each_entry(dev, &bus->devices, bus_list) {
3901 if (!pci_dev_trylock(dev))
3902 goto unlock;
3903 if (dev->subordinate) {
3904 if (!pci_bus_trylock(dev->subordinate)) {
3905 pci_dev_unlock(dev);
3906 goto unlock;
3907 }
3908 }
3909 }
3910 return 1;
3911
3912unlock:
3913 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3914 if (dev->subordinate)
3915 pci_bus_unlock(dev->subordinate);
3916 pci_dev_unlock(dev);
3917 }
3918 return 0;
3919}
3920
3921/* Do any devices on or below this slot prevent a bus reset? */
3922static bool pci_slot_resetable(struct pci_slot *slot)
3923{
3924 struct pci_dev *dev;
3925
3926 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3927 if (!dev->slot || dev->slot != slot)
3928 continue;
3929 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3930 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3931 return false;
3932 }
3933
3934 return true;
3935}
3936
3937/* Lock devices from the top of the tree down */
3938static void pci_slot_lock(struct pci_slot *slot)
3939{
3940 struct pci_dev *dev;
3941
3942 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3943 if (!dev->slot || dev->slot != slot)
3944 continue;
3945 pci_dev_lock(dev);
3946 if (dev->subordinate)
3947 pci_bus_lock(dev->subordinate);
3948 }
3949}
3950
3951/* Unlock devices from the bottom of the tree up */
3952static void pci_slot_unlock(struct pci_slot *slot)
3953{
3954 struct pci_dev *dev;
3955
3956 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3957 if (!dev->slot || dev->slot != slot)
3958 continue;
3959 if (dev->subordinate)
3960 pci_bus_unlock(dev->subordinate);
3961 pci_dev_unlock(dev);
3962 }
3963}
3964
3965/* Return 1 on successful lock, 0 on contention */
3966static int pci_slot_trylock(struct pci_slot *slot)
3967{
3968 struct pci_dev *dev;
3969
3970 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3971 if (!dev->slot || dev->slot != slot)
3972 continue;
3973 if (!pci_dev_trylock(dev))
3974 goto unlock;
3975 if (dev->subordinate) {
3976 if (!pci_bus_trylock(dev->subordinate)) {
3977 pci_dev_unlock(dev);
3978 goto unlock;
3979 }
3980 }
3981 }
3982 return 1;
3983
3984unlock:
3985 list_for_each_entry_continue_reverse(dev,
3986 &slot->bus->devices, bus_list) {
3987 if (!dev->slot || dev->slot != slot)
3988 continue;
3989 if (dev->subordinate)
3990 pci_bus_unlock(dev->subordinate);
3991 pci_dev_unlock(dev);
3992 }
3993 return 0;
3994}
3995
3996/* Save and disable devices from the top of the tree down */
3997static void pci_bus_save_and_disable(struct pci_bus *bus)
3998{
3999 struct pci_dev *dev;
4000
4001 list_for_each_entry(dev, &bus->devices, bus_list) {
4002 pci_dev_save_and_disable(dev);
4003 if (dev->subordinate)
4004 pci_bus_save_and_disable(dev->subordinate);
4005 }
4006}
4007
4008/*
4009 * Restore devices from top of the tree down - parent bridges need to be
4010 * restored before we can get to subordinate devices.
4011 */
4012static void pci_bus_restore(struct pci_bus *bus)
4013{
4014 struct pci_dev *dev;
4015
4016 list_for_each_entry(dev, &bus->devices, bus_list) {
4017 pci_dev_restore(dev);
4018 if (dev->subordinate)
4019 pci_bus_restore(dev->subordinate);
4020 }
4021}
4022
4023/* Save and disable devices from the top of the tree down */
4024static void pci_slot_save_and_disable(struct pci_slot *slot)
4025{
4026 struct pci_dev *dev;
4027
4028 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4029 if (!dev->slot || dev->slot != slot)
4030 continue;
4031 pci_dev_save_and_disable(dev);
4032 if (dev->subordinate)
4033 pci_bus_save_and_disable(dev->subordinate);
4034 }
4035}
4036
4037/*
4038 * Restore devices from top of the tree down - parent bridges need to be
4039 * restored before we can get to subordinate devices.
4040 */
4041static void pci_slot_restore(struct pci_slot *slot)
4042{
4043 struct pci_dev *dev;
4044
4045 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4046 if (!dev->slot || dev->slot != slot)
4047 continue;
4048 pci_dev_restore(dev);
4049 if (dev->subordinate)
4050 pci_bus_restore(dev->subordinate);
4051 }
4052}
4053
4054static int pci_slot_reset(struct pci_slot *slot, int probe)
4055{
4056 int rc;
4057
4058 if (!slot || !pci_slot_resetable(slot))
4059 return -ENOTTY;
4060
4061 if (!probe)
4062 pci_slot_lock(slot);
4063
4064 might_sleep();
4065
4066 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4067
4068 if (!probe)
4069 pci_slot_unlock(slot);
4070
4071 return rc;
4072}
4073
4074/**
4075 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4076 * @slot: PCI slot to probe
4077 *
4078 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4079 */
4080int pci_probe_reset_slot(struct pci_slot *slot)
4081{
4082 return pci_slot_reset(slot, 1);
4083}
4084EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4085
4086/**
4087 * pci_reset_slot - reset a PCI slot
4088 * @slot: PCI slot to reset
4089 *
4090 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4091 * independent of other slots. For instance, some slots may support slot power
4092 * control. In the case of a 1:1 bus to slot architecture, this function may
4093 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4094 * Generally a slot reset should be attempted before a bus reset. All of the
4095 * function of the slot and any subordinate buses behind the slot are reset
4096 * through this function. PCI config space of all devices in the slot and
4097 * behind the slot is saved before and restored after reset.
4098 *
4099 * Return 0 on success, non-zero on error.
4100 */
4101int pci_reset_slot(struct pci_slot *slot)
4102{
4103 int rc;
4104
4105 rc = pci_slot_reset(slot, 1);
4106 if (rc)
4107 return rc;
4108
4109 pci_slot_save_and_disable(slot);
4110
4111 rc = pci_slot_reset(slot, 0);
4112
4113 pci_slot_restore(slot);
4114
4115 return rc;
4116}
4117EXPORT_SYMBOL_GPL(pci_reset_slot);
4118
4119/**
4120 * pci_try_reset_slot - Try to reset a PCI slot
4121 * @slot: PCI slot to reset
4122 *
4123 * Same as above except return -EAGAIN if the slot cannot be locked
4124 */
4125int pci_try_reset_slot(struct pci_slot *slot)
4126{
4127 int rc;
4128
4129 rc = pci_slot_reset(slot, 1);
4130 if (rc)
4131 return rc;
4132
4133 pci_slot_save_and_disable(slot);
4134
4135 if (pci_slot_trylock(slot)) {
4136 might_sleep();
4137 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4138 pci_slot_unlock(slot);
4139 } else
4140 rc = -EAGAIN;
4141
4142 pci_slot_restore(slot);
4143
4144 return rc;
4145}
4146EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4147
4148static int pci_bus_reset(struct pci_bus *bus, int probe)
4149{
4150 if (!bus->self || !pci_bus_resetable(bus))
4151 return -ENOTTY;
4152
4153 if (probe)
4154 return 0;
4155
4156 pci_bus_lock(bus);
4157
4158 might_sleep();
4159
4160 pci_reset_bridge_secondary_bus(bus->self);
4161
4162 pci_bus_unlock(bus);
4163
4164 return 0;
4165}
4166
4167/**
4168 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4169 * @bus: PCI bus to probe
4170 *
4171 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4172 */
4173int pci_probe_reset_bus(struct pci_bus *bus)
4174{
4175 return pci_bus_reset(bus, 1);
4176}
4177EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4178
4179/**
4180 * pci_reset_bus - reset a PCI bus
4181 * @bus: top level PCI bus to reset
4182 *
4183 * Do a bus reset on the given bus and any subordinate buses, saving
4184 * and restoring state of all devices.
4185 *
4186 * Return 0 on success, non-zero on error.
4187 */
4188int pci_reset_bus(struct pci_bus *bus)
4189{
4190 int rc;
4191
4192 rc = pci_bus_reset(bus, 1);
4193 if (rc)
4194 return rc;
4195
4196 pci_bus_save_and_disable(bus);
4197
4198 rc = pci_bus_reset(bus, 0);
4199
4200 pci_bus_restore(bus);
4201
4202 return rc;
4203}
4204EXPORT_SYMBOL_GPL(pci_reset_bus);
4205
4206/**
4207 * pci_try_reset_bus - Try to reset a PCI bus
4208 * @bus: top level PCI bus to reset
4209 *
4210 * Same as above except return -EAGAIN if the bus cannot be locked
4211 */
4212int pci_try_reset_bus(struct pci_bus *bus)
4213{
4214 int rc;
4215
4216 rc = pci_bus_reset(bus, 1);
4217 if (rc)
4218 return rc;
4219
4220 pci_bus_save_and_disable(bus);
4221
4222 if (pci_bus_trylock(bus)) {
4223 might_sleep();
4224 pci_reset_bridge_secondary_bus(bus->self);
4225 pci_bus_unlock(bus);
4226 } else
4227 rc = -EAGAIN;
4228
4229 pci_bus_restore(bus);
4230
4231 return rc;
4232}
4233EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4234
4235/**
4236 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4237 * @dev: PCI device to query
4238 *
4239 * Returns mmrbc: maximum designed memory read count in bytes
4240 * or appropriate error value.
4241 */
4242int pcix_get_max_mmrbc(struct pci_dev *dev)
4243{
4244 int cap;
4245 u32 stat;
4246
4247 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4248 if (!cap)
4249 return -EINVAL;
4250
4251 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4252 return -EINVAL;
4253
4254 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4255}
4256EXPORT_SYMBOL(pcix_get_max_mmrbc);
4257
4258/**
4259 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4260 * @dev: PCI device to query
4261 *
4262 * Returns mmrbc: maximum memory read count in bytes
4263 * or appropriate error value.
4264 */
4265int pcix_get_mmrbc(struct pci_dev *dev)
4266{
4267 int cap;
4268 u16 cmd;
4269
4270 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4271 if (!cap)
4272 return -EINVAL;
4273
4274 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4275 return -EINVAL;
4276
4277 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4278}
4279EXPORT_SYMBOL(pcix_get_mmrbc);
4280
4281/**
4282 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4283 * @dev: PCI device to query
4284 * @mmrbc: maximum memory read count in bytes
4285 * valid values are 512, 1024, 2048, 4096
4286 *
4287 * If possible sets maximum memory read byte count, some bridges have erratas
4288 * that prevent this.
4289 */
4290int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4291{
4292 int cap;
4293 u32 stat, v, o;
4294 u16 cmd;
4295
4296 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4297 return -EINVAL;
4298
4299 v = ffs(mmrbc) - 10;
4300
4301 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4302 if (!cap)
4303 return -EINVAL;
4304
4305 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4306 return -EINVAL;
4307
4308 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4309 return -E2BIG;
4310
4311 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4312 return -EINVAL;
4313
4314 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4315 if (o != v) {
4316 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4317 return -EIO;
4318
4319 cmd &= ~PCI_X_CMD_MAX_READ;
4320 cmd |= v << 2;
4321 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4322 return -EIO;
4323 }
4324 return 0;
4325}
4326EXPORT_SYMBOL(pcix_set_mmrbc);
4327
4328/**
4329 * pcie_get_readrq - get PCI Express read request size
4330 * @dev: PCI device to query
4331 *
4332 * Returns maximum memory read request in bytes
4333 * or appropriate error value.
4334 */
4335int pcie_get_readrq(struct pci_dev *dev)
4336{
4337 u16 ctl;
4338
4339 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4340
4341 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4342}
4343EXPORT_SYMBOL(pcie_get_readrq);
4344
4345/**
4346 * pcie_set_readrq - set PCI Express maximum memory read request
4347 * @dev: PCI device to query
4348 * @rq: maximum memory read count in bytes
4349 * valid values are 128, 256, 512, 1024, 2048, 4096
4350 *
4351 * If possible sets maximum memory read request in bytes
4352 */
4353int pcie_set_readrq(struct pci_dev *dev, int rq)
4354{
4355 u16 v;
4356
4357 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4358 return -EINVAL;
4359
4360 /*
4361 * If using the "performance" PCIe config, we clamp the
4362 * read rq size to the max packet size to prevent the
4363 * host bridge generating requests larger than we can
4364 * cope with
4365 */
4366 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4367 int mps = pcie_get_mps(dev);
4368
4369 if (mps < rq)
4370 rq = mps;
4371 }
4372
4373 v = (ffs(rq) - 8) << 12;
4374
4375 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4376 PCI_EXP_DEVCTL_READRQ, v);
4377}
4378EXPORT_SYMBOL(pcie_set_readrq);
4379
4380/**
4381 * pcie_get_mps - get PCI Express maximum payload size
4382 * @dev: PCI device to query
4383 *
4384 * Returns maximum payload size in bytes
4385 */
4386int pcie_get_mps(struct pci_dev *dev)
4387{
4388 u16 ctl;
4389
4390 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4391
4392 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4393}
4394EXPORT_SYMBOL(pcie_get_mps);
4395
4396/**
4397 * pcie_set_mps - set PCI Express maximum payload size
4398 * @dev: PCI device to query
4399 * @mps: maximum payload size in bytes
4400 * valid values are 128, 256, 512, 1024, 2048, 4096
4401 *
4402 * If possible sets maximum payload size
4403 */
4404int pcie_set_mps(struct pci_dev *dev, int mps)
4405{
4406 u16 v;
4407
4408 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4409 return -EINVAL;
4410
4411 v = ffs(mps) - 8;
4412 if (v > dev->pcie_mpss)
4413 return -EINVAL;
4414 v <<= 5;
4415
4416 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4417 PCI_EXP_DEVCTL_PAYLOAD, v);
4418}
4419EXPORT_SYMBOL(pcie_set_mps);
4420
4421/**
4422 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4423 * @dev: PCI device to query
4424 * @speed: storage for minimum speed
4425 * @width: storage for minimum width
4426 *
4427 * This function will walk up the PCI device chain and determine the minimum
4428 * link width and speed of the device.
4429 */
4430int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4431 enum pcie_link_width *width)
4432{
4433 int ret;
4434
4435 *speed = PCI_SPEED_UNKNOWN;
4436 *width = PCIE_LNK_WIDTH_UNKNOWN;
4437
4438 while (dev) {
4439 u16 lnksta;
4440 enum pci_bus_speed next_speed;
4441 enum pcie_link_width next_width;
4442
4443 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4444 if (ret)
4445 return ret;
4446
4447 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4448 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4449 PCI_EXP_LNKSTA_NLW_SHIFT;
4450
4451 if (next_speed < *speed)
4452 *speed = next_speed;
4453
4454 if (next_width < *width)
4455 *width = next_width;
4456
4457 dev = dev->bus->self;
4458 }
4459
4460 return 0;
4461}
4462EXPORT_SYMBOL(pcie_get_minimum_link);
4463
4464/**
4465 * pci_select_bars - Make BAR mask from the type of resource
4466 * @dev: the PCI device for which BAR mask is made
4467 * @flags: resource type mask to be selected
4468 *
4469 * This helper routine makes bar mask from the type of resource.
4470 */
4471int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4472{
4473 int i, bars = 0;
4474 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4475 if (pci_resource_flags(dev, i) & flags)
4476 bars |= (1 << i);
4477 return bars;
4478}
4479EXPORT_SYMBOL(pci_select_bars);
4480
4481/**
4482 * pci_resource_bar - get position of the BAR associated with a resource
4483 * @dev: the PCI device
4484 * @resno: the resource number
4485 * @type: the BAR type to be filled in
4486 *
4487 * Returns BAR position in config space, or 0 if the BAR is invalid.
4488 */
4489int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4490{
4491 int reg;
4492
4493 if (resno < PCI_ROM_RESOURCE) {
4494 *type = pci_bar_unknown;
4495 return PCI_BASE_ADDRESS_0 + 4 * resno;
4496 } else if (resno == PCI_ROM_RESOURCE) {
4497 *type = pci_bar_mem32;
4498 return dev->rom_base_reg;
4499 } else if (resno < PCI_BRIDGE_RESOURCES) {
4500 /* device specific resource */
4501 *type = pci_bar_unknown;
4502 reg = pci_iov_resource_bar(dev, resno);
4503 if (reg)
4504 return reg;
4505 }
4506
4507 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4508 return 0;
4509}
4510
4511/* Some architectures require additional programming to enable VGA */
4512static arch_set_vga_state_t arch_set_vga_state;
4513
4514void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4515{
4516 arch_set_vga_state = func; /* NULL disables */
4517}
4518
4519static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4520 unsigned int command_bits, u32 flags)
4521{
4522 if (arch_set_vga_state)
4523 return arch_set_vga_state(dev, decode, command_bits,
4524 flags);
4525 return 0;
4526}
4527
4528/**
4529 * pci_set_vga_state - set VGA decode state on device and parents if requested
4530 * @dev: the PCI device
4531 * @decode: true = enable decoding, false = disable decoding
4532 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4533 * @flags: traverse ancestors and change bridges
4534 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4535 */
4536int pci_set_vga_state(struct pci_dev *dev, bool decode,
4537 unsigned int command_bits, u32 flags)
4538{
4539 struct pci_bus *bus;
4540 struct pci_dev *bridge;
4541 u16 cmd;
4542 int rc;
4543
4544 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4545
4546 /* ARCH specific VGA enables */
4547 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4548 if (rc)
4549 return rc;
4550
4551 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4552 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4553 if (decode == true)
4554 cmd |= command_bits;
4555 else
4556 cmd &= ~command_bits;
4557 pci_write_config_word(dev, PCI_COMMAND, cmd);
4558 }
4559
4560 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4561 return 0;
4562
4563 bus = dev->bus;
4564 while (bus) {
4565 bridge = bus->self;
4566 if (bridge) {
4567 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4568 &cmd);
4569 if (decode == true)
4570 cmd |= PCI_BRIDGE_CTL_VGA;
4571 else
4572 cmd &= ~PCI_BRIDGE_CTL_VGA;
4573 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4574 cmd);
4575 }
4576 bus = bus->parent;
4577 }
4578 return 0;
4579}
4580
4581bool pci_device_is_present(struct pci_dev *pdev)
4582{
4583 u32 v;
4584
4585 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4586}
4587EXPORT_SYMBOL_GPL(pci_device_is_present);
4588
4589void pci_ignore_hotplug(struct pci_dev *dev)
4590{
4591 struct pci_dev *bridge = dev->bus->self;
4592
4593 dev->ignore_hotplug = 1;
4594 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4595 if (bridge)
4596 bridge->ignore_hotplug = 1;
4597}
4598EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4599
4600#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4601static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4602static DEFINE_SPINLOCK(resource_alignment_lock);
4603
4604/**
4605 * pci_specified_resource_alignment - get resource alignment specified by user.
4606 * @dev: the PCI device to get
4607 *
4608 * RETURNS: Resource alignment if it is specified.
4609 * Zero if it is not specified.
4610 */
4611static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4612{
4613 int seg, bus, slot, func, align_order, count;
4614 resource_size_t align = 0;
4615 char *p;
4616
4617 spin_lock(&resource_alignment_lock);
4618 p = resource_alignment_param;
4619 while (*p) {
4620 count = 0;
4621 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4622 p[count] == '@') {
4623 p += count + 1;
4624 } else {
4625 align_order = -1;
4626 }
4627 if (sscanf(p, "%x:%x:%x.%x%n",
4628 &seg, &bus, &slot, &func, &count) != 4) {
4629 seg = 0;
4630 if (sscanf(p, "%x:%x.%x%n",
4631 &bus, &slot, &func, &count) != 3) {
4632 /* Invalid format */
4633 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4634 p);
4635 break;
4636 }
4637 }
4638 p += count;
4639 if (seg == pci_domain_nr(dev->bus) &&
4640 bus == dev->bus->number &&
4641 slot == PCI_SLOT(dev->devfn) &&
4642 func == PCI_FUNC(dev->devfn)) {
4643 if (align_order == -1)
4644 align = PAGE_SIZE;
4645 else
4646 align = 1 << align_order;
4647 /* Found */
4648 break;
4649 }
4650 if (*p != ';' && *p != ',') {
4651 /* End of param or invalid format */
4652 break;
4653 }
4654 p++;
4655 }
4656 spin_unlock(&resource_alignment_lock);
4657 return align;
4658}
4659
4660/*
4661 * This function disables memory decoding and releases memory resources
4662 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4663 * It also rounds up size to specified alignment.
4664 * Later on, the kernel will assign page-aligned memory resource back
4665 * to the device.
4666 */
4667void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4668{
4669 int i;
4670 struct resource *r;
4671 resource_size_t align, size;
4672 u16 command;
4673
4674 /* check if specified PCI is target device to reassign */
4675 align = pci_specified_resource_alignment(dev);
4676 if (!align)
4677 return;
4678
4679 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4680 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4681 dev_warn(&dev->dev,
4682 "Can't reassign resources to host bridge.\n");
4683 return;
4684 }
4685
4686 dev_info(&dev->dev,
4687 "Disabling memory decoding and releasing memory resources.\n");
4688 pci_read_config_word(dev, PCI_COMMAND, &command);
4689 command &= ~PCI_COMMAND_MEMORY;
4690 pci_write_config_word(dev, PCI_COMMAND, command);
4691
4692 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4693 r = &dev->resource[i];
4694 if (!(r->flags & IORESOURCE_MEM))
4695 continue;
4696 size = resource_size(r);
4697 if (size < align) {
4698 size = align;
4699 dev_info(&dev->dev,
4700 "Rounding up size of resource #%d to %#llx.\n",
4701 i, (unsigned long long)size);
4702 }
4703 r->flags |= IORESOURCE_UNSET;
4704 r->end = size - 1;
4705 r->start = 0;
4706 }
4707 /* Need to disable bridge's resource window,
4708 * to enable the kernel to reassign new resource
4709 * window later on.
4710 */
4711 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4712 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4713 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4714 r = &dev->resource[i];
4715 if (!(r->flags & IORESOURCE_MEM))
4716 continue;
4717 r->flags |= IORESOURCE_UNSET;
4718 r->end = resource_size(r) - 1;
4719 r->start = 0;
4720 }
4721 pci_disable_bridge_window(dev);
4722 }
4723}
4724
4725static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4726{
4727 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4728 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4729 spin_lock(&resource_alignment_lock);
4730 strncpy(resource_alignment_param, buf, count);
4731 resource_alignment_param[count] = '\0';
4732 spin_unlock(&resource_alignment_lock);
4733 return count;
4734}
4735
4736static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4737{
4738 size_t count;
4739 spin_lock(&resource_alignment_lock);
4740 count = snprintf(buf, size, "%s", resource_alignment_param);
4741 spin_unlock(&resource_alignment_lock);
4742 return count;
4743}
4744
4745static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4746{
4747 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4748}
4749
4750static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4751 const char *buf, size_t count)
4752{
4753 return pci_set_resource_alignment_param(buf, count);
4754}
4755
4756BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4757 pci_resource_alignment_store);
4758
4759static int __init pci_resource_alignment_sysfs_init(void)
4760{
4761 return bus_create_file(&pci_bus_type,
4762 &bus_attr_resource_alignment);
4763}
4764late_initcall(pci_resource_alignment_sysfs_init);
4765
4766static void pci_no_domains(void)
4767{
4768#ifdef CONFIG_PCI_DOMAINS
4769 pci_domains_supported = 0;
4770#endif
4771}
4772
4773#ifdef CONFIG_PCI_DOMAINS
4774static atomic_t __domain_nr = ATOMIC_INIT(-1);
4775
4776int pci_get_new_domain_nr(void)
4777{
4778 return atomic_inc_return(&__domain_nr);
4779}
4780
4781#ifdef CONFIG_PCI_DOMAINS_GENERIC
4782void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
4783{
4784 static int use_dt_domains = -1;
4785 int domain = -1;
4786
4787 if (parent)
4788 domain = of_get_pci_domain_nr(parent->of_node);
4789 /*
4790 * Check DT domain and use_dt_domains values.
4791 *
4792 * If DT domain property is valid (domain >= 0) and
4793 * use_dt_domains != 0, the DT assignment is valid since this means
4794 * we have not previously allocated a domain number by using
4795 * pci_get_new_domain_nr(); we should also update use_dt_domains to
4796 * 1, to indicate that we have just assigned a domain number from
4797 * DT.
4798 *
4799 * If DT domain property value is not valid (ie domain < 0), and we
4800 * have not previously assigned a domain number from DT
4801 * (use_dt_domains != 1) we should assign a domain number by
4802 * using the:
4803 *
4804 * pci_get_new_domain_nr()
4805 *
4806 * API and update the use_dt_domains value to keep track of method we
4807 * are using to assign domain numbers (use_dt_domains = 0).
4808 *
4809 * All other combinations imply we have a platform that is trying
4810 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
4811 * which is a recipe for domain mishandling and it is prevented by
4812 * invalidating the domain value (domain = -1) and printing a
4813 * corresponding error.
4814 */
4815 if (domain >= 0 && use_dt_domains) {
4816 use_dt_domains = 1;
4817 } else if (domain < 0 && use_dt_domains != 1) {
4818 use_dt_domains = 0;
4819 domain = pci_get_new_domain_nr();
4820 } else {
4821 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
4822 parent->of_node->full_name);
4823 domain = -1;
4824 }
4825
4826 bus->domain_nr = domain;
4827}
4828#endif
4829#endif
4830
4831/**
4832 * pci_ext_cfg_avail - can we access extended PCI config space?
4833 *
4834 * Returns 1 if we can access PCI extended config space (offsets
4835 * greater than 0xff). This is the default implementation. Architecture
4836 * implementations can override this.
4837 */
4838int __weak pci_ext_cfg_avail(void)
4839{
4840 return 1;
4841}
4842
4843void __weak pci_fixup_cardbus(struct pci_bus *bus)
4844{
4845}
4846EXPORT_SYMBOL(pci_fixup_cardbus);
4847
4848static int __init pci_setup(char *str)
4849{
4850 while (str) {
4851 char *k = strchr(str, ',');
4852 if (k)
4853 *k++ = 0;
4854 if (*str && (str = pcibios_setup(str)) && *str) {
4855 if (!strcmp(str, "nomsi")) {
4856 pci_no_msi();
4857 } else if (!strcmp(str, "noaer")) {
4858 pci_no_aer();
4859 } else if (!strncmp(str, "realloc=", 8)) {
4860 pci_realloc_get_opt(str + 8);
4861 } else if (!strncmp(str, "realloc", 7)) {
4862 pci_realloc_get_opt("on");
4863 } else if (!strcmp(str, "nodomains")) {
4864 pci_no_domains();
4865 } else if (!strncmp(str, "noari", 5)) {
4866 pcie_ari_disabled = true;
4867 } else if (!strncmp(str, "cbiosize=", 9)) {
4868 pci_cardbus_io_size = memparse(str + 9, &str);
4869 } else if (!strncmp(str, "cbmemsize=", 10)) {
4870 pci_cardbus_mem_size = memparse(str + 10, &str);
4871 } else if (!strncmp(str, "resource_alignment=", 19)) {
4872 pci_set_resource_alignment_param(str + 19,
4873 strlen(str + 19));
4874 } else if (!strncmp(str, "ecrc=", 5)) {
4875 pcie_ecrc_get_policy(str + 5);
4876 } else if (!strncmp(str, "hpiosize=", 9)) {
4877 pci_hotplug_io_size = memparse(str + 9, &str);
4878 } else if (!strncmp(str, "hpmemsize=", 10)) {
4879 pci_hotplug_mem_size = memparse(str + 10, &str);
4880 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4881 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4882 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4883 pcie_bus_config = PCIE_BUS_SAFE;
4884 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4885 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4886 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4887 pcie_bus_config = PCIE_BUS_PEER2PEER;
4888 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4889 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4890 } else {
4891 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4892 str);
4893 }
4894 }
4895 str = k;
4896 }
4897 return 0;
4898}
4899early_param("pci", pci_setup);
1/*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/acpi.h>
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/dmi.h>
14#include <linux/init.h>
15#include <linux/of.h>
16#include <linux/of_pci.h>
17#include <linux/pci.h>
18#include <linux/pm.h>
19#include <linux/slab.h>
20#include <linux/module.h>
21#include <linux/spinlock.h>
22#include <linux/string.h>
23#include <linux/log2.h>
24#include <linux/pci-aspm.h>
25#include <linux/pm_wakeup.h>
26#include <linux/interrupt.h>
27#include <linux/device.h>
28#include <linux/pm_runtime.h>
29#include <linux/pci_hotplug.h>
30#include <linux/vmalloc.h>
31#include <asm/setup.h>
32#include <asm/dma.h>
33#include <linux/aer.h>
34#include "pci.h"
35
36const char *pci_power_names[] = {
37 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
38};
39EXPORT_SYMBOL_GPL(pci_power_names);
40
41int isa_dma_bridge_buggy;
42EXPORT_SYMBOL(isa_dma_bridge_buggy);
43
44int pci_pci_problems;
45EXPORT_SYMBOL(pci_pci_problems);
46
47unsigned int pci_pm_d3_delay;
48
49static void pci_pme_list_scan(struct work_struct *work);
50
51static LIST_HEAD(pci_pme_list);
52static DEFINE_MUTEX(pci_pme_list_mutex);
53static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
54
55struct pci_pme_device {
56 struct list_head list;
57 struct pci_dev *dev;
58};
59
60#define PME_TIMEOUT 1000 /* How long between PME checks */
61
62static void pci_dev_d3_sleep(struct pci_dev *dev)
63{
64 unsigned int delay = dev->d3_delay;
65
66 if (delay < pci_pm_d3_delay)
67 delay = pci_pm_d3_delay;
68
69 msleep(delay);
70}
71
72#ifdef CONFIG_PCI_DOMAINS
73int pci_domains_supported = 1;
74#endif
75
76#define DEFAULT_CARDBUS_IO_SIZE (256)
77#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
78/* pci=cbmemsize=nnM,cbiosize=nn can override this */
79unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
80unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
81
82#define DEFAULT_HOTPLUG_IO_SIZE (256)
83#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
84/* pci=hpmemsize=nnM,hpiosize=nn can override this */
85unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
86unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
87
88#define DEFAULT_HOTPLUG_BUS_SIZE 1
89unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
90
91enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
92
93/*
94 * The default CLS is used if arch didn't set CLS explicitly and not
95 * all pci devices agree on the same value. Arch can override either
96 * the dfl or actual value as it sees fit. Don't forget this is
97 * measured in 32-bit words, not bytes.
98 */
99u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
100u8 pci_cache_line_size;
101
102/*
103 * If we set up a device for bus mastering, we need to check the latency
104 * timer as certain BIOSes forget to set it properly.
105 */
106unsigned int pcibios_max_latency = 255;
107
108/* If set, the PCIe ARI capability will not be used. */
109static bool pcie_ari_disabled;
110
111/* Disable bridge_d3 for all PCIe ports */
112static bool pci_bridge_d3_disable;
113/* Force bridge_d3 for all PCIe ports */
114static bool pci_bridge_d3_force;
115
116static int __init pcie_port_pm_setup(char *str)
117{
118 if (!strcmp(str, "off"))
119 pci_bridge_d3_disable = true;
120 else if (!strcmp(str, "force"))
121 pci_bridge_d3_force = true;
122 return 1;
123}
124__setup("pcie_port_pm=", pcie_port_pm_setup);
125
126/**
127 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
128 * @bus: pointer to PCI bus structure to search
129 *
130 * Given a PCI bus, returns the highest PCI bus number present in the set
131 * including the given PCI bus and its list of child PCI buses.
132 */
133unsigned char pci_bus_max_busnr(struct pci_bus *bus)
134{
135 struct pci_bus *tmp;
136 unsigned char max, n;
137
138 max = bus->busn_res.end;
139 list_for_each_entry(tmp, &bus->children, node) {
140 n = pci_bus_max_busnr(tmp);
141 if (n > max)
142 max = n;
143 }
144 return max;
145}
146EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
147
148#ifdef CONFIG_HAS_IOMEM
149void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
150{
151 struct resource *res = &pdev->resource[bar];
152
153 /*
154 * Make sure the BAR is actually a memory resource, not an IO resource
155 */
156 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
157 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
158 return NULL;
159 }
160 return ioremap_nocache(res->start, resource_size(res));
161}
162EXPORT_SYMBOL_GPL(pci_ioremap_bar);
163
164void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
165{
166 /*
167 * Make sure the BAR is actually a memory resource, not an IO resource
168 */
169 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
170 WARN_ON(1);
171 return NULL;
172 }
173 return ioremap_wc(pci_resource_start(pdev, bar),
174 pci_resource_len(pdev, bar));
175}
176EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
177#endif
178
179
180static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
181 u8 pos, int cap, int *ttl)
182{
183 u8 id;
184 u16 ent;
185
186 pci_bus_read_config_byte(bus, devfn, pos, &pos);
187
188 while ((*ttl)--) {
189 if (pos < 0x40)
190 break;
191 pos &= ~3;
192 pci_bus_read_config_word(bus, devfn, pos, &ent);
193
194 id = ent & 0xff;
195 if (id == 0xff)
196 break;
197 if (id == cap)
198 return pos;
199 pos = (ent >> 8);
200 }
201 return 0;
202}
203
204static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
205 u8 pos, int cap)
206{
207 int ttl = PCI_FIND_CAP_TTL;
208
209 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
210}
211
212int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
213{
214 return __pci_find_next_cap(dev->bus, dev->devfn,
215 pos + PCI_CAP_LIST_NEXT, cap);
216}
217EXPORT_SYMBOL_GPL(pci_find_next_capability);
218
219static int __pci_bus_find_cap_start(struct pci_bus *bus,
220 unsigned int devfn, u8 hdr_type)
221{
222 u16 status;
223
224 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
225 if (!(status & PCI_STATUS_CAP_LIST))
226 return 0;
227
228 switch (hdr_type) {
229 case PCI_HEADER_TYPE_NORMAL:
230 case PCI_HEADER_TYPE_BRIDGE:
231 return PCI_CAPABILITY_LIST;
232 case PCI_HEADER_TYPE_CARDBUS:
233 return PCI_CB_CAPABILITY_LIST;
234 }
235
236 return 0;
237}
238
239/**
240 * pci_find_capability - query for devices' capabilities
241 * @dev: PCI device to query
242 * @cap: capability code
243 *
244 * Tell if a device supports a given PCI capability.
245 * Returns the address of the requested capability structure within the
246 * device's PCI configuration space or 0 in case the device does not
247 * support it. Possible values for @cap:
248 *
249 * %PCI_CAP_ID_PM Power Management
250 * %PCI_CAP_ID_AGP Accelerated Graphics Port
251 * %PCI_CAP_ID_VPD Vital Product Data
252 * %PCI_CAP_ID_SLOTID Slot Identification
253 * %PCI_CAP_ID_MSI Message Signalled Interrupts
254 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
255 * %PCI_CAP_ID_PCIX PCI-X
256 * %PCI_CAP_ID_EXP PCI Express
257 */
258int pci_find_capability(struct pci_dev *dev, int cap)
259{
260 int pos;
261
262 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
263 if (pos)
264 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
265
266 return pos;
267}
268EXPORT_SYMBOL(pci_find_capability);
269
270/**
271 * pci_bus_find_capability - query for devices' capabilities
272 * @bus: the PCI bus to query
273 * @devfn: PCI device to query
274 * @cap: capability code
275 *
276 * Like pci_find_capability() but works for pci devices that do not have a
277 * pci_dev structure set up yet.
278 *
279 * Returns the address of the requested capability structure within the
280 * device's PCI configuration space or 0 in case the device does not
281 * support it.
282 */
283int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
284{
285 int pos;
286 u8 hdr_type;
287
288 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
289
290 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
291 if (pos)
292 pos = __pci_find_next_cap(bus, devfn, pos, cap);
293
294 return pos;
295}
296EXPORT_SYMBOL(pci_bus_find_capability);
297
298/**
299 * pci_find_next_ext_capability - Find an extended capability
300 * @dev: PCI device to query
301 * @start: address at which to start looking (0 to start at beginning of list)
302 * @cap: capability code
303 *
304 * Returns the address of the next matching extended capability structure
305 * within the device's PCI configuration space or 0 if the device does
306 * not support it. Some capabilities can occur several times, e.g., the
307 * vendor-specific capability, and this provides a way to find them all.
308 */
309int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
310{
311 u32 header;
312 int ttl;
313 int pos = PCI_CFG_SPACE_SIZE;
314
315 /* minimum 8 bytes per capability */
316 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
317
318 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
319 return 0;
320
321 if (start)
322 pos = start;
323
324 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
325 return 0;
326
327 /*
328 * If we have no capabilities, this is indicated by cap ID,
329 * cap version and next pointer all being 0.
330 */
331 if (header == 0)
332 return 0;
333
334 while (ttl-- > 0) {
335 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
336 return pos;
337
338 pos = PCI_EXT_CAP_NEXT(header);
339 if (pos < PCI_CFG_SPACE_SIZE)
340 break;
341
342 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
343 break;
344 }
345
346 return 0;
347}
348EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
349
350/**
351 * pci_find_ext_capability - Find an extended capability
352 * @dev: PCI device to query
353 * @cap: capability code
354 *
355 * Returns the address of the requested extended capability structure
356 * within the device's PCI configuration space or 0 if the device does
357 * not support it. Possible values for @cap:
358 *
359 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
360 * %PCI_EXT_CAP_ID_VC Virtual Channel
361 * %PCI_EXT_CAP_ID_DSN Device Serial Number
362 * %PCI_EXT_CAP_ID_PWR Power Budgeting
363 */
364int pci_find_ext_capability(struct pci_dev *dev, int cap)
365{
366 return pci_find_next_ext_capability(dev, 0, cap);
367}
368EXPORT_SYMBOL_GPL(pci_find_ext_capability);
369
370static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
371{
372 int rc, ttl = PCI_FIND_CAP_TTL;
373 u8 cap, mask;
374
375 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
376 mask = HT_3BIT_CAP_MASK;
377 else
378 mask = HT_5BIT_CAP_MASK;
379
380 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
381 PCI_CAP_ID_HT, &ttl);
382 while (pos) {
383 rc = pci_read_config_byte(dev, pos + 3, &cap);
384 if (rc != PCIBIOS_SUCCESSFUL)
385 return 0;
386
387 if ((cap & mask) == ht_cap)
388 return pos;
389
390 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
391 pos + PCI_CAP_LIST_NEXT,
392 PCI_CAP_ID_HT, &ttl);
393 }
394
395 return 0;
396}
397/**
398 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
399 * @dev: PCI device to query
400 * @pos: Position from which to continue searching
401 * @ht_cap: Hypertransport capability code
402 *
403 * To be used in conjunction with pci_find_ht_capability() to search for
404 * all capabilities matching @ht_cap. @pos should always be a value returned
405 * from pci_find_ht_capability().
406 *
407 * NB. To be 100% safe against broken PCI devices, the caller should take
408 * steps to avoid an infinite loop.
409 */
410int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
411{
412 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
413}
414EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
415
416/**
417 * pci_find_ht_capability - query a device's Hypertransport capabilities
418 * @dev: PCI device to query
419 * @ht_cap: Hypertransport capability code
420 *
421 * Tell if a device supports a given Hypertransport capability.
422 * Returns an address within the device's PCI configuration space
423 * or 0 in case the device does not support the request capability.
424 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
425 * which has a Hypertransport capability matching @ht_cap.
426 */
427int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
428{
429 int pos;
430
431 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
432 if (pos)
433 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
434
435 return pos;
436}
437EXPORT_SYMBOL_GPL(pci_find_ht_capability);
438
439/**
440 * pci_find_parent_resource - return resource region of parent bus of given region
441 * @dev: PCI device structure contains resources to be searched
442 * @res: child resource record for which parent is sought
443 *
444 * For given resource region of given device, return the resource
445 * region of parent bus the given region is contained in.
446 */
447struct resource *pci_find_parent_resource(const struct pci_dev *dev,
448 struct resource *res)
449{
450 const struct pci_bus *bus = dev->bus;
451 struct resource *r;
452 int i;
453
454 pci_bus_for_each_resource(bus, r, i) {
455 if (!r)
456 continue;
457 if (res->start && resource_contains(r, res)) {
458
459 /*
460 * If the window is prefetchable but the BAR is
461 * not, the allocator made a mistake.
462 */
463 if (r->flags & IORESOURCE_PREFETCH &&
464 !(res->flags & IORESOURCE_PREFETCH))
465 return NULL;
466
467 /*
468 * If we're below a transparent bridge, there may
469 * be both a positively-decoded aperture and a
470 * subtractively-decoded region that contain the BAR.
471 * We want the positively-decoded one, so this depends
472 * on pci_bus_for_each_resource() giving us those
473 * first.
474 */
475 return r;
476 }
477 }
478 return NULL;
479}
480EXPORT_SYMBOL(pci_find_parent_resource);
481
482/**
483 * pci_find_resource - Return matching PCI device resource
484 * @dev: PCI device to query
485 * @res: Resource to look for
486 *
487 * Goes over standard PCI resources (BARs) and checks if the given resource
488 * is partially or fully contained in any of them. In that case the
489 * matching resource is returned, %NULL otherwise.
490 */
491struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
492{
493 int i;
494
495 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
496 struct resource *r = &dev->resource[i];
497
498 if (r->start && resource_contains(r, res))
499 return r;
500 }
501
502 return NULL;
503}
504EXPORT_SYMBOL(pci_find_resource);
505
506/**
507 * pci_find_pcie_root_port - return PCIe Root Port
508 * @dev: PCI device to query
509 *
510 * Traverse up the parent chain and return the PCIe Root Port PCI Device
511 * for a given PCI Device.
512 */
513struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
514{
515 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
516
517 bridge = pci_upstream_bridge(dev);
518 while (bridge && pci_is_pcie(bridge)) {
519 highest_pcie_bridge = bridge;
520 bridge = pci_upstream_bridge(bridge);
521 }
522
523 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
524 return NULL;
525
526 return highest_pcie_bridge;
527}
528EXPORT_SYMBOL(pci_find_pcie_root_port);
529
530/**
531 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
532 * @dev: the PCI device to operate on
533 * @pos: config space offset of status word
534 * @mask: mask of bit(s) to care about in status word
535 *
536 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
537 */
538int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
539{
540 int i;
541
542 /* Wait for Transaction Pending bit clean */
543 for (i = 0; i < 4; i++) {
544 u16 status;
545 if (i)
546 msleep((1 << (i - 1)) * 100);
547
548 pci_read_config_word(dev, pos, &status);
549 if (!(status & mask))
550 return 1;
551 }
552
553 return 0;
554}
555
556/**
557 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
558 * @dev: PCI device to have its BARs restored
559 *
560 * Restore the BAR values for a given device, so as to make it
561 * accessible by its driver.
562 */
563static void pci_restore_bars(struct pci_dev *dev)
564{
565 int i;
566
567 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
568 pci_update_resource(dev, i);
569}
570
571static const struct pci_platform_pm_ops *pci_platform_pm;
572
573int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
574{
575 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
576 !ops->choose_state || !ops->sleep_wake || !ops->run_wake ||
577 !ops->need_resume)
578 return -EINVAL;
579 pci_platform_pm = ops;
580 return 0;
581}
582
583static inline bool platform_pci_power_manageable(struct pci_dev *dev)
584{
585 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
586}
587
588static inline int platform_pci_set_power_state(struct pci_dev *dev,
589 pci_power_t t)
590{
591 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
592}
593
594static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
595{
596 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
597}
598
599static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
600{
601 return pci_platform_pm ?
602 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
603}
604
605static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
606{
607 return pci_platform_pm ?
608 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
609}
610
611static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
612{
613 return pci_platform_pm ?
614 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
615}
616
617static inline bool platform_pci_need_resume(struct pci_dev *dev)
618{
619 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
620}
621
622/**
623 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
624 * given PCI device
625 * @dev: PCI device to handle.
626 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
627 *
628 * RETURN VALUE:
629 * -EINVAL if the requested state is invalid.
630 * -EIO if device does not support PCI PM or its PM capabilities register has a
631 * wrong version, or device doesn't support the requested state.
632 * 0 if device already is in the requested state.
633 * 0 if device's power state has been successfully changed.
634 */
635static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
636{
637 u16 pmcsr;
638 bool need_restore = false;
639
640 /* Check if we're already there */
641 if (dev->current_state == state)
642 return 0;
643
644 if (!dev->pm_cap)
645 return -EIO;
646
647 if (state < PCI_D0 || state > PCI_D3hot)
648 return -EINVAL;
649
650 /* Validate current state:
651 * Can enter D0 from any state, but if we can only go deeper
652 * to sleep if we're already in a low power state
653 */
654 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
655 && dev->current_state > state) {
656 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
657 dev->current_state, state);
658 return -EINVAL;
659 }
660
661 /* check if this device supports the desired state */
662 if ((state == PCI_D1 && !dev->d1_support)
663 || (state == PCI_D2 && !dev->d2_support))
664 return -EIO;
665
666 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
667
668 /* If we're (effectively) in D3, force entire word to 0.
669 * This doesn't affect PME_Status, disables PME_En, and
670 * sets PowerState to 0.
671 */
672 switch (dev->current_state) {
673 case PCI_D0:
674 case PCI_D1:
675 case PCI_D2:
676 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
677 pmcsr |= state;
678 break;
679 case PCI_D3hot:
680 case PCI_D3cold:
681 case PCI_UNKNOWN: /* Boot-up */
682 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
683 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
684 need_restore = true;
685 /* Fall-through: force to D0 */
686 default:
687 pmcsr = 0;
688 break;
689 }
690
691 /* enter specified state */
692 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
693
694 /* Mandatory power management transition delays */
695 /* see PCI PM 1.1 5.6.1 table 18 */
696 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
697 pci_dev_d3_sleep(dev);
698 else if (state == PCI_D2 || dev->current_state == PCI_D2)
699 udelay(PCI_PM_D2_DELAY);
700
701 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
702 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
703 if (dev->current_state != state && printk_ratelimit())
704 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
705 dev->current_state);
706
707 /*
708 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
709 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
710 * from D3hot to D0 _may_ perform an internal reset, thereby
711 * going to "D0 Uninitialized" rather than "D0 Initialized".
712 * For example, at least some versions of the 3c905B and the
713 * 3c556B exhibit this behaviour.
714 *
715 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
716 * devices in a D3hot state at boot. Consequently, we need to
717 * restore at least the BARs so that the device will be
718 * accessible to its driver.
719 */
720 if (need_restore)
721 pci_restore_bars(dev);
722
723 if (dev->bus->self)
724 pcie_aspm_pm_state_change(dev->bus->self);
725
726 return 0;
727}
728
729/**
730 * pci_update_current_state - Read power state of given device and cache it
731 * @dev: PCI device to handle.
732 * @state: State to cache in case the device doesn't have the PM capability
733 *
734 * The power state is read from the PMCSR register, which however is
735 * inaccessible in D3cold. The platform firmware is therefore queried first
736 * to detect accessibility of the register. In case the platform firmware
737 * reports an incorrect state or the device isn't power manageable by the
738 * platform at all, we try to detect D3cold by testing accessibility of the
739 * vendor ID in config space.
740 */
741void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
742{
743 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
744 !pci_device_is_present(dev)) {
745 dev->current_state = PCI_D3cold;
746 } else if (dev->pm_cap) {
747 u16 pmcsr;
748
749 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
750 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
751 } else {
752 dev->current_state = state;
753 }
754}
755
756/**
757 * pci_power_up - Put the given device into D0 forcibly
758 * @dev: PCI device to power up
759 */
760void pci_power_up(struct pci_dev *dev)
761{
762 if (platform_pci_power_manageable(dev))
763 platform_pci_set_power_state(dev, PCI_D0);
764
765 pci_raw_set_power_state(dev, PCI_D0);
766 pci_update_current_state(dev, PCI_D0);
767}
768
769/**
770 * pci_platform_power_transition - Use platform to change device power state
771 * @dev: PCI device to handle.
772 * @state: State to put the device into.
773 */
774static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
775{
776 int error;
777
778 if (platform_pci_power_manageable(dev)) {
779 error = platform_pci_set_power_state(dev, state);
780 if (!error)
781 pci_update_current_state(dev, state);
782 } else
783 error = -ENODEV;
784
785 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
786 dev->current_state = PCI_D0;
787
788 return error;
789}
790
791/**
792 * pci_wakeup - Wake up a PCI device
793 * @pci_dev: Device to handle.
794 * @ign: ignored parameter
795 */
796static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
797{
798 pci_wakeup_event(pci_dev);
799 pm_request_resume(&pci_dev->dev);
800 return 0;
801}
802
803/**
804 * pci_wakeup_bus - Walk given bus and wake up devices on it
805 * @bus: Top bus of the subtree to walk.
806 */
807static void pci_wakeup_bus(struct pci_bus *bus)
808{
809 if (bus)
810 pci_walk_bus(bus, pci_wakeup, NULL);
811}
812
813/**
814 * __pci_start_power_transition - Start power transition of a PCI device
815 * @dev: PCI device to handle.
816 * @state: State to put the device into.
817 */
818static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
819{
820 if (state == PCI_D0) {
821 pci_platform_power_transition(dev, PCI_D0);
822 /*
823 * Mandatory power management transition delays, see
824 * PCI Express Base Specification Revision 2.0 Section
825 * 6.6.1: Conventional Reset. Do not delay for
826 * devices powered on/off by corresponding bridge,
827 * because have already delayed for the bridge.
828 */
829 if (dev->runtime_d3cold) {
830 msleep(dev->d3cold_delay);
831 /*
832 * When powering on a bridge from D3cold, the
833 * whole hierarchy may be powered on into
834 * D0uninitialized state, resume them to give
835 * them a chance to suspend again
836 */
837 pci_wakeup_bus(dev->subordinate);
838 }
839 }
840}
841
842/**
843 * __pci_dev_set_current_state - Set current state of a PCI device
844 * @dev: Device to handle
845 * @data: pointer to state to be set
846 */
847static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
848{
849 pci_power_t state = *(pci_power_t *)data;
850
851 dev->current_state = state;
852 return 0;
853}
854
855/**
856 * __pci_bus_set_current_state - Walk given bus and set current state of devices
857 * @bus: Top bus of the subtree to walk.
858 * @state: state to be set
859 */
860static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
861{
862 if (bus)
863 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
864}
865
866/**
867 * __pci_complete_power_transition - Complete power transition of a PCI device
868 * @dev: PCI device to handle.
869 * @state: State to put the device into.
870 *
871 * This function should not be called directly by device drivers.
872 */
873int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
874{
875 int ret;
876
877 if (state <= PCI_D0)
878 return -EINVAL;
879 ret = pci_platform_power_transition(dev, state);
880 /* Power off the bridge may power off the whole hierarchy */
881 if (!ret && state == PCI_D3cold)
882 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
883 return ret;
884}
885EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
886
887/**
888 * pci_set_power_state - Set the power state of a PCI device
889 * @dev: PCI device to handle.
890 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
891 *
892 * Transition a device to a new power state, using the platform firmware and/or
893 * the device's PCI PM registers.
894 *
895 * RETURN VALUE:
896 * -EINVAL if the requested state is invalid.
897 * -EIO if device does not support PCI PM or its PM capabilities register has a
898 * wrong version, or device doesn't support the requested state.
899 * 0 if device already is in the requested state.
900 * 0 if device's power state has been successfully changed.
901 */
902int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
903{
904 int error;
905
906 /* bound the state we're entering */
907 if (state > PCI_D3cold)
908 state = PCI_D3cold;
909 else if (state < PCI_D0)
910 state = PCI_D0;
911 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
912 /*
913 * If the device or the parent bridge do not support PCI PM,
914 * ignore the request if we're doing anything other than putting
915 * it into D0 (which would only happen on boot).
916 */
917 return 0;
918
919 /* Check if we're already there */
920 if (dev->current_state == state)
921 return 0;
922
923 __pci_start_power_transition(dev, state);
924
925 /* This device is quirked not to be put into D3, so
926 don't put it in D3 */
927 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
928 return 0;
929
930 /*
931 * To put device in D3cold, we put device into D3hot in native
932 * way, then put device into D3cold with platform ops
933 */
934 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
935 PCI_D3hot : state);
936
937 if (!__pci_complete_power_transition(dev, state))
938 error = 0;
939
940 return error;
941}
942EXPORT_SYMBOL(pci_set_power_state);
943
944/**
945 * pci_choose_state - Choose the power state of a PCI device
946 * @dev: PCI device to be suspended
947 * @state: target sleep state for the whole system. This is the value
948 * that is passed to suspend() function.
949 *
950 * Returns PCI power state suitable for given device and given system
951 * message.
952 */
953
954pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
955{
956 pci_power_t ret;
957
958 if (!dev->pm_cap)
959 return PCI_D0;
960
961 ret = platform_pci_choose_state(dev);
962 if (ret != PCI_POWER_ERROR)
963 return ret;
964
965 switch (state.event) {
966 case PM_EVENT_ON:
967 return PCI_D0;
968 case PM_EVENT_FREEZE:
969 case PM_EVENT_PRETHAW:
970 /* REVISIT both freeze and pre-thaw "should" use D0 */
971 case PM_EVENT_SUSPEND:
972 case PM_EVENT_HIBERNATE:
973 return PCI_D3hot;
974 default:
975 dev_info(&dev->dev, "unrecognized suspend event %d\n",
976 state.event);
977 BUG();
978 }
979 return PCI_D0;
980}
981EXPORT_SYMBOL(pci_choose_state);
982
983#define PCI_EXP_SAVE_REGS 7
984
985static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
986 u16 cap, bool extended)
987{
988 struct pci_cap_saved_state *tmp;
989
990 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
991 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
992 return tmp;
993 }
994 return NULL;
995}
996
997struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
998{
999 return _pci_find_saved_cap(dev, cap, false);
1000}
1001
1002struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1003{
1004 return _pci_find_saved_cap(dev, cap, true);
1005}
1006
1007static int pci_save_pcie_state(struct pci_dev *dev)
1008{
1009 int i = 0;
1010 struct pci_cap_saved_state *save_state;
1011 u16 *cap;
1012
1013 if (!pci_is_pcie(dev))
1014 return 0;
1015
1016 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1017 if (!save_state) {
1018 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1019 return -ENOMEM;
1020 }
1021
1022 cap = (u16 *)&save_state->cap.data[0];
1023 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1024 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1025 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1026 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1027 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1028 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1029 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1030
1031 return 0;
1032}
1033
1034static void pci_restore_pcie_state(struct pci_dev *dev)
1035{
1036 int i = 0;
1037 struct pci_cap_saved_state *save_state;
1038 u16 *cap;
1039
1040 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1041 if (!save_state)
1042 return;
1043
1044 cap = (u16 *)&save_state->cap.data[0];
1045 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1046 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1047 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1048 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1049 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1050 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1051 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1052}
1053
1054
1055static int pci_save_pcix_state(struct pci_dev *dev)
1056{
1057 int pos;
1058 struct pci_cap_saved_state *save_state;
1059
1060 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1061 if (!pos)
1062 return 0;
1063
1064 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1065 if (!save_state) {
1066 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1067 return -ENOMEM;
1068 }
1069
1070 pci_read_config_word(dev, pos + PCI_X_CMD,
1071 (u16 *)save_state->cap.data);
1072
1073 return 0;
1074}
1075
1076static void pci_restore_pcix_state(struct pci_dev *dev)
1077{
1078 int i = 0, pos;
1079 struct pci_cap_saved_state *save_state;
1080 u16 *cap;
1081
1082 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1083 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1084 if (!save_state || !pos)
1085 return;
1086 cap = (u16 *)&save_state->cap.data[0];
1087
1088 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1089}
1090
1091
1092/**
1093 * pci_save_state - save the PCI configuration space of a device before suspending
1094 * @dev: - PCI device that we're dealing with
1095 */
1096int pci_save_state(struct pci_dev *dev)
1097{
1098 int i;
1099 /* XXX: 100% dword access ok here? */
1100 for (i = 0; i < 16; i++)
1101 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1102 dev->state_saved = true;
1103
1104 i = pci_save_pcie_state(dev);
1105 if (i != 0)
1106 return i;
1107
1108 i = pci_save_pcix_state(dev);
1109 if (i != 0)
1110 return i;
1111
1112 return pci_save_vc_state(dev);
1113}
1114EXPORT_SYMBOL(pci_save_state);
1115
1116static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1117 u32 saved_val, int retry)
1118{
1119 u32 val;
1120
1121 pci_read_config_dword(pdev, offset, &val);
1122 if (val == saved_val)
1123 return;
1124
1125 for (;;) {
1126 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1127 offset, val, saved_val);
1128 pci_write_config_dword(pdev, offset, saved_val);
1129 if (retry-- <= 0)
1130 return;
1131
1132 pci_read_config_dword(pdev, offset, &val);
1133 if (val == saved_val)
1134 return;
1135
1136 mdelay(1);
1137 }
1138}
1139
1140static void pci_restore_config_space_range(struct pci_dev *pdev,
1141 int start, int end, int retry)
1142{
1143 int index;
1144
1145 for (index = end; index >= start; index--)
1146 pci_restore_config_dword(pdev, 4 * index,
1147 pdev->saved_config_space[index],
1148 retry);
1149}
1150
1151static void pci_restore_config_space(struct pci_dev *pdev)
1152{
1153 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1154 pci_restore_config_space_range(pdev, 10, 15, 0);
1155 /* Restore BARs before the command register. */
1156 pci_restore_config_space_range(pdev, 4, 9, 10);
1157 pci_restore_config_space_range(pdev, 0, 3, 0);
1158 } else {
1159 pci_restore_config_space_range(pdev, 0, 15, 0);
1160 }
1161}
1162
1163/**
1164 * pci_restore_state - Restore the saved state of a PCI device
1165 * @dev: - PCI device that we're dealing with
1166 */
1167void pci_restore_state(struct pci_dev *dev)
1168{
1169 if (!dev->state_saved)
1170 return;
1171
1172 /* PCI Express register must be restored first */
1173 pci_restore_pcie_state(dev);
1174 pci_restore_ats_state(dev);
1175 pci_restore_vc_state(dev);
1176
1177 pci_cleanup_aer_error_status_regs(dev);
1178
1179 pci_restore_config_space(dev);
1180
1181 pci_restore_pcix_state(dev);
1182 pci_restore_msi_state(dev);
1183
1184 /* Restore ACS and IOV configuration state */
1185 pci_enable_acs(dev);
1186 pci_restore_iov_state(dev);
1187
1188 dev->state_saved = false;
1189}
1190EXPORT_SYMBOL(pci_restore_state);
1191
1192struct pci_saved_state {
1193 u32 config_space[16];
1194 struct pci_cap_saved_data cap[0];
1195};
1196
1197/**
1198 * pci_store_saved_state - Allocate and return an opaque struct containing
1199 * the device saved state.
1200 * @dev: PCI device that we're dealing with
1201 *
1202 * Return NULL if no state or error.
1203 */
1204struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1205{
1206 struct pci_saved_state *state;
1207 struct pci_cap_saved_state *tmp;
1208 struct pci_cap_saved_data *cap;
1209 size_t size;
1210
1211 if (!dev->state_saved)
1212 return NULL;
1213
1214 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1215
1216 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1217 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1218
1219 state = kzalloc(size, GFP_KERNEL);
1220 if (!state)
1221 return NULL;
1222
1223 memcpy(state->config_space, dev->saved_config_space,
1224 sizeof(state->config_space));
1225
1226 cap = state->cap;
1227 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1228 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1229 memcpy(cap, &tmp->cap, len);
1230 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1231 }
1232 /* Empty cap_save terminates list */
1233
1234 return state;
1235}
1236EXPORT_SYMBOL_GPL(pci_store_saved_state);
1237
1238/**
1239 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1240 * @dev: PCI device that we're dealing with
1241 * @state: Saved state returned from pci_store_saved_state()
1242 */
1243int pci_load_saved_state(struct pci_dev *dev,
1244 struct pci_saved_state *state)
1245{
1246 struct pci_cap_saved_data *cap;
1247
1248 dev->state_saved = false;
1249
1250 if (!state)
1251 return 0;
1252
1253 memcpy(dev->saved_config_space, state->config_space,
1254 sizeof(state->config_space));
1255
1256 cap = state->cap;
1257 while (cap->size) {
1258 struct pci_cap_saved_state *tmp;
1259
1260 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1261 if (!tmp || tmp->cap.size != cap->size)
1262 return -EINVAL;
1263
1264 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1265 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1266 sizeof(struct pci_cap_saved_data) + cap->size);
1267 }
1268
1269 dev->state_saved = true;
1270 return 0;
1271}
1272EXPORT_SYMBOL_GPL(pci_load_saved_state);
1273
1274/**
1275 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1276 * and free the memory allocated for it.
1277 * @dev: PCI device that we're dealing with
1278 * @state: Pointer to saved state returned from pci_store_saved_state()
1279 */
1280int pci_load_and_free_saved_state(struct pci_dev *dev,
1281 struct pci_saved_state **state)
1282{
1283 int ret = pci_load_saved_state(dev, *state);
1284 kfree(*state);
1285 *state = NULL;
1286 return ret;
1287}
1288EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1289
1290int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1291{
1292 return pci_enable_resources(dev, bars);
1293}
1294
1295static int do_pci_enable_device(struct pci_dev *dev, int bars)
1296{
1297 int err;
1298 struct pci_dev *bridge;
1299 u16 cmd;
1300 u8 pin;
1301
1302 err = pci_set_power_state(dev, PCI_D0);
1303 if (err < 0 && err != -EIO)
1304 return err;
1305
1306 bridge = pci_upstream_bridge(dev);
1307 if (bridge)
1308 pcie_aspm_powersave_config_link(bridge);
1309
1310 err = pcibios_enable_device(dev, bars);
1311 if (err < 0)
1312 return err;
1313 pci_fixup_device(pci_fixup_enable, dev);
1314
1315 if (dev->msi_enabled || dev->msix_enabled)
1316 return 0;
1317
1318 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1319 if (pin) {
1320 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1321 if (cmd & PCI_COMMAND_INTX_DISABLE)
1322 pci_write_config_word(dev, PCI_COMMAND,
1323 cmd & ~PCI_COMMAND_INTX_DISABLE);
1324 }
1325
1326 return 0;
1327}
1328
1329/**
1330 * pci_reenable_device - Resume abandoned device
1331 * @dev: PCI device to be resumed
1332 *
1333 * Note this function is a backend of pci_default_resume and is not supposed
1334 * to be called by normal code, write proper resume handler and use it instead.
1335 */
1336int pci_reenable_device(struct pci_dev *dev)
1337{
1338 if (pci_is_enabled(dev))
1339 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1340 return 0;
1341}
1342EXPORT_SYMBOL(pci_reenable_device);
1343
1344static void pci_enable_bridge(struct pci_dev *dev)
1345{
1346 struct pci_dev *bridge;
1347 int retval;
1348
1349 bridge = pci_upstream_bridge(dev);
1350 if (bridge)
1351 pci_enable_bridge(bridge);
1352
1353 if (pci_is_enabled(dev)) {
1354 if (!dev->is_busmaster)
1355 pci_set_master(dev);
1356 return;
1357 }
1358
1359 retval = pci_enable_device(dev);
1360 if (retval)
1361 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1362 retval);
1363 pci_set_master(dev);
1364}
1365
1366static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1367{
1368 struct pci_dev *bridge;
1369 int err;
1370 int i, bars = 0;
1371
1372 /*
1373 * Power state could be unknown at this point, either due to a fresh
1374 * boot or a device removal call. So get the current power state
1375 * so that things like MSI message writing will behave as expected
1376 * (e.g. if the device really is in D0 at enable time).
1377 */
1378 if (dev->pm_cap) {
1379 u16 pmcsr;
1380 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1381 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1382 }
1383
1384 if (atomic_inc_return(&dev->enable_cnt) > 1)
1385 return 0; /* already enabled */
1386
1387 bridge = pci_upstream_bridge(dev);
1388 if (bridge)
1389 pci_enable_bridge(bridge);
1390
1391 /* only skip sriov related */
1392 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1393 if (dev->resource[i].flags & flags)
1394 bars |= (1 << i);
1395 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1396 if (dev->resource[i].flags & flags)
1397 bars |= (1 << i);
1398
1399 err = do_pci_enable_device(dev, bars);
1400 if (err < 0)
1401 atomic_dec(&dev->enable_cnt);
1402 return err;
1403}
1404
1405/**
1406 * pci_enable_device_io - Initialize a device for use with IO space
1407 * @dev: PCI device to be initialized
1408 *
1409 * Initialize device before it's used by a driver. Ask low-level code
1410 * to enable I/O resources. Wake up the device if it was suspended.
1411 * Beware, this function can fail.
1412 */
1413int pci_enable_device_io(struct pci_dev *dev)
1414{
1415 return pci_enable_device_flags(dev, IORESOURCE_IO);
1416}
1417EXPORT_SYMBOL(pci_enable_device_io);
1418
1419/**
1420 * pci_enable_device_mem - Initialize a device for use with Memory space
1421 * @dev: PCI device to be initialized
1422 *
1423 * Initialize device before it's used by a driver. Ask low-level code
1424 * to enable Memory resources. Wake up the device if it was suspended.
1425 * Beware, this function can fail.
1426 */
1427int pci_enable_device_mem(struct pci_dev *dev)
1428{
1429 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1430}
1431EXPORT_SYMBOL(pci_enable_device_mem);
1432
1433/**
1434 * pci_enable_device - Initialize device before it's used by a driver.
1435 * @dev: PCI device to be initialized
1436 *
1437 * Initialize device before it's used by a driver. Ask low-level code
1438 * to enable I/O and memory. Wake up the device if it was suspended.
1439 * Beware, this function can fail.
1440 *
1441 * Note we don't actually enable the device many times if we call
1442 * this function repeatedly (we just increment the count).
1443 */
1444int pci_enable_device(struct pci_dev *dev)
1445{
1446 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1447}
1448EXPORT_SYMBOL(pci_enable_device);
1449
1450/*
1451 * Managed PCI resources. This manages device on/off, intx/msi/msix
1452 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1453 * there's no need to track it separately. pci_devres is initialized
1454 * when a device is enabled using managed PCI device enable interface.
1455 */
1456struct pci_devres {
1457 unsigned int enabled:1;
1458 unsigned int pinned:1;
1459 unsigned int orig_intx:1;
1460 unsigned int restore_intx:1;
1461 u32 region_mask;
1462};
1463
1464static void pcim_release(struct device *gendev, void *res)
1465{
1466 struct pci_dev *dev = to_pci_dev(gendev);
1467 struct pci_devres *this = res;
1468 int i;
1469
1470 if (dev->msi_enabled)
1471 pci_disable_msi(dev);
1472 if (dev->msix_enabled)
1473 pci_disable_msix(dev);
1474
1475 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1476 if (this->region_mask & (1 << i))
1477 pci_release_region(dev, i);
1478
1479 if (this->restore_intx)
1480 pci_intx(dev, this->orig_intx);
1481
1482 if (this->enabled && !this->pinned)
1483 pci_disable_device(dev);
1484}
1485
1486static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1487{
1488 struct pci_devres *dr, *new_dr;
1489
1490 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1491 if (dr)
1492 return dr;
1493
1494 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1495 if (!new_dr)
1496 return NULL;
1497 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1498}
1499
1500static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1501{
1502 if (pci_is_managed(pdev))
1503 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1504 return NULL;
1505}
1506
1507/**
1508 * pcim_enable_device - Managed pci_enable_device()
1509 * @pdev: PCI device to be initialized
1510 *
1511 * Managed pci_enable_device().
1512 */
1513int pcim_enable_device(struct pci_dev *pdev)
1514{
1515 struct pci_devres *dr;
1516 int rc;
1517
1518 dr = get_pci_dr(pdev);
1519 if (unlikely(!dr))
1520 return -ENOMEM;
1521 if (dr->enabled)
1522 return 0;
1523
1524 rc = pci_enable_device(pdev);
1525 if (!rc) {
1526 pdev->is_managed = 1;
1527 dr->enabled = 1;
1528 }
1529 return rc;
1530}
1531EXPORT_SYMBOL(pcim_enable_device);
1532
1533/**
1534 * pcim_pin_device - Pin managed PCI device
1535 * @pdev: PCI device to pin
1536 *
1537 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1538 * driver detach. @pdev must have been enabled with
1539 * pcim_enable_device().
1540 */
1541void pcim_pin_device(struct pci_dev *pdev)
1542{
1543 struct pci_devres *dr;
1544
1545 dr = find_pci_dr(pdev);
1546 WARN_ON(!dr || !dr->enabled);
1547 if (dr)
1548 dr->pinned = 1;
1549}
1550EXPORT_SYMBOL(pcim_pin_device);
1551
1552/*
1553 * pcibios_add_device - provide arch specific hooks when adding device dev
1554 * @dev: the PCI device being added
1555 *
1556 * Permits the platform to provide architecture specific functionality when
1557 * devices are added. This is the default implementation. Architecture
1558 * implementations can override this.
1559 */
1560int __weak pcibios_add_device(struct pci_dev *dev)
1561{
1562 return 0;
1563}
1564
1565/**
1566 * pcibios_release_device - provide arch specific hooks when releasing device dev
1567 * @dev: the PCI device being released
1568 *
1569 * Permits the platform to provide architecture specific functionality when
1570 * devices are released. This is the default implementation. Architecture
1571 * implementations can override this.
1572 */
1573void __weak pcibios_release_device(struct pci_dev *dev) {}
1574
1575/**
1576 * pcibios_disable_device - disable arch specific PCI resources for device dev
1577 * @dev: the PCI device to disable
1578 *
1579 * Disables architecture specific PCI resources for the device. This
1580 * is the default implementation. Architecture implementations can
1581 * override this.
1582 */
1583void __weak pcibios_disable_device(struct pci_dev *dev) {}
1584
1585/**
1586 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1587 * @irq: ISA IRQ to penalize
1588 * @active: IRQ active or not
1589 *
1590 * Permits the platform to provide architecture-specific functionality when
1591 * penalizing ISA IRQs. This is the default implementation. Architecture
1592 * implementations can override this.
1593 */
1594void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1595
1596static void do_pci_disable_device(struct pci_dev *dev)
1597{
1598 u16 pci_command;
1599
1600 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1601 if (pci_command & PCI_COMMAND_MASTER) {
1602 pci_command &= ~PCI_COMMAND_MASTER;
1603 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1604 }
1605
1606 pcibios_disable_device(dev);
1607}
1608
1609/**
1610 * pci_disable_enabled_device - Disable device without updating enable_cnt
1611 * @dev: PCI device to disable
1612 *
1613 * NOTE: This function is a backend of PCI power management routines and is
1614 * not supposed to be called drivers.
1615 */
1616void pci_disable_enabled_device(struct pci_dev *dev)
1617{
1618 if (pci_is_enabled(dev))
1619 do_pci_disable_device(dev);
1620}
1621
1622/**
1623 * pci_disable_device - Disable PCI device after use
1624 * @dev: PCI device to be disabled
1625 *
1626 * Signal to the system that the PCI device is not in use by the system
1627 * anymore. This only involves disabling PCI bus-mastering, if active.
1628 *
1629 * Note we don't actually disable the device until all callers of
1630 * pci_enable_device() have called pci_disable_device().
1631 */
1632void pci_disable_device(struct pci_dev *dev)
1633{
1634 struct pci_devres *dr;
1635
1636 dr = find_pci_dr(dev);
1637 if (dr)
1638 dr->enabled = 0;
1639
1640 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1641 "disabling already-disabled device");
1642
1643 if (atomic_dec_return(&dev->enable_cnt) != 0)
1644 return;
1645
1646 do_pci_disable_device(dev);
1647
1648 dev->is_busmaster = 0;
1649}
1650EXPORT_SYMBOL(pci_disable_device);
1651
1652/**
1653 * pcibios_set_pcie_reset_state - set reset state for device dev
1654 * @dev: the PCIe device reset
1655 * @state: Reset state to enter into
1656 *
1657 *
1658 * Sets the PCIe reset state for the device. This is the default
1659 * implementation. Architecture implementations can override this.
1660 */
1661int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1662 enum pcie_reset_state state)
1663{
1664 return -EINVAL;
1665}
1666
1667/**
1668 * pci_set_pcie_reset_state - set reset state for device dev
1669 * @dev: the PCIe device reset
1670 * @state: Reset state to enter into
1671 *
1672 *
1673 * Sets the PCI reset state for the device.
1674 */
1675int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1676{
1677 return pcibios_set_pcie_reset_state(dev, state);
1678}
1679EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1680
1681/**
1682 * pci_check_pme_status - Check if given device has generated PME.
1683 * @dev: Device to check.
1684 *
1685 * Check the PME status of the device and if set, clear it and clear PME enable
1686 * (if set). Return 'true' if PME status and PME enable were both set or
1687 * 'false' otherwise.
1688 */
1689bool pci_check_pme_status(struct pci_dev *dev)
1690{
1691 int pmcsr_pos;
1692 u16 pmcsr;
1693 bool ret = false;
1694
1695 if (!dev->pm_cap)
1696 return false;
1697
1698 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1699 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1700 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1701 return false;
1702
1703 /* Clear PME status. */
1704 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1705 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1706 /* Disable PME to avoid interrupt flood. */
1707 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1708 ret = true;
1709 }
1710
1711 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1712
1713 return ret;
1714}
1715
1716/**
1717 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1718 * @dev: Device to handle.
1719 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1720 *
1721 * Check if @dev has generated PME and queue a resume request for it in that
1722 * case.
1723 */
1724static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1725{
1726 if (pme_poll_reset && dev->pme_poll)
1727 dev->pme_poll = false;
1728
1729 if (pci_check_pme_status(dev)) {
1730 pci_wakeup_event(dev);
1731 pm_request_resume(&dev->dev);
1732 }
1733 return 0;
1734}
1735
1736/**
1737 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1738 * @bus: Top bus of the subtree to walk.
1739 */
1740void pci_pme_wakeup_bus(struct pci_bus *bus)
1741{
1742 if (bus)
1743 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1744}
1745
1746
1747/**
1748 * pci_pme_capable - check the capability of PCI device to generate PME#
1749 * @dev: PCI device to handle.
1750 * @state: PCI state from which device will issue PME#.
1751 */
1752bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1753{
1754 if (!dev->pm_cap)
1755 return false;
1756
1757 return !!(dev->pme_support & (1 << state));
1758}
1759EXPORT_SYMBOL(pci_pme_capable);
1760
1761static void pci_pme_list_scan(struct work_struct *work)
1762{
1763 struct pci_pme_device *pme_dev, *n;
1764
1765 mutex_lock(&pci_pme_list_mutex);
1766 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1767 if (pme_dev->dev->pme_poll) {
1768 struct pci_dev *bridge;
1769
1770 bridge = pme_dev->dev->bus->self;
1771 /*
1772 * If bridge is in low power state, the
1773 * configuration space of subordinate devices
1774 * may be not accessible
1775 */
1776 if (bridge && bridge->current_state != PCI_D0)
1777 continue;
1778 pci_pme_wakeup(pme_dev->dev, NULL);
1779 } else {
1780 list_del(&pme_dev->list);
1781 kfree(pme_dev);
1782 }
1783 }
1784 if (!list_empty(&pci_pme_list))
1785 schedule_delayed_work(&pci_pme_work,
1786 msecs_to_jiffies(PME_TIMEOUT));
1787 mutex_unlock(&pci_pme_list_mutex);
1788}
1789
1790static void __pci_pme_active(struct pci_dev *dev, bool enable)
1791{
1792 u16 pmcsr;
1793
1794 if (!dev->pme_support)
1795 return;
1796
1797 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1798 /* Clear PME_Status by writing 1 to it and enable PME# */
1799 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1800 if (!enable)
1801 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1802
1803 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1804}
1805
1806/**
1807 * pci_pme_active - enable or disable PCI device's PME# function
1808 * @dev: PCI device to handle.
1809 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1810 *
1811 * The caller must verify that the device is capable of generating PME# before
1812 * calling this function with @enable equal to 'true'.
1813 */
1814void pci_pme_active(struct pci_dev *dev, bool enable)
1815{
1816 __pci_pme_active(dev, enable);
1817
1818 /*
1819 * PCI (as opposed to PCIe) PME requires that the device have
1820 * its PME# line hooked up correctly. Not all hardware vendors
1821 * do this, so the PME never gets delivered and the device
1822 * remains asleep. The easiest way around this is to
1823 * periodically walk the list of suspended devices and check
1824 * whether any have their PME flag set. The assumption is that
1825 * we'll wake up often enough anyway that this won't be a huge
1826 * hit, and the power savings from the devices will still be a
1827 * win.
1828 *
1829 * Although PCIe uses in-band PME message instead of PME# line
1830 * to report PME, PME does not work for some PCIe devices in
1831 * reality. For example, there are devices that set their PME
1832 * status bits, but don't really bother to send a PME message;
1833 * there are PCI Express Root Ports that don't bother to
1834 * trigger interrupts when they receive PME messages from the
1835 * devices below. So PME poll is used for PCIe devices too.
1836 */
1837
1838 if (dev->pme_poll) {
1839 struct pci_pme_device *pme_dev;
1840 if (enable) {
1841 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1842 GFP_KERNEL);
1843 if (!pme_dev) {
1844 dev_warn(&dev->dev, "can't enable PME#\n");
1845 return;
1846 }
1847 pme_dev->dev = dev;
1848 mutex_lock(&pci_pme_list_mutex);
1849 list_add(&pme_dev->list, &pci_pme_list);
1850 if (list_is_singular(&pci_pme_list))
1851 schedule_delayed_work(&pci_pme_work,
1852 msecs_to_jiffies(PME_TIMEOUT));
1853 mutex_unlock(&pci_pme_list_mutex);
1854 } else {
1855 mutex_lock(&pci_pme_list_mutex);
1856 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1857 if (pme_dev->dev == dev) {
1858 list_del(&pme_dev->list);
1859 kfree(pme_dev);
1860 break;
1861 }
1862 }
1863 mutex_unlock(&pci_pme_list_mutex);
1864 }
1865 }
1866
1867 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1868}
1869EXPORT_SYMBOL(pci_pme_active);
1870
1871/**
1872 * __pci_enable_wake - enable PCI device as wakeup event source
1873 * @dev: PCI device affected
1874 * @state: PCI state from which device will issue wakeup events
1875 * @runtime: True if the events are to be generated at run time
1876 * @enable: True to enable event generation; false to disable
1877 *
1878 * This enables the device as a wakeup event source, or disables it.
1879 * When such events involves platform-specific hooks, those hooks are
1880 * called automatically by this routine.
1881 *
1882 * Devices with legacy power management (no standard PCI PM capabilities)
1883 * always require such platform hooks.
1884 *
1885 * RETURN VALUE:
1886 * 0 is returned on success
1887 * -EINVAL is returned if device is not supposed to wake up the system
1888 * Error code depending on the platform is returned if both the platform and
1889 * the native mechanism fail to enable the generation of wake-up events
1890 */
1891int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1892 bool runtime, bool enable)
1893{
1894 int ret = 0;
1895
1896 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1897 return -EINVAL;
1898
1899 /* Don't do the same thing twice in a row for one device. */
1900 if (!!enable == !!dev->wakeup_prepared)
1901 return 0;
1902
1903 /*
1904 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1905 * Anderson we should be doing PME# wake enable followed by ACPI wake
1906 * enable. To disable wake-up we call the platform first, for symmetry.
1907 */
1908
1909 if (enable) {
1910 int error;
1911
1912 if (pci_pme_capable(dev, state))
1913 pci_pme_active(dev, true);
1914 else
1915 ret = 1;
1916 error = runtime ? platform_pci_run_wake(dev, true) :
1917 platform_pci_sleep_wake(dev, true);
1918 if (ret)
1919 ret = error;
1920 if (!ret)
1921 dev->wakeup_prepared = true;
1922 } else {
1923 if (runtime)
1924 platform_pci_run_wake(dev, false);
1925 else
1926 platform_pci_sleep_wake(dev, false);
1927 pci_pme_active(dev, false);
1928 dev->wakeup_prepared = false;
1929 }
1930
1931 return ret;
1932}
1933EXPORT_SYMBOL(__pci_enable_wake);
1934
1935/**
1936 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1937 * @dev: PCI device to prepare
1938 * @enable: True to enable wake-up event generation; false to disable
1939 *
1940 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1941 * and this function allows them to set that up cleanly - pci_enable_wake()
1942 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1943 * ordering constraints.
1944 *
1945 * This function only returns error code if the device is not capable of
1946 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1947 * enable wake-up power for it.
1948 */
1949int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1950{
1951 return pci_pme_capable(dev, PCI_D3cold) ?
1952 pci_enable_wake(dev, PCI_D3cold, enable) :
1953 pci_enable_wake(dev, PCI_D3hot, enable);
1954}
1955EXPORT_SYMBOL(pci_wake_from_d3);
1956
1957/**
1958 * pci_target_state - find an appropriate low power state for a given PCI dev
1959 * @dev: PCI device
1960 *
1961 * Use underlying platform code to find a supported low power state for @dev.
1962 * If the platform can't manage @dev, return the deepest state from which it
1963 * can generate wake events, based on any available PME info.
1964 */
1965static pci_power_t pci_target_state(struct pci_dev *dev)
1966{
1967 pci_power_t target_state = PCI_D3hot;
1968
1969 if (platform_pci_power_manageable(dev)) {
1970 /*
1971 * Call the platform to choose the target state of the device
1972 * and enable wake-up from this state if supported.
1973 */
1974 pci_power_t state = platform_pci_choose_state(dev);
1975
1976 switch (state) {
1977 case PCI_POWER_ERROR:
1978 case PCI_UNKNOWN:
1979 break;
1980 case PCI_D1:
1981 case PCI_D2:
1982 if (pci_no_d1d2(dev))
1983 break;
1984 default:
1985 target_state = state;
1986 }
1987
1988 return target_state;
1989 }
1990
1991 if (!dev->pm_cap)
1992 target_state = PCI_D0;
1993
1994 /*
1995 * If the device is in D3cold even though it's not power-manageable by
1996 * the platform, it may have been powered down by non-standard means.
1997 * Best to let it slumber.
1998 */
1999 if (dev->current_state == PCI_D3cold)
2000 target_state = PCI_D3cold;
2001
2002 if (device_may_wakeup(&dev->dev)) {
2003 /*
2004 * Find the deepest state from which the device can generate
2005 * wake-up events, make it the target state and enable device
2006 * to generate PME#.
2007 */
2008 if (dev->pme_support) {
2009 while (target_state
2010 && !(dev->pme_support & (1 << target_state)))
2011 target_state--;
2012 }
2013 }
2014
2015 return target_state;
2016}
2017
2018/**
2019 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2020 * @dev: Device to handle.
2021 *
2022 * Choose the power state appropriate for the device depending on whether
2023 * it can wake up the system and/or is power manageable by the platform
2024 * (PCI_D3hot is the default) and put the device into that state.
2025 */
2026int pci_prepare_to_sleep(struct pci_dev *dev)
2027{
2028 pci_power_t target_state = pci_target_state(dev);
2029 int error;
2030
2031 if (target_state == PCI_POWER_ERROR)
2032 return -EIO;
2033
2034 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
2035
2036 error = pci_set_power_state(dev, target_state);
2037
2038 if (error)
2039 pci_enable_wake(dev, target_state, false);
2040
2041 return error;
2042}
2043EXPORT_SYMBOL(pci_prepare_to_sleep);
2044
2045/**
2046 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2047 * @dev: Device to handle.
2048 *
2049 * Disable device's system wake-up capability and put it into D0.
2050 */
2051int pci_back_from_sleep(struct pci_dev *dev)
2052{
2053 pci_enable_wake(dev, PCI_D0, false);
2054 return pci_set_power_state(dev, PCI_D0);
2055}
2056EXPORT_SYMBOL(pci_back_from_sleep);
2057
2058/**
2059 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2060 * @dev: PCI device being suspended.
2061 *
2062 * Prepare @dev to generate wake-up events at run time and put it into a low
2063 * power state.
2064 */
2065int pci_finish_runtime_suspend(struct pci_dev *dev)
2066{
2067 pci_power_t target_state = pci_target_state(dev);
2068 int error;
2069
2070 if (target_state == PCI_POWER_ERROR)
2071 return -EIO;
2072
2073 dev->runtime_d3cold = target_state == PCI_D3cold;
2074
2075 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
2076
2077 error = pci_set_power_state(dev, target_state);
2078
2079 if (error) {
2080 __pci_enable_wake(dev, target_state, true, false);
2081 dev->runtime_d3cold = false;
2082 }
2083
2084 return error;
2085}
2086
2087/**
2088 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2089 * @dev: Device to check.
2090 *
2091 * Return true if the device itself is capable of generating wake-up events
2092 * (through the platform or using the native PCIe PME) or if the device supports
2093 * PME and one of its upstream bridges can generate wake-up events.
2094 */
2095bool pci_dev_run_wake(struct pci_dev *dev)
2096{
2097 struct pci_bus *bus = dev->bus;
2098
2099 if (device_run_wake(&dev->dev))
2100 return true;
2101
2102 if (!dev->pme_support)
2103 return false;
2104
2105 /* PME-capable in principle, but not from the intended sleep state */
2106 if (!pci_pme_capable(dev, pci_target_state(dev)))
2107 return false;
2108
2109 while (bus->parent) {
2110 struct pci_dev *bridge = bus->self;
2111
2112 if (device_run_wake(&bridge->dev))
2113 return true;
2114
2115 bus = bus->parent;
2116 }
2117
2118 /* We have reached the root bus. */
2119 if (bus->bridge)
2120 return device_run_wake(bus->bridge);
2121
2122 return false;
2123}
2124EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2125
2126/**
2127 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2128 * @pci_dev: Device to check.
2129 *
2130 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2131 * reconfigured due to wakeup settings difference between system and runtime
2132 * suspend and the current power state of it is suitable for the upcoming
2133 * (system) transition.
2134 *
2135 * If the device is not configured for system wakeup, disable PME for it before
2136 * returning 'true' to prevent it from waking up the system unnecessarily.
2137 */
2138bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2139{
2140 struct device *dev = &pci_dev->dev;
2141
2142 if (!pm_runtime_suspended(dev)
2143 || pci_target_state(pci_dev) != pci_dev->current_state
2144 || platform_pci_need_resume(pci_dev))
2145 return false;
2146
2147 /*
2148 * At this point the device is good to go unless it's been configured
2149 * to generate PME at the runtime suspend time, but it is not supposed
2150 * to wake up the system. In that case, simply disable PME for it
2151 * (it will have to be re-enabled on exit from system resume).
2152 *
2153 * If the device's power state is D3cold and the platform check above
2154 * hasn't triggered, the device's configuration is suitable and we don't
2155 * need to manipulate it at all.
2156 */
2157 spin_lock_irq(&dev->power.lock);
2158
2159 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2160 !device_may_wakeup(dev))
2161 __pci_pme_active(pci_dev, false);
2162
2163 spin_unlock_irq(&dev->power.lock);
2164 return true;
2165}
2166
2167/**
2168 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2169 * @pci_dev: Device to handle.
2170 *
2171 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2172 * it might have been disabled during the prepare phase of system suspend if
2173 * the device was not configured for system wakeup.
2174 */
2175void pci_dev_complete_resume(struct pci_dev *pci_dev)
2176{
2177 struct device *dev = &pci_dev->dev;
2178
2179 if (!pci_dev_run_wake(pci_dev))
2180 return;
2181
2182 spin_lock_irq(&dev->power.lock);
2183
2184 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2185 __pci_pme_active(pci_dev, true);
2186
2187 spin_unlock_irq(&dev->power.lock);
2188}
2189
2190void pci_config_pm_runtime_get(struct pci_dev *pdev)
2191{
2192 struct device *dev = &pdev->dev;
2193 struct device *parent = dev->parent;
2194
2195 if (parent)
2196 pm_runtime_get_sync(parent);
2197 pm_runtime_get_noresume(dev);
2198 /*
2199 * pdev->current_state is set to PCI_D3cold during suspending,
2200 * so wait until suspending completes
2201 */
2202 pm_runtime_barrier(dev);
2203 /*
2204 * Only need to resume devices in D3cold, because config
2205 * registers are still accessible for devices suspended but
2206 * not in D3cold.
2207 */
2208 if (pdev->current_state == PCI_D3cold)
2209 pm_runtime_resume(dev);
2210}
2211
2212void pci_config_pm_runtime_put(struct pci_dev *pdev)
2213{
2214 struct device *dev = &pdev->dev;
2215 struct device *parent = dev->parent;
2216
2217 pm_runtime_put(dev);
2218 if (parent)
2219 pm_runtime_put_sync(parent);
2220}
2221
2222/**
2223 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2224 * @bridge: Bridge to check
2225 *
2226 * This function checks if it is possible to move the bridge to D3.
2227 * Currently we only allow D3 for recent enough PCIe ports.
2228 */
2229bool pci_bridge_d3_possible(struct pci_dev *bridge)
2230{
2231 unsigned int year;
2232
2233 if (!pci_is_pcie(bridge))
2234 return false;
2235
2236 switch (pci_pcie_type(bridge)) {
2237 case PCI_EXP_TYPE_ROOT_PORT:
2238 case PCI_EXP_TYPE_UPSTREAM:
2239 case PCI_EXP_TYPE_DOWNSTREAM:
2240 if (pci_bridge_d3_disable)
2241 return false;
2242
2243 /*
2244 * Hotplug interrupts cannot be delivered if the link is down,
2245 * so parents of a hotplug port must stay awake. In addition,
2246 * hotplug ports handled by firmware in System Management Mode
2247 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2248 * For simplicity, disallow in general for now.
2249 */
2250 if (bridge->is_hotplug_bridge)
2251 return false;
2252
2253 if (pci_bridge_d3_force)
2254 return true;
2255
2256 /*
2257 * It should be safe to put PCIe ports from 2015 or newer
2258 * to D3.
2259 */
2260 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2261 year >= 2015) {
2262 return true;
2263 }
2264 break;
2265 }
2266
2267 return false;
2268}
2269
2270static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2271{
2272 bool *d3cold_ok = data;
2273
2274 if (/* The device needs to be allowed to go D3cold ... */
2275 dev->no_d3cold || !dev->d3cold_allowed ||
2276
2277 /* ... and if it is wakeup capable to do so from D3cold. */
2278 (device_may_wakeup(&dev->dev) &&
2279 !pci_pme_capable(dev, PCI_D3cold)) ||
2280
2281 /* If it is a bridge it must be allowed to go to D3. */
2282 !pci_power_manageable(dev))
2283
2284 *d3cold_ok = false;
2285
2286 return !*d3cold_ok;
2287}
2288
2289/*
2290 * pci_bridge_d3_update - Update bridge D3 capabilities
2291 * @dev: PCI device which is changed
2292 *
2293 * Update upstream bridge PM capabilities accordingly depending on if the
2294 * device PM configuration was changed or the device is being removed. The
2295 * change is also propagated upstream.
2296 */
2297void pci_bridge_d3_update(struct pci_dev *dev)
2298{
2299 bool remove = !device_is_registered(&dev->dev);
2300 struct pci_dev *bridge;
2301 bool d3cold_ok = true;
2302
2303 bridge = pci_upstream_bridge(dev);
2304 if (!bridge || !pci_bridge_d3_possible(bridge))
2305 return;
2306
2307 /*
2308 * If D3 is currently allowed for the bridge, removing one of its
2309 * children won't change that.
2310 */
2311 if (remove && bridge->bridge_d3)
2312 return;
2313
2314 /*
2315 * If D3 is currently allowed for the bridge and a child is added or
2316 * changed, disallowance of D3 can only be caused by that child, so
2317 * we only need to check that single device, not any of its siblings.
2318 *
2319 * If D3 is currently not allowed for the bridge, checking the device
2320 * first may allow us to skip checking its siblings.
2321 */
2322 if (!remove)
2323 pci_dev_check_d3cold(dev, &d3cold_ok);
2324
2325 /*
2326 * If D3 is currently not allowed for the bridge, this may be caused
2327 * either by the device being changed/removed or any of its siblings,
2328 * so we need to go through all children to find out if one of them
2329 * continues to block D3.
2330 */
2331 if (d3cold_ok && !bridge->bridge_d3)
2332 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2333 &d3cold_ok);
2334
2335 if (bridge->bridge_d3 != d3cold_ok) {
2336 bridge->bridge_d3 = d3cold_ok;
2337 /* Propagate change to upstream bridges */
2338 pci_bridge_d3_update(bridge);
2339 }
2340}
2341
2342/**
2343 * pci_d3cold_enable - Enable D3cold for device
2344 * @dev: PCI device to handle
2345 *
2346 * This function can be used in drivers to enable D3cold from the device
2347 * they handle. It also updates upstream PCI bridge PM capabilities
2348 * accordingly.
2349 */
2350void pci_d3cold_enable(struct pci_dev *dev)
2351{
2352 if (dev->no_d3cold) {
2353 dev->no_d3cold = false;
2354 pci_bridge_d3_update(dev);
2355 }
2356}
2357EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2358
2359/**
2360 * pci_d3cold_disable - Disable D3cold for device
2361 * @dev: PCI device to handle
2362 *
2363 * This function can be used in drivers to disable D3cold from the device
2364 * they handle. It also updates upstream PCI bridge PM capabilities
2365 * accordingly.
2366 */
2367void pci_d3cold_disable(struct pci_dev *dev)
2368{
2369 if (!dev->no_d3cold) {
2370 dev->no_d3cold = true;
2371 pci_bridge_d3_update(dev);
2372 }
2373}
2374EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2375
2376/**
2377 * pci_pm_init - Initialize PM functions of given PCI device
2378 * @dev: PCI device to handle.
2379 */
2380void pci_pm_init(struct pci_dev *dev)
2381{
2382 int pm;
2383 u16 pmc;
2384
2385 pm_runtime_forbid(&dev->dev);
2386 pm_runtime_set_active(&dev->dev);
2387 pm_runtime_enable(&dev->dev);
2388 device_enable_async_suspend(&dev->dev);
2389 dev->wakeup_prepared = false;
2390
2391 dev->pm_cap = 0;
2392 dev->pme_support = 0;
2393
2394 /* find PCI PM capability in list */
2395 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2396 if (!pm)
2397 return;
2398 /* Check device's ability to generate PME# */
2399 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2400
2401 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2402 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2403 pmc & PCI_PM_CAP_VER_MASK);
2404 return;
2405 }
2406
2407 dev->pm_cap = pm;
2408 dev->d3_delay = PCI_PM_D3_WAIT;
2409 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2410 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2411 dev->d3cold_allowed = true;
2412
2413 dev->d1_support = false;
2414 dev->d2_support = false;
2415 if (!pci_no_d1d2(dev)) {
2416 if (pmc & PCI_PM_CAP_D1)
2417 dev->d1_support = true;
2418 if (pmc & PCI_PM_CAP_D2)
2419 dev->d2_support = true;
2420
2421 if (dev->d1_support || dev->d2_support)
2422 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2423 dev->d1_support ? " D1" : "",
2424 dev->d2_support ? " D2" : "");
2425 }
2426
2427 pmc &= PCI_PM_CAP_PME_MASK;
2428 if (pmc) {
2429 dev_printk(KERN_DEBUG, &dev->dev,
2430 "PME# supported from%s%s%s%s%s\n",
2431 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2432 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2433 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2434 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2435 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2436 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2437 dev->pme_poll = true;
2438 /*
2439 * Make device's PM flags reflect the wake-up capability, but
2440 * let the user space enable it to wake up the system as needed.
2441 */
2442 device_set_wakeup_capable(&dev->dev, true);
2443 /* Disable the PME# generation functionality */
2444 pci_pme_active(dev, false);
2445 }
2446}
2447
2448static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2449{
2450 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2451
2452 switch (prop) {
2453 case PCI_EA_P_MEM:
2454 case PCI_EA_P_VF_MEM:
2455 flags |= IORESOURCE_MEM;
2456 break;
2457 case PCI_EA_P_MEM_PREFETCH:
2458 case PCI_EA_P_VF_MEM_PREFETCH:
2459 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2460 break;
2461 case PCI_EA_P_IO:
2462 flags |= IORESOURCE_IO;
2463 break;
2464 default:
2465 return 0;
2466 }
2467
2468 return flags;
2469}
2470
2471static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2472 u8 prop)
2473{
2474 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2475 return &dev->resource[bei];
2476#ifdef CONFIG_PCI_IOV
2477 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2478 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2479 return &dev->resource[PCI_IOV_RESOURCES +
2480 bei - PCI_EA_BEI_VF_BAR0];
2481#endif
2482 else if (bei == PCI_EA_BEI_ROM)
2483 return &dev->resource[PCI_ROM_RESOURCE];
2484 else
2485 return NULL;
2486}
2487
2488/* Read an Enhanced Allocation (EA) entry */
2489static int pci_ea_read(struct pci_dev *dev, int offset)
2490{
2491 struct resource *res;
2492 int ent_size, ent_offset = offset;
2493 resource_size_t start, end;
2494 unsigned long flags;
2495 u32 dw0, bei, base, max_offset;
2496 u8 prop;
2497 bool support_64 = (sizeof(resource_size_t) >= 8);
2498
2499 pci_read_config_dword(dev, ent_offset, &dw0);
2500 ent_offset += 4;
2501
2502 /* Entry size field indicates DWORDs after 1st */
2503 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2504
2505 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2506 goto out;
2507
2508 bei = (dw0 & PCI_EA_BEI) >> 4;
2509 prop = (dw0 & PCI_EA_PP) >> 8;
2510
2511 /*
2512 * If the Property is in the reserved range, try the Secondary
2513 * Property instead.
2514 */
2515 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2516 prop = (dw0 & PCI_EA_SP) >> 16;
2517 if (prop > PCI_EA_P_BRIDGE_IO)
2518 goto out;
2519
2520 res = pci_ea_get_resource(dev, bei, prop);
2521 if (!res) {
2522 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2523 goto out;
2524 }
2525
2526 flags = pci_ea_flags(dev, prop);
2527 if (!flags) {
2528 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2529 goto out;
2530 }
2531
2532 /* Read Base */
2533 pci_read_config_dword(dev, ent_offset, &base);
2534 start = (base & PCI_EA_FIELD_MASK);
2535 ent_offset += 4;
2536
2537 /* Read MaxOffset */
2538 pci_read_config_dword(dev, ent_offset, &max_offset);
2539 ent_offset += 4;
2540
2541 /* Read Base MSBs (if 64-bit entry) */
2542 if (base & PCI_EA_IS_64) {
2543 u32 base_upper;
2544
2545 pci_read_config_dword(dev, ent_offset, &base_upper);
2546 ent_offset += 4;
2547
2548 flags |= IORESOURCE_MEM_64;
2549
2550 /* entry starts above 32-bit boundary, can't use */
2551 if (!support_64 && base_upper)
2552 goto out;
2553
2554 if (support_64)
2555 start |= ((u64)base_upper << 32);
2556 }
2557
2558 end = start + (max_offset | 0x03);
2559
2560 /* Read MaxOffset MSBs (if 64-bit entry) */
2561 if (max_offset & PCI_EA_IS_64) {
2562 u32 max_offset_upper;
2563
2564 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2565 ent_offset += 4;
2566
2567 flags |= IORESOURCE_MEM_64;
2568
2569 /* entry too big, can't use */
2570 if (!support_64 && max_offset_upper)
2571 goto out;
2572
2573 if (support_64)
2574 end += ((u64)max_offset_upper << 32);
2575 }
2576
2577 if (end < start) {
2578 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2579 goto out;
2580 }
2581
2582 if (ent_size != ent_offset - offset) {
2583 dev_err(&dev->dev,
2584 "EA Entry Size (%d) does not match length read (%d)\n",
2585 ent_size, ent_offset - offset);
2586 goto out;
2587 }
2588
2589 res->name = pci_name(dev);
2590 res->start = start;
2591 res->end = end;
2592 res->flags = flags;
2593
2594 if (bei <= PCI_EA_BEI_BAR5)
2595 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2596 bei, res, prop);
2597 else if (bei == PCI_EA_BEI_ROM)
2598 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2599 res, prop);
2600 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2601 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2602 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2603 else
2604 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2605 bei, res, prop);
2606
2607out:
2608 return offset + ent_size;
2609}
2610
2611/* Enhanced Allocation Initialization */
2612void pci_ea_init(struct pci_dev *dev)
2613{
2614 int ea;
2615 u8 num_ent;
2616 int offset;
2617 int i;
2618
2619 /* find PCI EA capability in list */
2620 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2621 if (!ea)
2622 return;
2623
2624 /* determine the number of entries */
2625 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2626 &num_ent);
2627 num_ent &= PCI_EA_NUM_ENT_MASK;
2628
2629 offset = ea + PCI_EA_FIRST_ENT;
2630
2631 /* Skip DWORD 2 for type 1 functions */
2632 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2633 offset += 4;
2634
2635 /* parse each EA entry */
2636 for (i = 0; i < num_ent; ++i)
2637 offset = pci_ea_read(dev, offset);
2638}
2639
2640static void pci_add_saved_cap(struct pci_dev *pci_dev,
2641 struct pci_cap_saved_state *new_cap)
2642{
2643 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2644}
2645
2646/**
2647 * _pci_add_cap_save_buffer - allocate buffer for saving given
2648 * capability registers
2649 * @dev: the PCI device
2650 * @cap: the capability to allocate the buffer for
2651 * @extended: Standard or Extended capability ID
2652 * @size: requested size of the buffer
2653 */
2654static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2655 bool extended, unsigned int size)
2656{
2657 int pos;
2658 struct pci_cap_saved_state *save_state;
2659
2660 if (extended)
2661 pos = pci_find_ext_capability(dev, cap);
2662 else
2663 pos = pci_find_capability(dev, cap);
2664
2665 if (!pos)
2666 return 0;
2667
2668 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2669 if (!save_state)
2670 return -ENOMEM;
2671
2672 save_state->cap.cap_nr = cap;
2673 save_state->cap.cap_extended = extended;
2674 save_state->cap.size = size;
2675 pci_add_saved_cap(dev, save_state);
2676
2677 return 0;
2678}
2679
2680int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2681{
2682 return _pci_add_cap_save_buffer(dev, cap, false, size);
2683}
2684
2685int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2686{
2687 return _pci_add_cap_save_buffer(dev, cap, true, size);
2688}
2689
2690/**
2691 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2692 * @dev: the PCI device
2693 */
2694void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2695{
2696 int error;
2697
2698 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2699 PCI_EXP_SAVE_REGS * sizeof(u16));
2700 if (error)
2701 dev_err(&dev->dev,
2702 "unable to preallocate PCI Express save buffer\n");
2703
2704 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2705 if (error)
2706 dev_err(&dev->dev,
2707 "unable to preallocate PCI-X save buffer\n");
2708
2709 pci_allocate_vc_save_buffers(dev);
2710}
2711
2712void pci_free_cap_save_buffers(struct pci_dev *dev)
2713{
2714 struct pci_cap_saved_state *tmp;
2715 struct hlist_node *n;
2716
2717 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2718 kfree(tmp);
2719}
2720
2721/**
2722 * pci_configure_ari - enable or disable ARI forwarding
2723 * @dev: the PCI device
2724 *
2725 * If @dev and its upstream bridge both support ARI, enable ARI in the
2726 * bridge. Otherwise, disable ARI in the bridge.
2727 */
2728void pci_configure_ari(struct pci_dev *dev)
2729{
2730 u32 cap;
2731 struct pci_dev *bridge;
2732
2733 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2734 return;
2735
2736 bridge = dev->bus->self;
2737 if (!bridge)
2738 return;
2739
2740 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2741 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2742 return;
2743
2744 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2745 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2746 PCI_EXP_DEVCTL2_ARI);
2747 bridge->ari_enabled = 1;
2748 } else {
2749 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2750 PCI_EXP_DEVCTL2_ARI);
2751 bridge->ari_enabled = 0;
2752 }
2753}
2754
2755static int pci_acs_enable;
2756
2757/**
2758 * pci_request_acs - ask for ACS to be enabled if supported
2759 */
2760void pci_request_acs(void)
2761{
2762 pci_acs_enable = 1;
2763}
2764
2765/**
2766 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2767 * @dev: the PCI device
2768 */
2769static void pci_std_enable_acs(struct pci_dev *dev)
2770{
2771 int pos;
2772 u16 cap;
2773 u16 ctrl;
2774
2775 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2776 if (!pos)
2777 return;
2778
2779 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2780 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2781
2782 /* Source Validation */
2783 ctrl |= (cap & PCI_ACS_SV);
2784
2785 /* P2P Request Redirect */
2786 ctrl |= (cap & PCI_ACS_RR);
2787
2788 /* P2P Completion Redirect */
2789 ctrl |= (cap & PCI_ACS_CR);
2790
2791 /* Upstream Forwarding */
2792 ctrl |= (cap & PCI_ACS_UF);
2793
2794 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2795}
2796
2797/**
2798 * pci_enable_acs - enable ACS if hardware support it
2799 * @dev: the PCI device
2800 */
2801void pci_enable_acs(struct pci_dev *dev)
2802{
2803 if (!pci_acs_enable)
2804 return;
2805
2806 if (!pci_dev_specific_enable_acs(dev))
2807 return;
2808
2809 pci_std_enable_acs(dev);
2810}
2811
2812static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2813{
2814 int pos;
2815 u16 cap, ctrl;
2816
2817 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2818 if (!pos)
2819 return false;
2820
2821 /*
2822 * Except for egress control, capabilities are either required
2823 * or only required if controllable. Features missing from the
2824 * capability field can therefore be assumed as hard-wired enabled.
2825 */
2826 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2827 acs_flags &= (cap | PCI_ACS_EC);
2828
2829 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2830 return (ctrl & acs_flags) == acs_flags;
2831}
2832
2833/**
2834 * pci_acs_enabled - test ACS against required flags for a given device
2835 * @pdev: device to test
2836 * @acs_flags: required PCI ACS flags
2837 *
2838 * Return true if the device supports the provided flags. Automatically
2839 * filters out flags that are not implemented on multifunction devices.
2840 *
2841 * Note that this interface checks the effective ACS capabilities of the
2842 * device rather than the actual capabilities. For instance, most single
2843 * function endpoints are not required to support ACS because they have no
2844 * opportunity for peer-to-peer access. We therefore return 'true'
2845 * regardless of whether the device exposes an ACS capability. This makes
2846 * it much easier for callers of this function to ignore the actual type
2847 * or topology of the device when testing ACS support.
2848 */
2849bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2850{
2851 int ret;
2852
2853 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2854 if (ret >= 0)
2855 return ret > 0;
2856
2857 /*
2858 * Conventional PCI and PCI-X devices never support ACS, either
2859 * effectively or actually. The shared bus topology implies that
2860 * any device on the bus can receive or snoop DMA.
2861 */
2862 if (!pci_is_pcie(pdev))
2863 return false;
2864
2865 switch (pci_pcie_type(pdev)) {
2866 /*
2867 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2868 * but since their primary interface is PCI/X, we conservatively
2869 * handle them as we would a non-PCIe device.
2870 */
2871 case PCI_EXP_TYPE_PCIE_BRIDGE:
2872 /*
2873 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2874 * applicable... must never implement an ACS Extended Capability...".
2875 * This seems arbitrary, but we take a conservative interpretation
2876 * of this statement.
2877 */
2878 case PCI_EXP_TYPE_PCI_BRIDGE:
2879 case PCI_EXP_TYPE_RC_EC:
2880 return false;
2881 /*
2882 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2883 * implement ACS in order to indicate their peer-to-peer capabilities,
2884 * regardless of whether they are single- or multi-function devices.
2885 */
2886 case PCI_EXP_TYPE_DOWNSTREAM:
2887 case PCI_EXP_TYPE_ROOT_PORT:
2888 return pci_acs_flags_enabled(pdev, acs_flags);
2889 /*
2890 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2891 * implemented by the remaining PCIe types to indicate peer-to-peer
2892 * capabilities, but only when they are part of a multifunction
2893 * device. The footnote for section 6.12 indicates the specific
2894 * PCIe types included here.
2895 */
2896 case PCI_EXP_TYPE_ENDPOINT:
2897 case PCI_EXP_TYPE_UPSTREAM:
2898 case PCI_EXP_TYPE_LEG_END:
2899 case PCI_EXP_TYPE_RC_END:
2900 if (!pdev->multifunction)
2901 break;
2902
2903 return pci_acs_flags_enabled(pdev, acs_flags);
2904 }
2905
2906 /*
2907 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2908 * to single function devices with the exception of downstream ports.
2909 */
2910 return true;
2911}
2912
2913/**
2914 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2915 * @start: starting downstream device
2916 * @end: ending upstream device or NULL to search to the root bus
2917 * @acs_flags: required flags
2918 *
2919 * Walk up a device tree from start to end testing PCI ACS support. If
2920 * any step along the way does not support the required flags, return false.
2921 */
2922bool pci_acs_path_enabled(struct pci_dev *start,
2923 struct pci_dev *end, u16 acs_flags)
2924{
2925 struct pci_dev *pdev, *parent = start;
2926
2927 do {
2928 pdev = parent;
2929
2930 if (!pci_acs_enabled(pdev, acs_flags))
2931 return false;
2932
2933 if (pci_is_root_bus(pdev->bus))
2934 return (end == NULL);
2935
2936 parent = pdev->bus->self;
2937 } while (pdev != end);
2938
2939 return true;
2940}
2941
2942/**
2943 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2944 * @dev: the PCI device
2945 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2946 *
2947 * Perform INTx swizzling for a device behind one level of bridge. This is
2948 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2949 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2950 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2951 * the PCI Express Base Specification, Revision 2.1)
2952 */
2953u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2954{
2955 int slot;
2956
2957 if (pci_ari_enabled(dev->bus))
2958 slot = 0;
2959 else
2960 slot = PCI_SLOT(dev->devfn);
2961
2962 return (((pin - 1) + slot) % 4) + 1;
2963}
2964
2965int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2966{
2967 u8 pin;
2968
2969 pin = dev->pin;
2970 if (!pin)
2971 return -1;
2972
2973 while (!pci_is_root_bus(dev->bus)) {
2974 pin = pci_swizzle_interrupt_pin(dev, pin);
2975 dev = dev->bus->self;
2976 }
2977 *bridge = dev;
2978 return pin;
2979}
2980
2981/**
2982 * pci_common_swizzle - swizzle INTx all the way to root bridge
2983 * @dev: the PCI device
2984 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2985 *
2986 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2987 * bridges all the way up to a PCI root bus.
2988 */
2989u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2990{
2991 u8 pin = *pinp;
2992
2993 while (!pci_is_root_bus(dev->bus)) {
2994 pin = pci_swizzle_interrupt_pin(dev, pin);
2995 dev = dev->bus->self;
2996 }
2997 *pinp = pin;
2998 return PCI_SLOT(dev->devfn);
2999}
3000EXPORT_SYMBOL_GPL(pci_common_swizzle);
3001
3002/**
3003 * pci_release_region - Release a PCI bar
3004 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3005 * @bar: BAR to release
3006 *
3007 * Releases the PCI I/O and memory resources previously reserved by a
3008 * successful call to pci_request_region. Call this function only
3009 * after all use of the PCI regions has ceased.
3010 */
3011void pci_release_region(struct pci_dev *pdev, int bar)
3012{
3013 struct pci_devres *dr;
3014
3015 if (pci_resource_len(pdev, bar) == 0)
3016 return;
3017 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3018 release_region(pci_resource_start(pdev, bar),
3019 pci_resource_len(pdev, bar));
3020 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3021 release_mem_region(pci_resource_start(pdev, bar),
3022 pci_resource_len(pdev, bar));
3023
3024 dr = find_pci_dr(pdev);
3025 if (dr)
3026 dr->region_mask &= ~(1 << bar);
3027}
3028EXPORT_SYMBOL(pci_release_region);
3029
3030/**
3031 * __pci_request_region - Reserved PCI I/O and memory resource
3032 * @pdev: PCI device whose resources are to be reserved
3033 * @bar: BAR to be reserved
3034 * @res_name: Name to be associated with resource.
3035 * @exclusive: whether the region access is exclusive or not
3036 *
3037 * Mark the PCI region associated with PCI device @pdev BR @bar as
3038 * being reserved by owner @res_name. Do not access any
3039 * address inside the PCI regions unless this call returns
3040 * successfully.
3041 *
3042 * If @exclusive is set, then the region is marked so that userspace
3043 * is explicitly not allowed to map the resource via /dev/mem or
3044 * sysfs MMIO access.
3045 *
3046 * Returns 0 on success, or %EBUSY on error. A warning
3047 * message is also printed on failure.
3048 */
3049static int __pci_request_region(struct pci_dev *pdev, int bar,
3050 const char *res_name, int exclusive)
3051{
3052 struct pci_devres *dr;
3053
3054 if (pci_resource_len(pdev, bar) == 0)
3055 return 0;
3056
3057 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3058 if (!request_region(pci_resource_start(pdev, bar),
3059 pci_resource_len(pdev, bar), res_name))
3060 goto err_out;
3061 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3062 if (!__request_mem_region(pci_resource_start(pdev, bar),
3063 pci_resource_len(pdev, bar), res_name,
3064 exclusive))
3065 goto err_out;
3066 }
3067
3068 dr = find_pci_dr(pdev);
3069 if (dr)
3070 dr->region_mask |= 1 << bar;
3071
3072 return 0;
3073
3074err_out:
3075 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
3076 &pdev->resource[bar]);
3077 return -EBUSY;
3078}
3079
3080/**
3081 * pci_request_region - Reserve PCI I/O and memory resource
3082 * @pdev: PCI device whose resources are to be reserved
3083 * @bar: BAR to be reserved
3084 * @res_name: Name to be associated with resource
3085 *
3086 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3087 * being reserved by owner @res_name. Do not access any
3088 * address inside the PCI regions unless this call returns
3089 * successfully.
3090 *
3091 * Returns 0 on success, or %EBUSY on error. A warning
3092 * message is also printed on failure.
3093 */
3094int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3095{
3096 return __pci_request_region(pdev, bar, res_name, 0);
3097}
3098EXPORT_SYMBOL(pci_request_region);
3099
3100/**
3101 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3102 * @pdev: PCI device whose resources are to be reserved
3103 * @bar: BAR to be reserved
3104 * @res_name: Name to be associated with resource.
3105 *
3106 * Mark the PCI region associated with PCI device @pdev BR @bar as
3107 * being reserved by owner @res_name. Do not access any
3108 * address inside the PCI regions unless this call returns
3109 * successfully.
3110 *
3111 * Returns 0 on success, or %EBUSY on error. A warning
3112 * message is also printed on failure.
3113 *
3114 * The key difference that _exclusive makes it that userspace is
3115 * explicitly not allowed to map the resource via /dev/mem or
3116 * sysfs.
3117 */
3118int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3119 const char *res_name)
3120{
3121 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3122}
3123EXPORT_SYMBOL(pci_request_region_exclusive);
3124
3125/**
3126 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3127 * @pdev: PCI device whose resources were previously reserved
3128 * @bars: Bitmask of BARs to be released
3129 *
3130 * Release selected PCI I/O and memory resources previously reserved.
3131 * Call this function only after all use of the PCI regions has ceased.
3132 */
3133void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3134{
3135 int i;
3136
3137 for (i = 0; i < 6; i++)
3138 if (bars & (1 << i))
3139 pci_release_region(pdev, i);
3140}
3141EXPORT_SYMBOL(pci_release_selected_regions);
3142
3143static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3144 const char *res_name, int excl)
3145{
3146 int i;
3147
3148 for (i = 0; i < 6; i++)
3149 if (bars & (1 << i))
3150 if (__pci_request_region(pdev, i, res_name, excl))
3151 goto err_out;
3152 return 0;
3153
3154err_out:
3155 while (--i >= 0)
3156 if (bars & (1 << i))
3157 pci_release_region(pdev, i);
3158
3159 return -EBUSY;
3160}
3161
3162
3163/**
3164 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3165 * @pdev: PCI device whose resources are to be reserved
3166 * @bars: Bitmask of BARs to be requested
3167 * @res_name: Name to be associated with resource
3168 */
3169int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3170 const char *res_name)
3171{
3172 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3173}
3174EXPORT_SYMBOL(pci_request_selected_regions);
3175
3176int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3177 const char *res_name)
3178{
3179 return __pci_request_selected_regions(pdev, bars, res_name,
3180 IORESOURCE_EXCLUSIVE);
3181}
3182EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3183
3184/**
3185 * pci_release_regions - Release reserved PCI I/O and memory resources
3186 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3187 *
3188 * Releases all PCI I/O and memory resources previously reserved by a
3189 * successful call to pci_request_regions. Call this function only
3190 * after all use of the PCI regions has ceased.
3191 */
3192
3193void pci_release_regions(struct pci_dev *pdev)
3194{
3195 pci_release_selected_regions(pdev, (1 << 6) - 1);
3196}
3197EXPORT_SYMBOL(pci_release_regions);
3198
3199/**
3200 * pci_request_regions - Reserved PCI I/O and memory resources
3201 * @pdev: PCI device whose resources are to be reserved
3202 * @res_name: Name to be associated with resource.
3203 *
3204 * Mark all PCI regions associated with PCI device @pdev as
3205 * being reserved by owner @res_name. Do not access any
3206 * address inside the PCI regions unless this call returns
3207 * successfully.
3208 *
3209 * Returns 0 on success, or %EBUSY on error. A warning
3210 * message is also printed on failure.
3211 */
3212int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3213{
3214 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3215}
3216EXPORT_SYMBOL(pci_request_regions);
3217
3218/**
3219 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3220 * @pdev: PCI device whose resources are to be reserved
3221 * @res_name: Name to be associated with resource.
3222 *
3223 * Mark all PCI regions associated with PCI device @pdev as
3224 * being reserved by owner @res_name. Do not access any
3225 * address inside the PCI regions unless this call returns
3226 * successfully.
3227 *
3228 * pci_request_regions_exclusive() will mark the region so that
3229 * /dev/mem and the sysfs MMIO access will not be allowed.
3230 *
3231 * Returns 0 on success, or %EBUSY on error. A warning
3232 * message is also printed on failure.
3233 */
3234int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3235{
3236 return pci_request_selected_regions_exclusive(pdev,
3237 ((1 << 6) - 1), res_name);
3238}
3239EXPORT_SYMBOL(pci_request_regions_exclusive);
3240
3241#ifdef PCI_IOBASE
3242struct io_range {
3243 struct list_head list;
3244 phys_addr_t start;
3245 resource_size_t size;
3246};
3247
3248static LIST_HEAD(io_range_list);
3249static DEFINE_SPINLOCK(io_range_lock);
3250#endif
3251
3252/*
3253 * Record the PCI IO range (expressed as CPU physical address + size).
3254 * Return a negative value if an error has occured, zero otherwise
3255 */
3256int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3257{
3258 int err = 0;
3259
3260#ifdef PCI_IOBASE
3261 struct io_range *range;
3262 resource_size_t allocated_size = 0;
3263
3264 /* check if the range hasn't been previously recorded */
3265 spin_lock(&io_range_lock);
3266 list_for_each_entry(range, &io_range_list, list) {
3267 if (addr >= range->start && addr + size <= range->start + size) {
3268 /* range already registered, bail out */
3269 goto end_register;
3270 }
3271 allocated_size += range->size;
3272 }
3273
3274 /* range not registed yet, check for available space */
3275 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3276 /* if it's too big check if 64K space can be reserved */
3277 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3278 err = -E2BIG;
3279 goto end_register;
3280 }
3281
3282 size = SZ_64K;
3283 pr_warn("Requested IO range too big, new size set to 64K\n");
3284 }
3285
3286 /* add the range to the list */
3287 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3288 if (!range) {
3289 err = -ENOMEM;
3290 goto end_register;
3291 }
3292
3293 range->start = addr;
3294 range->size = size;
3295
3296 list_add_tail(&range->list, &io_range_list);
3297
3298end_register:
3299 spin_unlock(&io_range_lock);
3300#endif
3301
3302 return err;
3303}
3304
3305phys_addr_t pci_pio_to_address(unsigned long pio)
3306{
3307 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3308
3309#ifdef PCI_IOBASE
3310 struct io_range *range;
3311 resource_size_t allocated_size = 0;
3312
3313 if (pio > IO_SPACE_LIMIT)
3314 return address;
3315
3316 spin_lock(&io_range_lock);
3317 list_for_each_entry(range, &io_range_list, list) {
3318 if (pio >= allocated_size && pio < allocated_size + range->size) {
3319 address = range->start + pio - allocated_size;
3320 break;
3321 }
3322 allocated_size += range->size;
3323 }
3324 spin_unlock(&io_range_lock);
3325#endif
3326
3327 return address;
3328}
3329
3330unsigned long __weak pci_address_to_pio(phys_addr_t address)
3331{
3332#ifdef PCI_IOBASE
3333 struct io_range *res;
3334 resource_size_t offset = 0;
3335 unsigned long addr = -1;
3336
3337 spin_lock(&io_range_lock);
3338 list_for_each_entry(res, &io_range_list, list) {
3339 if (address >= res->start && address < res->start + res->size) {
3340 addr = address - res->start + offset;
3341 break;
3342 }
3343 offset += res->size;
3344 }
3345 spin_unlock(&io_range_lock);
3346
3347 return addr;
3348#else
3349 if (address > IO_SPACE_LIMIT)
3350 return (unsigned long)-1;
3351
3352 return (unsigned long) address;
3353#endif
3354}
3355
3356/**
3357 * pci_remap_iospace - Remap the memory mapped I/O space
3358 * @res: Resource describing the I/O space
3359 * @phys_addr: physical address of range to be mapped
3360 *
3361 * Remap the memory mapped I/O space described by the @res
3362 * and the CPU physical address @phys_addr into virtual address space.
3363 * Only architectures that have memory mapped IO functions defined
3364 * (and the PCI_IOBASE value defined) should call this function.
3365 */
3366int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3367{
3368#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3369 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3370
3371 if (!(res->flags & IORESOURCE_IO))
3372 return -EINVAL;
3373
3374 if (res->end > IO_SPACE_LIMIT)
3375 return -EINVAL;
3376
3377 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3378 pgprot_device(PAGE_KERNEL));
3379#else
3380 /* this architecture does not have memory mapped I/O space,
3381 so this function should never be called */
3382 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3383 return -ENODEV;
3384#endif
3385}
3386
3387/**
3388 * pci_unmap_iospace - Unmap the memory mapped I/O space
3389 * @res: resource to be unmapped
3390 *
3391 * Unmap the CPU virtual address @res from virtual address space.
3392 * Only architectures that have memory mapped IO functions defined
3393 * (and the PCI_IOBASE value defined) should call this function.
3394 */
3395void pci_unmap_iospace(struct resource *res)
3396{
3397#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3398 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3399
3400 unmap_kernel_range(vaddr, resource_size(res));
3401#endif
3402}
3403
3404static void __pci_set_master(struct pci_dev *dev, bool enable)
3405{
3406 u16 old_cmd, cmd;
3407
3408 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3409 if (enable)
3410 cmd = old_cmd | PCI_COMMAND_MASTER;
3411 else
3412 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3413 if (cmd != old_cmd) {
3414 dev_dbg(&dev->dev, "%s bus mastering\n",
3415 enable ? "enabling" : "disabling");
3416 pci_write_config_word(dev, PCI_COMMAND, cmd);
3417 }
3418 dev->is_busmaster = enable;
3419}
3420
3421/**
3422 * pcibios_setup - process "pci=" kernel boot arguments
3423 * @str: string used to pass in "pci=" kernel boot arguments
3424 *
3425 * Process kernel boot arguments. This is the default implementation.
3426 * Architecture specific implementations can override this as necessary.
3427 */
3428char * __weak __init pcibios_setup(char *str)
3429{
3430 return str;
3431}
3432
3433/**
3434 * pcibios_set_master - enable PCI bus-mastering for device dev
3435 * @dev: the PCI device to enable
3436 *
3437 * Enables PCI bus-mastering for the device. This is the default
3438 * implementation. Architecture specific implementations can override
3439 * this if necessary.
3440 */
3441void __weak pcibios_set_master(struct pci_dev *dev)
3442{
3443 u8 lat;
3444
3445 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3446 if (pci_is_pcie(dev))
3447 return;
3448
3449 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3450 if (lat < 16)
3451 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3452 else if (lat > pcibios_max_latency)
3453 lat = pcibios_max_latency;
3454 else
3455 return;
3456
3457 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3458}
3459
3460/**
3461 * pci_set_master - enables bus-mastering for device dev
3462 * @dev: the PCI device to enable
3463 *
3464 * Enables bus-mastering on the device and calls pcibios_set_master()
3465 * to do the needed arch specific settings.
3466 */
3467void pci_set_master(struct pci_dev *dev)
3468{
3469 __pci_set_master(dev, true);
3470 pcibios_set_master(dev);
3471}
3472EXPORT_SYMBOL(pci_set_master);
3473
3474/**
3475 * pci_clear_master - disables bus-mastering for device dev
3476 * @dev: the PCI device to disable
3477 */
3478void pci_clear_master(struct pci_dev *dev)
3479{
3480 __pci_set_master(dev, false);
3481}
3482EXPORT_SYMBOL(pci_clear_master);
3483
3484/**
3485 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3486 * @dev: the PCI device for which MWI is to be enabled
3487 *
3488 * Helper function for pci_set_mwi.
3489 * Originally copied from drivers/net/acenic.c.
3490 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3491 *
3492 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3493 */
3494int pci_set_cacheline_size(struct pci_dev *dev)
3495{
3496 u8 cacheline_size;
3497
3498 if (!pci_cache_line_size)
3499 return -EINVAL;
3500
3501 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3502 equal to or multiple of the right value. */
3503 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3504 if (cacheline_size >= pci_cache_line_size &&
3505 (cacheline_size % pci_cache_line_size) == 0)
3506 return 0;
3507
3508 /* Write the correct value. */
3509 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3510 /* Read it back. */
3511 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3512 if (cacheline_size == pci_cache_line_size)
3513 return 0;
3514
3515 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3516 pci_cache_line_size << 2);
3517
3518 return -EINVAL;
3519}
3520EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3521
3522/**
3523 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3524 * @dev: the PCI device for which MWI is enabled
3525 *
3526 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3527 *
3528 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3529 */
3530int pci_set_mwi(struct pci_dev *dev)
3531{
3532#ifdef PCI_DISABLE_MWI
3533 return 0;
3534#else
3535 int rc;
3536 u16 cmd;
3537
3538 rc = pci_set_cacheline_size(dev);
3539 if (rc)
3540 return rc;
3541
3542 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3543 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3544 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3545 cmd |= PCI_COMMAND_INVALIDATE;
3546 pci_write_config_word(dev, PCI_COMMAND, cmd);
3547 }
3548 return 0;
3549#endif
3550}
3551EXPORT_SYMBOL(pci_set_mwi);
3552
3553/**
3554 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3555 * @dev: the PCI device for which MWI is enabled
3556 *
3557 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3558 * Callers are not required to check the return value.
3559 *
3560 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3561 */
3562int pci_try_set_mwi(struct pci_dev *dev)
3563{
3564#ifdef PCI_DISABLE_MWI
3565 return 0;
3566#else
3567 return pci_set_mwi(dev);
3568#endif
3569}
3570EXPORT_SYMBOL(pci_try_set_mwi);
3571
3572/**
3573 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3574 * @dev: the PCI device to disable
3575 *
3576 * Disables PCI Memory-Write-Invalidate transaction on the device
3577 */
3578void pci_clear_mwi(struct pci_dev *dev)
3579{
3580#ifndef PCI_DISABLE_MWI
3581 u16 cmd;
3582
3583 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3584 if (cmd & PCI_COMMAND_INVALIDATE) {
3585 cmd &= ~PCI_COMMAND_INVALIDATE;
3586 pci_write_config_word(dev, PCI_COMMAND, cmd);
3587 }
3588#endif
3589}
3590EXPORT_SYMBOL(pci_clear_mwi);
3591
3592/**
3593 * pci_intx - enables/disables PCI INTx for device dev
3594 * @pdev: the PCI device to operate on
3595 * @enable: boolean: whether to enable or disable PCI INTx
3596 *
3597 * Enables/disables PCI INTx for device dev
3598 */
3599void pci_intx(struct pci_dev *pdev, int enable)
3600{
3601 u16 pci_command, new;
3602
3603 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3604
3605 if (enable)
3606 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3607 else
3608 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3609
3610 if (new != pci_command) {
3611 struct pci_devres *dr;
3612
3613 pci_write_config_word(pdev, PCI_COMMAND, new);
3614
3615 dr = find_pci_dr(pdev);
3616 if (dr && !dr->restore_intx) {
3617 dr->restore_intx = 1;
3618 dr->orig_intx = !enable;
3619 }
3620 }
3621}
3622EXPORT_SYMBOL_GPL(pci_intx);
3623
3624/**
3625 * pci_intx_mask_supported - probe for INTx masking support
3626 * @dev: the PCI device to operate on
3627 *
3628 * Check if the device dev support INTx masking via the config space
3629 * command word.
3630 */
3631bool pci_intx_mask_supported(struct pci_dev *dev)
3632{
3633 bool mask_supported = false;
3634 u16 orig, new;
3635
3636 if (dev->broken_intx_masking)
3637 return false;
3638
3639 pci_cfg_access_lock(dev);
3640
3641 pci_read_config_word(dev, PCI_COMMAND, &orig);
3642 pci_write_config_word(dev, PCI_COMMAND,
3643 orig ^ PCI_COMMAND_INTX_DISABLE);
3644 pci_read_config_word(dev, PCI_COMMAND, &new);
3645
3646 /*
3647 * There's no way to protect against hardware bugs or detect them
3648 * reliably, but as long as we know what the value should be, let's
3649 * go ahead and check it.
3650 */
3651 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3652 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3653 orig, new);
3654 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3655 mask_supported = true;
3656 pci_write_config_word(dev, PCI_COMMAND, orig);
3657 }
3658
3659 pci_cfg_access_unlock(dev);
3660 return mask_supported;
3661}
3662EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3663
3664static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3665{
3666 struct pci_bus *bus = dev->bus;
3667 bool mask_updated = true;
3668 u32 cmd_status_dword;
3669 u16 origcmd, newcmd;
3670 unsigned long flags;
3671 bool irq_pending;
3672
3673 /*
3674 * We do a single dword read to retrieve both command and status.
3675 * Document assumptions that make this possible.
3676 */
3677 BUILD_BUG_ON(PCI_COMMAND % 4);
3678 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3679
3680 raw_spin_lock_irqsave(&pci_lock, flags);
3681
3682 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3683
3684 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3685
3686 /*
3687 * Check interrupt status register to see whether our device
3688 * triggered the interrupt (when masking) or the next IRQ is
3689 * already pending (when unmasking).
3690 */
3691 if (mask != irq_pending) {
3692 mask_updated = false;
3693 goto done;
3694 }
3695
3696 origcmd = cmd_status_dword;
3697 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3698 if (mask)
3699 newcmd |= PCI_COMMAND_INTX_DISABLE;
3700 if (newcmd != origcmd)
3701 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3702
3703done:
3704 raw_spin_unlock_irqrestore(&pci_lock, flags);
3705
3706 return mask_updated;
3707}
3708
3709/**
3710 * pci_check_and_mask_intx - mask INTx on pending interrupt
3711 * @dev: the PCI device to operate on
3712 *
3713 * Check if the device dev has its INTx line asserted, mask it and
3714 * return true in that case. False is returned if not interrupt was
3715 * pending.
3716 */
3717bool pci_check_and_mask_intx(struct pci_dev *dev)
3718{
3719 return pci_check_and_set_intx_mask(dev, true);
3720}
3721EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3722
3723/**
3724 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3725 * @dev: the PCI device to operate on
3726 *
3727 * Check if the device dev has its INTx line asserted, unmask it if not
3728 * and return true. False is returned and the mask remains active if
3729 * there was still an interrupt pending.
3730 */
3731bool pci_check_and_unmask_intx(struct pci_dev *dev)
3732{
3733 return pci_check_and_set_intx_mask(dev, false);
3734}
3735EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3736
3737/**
3738 * pci_wait_for_pending_transaction - waits for pending transaction
3739 * @dev: the PCI device to operate on
3740 *
3741 * Return 0 if transaction is pending 1 otherwise.
3742 */
3743int pci_wait_for_pending_transaction(struct pci_dev *dev)
3744{
3745 if (!pci_is_pcie(dev))
3746 return 1;
3747
3748 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3749 PCI_EXP_DEVSTA_TRPND);
3750}
3751EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3752
3753/*
3754 * We should only need to wait 100ms after FLR, but some devices take longer.
3755 * Wait for up to 1000ms for config space to return something other than -1.
3756 * Intel IGD requires this when an LCD panel is attached. We read the 2nd
3757 * dword because VFs don't implement the 1st dword.
3758 */
3759static void pci_flr_wait(struct pci_dev *dev)
3760{
3761 int i = 0;
3762 u32 id;
3763
3764 do {
3765 msleep(100);
3766 pci_read_config_dword(dev, PCI_COMMAND, &id);
3767 } while (i++ < 10 && id == ~0);
3768
3769 if (id == ~0)
3770 dev_warn(&dev->dev, "Failed to return from FLR\n");
3771 else if (i > 1)
3772 dev_info(&dev->dev, "Required additional %dms to return from FLR\n",
3773 (i - 1) * 100);
3774}
3775
3776static int pcie_flr(struct pci_dev *dev, int probe)
3777{
3778 u32 cap;
3779
3780 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3781 if (!(cap & PCI_EXP_DEVCAP_FLR))
3782 return -ENOTTY;
3783
3784 if (probe)
3785 return 0;
3786
3787 if (!pci_wait_for_pending_transaction(dev))
3788 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3789
3790 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3791 pci_flr_wait(dev);
3792 return 0;
3793}
3794
3795static int pci_af_flr(struct pci_dev *dev, int probe)
3796{
3797 int pos;
3798 u8 cap;
3799
3800 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3801 if (!pos)
3802 return -ENOTTY;
3803
3804 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3805 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3806 return -ENOTTY;
3807
3808 if (probe)
3809 return 0;
3810
3811 /*
3812 * Wait for Transaction Pending bit to clear. A word-aligned test
3813 * is used, so we use the conrol offset rather than status and shift
3814 * the test bit to match.
3815 */
3816 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3817 PCI_AF_STATUS_TP << 8))
3818 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3819
3820 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3821 pci_flr_wait(dev);
3822 return 0;
3823}
3824
3825/**
3826 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3827 * @dev: Device to reset.
3828 * @probe: If set, only check if the device can be reset this way.
3829 *
3830 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3831 * unset, it will be reinitialized internally when going from PCI_D3hot to
3832 * PCI_D0. If that's the case and the device is not in a low-power state
3833 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3834 *
3835 * NOTE: This causes the caller to sleep for twice the device power transition
3836 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3837 * by default (i.e. unless the @dev's d3_delay field has a different value).
3838 * Moreover, only devices in D0 can be reset by this function.
3839 */
3840static int pci_pm_reset(struct pci_dev *dev, int probe)
3841{
3842 u16 csr;
3843
3844 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3845 return -ENOTTY;
3846
3847 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3848 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3849 return -ENOTTY;
3850
3851 if (probe)
3852 return 0;
3853
3854 if (dev->current_state != PCI_D0)
3855 return -EINVAL;
3856
3857 csr &= ~PCI_PM_CTRL_STATE_MASK;
3858 csr |= PCI_D3hot;
3859 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3860 pci_dev_d3_sleep(dev);
3861
3862 csr &= ~PCI_PM_CTRL_STATE_MASK;
3863 csr |= PCI_D0;
3864 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3865 pci_dev_d3_sleep(dev);
3866
3867 return 0;
3868}
3869
3870void pci_reset_secondary_bus(struct pci_dev *dev)
3871{
3872 u16 ctrl;
3873
3874 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3875 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3876 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3877 /*
3878 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3879 * this to 2ms to ensure that we meet the minimum requirement.
3880 */
3881 msleep(2);
3882
3883 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3884 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3885
3886 /*
3887 * Trhfa for conventional PCI is 2^25 clock cycles.
3888 * Assuming a minimum 33MHz clock this results in a 1s
3889 * delay before we can consider subordinate devices to
3890 * be re-initialized. PCIe has some ways to shorten this,
3891 * but we don't make use of them yet.
3892 */
3893 ssleep(1);
3894}
3895
3896void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3897{
3898 pci_reset_secondary_bus(dev);
3899}
3900
3901/**
3902 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3903 * @dev: Bridge device
3904 *
3905 * Use the bridge control register to assert reset on the secondary bus.
3906 * Devices on the secondary bus are left in power-on state.
3907 */
3908void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3909{
3910 pcibios_reset_secondary_bus(dev);
3911}
3912EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3913
3914static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3915{
3916 struct pci_dev *pdev;
3917
3918 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3919 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3920 return -ENOTTY;
3921
3922 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3923 if (pdev != dev)
3924 return -ENOTTY;
3925
3926 if (probe)
3927 return 0;
3928
3929 pci_reset_bridge_secondary_bus(dev->bus->self);
3930
3931 return 0;
3932}
3933
3934static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3935{
3936 int rc = -ENOTTY;
3937
3938 if (!hotplug || !try_module_get(hotplug->ops->owner))
3939 return rc;
3940
3941 if (hotplug->ops->reset_slot)
3942 rc = hotplug->ops->reset_slot(hotplug, probe);
3943
3944 module_put(hotplug->ops->owner);
3945
3946 return rc;
3947}
3948
3949static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3950{
3951 struct pci_dev *pdev;
3952
3953 if (dev->subordinate || !dev->slot ||
3954 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3955 return -ENOTTY;
3956
3957 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3958 if (pdev != dev && pdev->slot == dev->slot)
3959 return -ENOTTY;
3960
3961 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3962}
3963
3964static int __pci_dev_reset(struct pci_dev *dev, int probe)
3965{
3966 int rc;
3967
3968 might_sleep();
3969
3970 rc = pci_dev_specific_reset(dev, probe);
3971 if (rc != -ENOTTY)
3972 goto done;
3973
3974 rc = pcie_flr(dev, probe);
3975 if (rc != -ENOTTY)
3976 goto done;
3977
3978 rc = pci_af_flr(dev, probe);
3979 if (rc != -ENOTTY)
3980 goto done;
3981
3982 rc = pci_pm_reset(dev, probe);
3983 if (rc != -ENOTTY)
3984 goto done;
3985
3986 rc = pci_dev_reset_slot_function(dev, probe);
3987 if (rc != -ENOTTY)
3988 goto done;
3989
3990 rc = pci_parent_bus_reset(dev, probe);
3991done:
3992 return rc;
3993}
3994
3995static void pci_dev_lock(struct pci_dev *dev)
3996{
3997 pci_cfg_access_lock(dev);
3998 /* block PM suspend, driver probe, etc. */
3999 device_lock(&dev->dev);
4000}
4001
4002/* Return 1 on successful lock, 0 on contention */
4003static int pci_dev_trylock(struct pci_dev *dev)
4004{
4005 if (pci_cfg_access_trylock(dev)) {
4006 if (device_trylock(&dev->dev))
4007 return 1;
4008 pci_cfg_access_unlock(dev);
4009 }
4010
4011 return 0;
4012}
4013
4014static void pci_dev_unlock(struct pci_dev *dev)
4015{
4016 device_unlock(&dev->dev);
4017 pci_cfg_access_unlock(dev);
4018}
4019
4020/**
4021 * pci_reset_notify - notify device driver of reset
4022 * @dev: device to be notified of reset
4023 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
4024 * completed
4025 *
4026 * Must be called prior to device access being disabled and after device
4027 * access is restored.
4028 */
4029static void pci_reset_notify(struct pci_dev *dev, bool prepare)
4030{
4031 const struct pci_error_handlers *err_handler =
4032 dev->driver ? dev->driver->err_handler : NULL;
4033 if (err_handler && err_handler->reset_notify)
4034 err_handler->reset_notify(dev, prepare);
4035}
4036
4037static void pci_dev_save_and_disable(struct pci_dev *dev)
4038{
4039 pci_reset_notify(dev, true);
4040
4041 /*
4042 * Wake-up device prior to save. PM registers default to D0 after
4043 * reset and a simple register restore doesn't reliably return
4044 * to a non-D0 state anyway.
4045 */
4046 pci_set_power_state(dev, PCI_D0);
4047
4048 pci_save_state(dev);
4049 /*
4050 * Disable the device by clearing the Command register, except for
4051 * INTx-disable which is set. This not only disables MMIO and I/O port
4052 * BARs, but also prevents the device from being Bus Master, preventing
4053 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4054 * compliant devices, INTx-disable prevents legacy interrupts.
4055 */
4056 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4057}
4058
4059static void pci_dev_restore(struct pci_dev *dev)
4060{
4061 pci_restore_state(dev);
4062 pci_reset_notify(dev, false);
4063}
4064
4065static int pci_dev_reset(struct pci_dev *dev, int probe)
4066{
4067 int rc;
4068
4069 if (!probe)
4070 pci_dev_lock(dev);
4071
4072 rc = __pci_dev_reset(dev, probe);
4073
4074 if (!probe)
4075 pci_dev_unlock(dev);
4076
4077 return rc;
4078}
4079
4080/**
4081 * __pci_reset_function - reset a PCI device function
4082 * @dev: PCI device to reset
4083 *
4084 * Some devices allow an individual function to be reset without affecting
4085 * other functions in the same device. The PCI device must be responsive
4086 * to PCI config space in order to use this function.
4087 *
4088 * The device function is presumed to be unused when this function is called.
4089 * Resetting the device will make the contents of PCI configuration space
4090 * random, so any caller of this must be prepared to reinitialise the
4091 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4092 * etc.
4093 *
4094 * Returns 0 if the device function was successfully reset or negative if the
4095 * device doesn't support resetting a single function.
4096 */
4097int __pci_reset_function(struct pci_dev *dev)
4098{
4099 return pci_dev_reset(dev, 0);
4100}
4101EXPORT_SYMBOL_GPL(__pci_reset_function);
4102
4103/**
4104 * __pci_reset_function_locked - reset a PCI device function while holding
4105 * the @dev mutex lock.
4106 * @dev: PCI device to reset
4107 *
4108 * Some devices allow an individual function to be reset without affecting
4109 * other functions in the same device. The PCI device must be responsive
4110 * to PCI config space in order to use this function.
4111 *
4112 * The device function is presumed to be unused and the caller is holding
4113 * the device mutex lock when this function is called.
4114 * Resetting the device will make the contents of PCI configuration space
4115 * random, so any caller of this must be prepared to reinitialise the
4116 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4117 * etc.
4118 *
4119 * Returns 0 if the device function was successfully reset or negative if the
4120 * device doesn't support resetting a single function.
4121 */
4122int __pci_reset_function_locked(struct pci_dev *dev)
4123{
4124 return __pci_dev_reset(dev, 0);
4125}
4126EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4127
4128/**
4129 * pci_probe_reset_function - check whether the device can be safely reset
4130 * @dev: PCI device to reset
4131 *
4132 * Some devices allow an individual function to be reset without affecting
4133 * other functions in the same device. The PCI device must be responsive
4134 * to PCI config space in order to use this function.
4135 *
4136 * Returns 0 if the device function can be reset or negative if the
4137 * device doesn't support resetting a single function.
4138 */
4139int pci_probe_reset_function(struct pci_dev *dev)
4140{
4141 return pci_dev_reset(dev, 1);
4142}
4143
4144/**
4145 * pci_reset_function - quiesce and reset a PCI device function
4146 * @dev: PCI device to reset
4147 *
4148 * Some devices allow an individual function to be reset without affecting
4149 * other functions in the same device. The PCI device must be responsive
4150 * to PCI config space in order to use this function.
4151 *
4152 * This function does not just reset the PCI portion of a device, but
4153 * clears all the state associated with the device. This function differs
4154 * from __pci_reset_function in that it saves and restores device state
4155 * over the reset.
4156 *
4157 * Returns 0 if the device function was successfully reset or negative if the
4158 * device doesn't support resetting a single function.
4159 */
4160int pci_reset_function(struct pci_dev *dev)
4161{
4162 int rc;
4163
4164 rc = pci_dev_reset(dev, 1);
4165 if (rc)
4166 return rc;
4167
4168 pci_dev_save_and_disable(dev);
4169
4170 rc = pci_dev_reset(dev, 0);
4171
4172 pci_dev_restore(dev);
4173
4174 return rc;
4175}
4176EXPORT_SYMBOL_GPL(pci_reset_function);
4177
4178/**
4179 * pci_try_reset_function - quiesce and reset a PCI device function
4180 * @dev: PCI device to reset
4181 *
4182 * Same as above, except return -EAGAIN if unable to lock device.
4183 */
4184int pci_try_reset_function(struct pci_dev *dev)
4185{
4186 int rc;
4187
4188 rc = pci_dev_reset(dev, 1);
4189 if (rc)
4190 return rc;
4191
4192 pci_dev_save_and_disable(dev);
4193
4194 if (pci_dev_trylock(dev)) {
4195 rc = __pci_dev_reset(dev, 0);
4196 pci_dev_unlock(dev);
4197 } else
4198 rc = -EAGAIN;
4199
4200 pci_dev_restore(dev);
4201
4202 return rc;
4203}
4204EXPORT_SYMBOL_GPL(pci_try_reset_function);
4205
4206/* Do any devices on or below this bus prevent a bus reset? */
4207static bool pci_bus_resetable(struct pci_bus *bus)
4208{
4209 struct pci_dev *dev;
4210
4211 list_for_each_entry(dev, &bus->devices, bus_list) {
4212 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4213 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4214 return false;
4215 }
4216
4217 return true;
4218}
4219
4220/* Lock devices from the top of the tree down */
4221static void pci_bus_lock(struct pci_bus *bus)
4222{
4223 struct pci_dev *dev;
4224
4225 list_for_each_entry(dev, &bus->devices, bus_list) {
4226 pci_dev_lock(dev);
4227 if (dev->subordinate)
4228 pci_bus_lock(dev->subordinate);
4229 }
4230}
4231
4232/* Unlock devices from the bottom of the tree up */
4233static void pci_bus_unlock(struct pci_bus *bus)
4234{
4235 struct pci_dev *dev;
4236
4237 list_for_each_entry(dev, &bus->devices, bus_list) {
4238 if (dev->subordinate)
4239 pci_bus_unlock(dev->subordinate);
4240 pci_dev_unlock(dev);
4241 }
4242}
4243
4244/* Return 1 on successful lock, 0 on contention */
4245static int pci_bus_trylock(struct pci_bus *bus)
4246{
4247 struct pci_dev *dev;
4248
4249 list_for_each_entry(dev, &bus->devices, bus_list) {
4250 if (!pci_dev_trylock(dev))
4251 goto unlock;
4252 if (dev->subordinate) {
4253 if (!pci_bus_trylock(dev->subordinate)) {
4254 pci_dev_unlock(dev);
4255 goto unlock;
4256 }
4257 }
4258 }
4259 return 1;
4260
4261unlock:
4262 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4263 if (dev->subordinate)
4264 pci_bus_unlock(dev->subordinate);
4265 pci_dev_unlock(dev);
4266 }
4267 return 0;
4268}
4269
4270/* Do any devices on or below this slot prevent a bus reset? */
4271static bool pci_slot_resetable(struct pci_slot *slot)
4272{
4273 struct pci_dev *dev;
4274
4275 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4276 if (!dev->slot || dev->slot != slot)
4277 continue;
4278 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4279 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4280 return false;
4281 }
4282
4283 return true;
4284}
4285
4286/* Lock devices from the top of the tree down */
4287static void pci_slot_lock(struct pci_slot *slot)
4288{
4289 struct pci_dev *dev;
4290
4291 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4292 if (!dev->slot || dev->slot != slot)
4293 continue;
4294 pci_dev_lock(dev);
4295 if (dev->subordinate)
4296 pci_bus_lock(dev->subordinate);
4297 }
4298}
4299
4300/* Unlock devices from the bottom of the tree up */
4301static void pci_slot_unlock(struct pci_slot *slot)
4302{
4303 struct pci_dev *dev;
4304
4305 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4306 if (!dev->slot || dev->slot != slot)
4307 continue;
4308 if (dev->subordinate)
4309 pci_bus_unlock(dev->subordinate);
4310 pci_dev_unlock(dev);
4311 }
4312}
4313
4314/* Return 1 on successful lock, 0 on contention */
4315static int pci_slot_trylock(struct pci_slot *slot)
4316{
4317 struct pci_dev *dev;
4318
4319 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4320 if (!dev->slot || dev->slot != slot)
4321 continue;
4322 if (!pci_dev_trylock(dev))
4323 goto unlock;
4324 if (dev->subordinate) {
4325 if (!pci_bus_trylock(dev->subordinate)) {
4326 pci_dev_unlock(dev);
4327 goto unlock;
4328 }
4329 }
4330 }
4331 return 1;
4332
4333unlock:
4334 list_for_each_entry_continue_reverse(dev,
4335 &slot->bus->devices, bus_list) {
4336 if (!dev->slot || dev->slot != slot)
4337 continue;
4338 if (dev->subordinate)
4339 pci_bus_unlock(dev->subordinate);
4340 pci_dev_unlock(dev);
4341 }
4342 return 0;
4343}
4344
4345/* Save and disable devices from the top of the tree down */
4346static void pci_bus_save_and_disable(struct pci_bus *bus)
4347{
4348 struct pci_dev *dev;
4349
4350 list_for_each_entry(dev, &bus->devices, bus_list) {
4351 pci_dev_save_and_disable(dev);
4352 if (dev->subordinate)
4353 pci_bus_save_and_disable(dev->subordinate);
4354 }
4355}
4356
4357/*
4358 * Restore devices from top of the tree down - parent bridges need to be
4359 * restored before we can get to subordinate devices.
4360 */
4361static void pci_bus_restore(struct pci_bus *bus)
4362{
4363 struct pci_dev *dev;
4364
4365 list_for_each_entry(dev, &bus->devices, bus_list) {
4366 pci_dev_restore(dev);
4367 if (dev->subordinate)
4368 pci_bus_restore(dev->subordinate);
4369 }
4370}
4371
4372/* Save and disable devices from the top of the tree down */
4373static void pci_slot_save_and_disable(struct pci_slot *slot)
4374{
4375 struct pci_dev *dev;
4376
4377 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4378 if (!dev->slot || dev->slot != slot)
4379 continue;
4380 pci_dev_save_and_disable(dev);
4381 if (dev->subordinate)
4382 pci_bus_save_and_disable(dev->subordinate);
4383 }
4384}
4385
4386/*
4387 * Restore devices from top of the tree down - parent bridges need to be
4388 * restored before we can get to subordinate devices.
4389 */
4390static void pci_slot_restore(struct pci_slot *slot)
4391{
4392 struct pci_dev *dev;
4393
4394 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4395 if (!dev->slot || dev->slot != slot)
4396 continue;
4397 pci_dev_restore(dev);
4398 if (dev->subordinate)
4399 pci_bus_restore(dev->subordinate);
4400 }
4401}
4402
4403static int pci_slot_reset(struct pci_slot *slot, int probe)
4404{
4405 int rc;
4406
4407 if (!slot || !pci_slot_resetable(slot))
4408 return -ENOTTY;
4409
4410 if (!probe)
4411 pci_slot_lock(slot);
4412
4413 might_sleep();
4414
4415 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4416
4417 if (!probe)
4418 pci_slot_unlock(slot);
4419
4420 return rc;
4421}
4422
4423/**
4424 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4425 * @slot: PCI slot to probe
4426 *
4427 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4428 */
4429int pci_probe_reset_slot(struct pci_slot *slot)
4430{
4431 return pci_slot_reset(slot, 1);
4432}
4433EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4434
4435/**
4436 * pci_reset_slot - reset a PCI slot
4437 * @slot: PCI slot to reset
4438 *
4439 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4440 * independent of other slots. For instance, some slots may support slot power
4441 * control. In the case of a 1:1 bus to slot architecture, this function may
4442 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4443 * Generally a slot reset should be attempted before a bus reset. All of the
4444 * function of the slot and any subordinate buses behind the slot are reset
4445 * through this function. PCI config space of all devices in the slot and
4446 * behind the slot is saved before and restored after reset.
4447 *
4448 * Return 0 on success, non-zero on error.
4449 */
4450int pci_reset_slot(struct pci_slot *slot)
4451{
4452 int rc;
4453
4454 rc = pci_slot_reset(slot, 1);
4455 if (rc)
4456 return rc;
4457
4458 pci_slot_save_and_disable(slot);
4459
4460 rc = pci_slot_reset(slot, 0);
4461
4462 pci_slot_restore(slot);
4463
4464 return rc;
4465}
4466EXPORT_SYMBOL_GPL(pci_reset_slot);
4467
4468/**
4469 * pci_try_reset_slot - Try to reset a PCI slot
4470 * @slot: PCI slot to reset
4471 *
4472 * Same as above except return -EAGAIN if the slot cannot be locked
4473 */
4474int pci_try_reset_slot(struct pci_slot *slot)
4475{
4476 int rc;
4477
4478 rc = pci_slot_reset(slot, 1);
4479 if (rc)
4480 return rc;
4481
4482 pci_slot_save_and_disable(slot);
4483
4484 if (pci_slot_trylock(slot)) {
4485 might_sleep();
4486 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4487 pci_slot_unlock(slot);
4488 } else
4489 rc = -EAGAIN;
4490
4491 pci_slot_restore(slot);
4492
4493 return rc;
4494}
4495EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4496
4497static int pci_bus_reset(struct pci_bus *bus, int probe)
4498{
4499 if (!bus->self || !pci_bus_resetable(bus))
4500 return -ENOTTY;
4501
4502 if (probe)
4503 return 0;
4504
4505 pci_bus_lock(bus);
4506
4507 might_sleep();
4508
4509 pci_reset_bridge_secondary_bus(bus->self);
4510
4511 pci_bus_unlock(bus);
4512
4513 return 0;
4514}
4515
4516/**
4517 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4518 * @bus: PCI bus to probe
4519 *
4520 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4521 */
4522int pci_probe_reset_bus(struct pci_bus *bus)
4523{
4524 return pci_bus_reset(bus, 1);
4525}
4526EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4527
4528/**
4529 * pci_reset_bus - reset a PCI bus
4530 * @bus: top level PCI bus to reset
4531 *
4532 * Do a bus reset on the given bus and any subordinate buses, saving
4533 * and restoring state of all devices.
4534 *
4535 * Return 0 on success, non-zero on error.
4536 */
4537int pci_reset_bus(struct pci_bus *bus)
4538{
4539 int rc;
4540
4541 rc = pci_bus_reset(bus, 1);
4542 if (rc)
4543 return rc;
4544
4545 pci_bus_save_and_disable(bus);
4546
4547 rc = pci_bus_reset(bus, 0);
4548
4549 pci_bus_restore(bus);
4550
4551 return rc;
4552}
4553EXPORT_SYMBOL_GPL(pci_reset_bus);
4554
4555/**
4556 * pci_try_reset_bus - Try to reset a PCI bus
4557 * @bus: top level PCI bus to reset
4558 *
4559 * Same as above except return -EAGAIN if the bus cannot be locked
4560 */
4561int pci_try_reset_bus(struct pci_bus *bus)
4562{
4563 int rc;
4564
4565 rc = pci_bus_reset(bus, 1);
4566 if (rc)
4567 return rc;
4568
4569 pci_bus_save_and_disable(bus);
4570
4571 if (pci_bus_trylock(bus)) {
4572 might_sleep();
4573 pci_reset_bridge_secondary_bus(bus->self);
4574 pci_bus_unlock(bus);
4575 } else
4576 rc = -EAGAIN;
4577
4578 pci_bus_restore(bus);
4579
4580 return rc;
4581}
4582EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4583
4584/**
4585 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4586 * @dev: PCI device to query
4587 *
4588 * Returns mmrbc: maximum designed memory read count in bytes
4589 * or appropriate error value.
4590 */
4591int pcix_get_max_mmrbc(struct pci_dev *dev)
4592{
4593 int cap;
4594 u32 stat;
4595
4596 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4597 if (!cap)
4598 return -EINVAL;
4599
4600 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4601 return -EINVAL;
4602
4603 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4604}
4605EXPORT_SYMBOL(pcix_get_max_mmrbc);
4606
4607/**
4608 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4609 * @dev: PCI device to query
4610 *
4611 * Returns mmrbc: maximum memory read count in bytes
4612 * or appropriate error value.
4613 */
4614int pcix_get_mmrbc(struct pci_dev *dev)
4615{
4616 int cap;
4617 u16 cmd;
4618
4619 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4620 if (!cap)
4621 return -EINVAL;
4622
4623 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4624 return -EINVAL;
4625
4626 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4627}
4628EXPORT_SYMBOL(pcix_get_mmrbc);
4629
4630/**
4631 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4632 * @dev: PCI device to query
4633 * @mmrbc: maximum memory read count in bytes
4634 * valid values are 512, 1024, 2048, 4096
4635 *
4636 * If possible sets maximum memory read byte count, some bridges have erratas
4637 * that prevent this.
4638 */
4639int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4640{
4641 int cap;
4642 u32 stat, v, o;
4643 u16 cmd;
4644
4645 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4646 return -EINVAL;
4647
4648 v = ffs(mmrbc) - 10;
4649
4650 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4651 if (!cap)
4652 return -EINVAL;
4653
4654 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4655 return -EINVAL;
4656
4657 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4658 return -E2BIG;
4659
4660 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4661 return -EINVAL;
4662
4663 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4664 if (o != v) {
4665 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4666 return -EIO;
4667
4668 cmd &= ~PCI_X_CMD_MAX_READ;
4669 cmd |= v << 2;
4670 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4671 return -EIO;
4672 }
4673 return 0;
4674}
4675EXPORT_SYMBOL(pcix_set_mmrbc);
4676
4677/**
4678 * pcie_get_readrq - get PCI Express read request size
4679 * @dev: PCI device to query
4680 *
4681 * Returns maximum memory read request in bytes
4682 * or appropriate error value.
4683 */
4684int pcie_get_readrq(struct pci_dev *dev)
4685{
4686 u16 ctl;
4687
4688 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4689
4690 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4691}
4692EXPORT_SYMBOL(pcie_get_readrq);
4693
4694/**
4695 * pcie_set_readrq - set PCI Express maximum memory read request
4696 * @dev: PCI device to query
4697 * @rq: maximum memory read count in bytes
4698 * valid values are 128, 256, 512, 1024, 2048, 4096
4699 *
4700 * If possible sets maximum memory read request in bytes
4701 */
4702int pcie_set_readrq(struct pci_dev *dev, int rq)
4703{
4704 u16 v;
4705
4706 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4707 return -EINVAL;
4708
4709 /*
4710 * If using the "performance" PCIe config, we clamp the
4711 * read rq size to the max packet size to prevent the
4712 * host bridge generating requests larger than we can
4713 * cope with
4714 */
4715 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4716 int mps = pcie_get_mps(dev);
4717
4718 if (mps < rq)
4719 rq = mps;
4720 }
4721
4722 v = (ffs(rq) - 8) << 12;
4723
4724 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4725 PCI_EXP_DEVCTL_READRQ, v);
4726}
4727EXPORT_SYMBOL(pcie_set_readrq);
4728
4729/**
4730 * pcie_get_mps - get PCI Express maximum payload size
4731 * @dev: PCI device to query
4732 *
4733 * Returns maximum payload size in bytes
4734 */
4735int pcie_get_mps(struct pci_dev *dev)
4736{
4737 u16 ctl;
4738
4739 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4740
4741 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4742}
4743EXPORT_SYMBOL(pcie_get_mps);
4744
4745/**
4746 * pcie_set_mps - set PCI Express maximum payload size
4747 * @dev: PCI device to query
4748 * @mps: maximum payload size in bytes
4749 * valid values are 128, 256, 512, 1024, 2048, 4096
4750 *
4751 * If possible sets maximum payload size
4752 */
4753int pcie_set_mps(struct pci_dev *dev, int mps)
4754{
4755 u16 v;
4756
4757 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4758 return -EINVAL;
4759
4760 v = ffs(mps) - 8;
4761 if (v > dev->pcie_mpss)
4762 return -EINVAL;
4763 v <<= 5;
4764
4765 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4766 PCI_EXP_DEVCTL_PAYLOAD, v);
4767}
4768EXPORT_SYMBOL(pcie_set_mps);
4769
4770/**
4771 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4772 * @dev: PCI device to query
4773 * @speed: storage for minimum speed
4774 * @width: storage for minimum width
4775 *
4776 * This function will walk up the PCI device chain and determine the minimum
4777 * link width and speed of the device.
4778 */
4779int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4780 enum pcie_link_width *width)
4781{
4782 int ret;
4783
4784 *speed = PCI_SPEED_UNKNOWN;
4785 *width = PCIE_LNK_WIDTH_UNKNOWN;
4786
4787 while (dev) {
4788 u16 lnksta;
4789 enum pci_bus_speed next_speed;
4790 enum pcie_link_width next_width;
4791
4792 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4793 if (ret)
4794 return ret;
4795
4796 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4797 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4798 PCI_EXP_LNKSTA_NLW_SHIFT;
4799
4800 if (next_speed < *speed)
4801 *speed = next_speed;
4802
4803 if (next_width < *width)
4804 *width = next_width;
4805
4806 dev = dev->bus->self;
4807 }
4808
4809 return 0;
4810}
4811EXPORT_SYMBOL(pcie_get_minimum_link);
4812
4813/**
4814 * pci_select_bars - Make BAR mask from the type of resource
4815 * @dev: the PCI device for which BAR mask is made
4816 * @flags: resource type mask to be selected
4817 *
4818 * This helper routine makes bar mask from the type of resource.
4819 */
4820int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4821{
4822 int i, bars = 0;
4823 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4824 if (pci_resource_flags(dev, i) & flags)
4825 bars |= (1 << i);
4826 return bars;
4827}
4828EXPORT_SYMBOL(pci_select_bars);
4829
4830/* Some architectures require additional programming to enable VGA */
4831static arch_set_vga_state_t arch_set_vga_state;
4832
4833void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4834{
4835 arch_set_vga_state = func; /* NULL disables */
4836}
4837
4838static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4839 unsigned int command_bits, u32 flags)
4840{
4841 if (arch_set_vga_state)
4842 return arch_set_vga_state(dev, decode, command_bits,
4843 flags);
4844 return 0;
4845}
4846
4847/**
4848 * pci_set_vga_state - set VGA decode state on device and parents if requested
4849 * @dev: the PCI device
4850 * @decode: true = enable decoding, false = disable decoding
4851 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4852 * @flags: traverse ancestors and change bridges
4853 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4854 */
4855int pci_set_vga_state(struct pci_dev *dev, bool decode,
4856 unsigned int command_bits, u32 flags)
4857{
4858 struct pci_bus *bus;
4859 struct pci_dev *bridge;
4860 u16 cmd;
4861 int rc;
4862
4863 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4864
4865 /* ARCH specific VGA enables */
4866 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4867 if (rc)
4868 return rc;
4869
4870 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4871 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4872 if (decode == true)
4873 cmd |= command_bits;
4874 else
4875 cmd &= ~command_bits;
4876 pci_write_config_word(dev, PCI_COMMAND, cmd);
4877 }
4878
4879 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4880 return 0;
4881
4882 bus = dev->bus;
4883 while (bus) {
4884 bridge = bus->self;
4885 if (bridge) {
4886 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4887 &cmd);
4888 if (decode == true)
4889 cmd |= PCI_BRIDGE_CTL_VGA;
4890 else
4891 cmd &= ~PCI_BRIDGE_CTL_VGA;
4892 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4893 cmd);
4894 }
4895 bus = bus->parent;
4896 }
4897 return 0;
4898}
4899
4900/**
4901 * pci_add_dma_alias - Add a DMA devfn alias for a device
4902 * @dev: the PCI device for which alias is added
4903 * @devfn: alias slot and function
4904 *
4905 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
4906 * It should be called early, preferably as PCI fixup header quirk.
4907 */
4908void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
4909{
4910 if (!dev->dma_alias_mask)
4911 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
4912 sizeof(long), GFP_KERNEL);
4913 if (!dev->dma_alias_mask) {
4914 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
4915 return;
4916 }
4917
4918 set_bit(devfn, dev->dma_alias_mask);
4919 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
4920 PCI_SLOT(devfn), PCI_FUNC(devfn));
4921}
4922
4923bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
4924{
4925 return (dev1->dma_alias_mask &&
4926 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
4927 (dev2->dma_alias_mask &&
4928 test_bit(dev1->devfn, dev2->dma_alias_mask));
4929}
4930
4931bool pci_device_is_present(struct pci_dev *pdev)
4932{
4933 u32 v;
4934
4935 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4936}
4937EXPORT_SYMBOL_GPL(pci_device_is_present);
4938
4939void pci_ignore_hotplug(struct pci_dev *dev)
4940{
4941 struct pci_dev *bridge = dev->bus->self;
4942
4943 dev->ignore_hotplug = 1;
4944 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4945 if (bridge)
4946 bridge->ignore_hotplug = 1;
4947}
4948EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4949
4950#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4951static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4952static DEFINE_SPINLOCK(resource_alignment_lock);
4953
4954/**
4955 * pci_specified_resource_alignment - get resource alignment specified by user.
4956 * @dev: the PCI device to get
4957 *
4958 * RETURNS: Resource alignment if it is specified.
4959 * Zero if it is not specified.
4960 */
4961static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4962{
4963 int seg, bus, slot, func, align_order, count;
4964 unsigned short vendor, device, subsystem_vendor, subsystem_device;
4965 resource_size_t align = 0;
4966 char *p;
4967
4968 spin_lock(&resource_alignment_lock);
4969 p = resource_alignment_param;
4970 if (!*p)
4971 goto out;
4972 if (pci_has_flag(PCI_PROBE_ONLY)) {
4973 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
4974 goto out;
4975 }
4976
4977 while (*p) {
4978 count = 0;
4979 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4980 p[count] == '@') {
4981 p += count + 1;
4982 } else {
4983 align_order = -1;
4984 }
4985 if (strncmp(p, "pci:", 4) == 0) {
4986 /* PCI vendor/device (subvendor/subdevice) ids are specified */
4987 p += 4;
4988 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
4989 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
4990 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
4991 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
4992 p);
4993 break;
4994 }
4995 subsystem_vendor = subsystem_device = 0;
4996 }
4997 p += count;
4998 if ((!vendor || (vendor == dev->vendor)) &&
4999 (!device || (device == dev->device)) &&
5000 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5001 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5002 if (align_order == -1)
5003 align = PAGE_SIZE;
5004 else
5005 align = 1 << align_order;
5006 /* Found */
5007 break;
5008 }
5009 }
5010 else {
5011 if (sscanf(p, "%x:%x:%x.%x%n",
5012 &seg, &bus, &slot, &func, &count) != 4) {
5013 seg = 0;
5014 if (sscanf(p, "%x:%x.%x%n",
5015 &bus, &slot, &func, &count) != 3) {
5016 /* Invalid format */
5017 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5018 p);
5019 break;
5020 }
5021 }
5022 p += count;
5023 if (seg == pci_domain_nr(dev->bus) &&
5024 bus == dev->bus->number &&
5025 slot == PCI_SLOT(dev->devfn) &&
5026 func == PCI_FUNC(dev->devfn)) {
5027 if (align_order == -1)
5028 align = PAGE_SIZE;
5029 else
5030 align = 1 << align_order;
5031 /* Found */
5032 break;
5033 }
5034 }
5035 if (*p != ';' && *p != ',') {
5036 /* End of param or invalid format */
5037 break;
5038 }
5039 p++;
5040 }
5041out:
5042 spin_unlock(&resource_alignment_lock);
5043 return align;
5044}
5045
5046/*
5047 * This function disables memory decoding and releases memory resources
5048 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5049 * It also rounds up size to specified alignment.
5050 * Later on, the kernel will assign page-aligned memory resource back
5051 * to the device.
5052 */
5053void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5054{
5055 int i;
5056 struct resource *r;
5057 resource_size_t align, size;
5058 u16 command;
5059
5060 /*
5061 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5062 * 3.4.1.11. Their resources are allocated from the space
5063 * described by the VF BARx register in the PF's SR-IOV capability.
5064 * We can't influence their alignment here.
5065 */
5066 if (dev->is_virtfn)
5067 return;
5068
5069 /* check if specified PCI is target device to reassign */
5070 align = pci_specified_resource_alignment(dev);
5071 if (!align)
5072 return;
5073
5074 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5075 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5076 dev_warn(&dev->dev,
5077 "Can't reassign resources to host bridge.\n");
5078 return;
5079 }
5080
5081 dev_info(&dev->dev,
5082 "Disabling memory decoding and releasing memory resources.\n");
5083 pci_read_config_word(dev, PCI_COMMAND, &command);
5084 command &= ~PCI_COMMAND_MEMORY;
5085 pci_write_config_word(dev, PCI_COMMAND, command);
5086
5087 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
5088 r = &dev->resource[i];
5089 if (!(r->flags & IORESOURCE_MEM))
5090 continue;
5091 if (r->flags & IORESOURCE_PCI_FIXED) {
5092 dev_info(&dev->dev, "Ignoring requested alignment for BAR%d: %pR\n",
5093 i, r);
5094 continue;
5095 }
5096
5097 size = resource_size(r);
5098 if (size < align) {
5099 size = align;
5100 dev_info(&dev->dev,
5101 "Rounding up size of resource #%d to %#llx.\n",
5102 i, (unsigned long long)size);
5103 }
5104 r->flags |= IORESOURCE_UNSET;
5105 r->end = size - 1;
5106 r->start = 0;
5107 }
5108 /* Need to disable bridge's resource window,
5109 * to enable the kernel to reassign new resource
5110 * window later on.
5111 */
5112 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5113 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5114 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5115 r = &dev->resource[i];
5116 if (!(r->flags & IORESOURCE_MEM))
5117 continue;
5118 r->flags |= IORESOURCE_UNSET;
5119 r->end = resource_size(r) - 1;
5120 r->start = 0;
5121 }
5122 pci_disable_bridge_window(dev);
5123 }
5124}
5125
5126static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5127{
5128 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5129 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5130 spin_lock(&resource_alignment_lock);
5131 strncpy(resource_alignment_param, buf, count);
5132 resource_alignment_param[count] = '\0';
5133 spin_unlock(&resource_alignment_lock);
5134 return count;
5135}
5136
5137static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5138{
5139 size_t count;
5140 spin_lock(&resource_alignment_lock);
5141 count = snprintf(buf, size, "%s", resource_alignment_param);
5142 spin_unlock(&resource_alignment_lock);
5143 return count;
5144}
5145
5146static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5147{
5148 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5149}
5150
5151static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5152 const char *buf, size_t count)
5153{
5154 return pci_set_resource_alignment_param(buf, count);
5155}
5156
5157static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5158 pci_resource_alignment_store);
5159
5160static int __init pci_resource_alignment_sysfs_init(void)
5161{
5162 return bus_create_file(&pci_bus_type,
5163 &bus_attr_resource_alignment);
5164}
5165late_initcall(pci_resource_alignment_sysfs_init);
5166
5167static void pci_no_domains(void)
5168{
5169#ifdef CONFIG_PCI_DOMAINS
5170 pci_domains_supported = 0;
5171#endif
5172}
5173
5174#ifdef CONFIG_PCI_DOMAINS
5175static atomic_t __domain_nr = ATOMIC_INIT(-1);
5176
5177int pci_get_new_domain_nr(void)
5178{
5179 return atomic_inc_return(&__domain_nr);
5180}
5181
5182#ifdef CONFIG_PCI_DOMAINS_GENERIC
5183static int of_pci_bus_find_domain_nr(struct device *parent)
5184{
5185 static int use_dt_domains = -1;
5186 int domain = -1;
5187
5188 if (parent)
5189 domain = of_get_pci_domain_nr(parent->of_node);
5190 /*
5191 * Check DT domain and use_dt_domains values.
5192 *
5193 * If DT domain property is valid (domain >= 0) and
5194 * use_dt_domains != 0, the DT assignment is valid since this means
5195 * we have not previously allocated a domain number by using
5196 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5197 * 1, to indicate that we have just assigned a domain number from
5198 * DT.
5199 *
5200 * If DT domain property value is not valid (ie domain < 0), and we
5201 * have not previously assigned a domain number from DT
5202 * (use_dt_domains != 1) we should assign a domain number by
5203 * using the:
5204 *
5205 * pci_get_new_domain_nr()
5206 *
5207 * API and update the use_dt_domains value to keep track of method we
5208 * are using to assign domain numbers (use_dt_domains = 0).
5209 *
5210 * All other combinations imply we have a platform that is trying
5211 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5212 * which is a recipe for domain mishandling and it is prevented by
5213 * invalidating the domain value (domain = -1) and printing a
5214 * corresponding error.
5215 */
5216 if (domain >= 0 && use_dt_domains) {
5217 use_dt_domains = 1;
5218 } else if (domain < 0 && use_dt_domains != 1) {
5219 use_dt_domains = 0;
5220 domain = pci_get_new_domain_nr();
5221 } else {
5222 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
5223 parent->of_node->full_name);
5224 domain = -1;
5225 }
5226
5227 return domain;
5228}
5229
5230int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5231{
5232 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5233 acpi_pci_bus_find_domain_nr(bus);
5234}
5235#endif
5236#endif
5237
5238/**
5239 * pci_ext_cfg_avail - can we access extended PCI config space?
5240 *
5241 * Returns 1 if we can access PCI extended config space (offsets
5242 * greater than 0xff). This is the default implementation. Architecture
5243 * implementations can override this.
5244 */
5245int __weak pci_ext_cfg_avail(void)
5246{
5247 return 1;
5248}
5249
5250void __weak pci_fixup_cardbus(struct pci_bus *bus)
5251{
5252}
5253EXPORT_SYMBOL(pci_fixup_cardbus);
5254
5255static int __init pci_setup(char *str)
5256{
5257 while (str) {
5258 char *k = strchr(str, ',');
5259 if (k)
5260 *k++ = 0;
5261 if (*str && (str = pcibios_setup(str)) && *str) {
5262 if (!strcmp(str, "nomsi")) {
5263 pci_no_msi();
5264 } else if (!strcmp(str, "noaer")) {
5265 pci_no_aer();
5266 } else if (!strncmp(str, "realloc=", 8)) {
5267 pci_realloc_get_opt(str + 8);
5268 } else if (!strncmp(str, "realloc", 7)) {
5269 pci_realloc_get_opt("on");
5270 } else if (!strcmp(str, "nodomains")) {
5271 pci_no_domains();
5272 } else if (!strncmp(str, "noari", 5)) {
5273 pcie_ari_disabled = true;
5274 } else if (!strncmp(str, "cbiosize=", 9)) {
5275 pci_cardbus_io_size = memparse(str + 9, &str);
5276 } else if (!strncmp(str, "cbmemsize=", 10)) {
5277 pci_cardbus_mem_size = memparse(str + 10, &str);
5278 } else if (!strncmp(str, "resource_alignment=", 19)) {
5279 pci_set_resource_alignment_param(str + 19,
5280 strlen(str + 19));
5281 } else if (!strncmp(str, "ecrc=", 5)) {
5282 pcie_ecrc_get_policy(str + 5);
5283 } else if (!strncmp(str, "hpiosize=", 9)) {
5284 pci_hotplug_io_size = memparse(str + 9, &str);
5285 } else if (!strncmp(str, "hpmemsize=", 10)) {
5286 pci_hotplug_mem_size = memparse(str + 10, &str);
5287 } else if (!strncmp(str, "hpbussize=", 10)) {
5288 pci_hotplug_bus_size =
5289 simple_strtoul(str + 10, &str, 0);
5290 if (pci_hotplug_bus_size > 0xff)
5291 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5292 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5293 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5294 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5295 pcie_bus_config = PCIE_BUS_SAFE;
5296 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5297 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5298 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5299 pcie_bus_config = PCIE_BUS_PEER2PEER;
5300 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5301 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5302 } else {
5303 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5304 str);
5305 }
5306 }
5307 str = k;
5308 }
5309 return 0;
5310}
5311early_param("pci", pci_setup);