Loading...
1/*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
8
9#include <linux/err.h>
10#include <linux/mm.h>
11#include <linux/irq.h>
12#include <linux/interrupt.h>
13#include <linux/export.h>
14#include <linux/ioport.h>
15#include <linux/pci.h>
16#include <linux/proc_fs.h>
17#include <linux/msi.h>
18#include <linux/smp.h>
19#include <linux/errno.h>
20#include <linux/io.h>
21#include <linux/slab.h>
22#include <linux/irqdomain.h>
23#include <linux/of_irq.h>
24
25#include "pci.h"
26
27static int pci_msi_enable = 1;
28int pci_msi_ignore_mask;
29
30#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
31
32#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
33static struct irq_domain *pci_msi_default_domain;
34static DEFINE_MUTEX(pci_msi_domain_lock);
35
36struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
37{
38 return pci_msi_default_domain;
39}
40
41static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
42{
43 struct irq_domain *domain;
44
45 domain = dev_get_msi_domain(&dev->dev);
46 if (domain)
47 return domain;
48
49 return arch_get_pci_msi_domain(dev);
50}
51
52static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
53{
54 struct irq_domain *domain;
55
56 domain = pci_msi_get_domain(dev);
57 if (domain && irq_domain_is_hierarchy(domain))
58 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
59
60 return arch_setup_msi_irqs(dev, nvec, type);
61}
62
63static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
64{
65 struct irq_domain *domain;
66
67 domain = pci_msi_get_domain(dev);
68 if (domain && irq_domain_is_hierarchy(domain))
69 pci_msi_domain_free_irqs(domain, dev);
70 else
71 arch_teardown_msi_irqs(dev);
72}
73#else
74#define pci_msi_setup_msi_irqs arch_setup_msi_irqs
75#define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
76#endif
77
78/* Arch hooks */
79
80int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
81{
82 struct msi_controller *chip = dev->bus->msi;
83 int err;
84
85 if (!chip || !chip->setup_irq)
86 return -EINVAL;
87
88 err = chip->setup_irq(chip, dev, desc);
89 if (err < 0)
90 return err;
91
92 irq_set_chip_data(desc->irq, chip);
93
94 return 0;
95}
96
97void __weak arch_teardown_msi_irq(unsigned int irq)
98{
99 struct msi_controller *chip = irq_get_chip_data(irq);
100
101 if (!chip || !chip->teardown_irq)
102 return;
103
104 chip->teardown_irq(chip, irq);
105}
106
107int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
108{
109 struct msi_controller *chip = dev->bus->msi;
110 struct msi_desc *entry;
111 int ret;
112
113 if (chip && chip->setup_irqs)
114 return chip->setup_irqs(chip, dev, nvec, type);
115 /*
116 * If an architecture wants to support multiple MSI, it needs to
117 * override arch_setup_msi_irqs()
118 */
119 if (type == PCI_CAP_ID_MSI && nvec > 1)
120 return 1;
121
122 for_each_pci_msi_entry(entry, dev) {
123 ret = arch_setup_msi_irq(dev, entry);
124 if (ret < 0)
125 return ret;
126 if (ret > 0)
127 return -ENOSPC;
128 }
129
130 return 0;
131}
132
133/*
134 * We have a default implementation available as a separate non-weak
135 * function, as it is used by the Xen x86 PCI code
136 */
137void default_teardown_msi_irqs(struct pci_dev *dev)
138{
139 int i;
140 struct msi_desc *entry;
141
142 for_each_pci_msi_entry(entry, dev)
143 if (entry->irq)
144 for (i = 0; i < entry->nvec_used; i++)
145 arch_teardown_msi_irq(entry->irq + i);
146}
147
148void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
149{
150 return default_teardown_msi_irqs(dev);
151}
152
153static void default_restore_msi_irq(struct pci_dev *dev, int irq)
154{
155 struct msi_desc *entry;
156
157 entry = NULL;
158 if (dev->msix_enabled) {
159 for_each_pci_msi_entry(entry, dev) {
160 if (irq == entry->irq)
161 break;
162 }
163 } else if (dev->msi_enabled) {
164 entry = irq_get_msi_desc(irq);
165 }
166
167 if (entry)
168 __pci_write_msi_msg(entry, &entry->msg);
169}
170
171void __weak arch_restore_msi_irqs(struct pci_dev *dev)
172{
173 return default_restore_msi_irqs(dev);
174}
175
176static inline __attribute_const__ u32 msi_mask(unsigned x)
177{
178 /* Don't shift by >= width of type */
179 if (x >= 5)
180 return 0xffffffff;
181 return (1 << (1 << x)) - 1;
182}
183
184/*
185 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
186 * mask all MSI interrupts by clearing the MSI enable bit does not work
187 * reliably as devices without an INTx disable bit will then generate a
188 * level IRQ which will never be cleared.
189 */
190u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
191{
192 u32 mask_bits = desc->masked;
193
194 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
195 return 0;
196
197 mask_bits &= ~mask;
198 mask_bits |= flag;
199 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
200 mask_bits);
201
202 return mask_bits;
203}
204
205static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
206{
207 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
208}
209
210/*
211 * This internal function does not flush PCI writes to the device.
212 * All users must ensure that they read from the device before either
213 * assuming that the device state is up to date, or returning out of this
214 * file. This saves a few milliseconds when initialising devices with lots
215 * of MSI-X interrupts.
216 */
217u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
218{
219 u32 mask_bits = desc->masked;
220 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
221 PCI_MSIX_ENTRY_VECTOR_CTRL;
222
223 if (pci_msi_ignore_mask)
224 return 0;
225
226 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
227 if (flag)
228 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
229 writel(mask_bits, desc->mask_base + offset);
230
231 return mask_bits;
232}
233
234static void msix_mask_irq(struct msi_desc *desc, u32 flag)
235{
236 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
237}
238
239static void msi_set_mask_bit(struct irq_data *data, u32 flag)
240{
241 struct msi_desc *desc = irq_data_get_msi_desc(data);
242
243 if (desc->msi_attrib.is_msix) {
244 msix_mask_irq(desc, flag);
245 readl(desc->mask_base); /* Flush write to device */
246 } else {
247 unsigned offset = data->irq - desc->irq;
248 msi_mask_irq(desc, 1 << offset, flag << offset);
249 }
250}
251
252/**
253 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
254 * @data: pointer to irqdata associated to that interrupt
255 */
256void pci_msi_mask_irq(struct irq_data *data)
257{
258 msi_set_mask_bit(data, 1);
259}
260EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
261
262/**
263 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
264 * @data: pointer to irqdata associated to that interrupt
265 */
266void pci_msi_unmask_irq(struct irq_data *data)
267{
268 msi_set_mask_bit(data, 0);
269}
270EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
271
272void default_restore_msi_irqs(struct pci_dev *dev)
273{
274 struct msi_desc *entry;
275
276 for_each_pci_msi_entry(entry, dev)
277 default_restore_msi_irq(dev, entry->irq);
278}
279
280void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
281{
282 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
283
284 BUG_ON(dev->current_state != PCI_D0);
285
286 if (entry->msi_attrib.is_msix) {
287 void __iomem *base = entry->mask_base +
288 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
289
290 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
291 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
292 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
293 } else {
294 int pos = dev->msi_cap;
295 u16 data;
296
297 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
298 &msg->address_lo);
299 if (entry->msi_attrib.is_64) {
300 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
301 &msg->address_hi);
302 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
303 } else {
304 msg->address_hi = 0;
305 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
306 }
307 msg->data = data;
308 }
309}
310
311void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
312{
313 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
314
315 if (dev->current_state != PCI_D0) {
316 /* Don't touch the hardware now */
317 } else if (entry->msi_attrib.is_msix) {
318 void __iomem *base;
319 base = entry->mask_base +
320 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
321
322 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
323 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
324 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
325 } else {
326 int pos = dev->msi_cap;
327 u16 msgctl;
328
329 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
330 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
331 msgctl |= entry->msi_attrib.multiple << 4;
332 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
333
334 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
335 msg->address_lo);
336 if (entry->msi_attrib.is_64) {
337 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
338 msg->address_hi);
339 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
340 msg->data);
341 } else {
342 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
343 msg->data);
344 }
345 }
346 entry->msg = *msg;
347}
348
349void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
350{
351 struct msi_desc *entry = irq_get_msi_desc(irq);
352
353 __pci_write_msi_msg(entry, msg);
354}
355EXPORT_SYMBOL_GPL(pci_write_msi_msg);
356
357static void free_msi_irqs(struct pci_dev *dev)
358{
359 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
360 struct msi_desc *entry, *tmp;
361 struct attribute **msi_attrs;
362 struct device_attribute *dev_attr;
363 int i, count = 0;
364
365 for_each_pci_msi_entry(entry, dev)
366 if (entry->irq)
367 for (i = 0; i < entry->nvec_used; i++)
368 BUG_ON(irq_has_action(entry->irq + i));
369
370 pci_msi_teardown_msi_irqs(dev);
371
372 list_for_each_entry_safe(entry, tmp, msi_list, list) {
373 if (entry->msi_attrib.is_msix) {
374 if (list_is_last(&entry->list, msi_list))
375 iounmap(entry->mask_base);
376 }
377
378 list_del(&entry->list);
379 kfree(entry);
380 }
381
382 if (dev->msi_irq_groups) {
383 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
384 msi_attrs = dev->msi_irq_groups[0]->attrs;
385 while (msi_attrs[count]) {
386 dev_attr = container_of(msi_attrs[count],
387 struct device_attribute, attr);
388 kfree(dev_attr->attr.name);
389 kfree(dev_attr);
390 ++count;
391 }
392 kfree(msi_attrs);
393 kfree(dev->msi_irq_groups[0]);
394 kfree(dev->msi_irq_groups);
395 dev->msi_irq_groups = NULL;
396 }
397}
398
399static void pci_intx_for_msi(struct pci_dev *dev, int enable)
400{
401 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
402 pci_intx(dev, enable);
403}
404
405static void __pci_restore_msi_state(struct pci_dev *dev)
406{
407 u16 control;
408 struct msi_desc *entry;
409
410 if (!dev->msi_enabled)
411 return;
412
413 entry = irq_get_msi_desc(dev->irq);
414
415 pci_intx_for_msi(dev, 0);
416 pci_msi_set_enable(dev, 0);
417 arch_restore_msi_irqs(dev);
418
419 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
420 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
421 entry->masked);
422 control &= ~PCI_MSI_FLAGS_QSIZE;
423 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
424 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
425}
426
427static void __pci_restore_msix_state(struct pci_dev *dev)
428{
429 struct msi_desc *entry;
430
431 if (!dev->msix_enabled)
432 return;
433 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
434
435 /* route the table */
436 pci_intx_for_msi(dev, 0);
437 pci_msix_clear_and_set_ctrl(dev, 0,
438 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
439
440 arch_restore_msi_irqs(dev);
441 for_each_pci_msi_entry(entry, dev)
442 msix_mask_irq(entry, entry->masked);
443
444 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
445}
446
447void pci_restore_msi_state(struct pci_dev *dev)
448{
449 __pci_restore_msi_state(dev);
450 __pci_restore_msix_state(dev);
451}
452EXPORT_SYMBOL_GPL(pci_restore_msi_state);
453
454static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
455 char *buf)
456{
457 struct msi_desc *entry;
458 unsigned long irq;
459 int retval;
460
461 retval = kstrtoul(attr->attr.name, 10, &irq);
462 if (retval)
463 return retval;
464
465 entry = irq_get_msi_desc(irq);
466 if (entry)
467 return sprintf(buf, "%s\n",
468 entry->msi_attrib.is_msix ? "msix" : "msi");
469
470 return -ENODEV;
471}
472
473static int populate_msi_sysfs(struct pci_dev *pdev)
474{
475 struct attribute **msi_attrs;
476 struct attribute *msi_attr;
477 struct device_attribute *msi_dev_attr;
478 struct attribute_group *msi_irq_group;
479 const struct attribute_group **msi_irq_groups;
480 struct msi_desc *entry;
481 int ret = -ENOMEM;
482 int num_msi = 0;
483 int count = 0;
484 int i;
485
486 /* Determine how many msi entries we have */
487 for_each_pci_msi_entry(entry, pdev)
488 num_msi += entry->nvec_used;
489 if (!num_msi)
490 return 0;
491
492 /* Dynamically create the MSI attributes for the PCI device */
493 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
494 if (!msi_attrs)
495 return -ENOMEM;
496 for_each_pci_msi_entry(entry, pdev) {
497 for (i = 0; i < entry->nvec_used; i++) {
498 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
499 if (!msi_dev_attr)
500 goto error_attrs;
501 msi_attrs[count] = &msi_dev_attr->attr;
502
503 sysfs_attr_init(&msi_dev_attr->attr);
504 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
505 entry->irq + i);
506 if (!msi_dev_attr->attr.name)
507 goto error_attrs;
508 msi_dev_attr->attr.mode = S_IRUGO;
509 msi_dev_attr->show = msi_mode_show;
510 ++count;
511 }
512 }
513
514 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
515 if (!msi_irq_group)
516 goto error_attrs;
517 msi_irq_group->name = "msi_irqs";
518 msi_irq_group->attrs = msi_attrs;
519
520 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
521 if (!msi_irq_groups)
522 goto error_irq_group;
523 msi_irq_groups[0] = msi_irq_group;
524
525 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
526 if (ret)
527 goto error_irq_groups;
528 pdev->msi_irq_groups = msi_irq_groups;
529
530 return 0;
531
532error_irq_groups:
533 kfree(msi_irq_groups);
534error_irq_group:
535 kfree(msi_irq_group);
536error_attrs:
537 count = 0;
538 msi_attr = msi_attrs[count];
539 while (msi_attr) {
540 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
541 kfree(msi_attr->name);
542 kfree(msi_dev_attr);
543 ++count;
544 msi_attr = msi_attrs[count];
545 }
546 kfree(msi_attrs);
547 return ret;
548}
549
550static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
551{
552 u16 control;
553 struct msi_desc *entry;
554
555 /* MSI Entry Initialization */
556 entry = alloc_msi_entry(&dev->dev);
557 if (!entry)
558 return NULL;
559
560 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
561
562 entry->msi_attrib.is_msix = 0;
563 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
564 entry->msi_attrib.entry_nr = 0;
565 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
566 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
567 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
568 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
569 entry->nvec_used = nvec;
570
571 if (control & PCI_MSI_FLAGS_64BIT)
572 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
573 else
574 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
575
576 /* Save the initial mask status */
577 if (entry->msi_attrib.maskbit)
578 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
579
580 return entry;
581}
582
583static int msi_verify_entries(struct pci_dev *dev)
584{
585 struct msi_desc *entry;
586
587 for_each_pci_msi_entry(entry, dev) {
588 if (!dev->no_64bit_msi || !entry->msg.address_hi)
589 continue;
590 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
591 " tried to assign one above 4G\n");
592 return -EIO;
593 }
594 return 0;
595}
596
597/**
598 * msi_capability_init - configure device's MSI capability structure
599 * @dev: pointer to the pci_dev data structure of MSI device function
600 * @nvec: number of interrupts to allocate
601 *
602 * Setup the MSI capability structure of the device with the requested
603 * number of interrupts. A return value of zero indicates the successful
604 * setup of an entry with the new MSI irq. A negative return value indicates
605 * an error, and a positive return value indicates the number of interrupts
606 * which could have been allocated.
607 */
608static int msi_capability_init(struct pci_dev *dev, int nvec)
609{
610 struct msi_desc *entry;
611 int ret;
612 unsigned mask;
613
614 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
615
616 entry = msi_setup_entry(dev, nvec);
617 if (!entry)
618 return -ENOMEM;
619
620 /* All MSIs are unmasked by default, Mask them all */
621 mask = msi_mask(entry->msi_attrib.multi_cap);
622 msi_mask_irq(entry, mask, mask);
623
624 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
625
626 /* Configure MSI capability structure */
627 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
628 if (ret) {
629 msi_mask_irq(entry, mask, ~mask);
630 free_msi_irqs(dev);
631 return ret;
632 }
633
634 ret = msi_verify_entries(dev);
635 if (ret) {
636 msi_mask_irq(entry, mask, ~mask);
637 free_msi_irqs(dev);
638 return ret;
639 }
640
641 ret = populate_msi_sysfs(dev);
642 if (ret) {
643 msi_mask_irq(entry, mask, ~mask);
644 free_msi_irqs(dev);
645 return ret;
646 }
647
648 /* Set MSI enabled bits */
649 pci_intx_for_msi(dev, 0);
650 pci_msi_set_enable(dev, 1);
651 dev->msi_enabled = 1;
652
653 pcibios_free_irq(dev);
654 dev->irq = entry->irq;
655 return 0;
656}
657
658static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
659{
660 resource_size_t phys_addr;
661 u32 table_offset;
662 unsigned long flags;
663 u8 bir;
664
665 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
666 &table_offset);
667 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
668 flags = pci_resource_flags(dev, bir);
669 if (!flags || (flags & IORESOURCE_UNSET))
670 return NULL;
671
672 table_offset &= PCI_MSIX_TABLE_OFFSET;
673 phys_addr = pci_resource_start(dev, bir) + table_offset;
674
675 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
676}
677
678static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
679 struct msix_entry *entries, int nvec)
680{
681 struct msi_desc *entry;
682 int i;
683
684 for (i = 0; i < nvec; i++) {
685 entry = alloc_msi_entry(&dev->dev);
686 if (!entry) {
687 if (!i)
688 iounmap(base);
689 else
690 free_msi_irqs(dev);
691 /* No enough memory. Don't try again */
692 return -ENOMEM;
693 }
694
695 entry->msi_attrib.is_msix = 1;
696 entry->msi_attrib.is_64 = 1;
697 entry->msi_attrib.entry_nr = entries[i].entry;
698 entry->msi_attrib.default_irq = dev->irq;
699 entry->mask_base = base;
700 entry->nvec_used = 1;
701
702 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
703 }
704
705 return 0;
706}
707
708static void msix_program_entries(struct pci_dev *dev,
709 struct msix_entry *entries)
710{
711 struct msi_desc *entry;
712 int i = 0;
713
714 for_each_pci_msi_entry(entry, dev) {
715 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
716 PCI_MSIX_ENTRY_VECTOR_CTRL;
717
718 entries[i].vector = entry->irq;
719 entry->masked = readl(entry->mask_base + offset);
720 msix_mask_irq(entry, 1);
721 i++;
722 }
723}
724
725/**
726 * msix_capability_init - configure device's MSI-X capability
727 * @dev: pointer to the pci_dev data structure of MSI-X device function
728 * @entries: pointer to an array of struct msix_entry entries
729 * @nvec: number of @entries
730 *
731 * Setup the MSI-X capability structure of device function with a
732 * single MSI-X irq. A return of zero indicates the successful setup of
733 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
734 **/
735static int msix_capability_init(struct pci_dev *dev,
736 struct msix_entry *entries, int nvec)
737{
738 int ret;
739 u16 control;
740 void __iomem *base;
741
742 /* Ensure MSI-X is disabled while it is set up */
743 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
744
745 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
746 /* Request & Map MSI-X table region */
747 base = msix_map_region(dev, msix_table_size(control));
748 if (!base)
749 return -ENOMEM;
750
751 ret = msix_setup_entries(dev, base, entries, nvec);
752 if (ret)
753 return ret;
754
755 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
756 if (ret)
757 goto out_avail;
758
759 /* Check if all MSI entries honor device restrictions */
760 ret = msi_verify_entries(dev);
761 if (ret)
762 goto out_free;
763
764 /*
765 * Some devices require MSI-X to be enabled before we can touch the
766 * MSI-X registers. We need to mask all the vectors to prevent
767 * interrupts coming in before they're fully set up.
768 */
769 pci_msix_clear_and_set_ctrl(dev, 0,
770 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
771
772 msix_program_entries(dev, entries);
773
774 ret = populate_msi_sysfs(dev);
775 if (ret)
776 goto out_free;
777
778 /* Set MSI-X enabled bits and unmask the function */
779 pci_intx_for_msi(dev, 0);
780 dev->msix_enabled = 1;
781 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
782
783 pcibios_free_irq(dev);
784 return 0;
785
786out_avail:
787 if (ret < 0) {
788 /*
789 * If we had some success, report the number of irqs
790 * we succeeded in setting up.
791 */
792 struct msi_desc *entry;
793 int avail = 0;
794
795 for_each_pci_msi_entry(entry, dev) {
796 if (entry->irq != 0)
797 avail++;
798 }
799 if (avail != 0)
800 ret = avail;
801 }
802
803out_free:
804 free_msi_irqs(dev);
805
806 return ret;
807}
808
809/**
810 * pci_msi_supported - check whether MSI may be enabled on a device
811 * @dev: pointer to the pci_dev data structure of MSI device function
812 * @nvec: how many MSIs have been requested ?
813 *
814 * Look at global flags, the device itself, and its parent buses
815 * to determine if MSI/-X are supported for the device. If MSI/-X is
816 * supported return 1, else return 0.
817 **/
818static int pci_msi_supported(struct pci_dev *dev, int nvec)
819{
820 struct pci_bus *bus;
821
822 /* MSI must be globally enabled and supported by the device */
823 if (!pci_msi_enable)
824 return 0;
825
826 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
827 return 0;
828
829 /*
830 * You can't ask to have 0 or less MSIs configured.
831 * a) it's stupid ..
832 * b) the list manipulation code assumes nvec >= 1.
833 */
834 if (nvec < 1)
835 return 0;
836
837 /*
838 * Any bridge which does NOT route MSI transactions from its
839 * secondary bus to its primary bus must set NO_MSI flag on
840 * the secondary pci_bus.
841 * We expect only arch-specific PCI host bus controller driver
842 * or quirks for specific PCI bridges to be setting NO_MSI.
843 */
844 for (bus = dev->bus; bus; bus = bus->parent)
845 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
846 return 0;
847
848 return 1;
849}
850
851/**
852 * pci_msi_vec_count - Return the number of MSI vectors a device can send
853 * @dev: device to report about
854 *
855 * This function returns the number of MSI vectors a device requested via
856 * Multiple Message Capable register. It returns a negative errno if the
857 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
858 * and returns a power of two, up to a maximum of 2^5 (32), according to the
859 * MSI specification.
860 **/
861int pci_msi_vec_count(struct pci_dev *dev)
862{
863 int ret;
864 u16 msgctl;
865
866 if (!dev->msi_cap)
867 return -EINVAL;
868
869 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
870 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
871
872 return ret;
873}
874EXPORT_SYMBOL(pci_msi_vec_count);
875
876void pci_msi_shutdown(struct pci_dev *dev)
877{
878 struct msi_desc *desc;
879 u32 mask;
880
881 if (!pci_msi_enable || !dev || !dev->msi_enabled)
882 return;
883
884 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
885 desc = first_pci_msi_entry(dev);
886
887 pci_msi_set_enable(dev, 0);
888 pci_intx_for_msi(dev, 1);
889 dev->msi_enabled = 0;
890
891 /* Return the device with MSI unmasked as initial states */
892 mask = msi_mask(desc->msi_attrib.multi_cap);
893 /* Keep cached state to be restored */
894 __pci_msi_desc_mask_irq(desc, mask, ~mask);
895
896 /* Restore dev->irq to its default pin-assertion irq */
897 dev->irq = desc->msi_attrib.default_irq;
898 pcibios_alloc_irq(dev);
899}
900
901void pci_disable_msi(struct pci_dev *dev)
902{
903 if (!pci_msi_enable || !dev || !dev->msi_enabled)
904 return;
905
906 pci_msi_shutdown(dev);
907 free_msi_irqs(dev);
908}
909EXPORT_SYMBOL(pci_disable_msi);
910
911/**
912 * pci_msix_vec_count - return the number of device's MSI-X table entries
913 * @dev: pointer to the pci_dev data structure of MSI-X device function
914 * This function returns the number of device's MSI-X table entries and
915 * therefore the number of MSI-X vectors device is capable of sending.
916 * It returns a negative errno if the device is not capable of sending MSI-X
917 * interrupts.
918 **/
919int pci_msix_vec_count(struct pci_dev *dev)
920{
921 u16 control;
922
923 if (!dev->msix_cap)
924 return -EINVAL;
925
926 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
927 return msix_table_size(control);
928}
929EXPORT_SYMBOL(pci_msix_vec_count);
930
931/**
932 * pci_enable_msix - configure device's MSI-X capability structure
933 * @dev: pointer to the pci_dev data structure of MSI-X device function
934 * @entries: pointer to an array of MSI-X entries
935 * @nvec: number of MSI-X irqs requested for allocation by device driver
936 *
937 * Setup the MSI-X capability structure of device function with the number
938 * of requested irqs upon its software driver call to request for
939 * MSI-X mode enabled on its hardware device function. A return of zero
940 * indicates the successful configuration of MSI-X capability structure
941 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
942 * Or a return of > 0 indicates that driver request is exceeding the number
943 * of irqs or MSI-X vectors available. Driver should use the returned value to
944 * re-send its request.
945 **/
946int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
947{
948 int nr_entries;
949 int i, j;
950
951 if (!pci_msi_supported(dev, nvec))
952 return -EINVAL;
953
954 if (!entries)
955 return -EINVAL;
956
957 nr_entries = pci_msix_vec_count(dev);
958 if (nr_entries < 0)
959 return nr_entries;
960 if (nvec > nr_entries)
961 return nr_entries;
962
963 /* Check for any invalid entries */
964 for (i = 0; i < nvec; i++) {
965 if (entries[i].entry >= nr_entries)
966 return -EINVAL; /* invalid entry */
967 for (j = i + 1; j < nvec; j++) {
968 if (entries[i].entry == entries[j].entry)
969 return -EINVAL; /* duplicate entry */
970 }
971 }
972 WARN_ON(!!dev->msix_enabled);
973
974 /* Check whether driver already requested for MSI irq */
975 if (dev->msi_enabled) {
976 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
977 return -EINVAL;
978 }
979 return msix_capability_init(dev, entries, nvec);
980}
981EXPORT_SYMBOL(pci_enable_msix);
982
983void pci_msix_shutdown(struct pci_dev *dev)
984{
985 struct msi_desc *entry;
986
987 if (!pci_msi_enable || !dev || !dev->msix_enabled)
988 return;
989
990 /* Return the device with MSI-X masked as initial states */
991 for_each_pci_msi_entry(entry, dev) {
992 /* Keep cached states to be restored */
993 __pci_msix_desc_mask_irq(entry, 1);
994 }
995
996 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
997 pci_intx_for_msi(dev, 1);
998 dev->msix_enabled = 0;
999 pcibios_alloc_irq(dev);
1000}
1001
1002void pci_disable_msix(struct pci_dev *dev)
1003{
1004 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1005 return;
1006
1007 pci_msix_shutdown(dev);
1008 free_msi_irqs(dev);
1009}
1010EXPORT_SYMBOL(pci_disable_msix);
1011
1012void pci_no_msi(void)
1013{
1014 pci_msi_enable = 0;
1015}
1016
1017/**
1018 * pci_msi_enabled - is MSI enabled?
1019 *
1020 * Returns true if MSI has not been disabled by the command-line option
1021 * pci=nomsi.
1022 **/
1023int pci_msi_enabled(void)
1024{
1025 return pci_msi_enable;
1026}
1027EXPORT_SYMBOL(pci_msi_enabled);
1028
1029/**
1030 * pci_enable_msi_range - configure device's MSI capability structure
1031 * @dev: device to configure
1032 * @minvec: minimal number of interrupts to configure
1033 * @maxvec: maximum number of interrupts to configure
1034 *
1035 * This function tries to allocate a maximum possible number of interrupts in a
1036 * range between @minvec and @maxvec. It returns a negative errno if an error
1037 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1038 * and updates the @dev's irq member to the lowest new interrupt number;
1039 * the other interrupt numbers allocated to this device are consecutive.
1040 **/
1041int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1042{
1043 int nvec;
1044 int rc;
1045
1046 if (!pci_msi_supported(dev, minvec))
1047 return -EINVAL;
1048
1049 WARN_ON(!!dev->msi_enabled);
1050
1051 /* Check whether driver already requested MSI-X irqs */
1052 if (dev->msix_enabled) {
1053 dev_info(&dev->dev,
1054 "can't enable MSI (MSI-X already enabled)\n");
1055 return -EINVAL;
1056 }
1057
1058 if (maxvec < minvec)
1059 return -ERANGE;
1060
1061 nvec = pci_msi_vec_count(dev);
1062 if (nvec < 0)
1063 return nvec;
1064 else if (nvec < minvec)
1065 return -EINVAL;
1066 else if (nvec > maxvec)
1067 nvec = maxvec;
1068
1069 do {
1070 rc = msi_capability_init(dev, nvec);
1071 if (rc < 0) {
1072 return rc;
1073 } else if (rc > 0) {
1074 if (rc < minvec)
1075 return -ENOSPC;
1076 nvec = rc;
1077 }
1078 } while (rc);
1079
1080 return nvec;
1081}
1082EXPORT_SYMBOL(pci_enable_msi_range);
1083
1084/**
1085 * pci_enable_msix_range - configure device's MSI-X capability structure
1086 * @dev: pointer to the pci_dev data structure of MSI-X device function
1087 * @entries: pointer to an array of MSI-X entries
1088 * @minvec: minimum number of MSI-X irqs requested
1089 * @maxvec: maximum number of MSI-X irqs requested
1090 *
1091 * Setup the MSI-X capability structure of device function with a maximum
1092 * possible number of interrupts in the range between @minvec and @maxvec
1093 * upon its software driver call to request for MSI-X mode enabled on its
1094 * hardware device function. It returns a negative errno if an error occurs.
1095 * If it succeeds, it returns the actual number of interrupts allocated and
1096 * indicates the successful configuration of MSI-X capability structure
1097 * with new allocated MSI-X interrupts.
1098 **/
1099int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1100 int minvec, int maxvec)
1101{
1102 int nvec = maxvec;
1103 int rc;
1104
1105 if (maxvec < minvec)
1106 return -ERANGE;
1107
1108 do {
1109 rc = pci_enable_msix(dev, entries, nvec);
1110 if (rc < 0) {
1111 return rc;
1112 } else if (rc > 0) {
1113 if (rc < minvec)
1114 return -ENOSPC;
1115 nvec = rc;
1116 }
1117 } while (rc);
1118
1119 return nvec;
1120}
1121EXPORT_SYMBOL(pci_enable_msix_range);
1122
1123struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1124{
1125 return to_pci_dev(desc->dev);
1126}
1127EXPORT_SYMBOL(msi_desc_to_pci_dev);
1128
1129void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1130{
1131 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1132
1133 return dev->bus->sysdata;
1134}
1135EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1136
1137#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1138/**
1139 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1140 * @irq_data: Pointer to interrupt data of the MSI interrupt
1141 * @msg: Pointer to the message
1142 */
1143void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1144{
1145 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1146
1147 /*
1148 * For MSI-X desc->irq is always equal to irq_data->irq. For
1149 * MSI only the first interrupt of MULTI MSI passes the test.
1150 */
1151 if (desc->irq == irq_data->irq)
1152 __pci_write_msi_msg(desc, msg);
1153}
1154
1155/**
1156 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1157 * @dev: Pointer to the PCI device
1158 * @desc: Pointer to the msi descriptor
1159 *
1160 * The ID number is only used within the irqdomain.
1161 */
1162irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1163 struct msi_desc *desc)
1164{
1165 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1166 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1167 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1168}
1169
1170static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1171{
1172 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1173}
1174
1175/**
1176 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1177 * @domain: The interrupt domain to check
1178 * @info: The domain info for verification
1179 * @dev: The device to check
1180 *
1181 * Returns:
1182 * 0 if the functionality is supported
1183 * 1 if Multi MSI is requested, but the domain does not support it
1184 * -ENOTSUPP otherwise
1185 */
1186int pci_msi_domain_check_cap(struct irq_domain *domain,
1187 struct msi_domain_info *info, struct device *dev)
1188{
1189 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1190
1191 /* Special handling to support pci_enable_msi_range() */
1192 if (pci_msi_desc_is_multi_msi(desc) &&
1193 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1194 return 1;
1195 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1196 return -ENOTSUPP;
1197
1198 return 0;
1199}
1200
1201static int pci_msi_domain_handle_error(struct irq_domain *domain,
1202 struct msi_desc *desc, int error)
1203{
1204 /* Special handling to support pci_enable_msi_range() */
1205 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1206 return 1;
1207
1208 return error;
1209}
1210
1211#ifdef GENERIC_MSI_DOMAIN_OPS
1212static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1213 struct msi_desc *desc)
1214{
1215 arg->desc = desc;
1216 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1217 desc);
1218}
1219#else
1220#define pci_msi_domain_set_desc NULL
1221#endif
1222
1223static struct msi_domain_ops pci_msi_domain_ops_default = {
1224 .set_desc = pci_msi_domain_set_desc,
1225 .msi_check = pci_msi_domain_check_cap,
1226 .handle_error = pci_msi_domain_handle_error,
1227};
1228
1229static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1230{
1231 struct msi_domain_ops *ops = info->ops;
1232
1233 if (ops == NULL) {
1234 info->ops = &pci_msi_domain_ops_default;
1235 } else {
1236 if (ops->set_desc == NULL)
1237 ops->set_desc = pci_msi_domain_set_desc;
1238 if (ops->msi_check == NULL)
1239 ops->msi_check = pci_msi_domain_check_cap;
1240 if (ops->handle_error == NULL)
1241 ops->handle_error = pci_msi_domain_handle_error;
1242 }
1243}
1244
1245static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1246{
1247 struct irq_chip *chip = info->chip;
1248
1249 BUG_ON(!chip);
1250 if (!chip->irq_write_msi_msg)
1251 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1252 if (!chip->irq_mask)
1253 chip->irq_mask = pci_msi_mask_irq;
1254 if (!chip->irq_unmask)
1255 chip->irq_unmask = pci_msi_unmask_irq;
1256}
1257
1258/**
1259 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1260 * @fwnode: Optional fwnode of the interrupt controller
1261 * @info: MSI domain info
1262 * @parent: Parent irq domain
1263 *
1264 * Updates the domain and chip ops and creates a MSI interrupt domain.
1265 *
1266 * Returns:
1267 * A domain pointer or NULL in case of failure.
1268 */
1269struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1270 struct msi_domain_info *info,
1271 struct irq_domain *parent)
1272{
1273 struct irq_domain *domain;
1274
1275 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1276 pci_msi_domain_update_dom_ops(info);
1277 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1278 pci_msi_domain_update_chip_ops(info);
1279
1280 domain = msi_create_irq_domain(fwnode, info, parent);
1281 if (!domain)
1282 return NULL;
1283
1284 domain->bus_token = DOMAIN_BUS_PCI_MSI;
1285 return domain;
1286}
1287EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1288
1289/**
1290 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1291 * @domain: The interrupt domain to allocate from
1292 * @dev: The device for which to allocate
1293 * @nvec: The number of interrupts to allocate
1294 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1295 *
1296 * Returns:
1297 * A virtual interrupt number or an error code in case of failure
1298 */
1299int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1300 int nvec, int type)
1301{
1302 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1303}
1304
1305/**
1306 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1307 * @domain: The interrupt domain
1308 * @dev: The device for which to free interrupts
1309 */
1310void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1311{
1312 msi_domain_free_irqs(domain, &dev->dev);
1313}
1314
1315/**
1316 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1317 * @fwnode: Optional fwnode of the interrupt controller
1318 * @info: MSI domain info
1319 * @parent: Parent irq domain
1320 *
1321 * Returns: A domain pointer or NULL in case of failure. If successful
1322 * the default PCI/MSI irqdomain pointer is updated.
1323 */
1324struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
1325 struct msi_domain_info *info, struct irq_domain *parent)
1326{
1327 struct irq_domain *domain;
1328
1329 mutex_lock(&pci_msi_domain_lock);
1330 if (pci_msi_default_domain) {
1331 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1332 domain = NULL;
1333 } else {
1334 domain = pci_msi_create_irq_domain(fwnode, info, parent);
1335 pci_msi_default_domain = domain;
1336 }
1337 mutex_unlock(&pci_msi_domain_lock);
1338
1339 return domain;
1340}
1341
1342static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1343{
1344 u32 *pa = data;
1345
1346 *pa = alias;
1347 return 0;
1348}
1349/**
1350 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1351 * @domain: The interrupt domain
1352 * @pdev: The PCI device.
1353 *
1354 * The RID for a device is formed from the alias, with a firmware
1355 * supplied mapping applied
1356 *
1357 * Returns: The RID.
1358 */
1359u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1360{
1361 struct device_node *of_node;
1362 u32 rid = 0;
1363
1364 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1365
1366 of_node = irq_domain_get_of_node(domain);
1367 if (of_node)
1368 rid = of_msi_map_rid(&pdev->dev, of_node, rid);
1369
1370 return rid;
1371}
1372
1373/**
1374 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1375 * @pdev: The PCI device
1376 *
1377 * Use the firmware data to find a device-specific MSI domain
1378 * (i.e. not one that is ste as a default).
1379 *
1380 * Returns: The coresponding MSI domain or NULL if none has been found.
1381 */
1382struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1383{
1384 u32 rid = 0;
1385
1386 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1387 return of_msi_map_get_device_domain(&pdev->dev, rid);
1388}
1389#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
1/*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
8 */
9
10#include <linux/err.h>
11#include <linux/mm.h>
12#include <linux/irq.h>
13#include <linux/interrupt.h>
14#include <linux/export.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18#include <linux/msi.h>
19#include <linux/smp.h>
20#include <linux/errno.h>
21#include <linux/io.h>
22#include <linux/acpi_iort.h>
23#include <linux/slab.h>
24#include <linux/irqdomain.h>
25#include <linux/of_irq.h>
26
27#include "pci.h"
28
29static int pci_msi_enable = 1;
30int pci_msi_ignore_mask;
31
32#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33
34#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
35static struct irq_domain *pci_msi_default_domain;
36static DEFINE_MUTEX(pci_msi_domain_lock);
37
38struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
39{
40 return pci_msi_default_domain;
41}
42
43static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
44{
45 struct irq_domain *domain;
46
47 domain = dev_get_msi_domain(&dev->dev);
48 if (domain)
49 return domain;
50
51 return arch_get_pci_msi_domain(dev);
52}
53
54static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
55{
56 struct irq_domain *domain;
57
58 domain = pci_msi_get_domain(dev);
59 if (domain && irq_domain_is_hierarchy(domain))
60 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
61
62 return arch_setup_msi_irqs(dev, nvec, type);
63}
64
65static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
66{
67 struct irq_domain *domain;
68
69 domain = pci_msi_get_domain(dev);
70 if (domain && irq_domain_is_hierarchy(domain))
71 pci_msi_domain_free_irqs(domain, dev);
72 else
73 arch_teardown_msi_irqs(dev);
74}
75#else
76#define pci_msi_setup_msi_irqs arch_setup_msi_irqs
77#define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
78#endif
79
80/* Arch hooks */
81
82int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
83{
84 struct msi_controller *chip = dev->bus->msi;
85 int err;
86
87 if (!chip || !chip->setup_irq)
88 return -EINVAL;
89
90 err = chip->setup_irq(chip, dev, desc);
91 if (err < 0)
92 return err;
93
94 irq_set_chip_data(desc->irq, chip);
95
96 return 0;
97}
98
99void __weak arch_teardown_msi_irq(unsigned int irq)
100{
101 struct msi_controller *chip = irq_get_chip_data(irq);
102
103 if (!chip || !chip->teardown_irq)
104 return;
105
106 chip->teardown_irq(chip, irq);
107}
108
109int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
110{
111 struct msi_controller *chip = dev->bus->msi;
112 struct msi_desc *entry;
113 int ret;
114
115 if (chip && chip->setup_irqs)
116 return chip->setup_irqs(chip, dev, nvec, type);
117 /*
118 * If an architecture wants to support multiple MSI, it needs to
119 * override arch_setup_msi_irqs()
120 */
121 if (type == PCI_CAP_ID_MSI && nvec > 1)
122 return 1;
123
124 for_each_pci_msi_entry(entry, dev) {
125 ret = arch_setup_msi_irq(dev, entry);
126 if (ret < 0)
127 return ret;
128 if (ret > 0)
129 return -ENOSPC;
130 }
131
132 return 0;
133}
134
135/*
136 * We have a default implementation available as a separate non-weak
137 * function, as it is used by the Xen x86 PCI code
138 */
139void default_teardown_msi_irqs(struct pci_dev *dev)
140{
141 int i;
142 struct msi_desc *entry;
143
144 for_each_pci_msi_entry(entry, dev)
145 if (entry->irq)
146 for (i = 0; i < entry->nvec_used; i++)
147 arch_teardown_msi_irq(entry->irq + i);
148}
149
150void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
151{
152 return default_teardown_msi_irqs(dev);
153}
154
155static void default_restore_msi_irq(struct pci_dev *dev, int irq)
156{
157 struct msi_desc *entry;
158
159 entry = NULL;
160 if (dev->msix_enabled) {
161 for_each_pci_msi_entry(entry, dev) {
162 if (irq == entry->irq)
163 break;
164 }
165 } else if (dev->msi_enabled) {
166 entry = irq_get_msi_desc(irq);
167 }
168
169 if (entry)
170 __pci_write_msi_msg(entry, &entry->msg);
171}
172
173void __weak arch_restore_msi_irqs(struct pci_dev *dev)
174{
175 return default_restore_msi_irqs(dev);
176}
177
178static inline __attribute_const__ u32 msi_mask(unsigned x)
179{
180 /* Don't shift by >= width of type */
181 if (x >= 5)
182 return 0xffffffff;
183 return (1 << (1 << x)) - 1;
184}
185
186/*
187 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
188 * mask all MSI interrupts by clearing the MSI enable bit does not work
189 * reliably as devices without an INTx disable bit will then generate a
190 * level IRQ which will never be cleared.
191 */
192u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
193{
194 u32 mask_bits = desc->masked;
195
196 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
197 return 0;
198
199 mask_bits &= ~mask;
200 mask_bits |= flag;
201 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
202 mask_bits);
203
204 return mask_bits;
205}
206
207static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
208{
209 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
210}
211
212static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
213{
214 return desc->mask_base +
215 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
216}
217
218/*
219 * This internal function does not flush PCI writes to the device.
220 * All users must ensure that they read from the device before either
221 * assuming that the device state is up to date, or returning out of this
222 * file. This saves a few milliseconds when initialising devices with lots
223 * of MSI-X interrupts.
224 */
225u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
226{
227 u32 mask_bits = desc->masked;
228
229 if (pci_msi_ignore_mask)
230 return 0;
231
232 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
233 if (flag)
234 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
235 writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL);
236
237 return mask_bits;
238}
239
240static void msix_mask_irq(struct msi_desc *desc, u32 flag)
241{
242 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
243}
244
245static void msi_set_mask_bit(struct irq_data *data, u32 flag)
246{
247 struct msi_desc *desc = irq_data_get_msi_desc(data);
248
249 if (desc->msi_attrib.is_msix) {
250 msix_mask_irq(desc, flag);
251 readl(desc->mask_base); /* Flush write to device */
252 } else {
253 unsigned offset = data->irq - desc->irq;
254 msi_mask_irq(desc, 1 << offset, flag << offset);
255 }
256}
257
258/**
259 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
260 * @data: pointer to irqdata associated to that interrupt
261 */
262void pci_msi_mask_irq(struct irq_data *data)
263{
264 msi_set_mask_bit(data, 1);
265}
266EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
267
268/**
269 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
270 * @data: pointer to irqdata associated to that interrupt
271 */
272void pci_msi_unmask_irq(struct irq_data *data)
273{
274 msi_set_mask_bit(data, 0);
275}
276EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
277
278void default_restore_msi_irqs(struct pci_dev *dev)
279{
280 struct msi_desc *entry;
281
282 for_each_pci_msi_entry(entry, dev)
283 default_restore_msi_irq(dev, entry->irq);
284}
285
286void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
287{
288 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
289
290 BUG_ON(dev->current_state != PCI_D0);
291
292 if (entry->msi_attrib.is_msix) {
293 void __iomem *base = pci_msix_desc_addr(entry);
294
295 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
296 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
297 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
298 } else {
299 int pos = dev->msi_cap;
300 u16 data;
301
302 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
303 &msg->address_lo);
304 if (entry->msi_attrib.is_64) {
305 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
306 &msg->address_hi);
307 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
308 } else {
309 msg->address_hi = 0;
310 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
311 }
312 msg->data = data;
313 }
314}
315
316void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
317{
318 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
319
320 if (dev->current_state != PCI_D0) {
321 /* Don't touch the hardware now */
322 } else if (entry->msi_attrib.is_msix) {
323 void __iomem *base = pci_msix_desc_addr(entry);
324
325 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
326 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
327 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
328 } else {
329 int pos = dev->msi_cap;
330 u16 msgctl;
331
332 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
333 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
334 msgctl |= entry->msi_attrib.multiple << 4;
335 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
336
337 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
338 msg->address_lo);
339 if (entry->msi_attrib.is_64) {
340 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
341 msg->address_hi);
342 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
343 msg->data);
344 } else {
345 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
346 msg->data);
347 }
348 }
349 entry->msg = *msg;
350}
351
352void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
353{
354 struct msi_desc *entry = irq_get_msi_desc(irq);
355
356 __pci_write_msi_msg(entry, msg);
357}
358EXPORT_SYMBOL_GPL(pci_write_msi_msg);
359
360static void free_msi_irqs(struct pci_dev *dev)
361{
362 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
363 struct msi_desc *entry, *tmp;
364 struct attribute **msi_attrs;
365 struct device_attribute *dev_attr;
366 int i, count = 0;
367
368 for_each_pci_msi_entry(entry, dev)
369 if (entry->irq)
370 for (i = 0; i < entry->nvec_used; i++)
371 BUG_ON(irq_has_action(entry->irq + i));
372
373 pci_msi_teardown_msi_irqs(dev);
374
375 list_for_each_entry_safe(entry, tmp, msi_list, list) {
376 if (entry->msi_attrib.is_msix) {
377 if (list_is_last(&entry->list, msi_list))
378 iounmap(entry->mask_base);
379 }
380
381 list_del(&entry->list);
382 kfree(entry);
383 }
384
385 if (dev->msi_irq_groups) {
386 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
387 msi_attrs = dev->msi_irq_groups[0]->attrs;
388 while (msi_attrs[count]) {
389 dev_attr = container_of(msi_attrs[count],
390 struct device_attribute, attr);
391 kfree(dev_attr->attr.name);
392 kfree(dev_attr);
393 ++count;
394 }
395 kfree(msi_attrs);
396 kfree(dev->msi_irq_groups[0]);
397 kfree(dev->msi_irq_groups);
398 dev->msi_irq_groups = NULL;
399 }
400}
401
402static void pci_intx_for_msi(struct pci_dev *dev, int enable)
403{
404 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
405 pci_intx(dev, enable);
406}
407
408static void __pci_restore_msi_state(struct pci_dev *dev)
409{
410 u16 control;
411 struct msi_desc *entry;
412
413 if (!dev->msi_enabled)
414 return;
415
416 entry = irq_get_msi_desc(dev->irq);
417
418 pci_intx_for_msi(dev, 0);
419 pci_msi_set_enable(dev, 0);
420 arch_restore_msi_irqs(dev);
421
422 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
423 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
424 entry->masked);
425 control &= ~PCI_MSI_FLAGS_QSIZE;
426 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
427 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
428}
429
430static void __pci_restore_msix_state(struct pci_dev *dev)
431{
432 struct msi_desc *entry;
433
434 if (!dev->msix_enabled)
435 return;
436 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
437
438 /* route the table */
439 pci_intx_for_msi(dev, 0);
440 pci_msix_clear_and_set_ctrl(dev, 0,
441 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
442
443 arch_restore_msi_irqs(dev);
444 for_each_pci_msi_entry(entry, dev)
445 msix_mask_irq(entry, entry->masked);
446
447 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
448}
449
450void pci_restore_msi_state(struct pci_dev *dev)
451{
452 __pci_restore_msi_state(dev);
453 __pci_restore_msix_state(dev);
454}
455EXPORT_SYMBOL_GPL(pci_restore_msi_state);
456
457static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
458 char *buf)
459{
460 struct msi_desc *entry;
461 unsigned long irq;
462 int retval;
463
464 retval = kstrtoul(attr->attr.name, 10, &irq);
465 if (retval)
466 return retval;
467
468 entry = irq_get_msi_desc(irq);
469 if (entry)
470 return sprintf(buf, "%s\n",
471 entry->msi_attrib.is_msix ? "msix" : "msi");
472
473 return -ENODEV;
474}
475
476static int populate_msi_sysfs(struct pci_dev *pdev)
477{
478 struct attribute **msi_attrs;
479 struct attribute *msi_attr;
480 struct device_attribute *msi_dev_attr;
481 struct attribute_group *msi_irq_group;
482 const struct attribute_group **msi_irq_groups;
483 struct msi_desc *entry;
484 int ret = -ENOMEM;
485 int num_msi = 0;
486 int count = 0;
487 int i;
488
489 /* Determine how many msi entries we have */
490 for_each_pci_msi_entry(entry, pdev)
491 num_msi += entry->nvec_used;
492 if (!num_msi)
493 return 0;
494
495 /* Dynamically create the MSI attributes for the PCI device */
496 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
497 if (!msi_attrs)
498 return -ENOMEM;
499 for_each_pci_msi_entry(entry, pdev) {
500 for (i = 0; i < entry->nvec_used; i++) {
501 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
502 if (!msi_dev_attr)
503 goto error_attrs;
504 msi_attrs[count] = &msi_dev_attr->attr;
505
506 sysfs_attr_init(&msi_dev_attr->attr);
507 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
508 entry->irq + i);
509 if (!msi_dev_attr->attr.name)
510 goto error_attrs;
511 msi_dev_attr->attr.mode = S_IRUGO;
512 msi_dev_attr->show = msi_mode_show;
513 ++count;
514 }
515 }
516
517 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
518 if (!msi_irq_group)
519 goto error_attrs;
520 msi_irq_group->name = "msi_irqs";
521 msi_irq_group->attrs = msi_attrs;
522
523 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
524 if (!msi_irq_groups)
525 goto error_irq_group;
526 msi_irq_groups[0] = msi_irq_group;
527
528 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
529 if (ret)
530 goto error_irq_groups;
531 pdev->msi_irq_groups = msi_irq_groups;
532
533 return 0;
534
535error_irq_groups:
536 kfree(msi_irq_groups);
537error_irq_group:
538 kfree(msi_irq_group);
539error_attrs:
540 count = 0;
541 msi_attr = msi_attrs[count];
542 while (msi_attr) {
543 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
544 kfree(msi_attr->name);
545 kfree(msi_dev_attr);
546 ++count;
547 msi_attr = msi_attrs[count];
548 }
549 kfree(msi_attrs);
550 return ret;
551}
552
553static struct msi_desc *
554msi_setup_entry(struct pci_dev *dev, int nvec, const struct irq_affinity *affd)
555{
556 struct cpumask *masks = NULL;
557 struct msi_desc *entry;
558 u16 control;
559
560 if (affd) {
561 masks = irq_create_affinity_masks(nvec, affd);
562 if (!masks)
563 pr_err("Unable to allocate affinity masks, ignoring\n");
564 }
565
566 /* MSI Entry Initialization */
567 entry = alloc_msi_entry(&dev->dev, nvec, masks);
568 if (!entry)
569 goto out;
570
571 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
572
573 entry->msi_attrib.is_msix = 0;
574 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
575 entry->msi_attrib.entry_nr = 0;
576 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
577 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
578 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
579 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
580
581 if (control & PCI_MSI_FLAGS_64BIT)
582 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
583 else
584 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
585
586 /* Save the initial mask status */
587 if (entry->msi_attrib.maskbit)
588 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
589
590out:
591 kfree(masks);
592 return entry;
593}
594
595static int msi_verify_entries(struct pci_dev *dev)
596{
597 struct msi_desc *entry;
598
599 for_each_pci_msi_entry(entry, dev) {
600 if (!dev->no_64bit_msi || !entry->msg.address_hi)
601 continue;
602 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
603 " tried to assign one above 4G\n");
604 return -EIO;
605 }
606 return 0;
607}
608
609/**
610 * msi_capability_init - configure device's MSI capability structure
611 * @dev: pointer to the pci_dev data structure of MSI device function
612 * @nvec: number of interrupts to allocate
613 * @affinity: flag to indicate cpu irq affinity mask should be set
614 *
615 * Setup the MSI capability structure of the device with the requested
616 * number of interrupts. A return value of zero indicates the successful
617 * setup of an entry with the new MSI irq. A negative return value indicates
618 * an error, and a positive return value indicates the number of interrupts
619 * which could have been allocated.
620 */
621static int msi_capability_init(struct pci_dev *dev, int nvec,
622 const struct irq_affinity *affd)
623{
624 struct msi_desc *entry;
625 int ret;
626 unsigned mask;
627
628 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
629
630 entry = msi_setup_entry(dev, nvec, affd);
631 if (!entry)
632 return -ENOMEM;
633
634 /* All MSIs are unmasked by default, Mask them all */
635 mask = msi_mask(entry->msi_attrib.multi_cap);
636 msi_mask_irq(entry, mask, mask);
637
638 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
639
640 /* Configure MSI capability structure */
641 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
642 if (ret) {
643 msi_mask_irq(entry, mask, ~mask);
644 free_msi_irqs(dev);
645 return ret;
646 }
647
648 ret = msi_verify_entries(dev);
649 if (ret) {
650 msi_mask_irq(entry, mask, ~mask);
651 free_msi_irqs(dev);
652 return ret;
653 }
654
655 ret = populate_msi_sysfs(dev);
656 if (ret) {
657 msi_mask_irq(entry, mask, ~mask);
658 free_msi_irqs(dev);
659 return ret;
660 }
661
662 /* Set MSI enabled bits */
663 pci_intx_for_msi(dev, 0);
664 pci_msi_set_enable(dev, 1);
665 dev->msi_enabled = 1;
666
667 pcibios_free_irq(dev);
668 dev->irq = entry->irq;
669 return 0;
670}
671
672static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
673{
674 resource_size_t phys_addr;
675 u32 table_offset;
676 unsigned long flags;
677 u8 bir;
678
679 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
680 &table_offset);
681 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
682 flags = pci_resource_flags(dev, bir);
683 if (!flags || (flags & IORESOURCE_UNSET))
684 return NULL;
685
686 table_offset &= PCI_MSIX_TABLE_OFFSET;
687 phys_addr = pci_resource_start(dev, bir) + table_offset;
688
689 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
690}
691
692static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
693 struct msix_entry *entries, int nvec,
694 const struct irq_affinity *affd)
695{
696 struct cpumask *curmsk, *masks = NULL;
697 struct msi_desc *entry;
698 int ret, i;
699
700 if (affd) {
701 masks = irq_create_affinity_masks(nvec, affd);
702 if (!masks)
703 pr_err("Unable to allocate affinity masks, ignoring\n");
704 }
705
706 for (i = 0, curmsk = masks; i < nvec; i++) {
707 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
708 if (!entry) {
709 if (!i)
710 iounmap(base);
711 else
712 free_msi_irqs(dev);
713 /* No enough memory. Don't try again */
714 ret = -ENOMEM;
715 goto out;
716 }
717
718 entry->msi_attrib.is_msix = 1;
719 entry->msi_attrib.is_64 = 1;
720 if (entries)
721 entry->msi_attrib.entry_nr = entries[i].entry;
722 else
723 entry->msi_attrib.entry_nr = i;
724 entry->msi_attrib.default_irq = dev->irq;
725 entry->mask_base = base;
726
727 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
728 if (masks)
729 curmsk++;
730 }
731 ret = 0;
732out:
733 kfree(masks);
734 return 0;
735}
736
737static void msix_program_entries(struct pci_dev *dev,
738 struct msix_entry *entries)
739{
740 struct msi_desc *entry;
741 int i = 0;
742
743 for_each_pci_msi_entry(entry, dev) {
744 if (entries)
745 entries[i++].vector = entry->irq;
746 entry->masked = readl(pci_msix_desc_addr(entry) +
747 PCI_MSIX_ENTRY_VECTOR_CTRL);
748 msix_mask_irq(entry, 1);
749 }
750}
751
752/**
753 * msix_capability_init - configure device's MSI-X capability
754 * @dev: pointer to the pci_dev data structure of MSI-X device function
755 * @entries: pointer to an array of struct msix_entry entries
756 * @nvec: number of @entries
757 * @affd: Optional pointer to enable automatic affinity assignement
758 *
759 * Setup the MSI-X capability structure of device function with a
760 * single MSI-X irq. A return of zero indicates the successful setup of
761 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
762 **/
763static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
764 int nvec, const struct irq_affinity *affd)
765{
766 int ret;
767 u16 control;
768 void __iomem *base;
769
770 /* Ensure MSI-X is disabled while it is set up */
771 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
772
773 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
774 /* Request & Map MSI-X table region */
775 base = msix_map_region(dev, msix_table_size(control));
776 if (!base)
777 return -ENOMEM;
778
779 ret = msix_setup_entries(dev, base, entries, nvec, affd);
780 if (ret)
781 return ret;
782
783 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
784 if (ret)
785 goto out_avail;
786
787 /* Check if all MSI entries honor device restrictions */
788 ret = msi_verify_entries(dev);
789 if (ret)
790 goto out_free;
791
792 /*
793 * Some devices require MSI-X to be enabled before we can touch the
794 * MSI-X registers. We need to mask all the vectors to prevent
795 * interrupts coming in before they're fully set up.
796 */
797 pci_msix_clear_and_set_ctrl(dev, 0,
798 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
799
800 msix_program_entries(dev, entries);
801
802 ret = populate_msi_sysfs(dev);
803 if (ret)
804 goto out_free;
805
806 /* Set MSI-X enabled bits and unmask the function */
807 pci_intx_for_msi(dev, 0);
808 dev->msix_enabled = 1;
809 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
810
811 pcibios_free_irq(dev);
812 return 0;
813
814out_avail:
815 if (ret < 0) {
816 /*
817 * If we had some success, report the number of irqs
818 * we succeeded in setting up.
819 */
820 struct msi_desc *entry;
821 int avail = 0;
822
823 for_each_pci_msi_entry(entry, dev) {
824 if (entry->irq != 0)
825 avail++;
826 }
827 if (avail != 0)
828 ret = avail;
829 }
830
831out_free:
832 free_msi_irqs(dev);
833
834 return ret;
835}
836
837/**
838 * pci_msi_supported - check whether MSI may be enabled on a device
839 * @dev: pointer to the pci_dev data structure of MSI device function
840 * @nvec: how many MSIs have been requested ?
841 *
842 * Look at global flags, the device itself, and its parent buses
843 * to determine if MSI/-X are supported for the device. If MSI/-X is
844 * supported return 1, else return 0.
845 **/
846static int pci_msi_supported(struct pci_dev *dev, int nvec)
847{
848 struct pci_bus *bus;
849
850 /* MSI must be globally enabled and supported by the device */
851 if (!pci_msi_enable)
852 return 0;
853
854 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
855 return 0;
856
857 /*
858 * You can't ask to have 0 or less MSIs configured.
859 * a) it's stupid ..
860 * b) the list manipulation code assumes nvec >= 1.
861 */
862 if (nvec < 1)
863 return 0;
864
865 /*
866 * Any bridge which does NOT route MSI transactions from its
867 * secondary bus to its primary bus must set NO_MSI flag on
868 * the secondary pci_bus.
869 * We expect only arch-specific PCI host bus controller driver
870 * or quirks for specific PCI bridges to be setting NO_MSI.
871 */
872 for (bus = dev->bus; bus; bus = bus->parent)
873 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
874 return 0;
875
876 return 1;
877}
878
879/**
880 * pci_msi_vec_count - Return the number of MSI vectors a device can send
881 * @dev: device to report about
882 *
883 * This function returns the number of MSI vectors a device requested via
884 * Multiple Message Capable register. It returns a negative errno if the
885 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
886 * and returns a power of two, up to a maximum of 2^5 (32), according to the
887 * MSI specification.
888 **/
889int pci_msi_vec_count(struct pci_dev *dev)
890{
891 int ret;
892 u16 msgctl;
893
894 if (!dev->msi_cap)
895 return -EINVAL;
896
897 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
898 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
899
900 return ret;
901}
902EXPORT_SYMBOL(pci_msi_vec_count);
903
904void pci_msi_shutdown(struct pci_dev *dev)
905{
906 struct msi_desc *desc;
907 u32 mask;
908
909 if (!pci_msi_enable || !dev || !dev->msi_enabled)
910 return;
911
912 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
913 desc = first_pci_msi_entry(dev);
914
915 pci_msi_set_enable(dev, 0);
916 pci_intx_for_msi(dev, 1);
917 dev->msi_enabled = 0;
918
919 /* Return the device with MSI unmasked as initial states */
920 mask = msi_mask(desc->msi_attrib.multi_cap);
921 /* Keep cached state to be restored */
922 __pci_msi_desc_mask_irq(desc, mask, ~mask);
923
924 /* Restore dev->irq to its default pin-assertion irq */
925 dev->irq = desc->msi_attrib.default_irq;
926 pcibios_alloc_irq(dev);
927}
928
929void pci_disable_msi(struct pci_dev *dev)
930{
931 if (!pci_msi_enable || !dev || !dev->msi_enabled)
932 return;
933
934 pci_msi_shutdown(dev);
935 free_msi_irqs(dev);
936}
937EXPORT_SYMBOL(pci_disable_msi);
938
939/**
940 * pci_msix_vec_count - return the number of device's MSI-X table entries
941 * @dev: pointer to the pci_dev data structure of MSI-X device function
942 * This function returns the number of device's MSI-X table entries and
943 * therefore the number of MSI-X vectors device is capable of sending.
944 * It returns a negative errno if the device is not capable of sending MSI-X
945 * interrupts.
946 **/
947int pci_msix_vec_count(struct pci_dev *dev)
948{
949 u16 control;
950
951 if (!dev->msix_cap)
952 return -EINVAL;
953
954 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
955 return msix_table_size(control);
956}
957EXPORT_SYMBOL(pci_msix_vec_count);
958
959static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
960 int nvec, const struct irq_affinity *affd)
961{
962 int nr_entries;
963 int i, j;
964
965 if (!pci_msi_supported(dev, nvec))
966 return -EINVAL;
967
968 nr_entries = pci_msix_vec_count(dev);
969 if (nr_entries < 0)
970 return nr_entries;
971 if (nvec > nr_entries)
972 return nr_entries;
973
974 if (entries) {
975 /* Check for any invalid entries */
976 for (i = 0; i < nvec; i++) {
977 if (entries[i].entry >= nr_entries)
978 return -EINVAL; /* invalid entry */
979 for (j = i + 1; j < nvec; j++) {
980 if (entries[i].entry == entries[j].entry)
981 return -EINVAL; /* duplicate entry */
982 }
983 }
984 }
985 WARN_ON(!!dev->msix_enabled);
986
987 /* Check whether driver already requested for MSI irq */
988 if (dev->msi_enabled) {
989 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
990 return -EINVAL;
991 }
992 return msix_capability_init(dev, entries, nvec, affd);
993}
994
995/**
996 * pci_enable_msix - configure device's MSI-X capability structure
997 * @dev: pointer to the pci_dev data structure of MSI-X device function
998 * @entries: pointer to an array of MSI-X entries (optional)
999 * @nvec: number of MSI-X irqs requested for allocation by device driver
1000 *
1001 * Setup the MSI-X capability structure of device function with the number
1002 * of requested irqs upon its software driver call to request for
1003 * MSI-X mode enabled on its hardware device function. A return of zero
1004 * indicates the successful configuration of MSI-X capability structure
1005 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
1006 * Or a return of > 0 indicates that driver request is exceeding the number
1007 * of irqs or MSI-X vectors available. Driver should use the returned value to
1008 * re-send its request.
1009 **/
1010int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
1011{
1012 return __pci_enable_msix(dev, entries, nvec, NULL);
1013}
1014EXPORT_SYMBOL(pci_enable_msix);
1015
1016void pci_msix_shutdown(struct pci_dev *dev)
1017{
1018 struct msi_desc *entry;
1019
1020 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1021 return;
1022
1023 /* Return the device with MSI-X masked as initial states */
1024 for_each_pci_msi_entry(entry, dev) {
1025 /* Keep cached states to be restored */
1026 __pci_msix_desc_mask_irq(entry, 1);
1027 }
1028
1029 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1030 pci_intx_for_msi(dev, 1);
1031 dev->msix_enabled = 0;
1032 pcibios_alloc_irq(dev);
1033}
1034
1035void pci_disable_msix(struct pci_dev *dev)
1036{
1037 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1038 return;
1039
1040 pci_msix_shutdown(dev);
1041 free_msi_irqs(dev);
1042}
1043EXPORT_SYMBOL(pci_disable_msix);
1044
1045void pci_no_msi(void)
1046{
1047 pci_msi_enable = 0;
1048}
1049
1050/**
1051 * pci_msi_enabled - is MSI enabled?
1052 *
1053 * Returns true if MSI has not been disabled by the command-line option
1054 * pci=nomsi.
1055 **/
1056int pci_msi_enabled(void)
1057{
1058 return pci_msi_enable;
1059}
1060EXPORT_SYMBOL(pci_msi_enabled);
1061
1062static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1063 const struct irq_affinity *affd)
1064{
1065 int nvec;
1066 int rc;
1067
1068 if (!pci_msi_supported(dev, minvec))
1069 return -EINVAL;
1070
1071 WARN_ON(!!dev->msi_enabled);
1072
1073 /* Check whether driver already requested MSI-X irqs */
1074 if (dev->msix_enabled) {
1075 dev_info(&dev->dev,
1076 "can't enable MSI (MSI-X already enabled)\n");
1077 return -EINVAL;
1078 }
1079
1080 if (maxvec < minvec)
1081 return -ERANGE;
1082
1083 nvec = pci_msi_vec_count(dev);
1084 if (nvec < 0)
1085 return nvec;
1086 if (nvec < minvec)
1087 return -EINVAL;
1088
1089 if (nvec > maxvec)
1090 nvec = maxvec;
1091
1092 for (;;) {
1093 if (affd) {
1094 nvec = irq_calc_affinity_vectors(nvec, affd);
1095 if (nvec < minvec)
1096 return -ENOSPC;
1097 }
1098
1099 rc = msi_capability_init(dev, nvec, affd);
1100 if (rc == 0)
1101 return nvec;
1102
1103 if (rc < 0)
1104 return rc;
1105 if (rc < minvec)
1106 return -ENOSPC;
1107
1108 nvec = rc;
1109 }
1110}
1111
1112/**
1113 * pci_enable_msi_range - configure device's MSI capability structure
1114 * @dev: device to configure
1115 * @minvec: minimal number of interrupts to configure
1116 * @maxvec: maximum number of interrupts to configure
1117 *
1118 * This function tries to allocate a maximum possible number of interrupts in a
1119 * range between @minvec and @maxvec. It returns a negative errno if an error
1120 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1121 * and updates the @dev's irq member to the lowest new interrupt number;
1122 * the other interrupt numbers allocated to this device are consecutive.
1123 **/
1124int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1125{
1126 return __pci_enable_msi_range(dev, minvec, maxvec, NULL);
1127}
1128EXPORT_SYMBOL(pci_enable_msi_range);
1129
1130static int __pci_enable_msix_range(struct pci_dev *dev,
1131 struct msix_entry *entries, int minvec,
1132 int maxvec, const struct irq_affinity *affd)
1133{
1134 int rc, nvec = maxvec;
1135
1136 if (maxvec < minvec)
1137 return -ERANGE;
1138
1139 for (;;) {
1140 if (affd) {
1141 nvec = irq_calc_affinity_vectors(nvec, affd);
1142 if (nvec < minvec)
1143 return -ENOSPC;
1144 }
1145
1146 rc = __pci_enable_msix(dev, entries, nvec, affd);
1147 if (rc == 0)
1148 return nvec;
1149
1150 if (rc < 0)
1151 return rc;
1152 if (rc < minvec)
1153 return -ENOSPC;
1154
1155 nvec = rc;
1156 }
1157}
1158
1159/**
1160 * pci_enable_msix_range - configure device's MSI-X capability structure
1161 * @dev: pointer to the pci_dev data structure of MSI-X device function
1162 * @entries: pointer to an array of MSI-X entries
1163 * @minvec: minimum number of MSI-X irqs requested
1164 * @maxvec: maximum number of MSI-X irqs requested
1165 *
1166 * Setup the MSI-X capability structure of device function with a maximum
1167 * possible number of interrupts in the range between @minvec and @maxvec
1168 * upon its software driver call to request for MSI-X mode enabled on its
1169 * hardware device function. It returns a negative errno if an error occurs.
1170 * If it succeeds, it returns the actual number of interrupts allocated and
1171 * indicates the successful configuration of MSI-X capability structure
1172 * with new allocated MSI-X interrupts.
1173 **/
1174int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1175 int minvec, int maxvec)
1176{
1177 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL);
1178}
1179EXPORT_SYMBOL(pci_enable_msix_range);
1180
1181/**
1182 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1183 * @dev: PCI device to operate on
1184 * @min_vecs: minimum number of vectors required (must be >= 1)
1185 * @max_vecs: maximum (desired) number of vectors
1186 * @flags: flags or quirks for the allocation
1187 * @affd: optional description of the affinity requirements
1188 *
1189 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1190 * vectors if available, and fall back to a single legacy vector
1191 * if neither is available. Return the number of vectors allocated,
1192 * (which might be smaller than @max_vecs) if successful, or a negative
1193 * error code on error. If less than @min_vecs interrupt vectors are
1194 * available for @dev the function will fail with -ENOSPC.
1195 *
1196 * To get the Linux IRQ number used for a vector that can be passed to
1197 * request_irq() use the pci_irq_vector() helper.
1198 */
1199int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1200 unsigned int max_vecs, unsigned int flags,
1201 const struct irq_affinity *affd)
1202{
1203 static const struct irq_affinity msi_default_affd;
1204 int vecs = -ENOSPC;
1205
1206 if (flags & PCI_IRQ_AFFINITY) {
1207 if (!affd)
1208 affd = &msi_default_affd;
1209
1210 if (affd->pre_vectors + affd->post_vectors > min_vecs)
1211 return -EINVAL;
1212
1213 /*
1214 * If there aren't any vectors left after applying the pre/post
1215 * vectors don't bother with assigning affinity.
1216 */
1217 if (affd->pre_vectors + affd->post_vectors == min_vecs)
1218 affd = NULL;
1219 } else {
1220 if (WARN_ON(affd))
1221 affd = NULL;
1222 }
1223
1224 if (flags & PCI_IRQ_MSIX) {
1225 vecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1226 affd);
1227 if (vecs > 0)
1228 return vecs;
1229 }
1230
1231 if (flags & PCI_IRQ_MSI) {
1232 vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
1233 if (vecs > 0)
1234 return vecs;
1235 }
1236
1237 /* use legacy irq if allowed */
1238 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1) {
1239 pci_intx(dev, 1);
1240 return 1;
1241 }
1242
1243 return vecs;
1244}
1245EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1246
1247/**
1248 * pci_free_irq_vectors - free previously allocated IRQs for a device
1249 * @dev: PCI device to operate on
1250 *
1251 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1252 */
1253void pci_free_irq_vectors(struct pci_dev *dev)
1254{
1255 pci_disable_msix(dev);
1256 pci_disable_msi(dev);
1257}
1258EXPORT_SYMBOL(pci_free_irq_vectors);
1259
1260/**
1261 * pci_irq_vector - return Linux IRQ number of a device vector
1262 * @dev: PCI device to operate on
1263 * @nr: device-relative interrupt vector index (0-based).
1264 */
1265int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1266{
1267 if (dev->msix_enabled) {
1268 struct msi_desc *entry;
1269 int i = 0;
1270
1271 for_each_pci_msi_entry(entry, dev) {
1272 if (i == nr)
1273 return entry->irq;
1274 i++;
1275 }
1276 WARN_ON_ONCE(1);
1277 return -EINVAL;
1278 }
1279
1280 if (dev->msi_enabled) {
1281 struct msi_desc *entry = first_pci_msi_entry(dev);
1282
1283 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1284 return -EINVAL;
1285 } else {
1286 if (WARN_ON_ONCE(nr > 0))
1287 return -EINVAL;
1288 }
1289
1290 return dev->irq + nr;
1291}
1292EXPORT_SYMBOL(pci_irq_vector);
1293
1294/**
1295 * pci_irq_get_affinity - return the affinity of a particular msi vector
1296 * @dev: PCI device to operate on
1297 * @nr: device-relative interrupt vector index (0-based).
1298 */
1299const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1300{
1301 if (dev->msix_enabled) {
1302 struct msi_desc *entry;
1303 int i = 0;
1304
1305 for_each_pci_msi_entry(entry, dev) {
1306 if (i == nr)
1307 return entry->affinity;
1308 i++;
1309 }
1310 WARN_ON_ONCE(1);
1311 return NULL;
1312 } else if (dev->msi_enabled) {
1313 struct msi_desc *entry = first_pci_msi_entry(dev);
1314
1315 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1316 nr >= entry->nvec_used))
1317 return NULL;
1318
1319 return &entry->affinity[nr];
1320 } else {
1321 return cpu_possible_mask;
1322 }
1323}
1324EXPORT_SYMBOL(pci_irq_get_affinity);
1325
1326struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1327{
1328 return to_pci_dev(desc->dev);
1329}
1330EXPORT_SYMBOL(msi_desc_to_pci_dev);
1331
1332void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1333{
1334 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1335
1336 return dev->bus->sysdata;
1337}
1338EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1339
1340#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1341/**
1342 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1343 * @irq_data: Pointer to interrupt data of the MSI interrupt
1344 * @msg: Pointer to the message
1345 */
1346void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1347{
1348 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1349
1350 /*
1351 * For MSI-X desc->irq is always equal to irq_data->irq. For
1352 * MSI only the first interrupt of MULTI MSI passes the test.
1353 */
1354 if (desc->irq == irq_data->irq)
1355 __pci_write_msi_msg(desc, msg);
1356}
1357
1358/**
1359 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1360 * @dev: Pointer to the PCI device
1361 * @desc: Pointer to the msi descriptor
1362 *
1363 * The ID number is only used within the irqdomain.
1364 */
1365irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1366 struct msi_desc *desc)
1367{
1368 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1369 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1370 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1371}
1372
1373static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1374{
1375 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1376}
1377
1378/**
1379 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1380 * @domain: The interrupt domain to check
1381 * @info: The domain info for verification
1382 * @dev: The device to check
1383 *
1384 * Returns:
1385 * 0 if the functionality is supported
1386 * 1 if Multi MSI is requested, but the domain does not support it
1387 * -ENOTSUPP otherwise
1388 */
1389int pci_msi_domain_check_cap(struct irq_domain *domain,
1390 struct msi_domain_info *info, struct device *dev)
1391{
1392 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1393
1394 /* Special handling to support pci_enable_msi_range() */
1395 if (pci_msi_desc_is_multi_msi(desc) &&
1396 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1397 return 1;
1398 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1399 return -ENOTSUPP;
1400
1401 return 0;
1402}
1403
1404static int pci_msi_domain_handle_error(struct irq_domain *domain,
1405 struct msi_desc *desc, int error)
1406{
1407 /* Special handling to support pci_enable_msi_range() */
1408 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1409 return 1;
1410
1411 return error;
1412}
1413
1414#ifdef GENERIC_MSI_DOMAIN_OPS
1415static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1416 struct msi_desc *desc)
1417{
1418 arg->desc = desc;
1419 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1420 desc);
1421}
1422#else
1423#define pci_msi_domain_set_desc NULL
1424#endif
1425
1426static struct msi_domain_ops pci_msi_domain_ops_default = {
1427 .set_desc = pci_msi_domain_set_desc,
1428 .msi_check = pci_msi_domain_check_cap,
1429 .handle_error = pci_msi_domain_handle_error,
1430};
1431
1432static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1433{
1434 struct msi_domain_ops *ops = info->ops;
1435
1436 if (ops == NULL) {
1437 info->ops = &pci_msi_domain_ops_default;
1438 } else {
1439 if (ops->set_desc == NULL)
1440 ops->set_desc = pci_msi_domain_set_desc;
1441 if (ops->msi_check == NULL)
1442 ops->msi_check = pci_msi_domain_check_cap;
1443 if (ops->handle_error == NULL)
1444 ops->handle_error = pci_msi_domain_handle_error;
1445 }
1446}
1447
1448static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1449{
1450 struct irq_chip *chip = info->chip;
1451
1452 BUG_ON(!chip);
1453 if (!chip->irq_write_msi_msg)
1454 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1455 if (!chip->irq_mask)
1456 chip->irq_mask = pci_msi_mask_irq;
1457 if (!chip->irq_unmask)
1458 chip->irq_unmask = pci_msi_unmask_irq;
1459}
1460
1461/**
1462 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1463 * @fwnode: Optional fwnode of the interrupt controller
1464 * @info: MSI domain info
1465 * @parent: Parent irq domain
1466 *
1467 * Updates the domain and chip ops and creates a MSI interrupt domain.
1468 *
1469 * Returns:
1470 * A domain pointer or NULL in case of failure.
1471 */
1472struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1473 struct msi_domain_info *info,
1474 struct irq_domain *parent)
1475{
1476 struct irq_domain *domain;
1477
1478 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1479 pci_msi_domain_update_dom_ops(info);
1480 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1481 pci_msi_domain_update_chip_ops(info);
1482
1483 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1484
1485 domain = msi_create_irq_domain(fwnode, info, parent);
1486 if (!domain)
1487 return NULL;
1488
1489 domain->bus_token = DOMAIN_BUS_PCI_MSI;
1490 return domain;
1491}
1492EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1493
1494/**
1495 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1496 * @domain: The interrupt domain to allocate from
1497 * @dev: The device for which to allocate
1498 * @nvec: The number of interrupts to allocate
1499 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1500 *
1501 * Returns:
1502 * A virtual interrupt number or an error code in case of failure
1503 */
1504int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1505 int nvec, int type)
1506{
1507 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1508}
1509
1510/**
1511 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1512 * @domain: The interrupt domain
1513 * @dev: The device for which to free interrupts
1514 */
1515void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1516{
1517 msi_domain_free_irqs(domain, &dev->dev);
1518}
1519
1520/**
1521 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1522 * @fwnode: Optional fwnode of the interrupt controller
1523 * @info: MSI domain info
1524 * @parent: Parent irq domain
1525 *
1526 * Returns: A domain pointer or NULL in case of failure. If successful
1527 * the default PCI/MSI irqdomain pointer is updated.
1528 */
1529struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
1530 struct msi_domain_info *info, struct irq_domain *parent)
1531{
1532 struct irq_domain *domain;
1533
1534 mutex_lock(&pci_msi_domain_lock);
1535 if (pci_msi_default_domain) {
1536 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1537 domain = NULL;
1538 } else {
1539 domain = pci_msi_create_irq_domain(fwnode, info, parent);
1540 pci_msi_default_domain = domain;
1541 }
1542 mutex_unlock(&pci_msi_domain_lock);
1543
1544 return domain;
1545}
1546
1547static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1548{
1549 u32 *pa = data;
1550
1551 *pa = alias;
1552 return 0;
1553}
1554/**
1555 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1556 * @domain: The interrupt domain
1557 * @pdev: The PCI device.
1558 *
1559 * The RID for a device is formed from the alias, with a firmware
1560 * supplied mapping applied
1561 *
1562 * Returns: The RID.
1563 */
1564u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1565{
1566 struct device_node *of_node;
1567 u32 rid = 0;
1568
1569 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1570
1571 of_node = irq_domain_get_of_node(domain);
1572 rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) :
1573 iort_msi_map_rid(&pdev->dev, rid);
1574
1575 return rid;
1576}
1577
1578/**
1579 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1580 * @pdev: The PCI device
1581 *
1582 * Use the firmware data to find a device-specific MSI domain
1583 * (i.e. not one that is ste as a default).
1584 *
1585 * Returns: The coresponding MSI domain or NULL if none has been found.
1586 */
1587struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1588{
1589 struct irq_domain *dom;
1590 u32 rid = 0;
1591
1592 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1593 dom = of_msi_map_get_device_domain(&pdev->dev, rid);
1594 if (!dom)
1595 dom = iort_get_device_domain(&pdev->dev, rid);
1596 return dom;
1597}
1598#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */