Loading...
1/*
2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/io.h>
18#include <linux/device.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22
23#include <linux/clk.h>
24#include <linux/gpio.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27#include <linux/scatterlist.h>
28#include <linux/dma-mapping.h>
29#include <linux/slab.h>
30#include <linux/reset.h>
31#include <linux/regulator/consumer.h>
32
33#include <linux/of_address.h>
34#include <linux/of_gpio.h>
35#include <linux/of_platform.h>
36
37#include <linux/mmc/host.h>
38#include <linux/mmc/sd.h>
39#include <linux/mmc/sdio.h>
40#include <linux/mmc/mmc.h>
41#include <linux/mmc/core.h>
42#include <linux/mmc/card.h>
43#include <linux/mmc/slot-gpio.h>
44
45/* register offset definitions */
46#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
47#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
48#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
49#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
50#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
51#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
52#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
53#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
54#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
55#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
56#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
57#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
58#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
59#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
60#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
61#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
62#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
63#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
64#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
65#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
66#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
67#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
68#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
69#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
70#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
71#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
72#define SDXC_REG_CHDA (0x90)
73#define SDXC_REG_CBDA (0x94)
74
75#define mmc_readl(host, reg) \
76 readl((host)->reg_base + SDXC_##reg)
77#define mmc_writel(host, reg, value) \
78 writel((value), (host)->reg_base + SDXC_##reg)
79
80/* global control register bits */
81#define SDXC_SOFT_RESET BIT(0)
82#define SDXC_FIFO_RESET BIT(1)
83#define SDXC_DMA_RESET BIT(2)
84#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
85#define SDXC_DMA_ENABLE_BIT BIT(5)
86#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
87#define SDXC_POSEDGE_LATCH_DATA BIT(9)
88#define SDXC_DDR_MODE BIT(10)
89#define SDXC_MEMORY_ACCESS_DONE BIT(29)
90#define SDXC_ACCESS_DONE_DIRECT BIT(30)
91#define SDXC_ACCESS_BY_AHB BIT(31)
92#define SDXC_ACCESS_BY_DMA (0 << 31)
93#define SDXC_HARDWARE_RESET \
94 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
95
96/* clock control bits */
97#define SDXC_CARD_CLOCK_ON BIT(16)
98#define SDXC_LOW_POWER_ON BIT(17)
99
100/* bus width */
101#define SDXC_WIDTH1 0
102#define SDXC_WIDTH4 1
103#define SDXC_WIDTH8 2
104
105/* smc command bits */
106#define SDXC_RESP_EXPIRE BIT(6)
107#define SDXC_LONG_RESPONSE BIT(7)
108#define SDXC_CHECK_RESPONSE_CRC BIT(8)
109#define SDXC_DATA_EXPIRE BIT(9)
110#define SDXC_WRITE BIT(10)
111#define SDXC_SEQUENCE_MODE BIT(11)
112#define SDXC_SEND_AUTO_STOP BIT(12)
113#define SDXC_WAIT_PRE_OVER BIT(13)
114#define SDXC_STOP_ABORT_CMD BIT(14)
115#define SDXC_SEND_INIT_SEQUENCE BIT(15)
116#define SDXC_UPCLK_ONLY BIT(21)
117#define SDXC_READ_CEATA_DEV BIT(22)
118#define SDXC_CCS_EXPIRE BIT(23)
119#define SDXC_ENABLE_BIT_BOOT BIT(24)
120#define SDXC_ALT_BOOT_OPTIONS BIT(25)
121#define SDXC_BOOT_ACK_EXPIRE BIT(26)
122#define SDXC_BOOT_ABORT BIT(27)
123#define SDXC_VOLTAGE_SWITCH BIT(28)
124#define SDXC_USE_HOLD_REGISTER BIT(29)
125#define SDXC_START BIT(31)
126
127/* interrupt bits */
128#define SDXC_RESP_ERROR BIT(1)
129#define SDXC_COMMAND_DONE BIT(2)
130#define SDXC_DATA_OVER BIT(3)
131#define SDXC_TX_DATA_REQUEST BIT(4)
132#define SDXC_RX_DATA_REQUEST BIT(5)
133#define SDXC_RESP_CRC_ERROR BIT(6)
134#define SDXC_DATA_CRC_ERROR BIT(7)
135#define SDXC_RESP_TIMEOUT BIT(8)
136#define SDXC_DATA_TIMEOUT BIT(9)
137#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
138#define SDXC_FIFO_RUN_ERROR BIT(11)
139#define SDXC_HARD_WARE_LOCKED BIT(12)
140#define SDXC_START_BIT_ERROR BIT(13)
141#define SDXC_AUTO_COMMAND_DONE BIT(14)
142#define SDXC_END_BIT_ERROR BIT(15)
143#define SDXC_SDIO_INTERRUPT BIT(16)
144#define SDXC_CARD_INSERT BIT(30)
145#define SDXC_CARD_REMOVE BIT(31)
146#define SDXC_INTERRUPT_ERROR_BIT \
147 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
148 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
149 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
150#define SDXC_INTERRUPT_DONE_BIT \
151 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
152 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
153
154/* status */
155#define SDXC_RXWL_FLAG BIT(0)
156#define SDXC_TXWL_FLAG BIT(1)
157#define SDXC_FIFO_EMPTY BIT(2)
158#define SDXC_FIFO_FULL BIT(3)
159#define SDXC_CARD_PRESENT BIT(8)
160#define SDXC_CARD_DATA_BUSY BIT(9)
161#define SDXC_DATA_FSM_BUSY BIT(10)
162#define SDXC_DMA_REQUEST BIT(31)
163#define SDXC_FIFO_SIZE 16
164
165/* Function select */
166#define SDXC_CEATA_ON (0xceaa << 16)
167#define SDXC_SEND_IRQ_RESPONSE BIT(0)
168#define SDXC_SDIO_READ_WAIT BIT(1)
169#define SDXC_ABORT_READ_DATA BIT(2)
170#define SDXC_SEND_CCSD BIT(8)
171#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
172#define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
173
174/* IDMA controller bus mod bit field */
175#define SDXC_IDMAC_SOFT_RESET BIT(0)
176#define SDXC_IDMAC_FIX_BURST BIT(1)
177#define SDXC_IDMAC_IDMA_ON BIT(7)
178#define SDXC_IDMAC_REFETCH_DES BIT(31)
179
180/* IDMA status bit field */
181#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
182#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
183#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
184#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
185#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
186#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
187#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
188#define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
189#define SDXC_IDMAC_IDLE (0 << 13)
190#define SDXC_IDMAC_SUSPEND (1 << 13)
191#define SDXC_IDMAC_DESC_READ (2 << 13)
192#define SDXC_IDMAC_DESC_CHECK (3 << 13)
193#define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
194#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
195#define SDXC_IDMAC_READ (6 << 13)
196#define SDXC_IDMAC_WRITE (7 << 13)
197#define SDXC_IDMAC_DESC_CLOSE (8 << 13)
198
199/*
200* If the idma-des-size-bits of property is ie 13, bufsize bits are:
201* Bits 0-12: buf1 size
202* Bits 13-25: buf2 size
203* Bits 26-31: not used
204* Since we only ever set buf1 size, we can simply store it directly.
205*/
206#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
207#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
208#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
209#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
210#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
211#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
212#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
213
214#define SDXC_CLK_400K 0
215#define SDXC_CLK_25M 1
216#define SDXC_CLK_50M 2
217#define SDXC_CLK_50M_DDR 3
218#define SDXC_CLK_50M_DDR_8BIT 4
219
220struct sunxi_mmc_clk_delay {
221 u32 output;
222 u32 sample;
223};
224
225struct sunxi_idma_des {
226 u32 config;
227 u32 buf_size;
228 u32 buf_addr_ptr1;
229 u32 buf_addr_ptr2;
230};
231
232struct sunxi_mmc_host {
233 struct mmc_host *mmc;
234 struct reset_control *reset;
235
236 /* IO mapping base */
237 void __iomem *reg_base;
238
239 /* clock management */
240 struct clk *clk_ahb;
241 struct clk *clk_mmc;
242 struct clk *clk_sample;
243 struct clk *clk_output;
244 const struct sunxi_mmc_clk_delay *clk_delays;
245
246 /* irq */
247 spinlock_t lock;
248 int irq;
249 u32 int_sum;
250 u32 sdio_imask;
251
252 /* dma */
253 u32 idma_des_size_bits;
254 dma_addr_t sg_dma;
255 void *sg_cpu;
256 bool wait_dma;
257
258 struct mmc_request *mrq;
259 struct mmc_request *manual_stop_mrq;
260 int ferror;
261
262 /* vqmmc */
263 bool vqmmc_enabled;
264};
265
266static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
267{
268 unsigned long expire = jiffies + msecs_to_jiffies(250);
269 u32 rval;
270
271 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
272 do {
273 rval = mmc_readl(host, REG_GCTRL);
274 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
275
276 if (rval & SDXC_HARDWARE_RESET) {
277 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
278 return -EIO;
279 }
280
281 return 0;
282}
283
284static int sunxi_mmc_init_host(struct mmc_host *mmc)
285{
286 u32 rval;
287 struct sunxi_mmc_host *host = mmc_priv(mmc);
288
289 if (sunxi_mmc_reset_host(host))
290 return -EIO;
291
292 /*
293 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
294 *
295 * TODO: sun9i has a larger FIFO and supports higher trigger values
296 */
297 mmc_writel(host, REG_FTRGL, 0x20070008);
298 /* Maximum timeout value */
299 mmc_writel(host, REG_TMOUT, 0xffffffff);
300 /* Unmask SDIO interrupt if needed */
301 mmc_writel(host, REG_IMASK, host->sdio_imask);
302 /* Clear all pending interrupts */
303 mmc_writel(host, REG_RINTR, 0xffffffff);
304 /* Debug register? undocumented */
305 mmc_writel(host, REG_DBGC, 0xdeb);
306 /* Enable CEATA support */
307 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
308 /* Set DMA descriptor list base address */
309 mmc_writel(host, REG_DLBA, host->sg_dma);
310
311 rval = mmc_readl(host, REG_GCTRL);
312 rval |= SDXC_INTERRUPT_ENABLE_BIT;
313 /* Undocumented, but found in Allwinner code */
314 rval &= ~SDXC_ACCESS_DONE_DIRECT;
315 mmc_writel(host, REG_GCTRL, rval);
316
317 return 0;
318}
319
320static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
321 struct mmc_data *data)
322{
323 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
324 dma_addr_t next_desc = host->sg_dma;
325 int i, max_len = (1 << host->idma_des_size_bits);
326
327 for (i = 0; i < data->sg_len; i++) {
328 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
329 SDXC_IDMAC_DES0_DIC;
330
331 if (data->sg[i].length == max_len)
332 pdes[i].buf_size = 0; /* 0 == max_len */
333 else
334 pdes[i].buf_size = data->sg[i].length;
335
336 next_desc += sizeof(struct sunxi_idma_des);
337 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
338 pdes[i].buf_addr_ptr2 = (u32)next_desc;
339 }
340
341 pdes[0].config |= SDXC_IDMAC_DES0_FD;
342 pdes[i - 1].config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER;
343 pdes[i - 1].config &= ~SDXC_IDMAC_DES0_DIC;
344 pdes[i - 1].buf_addr_ptr2 = 0;
345
346 /*
347 * Avoid the io-store starting the idmac hitting io-mem before the
348 * descriptors hit the main-mem.
349 */
350 wmb();
351}
352
353static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
354{
355 if (data->flags & MMC_DATA_WRITE)
356 return DMA_TO_DEVICE;
357 else
358 return DMA_FROM_DEVICE;
359}
360
361static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
362 struct mmc_data *data)
363{
364 u32 i, dma_len;
365 struct scatterlist *sg;
366
367 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
368 sunxi_mmc_get_dma_dir(data));
369 if (dma_len == 0) {
370 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
371 return -ENOMEM;
372 }
373
374 for_each_sg(data->sg, sg, data->sg_len, i) {
375 if (sg->offset & 3 || sg->length & 3) {
376 dev_err(mmc_dev(host->mmc),
377 "unaligned scatterlist: os %x length %d\n",
378 sg->offset, sg->length);
379 return -EINVAL;
380 }
381 }
382
383 return 0;
384}
385
386static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
387 struct mmc_data *data)
388{
389 u32 rval;
390
391 sunxi_mmc_init_idma_des(host, data);
392
393 rval = mmc_readl(host, REG_GCTRL);
394 rval |= SDXC_DMA_ENABLE_BIT;
395 mmc_writel(host, REG_GCTRL, rval);
396 rval |= SDXC_DMA_RESET;
397 mmc_writel(host, REG_GCTRL, rval);
398
399 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
400
401 if (!(data->flags & MMC_DATA_WRITE))
402 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
403
404 mmc_writel(host, REG_DMAC,
405 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
406}
407
408static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
409 struct mmc_request *req)
410{
411 u32 arg, cmd_val, ri;
412 unsigned long expire = jiffies + msecs_to_jiffies(1000);
413
414 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
415 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
416
417 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
418 cmd_val |= SD_IO_RW_DIRECT;
419 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
420 ((req->cmd->arg >> 28) & 0x7);
421 } else {
422 cmd_val |= MMC_STOP_TRANSMISSION;
423 arg = 0;
424 }
425
426 mmc_writel(host, REG_CARG, arg);
427 mmc_writel(host, REG_CMDR, cmd_val);
428
429 do {
430 ri = mmc_readl(host, REG_RINTR);
431 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
432 time_before(jiffies, expire));
433
434 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
435 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
436 if (req->stop)
437 req->stop->resp[0] = -ETIMEDOUT;
438 } else {
439 if (req->stop)
440 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
441 }
442
443 mmc_writel(host, REG_RINTR, 0xffff);
444}
445
446static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
447{
448 struct mmc_command *cmd = host->mrq->cmd;
449 struct mmc_data *data = host->mrq->data;
450
451 /* For some cmds timeout is normal with sd/mmc cards */
452 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
453 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
454 cmd->opcode == SD_IO_RW_DIRECT))
455 return;
456
457 dev_err(mmc_dev(host->mmc),
458 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
459 host->mmc->index, cmd->opcode,
460 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
461 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
462 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
463 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
464 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
465 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
466 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
467 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
468 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
469 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
470 );
471}
472
473/* Called in interrupt context! */
474static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
475{
476 struct mmc_request *mrq = host->mrq;
477 struct mmc_data *data = mrq->data;
478 u32 rval;
479
480 mmc_writel(host, REG_IMASK, host->sdio_imask);
481 mmc_writel(host, REG_IDIE, 0);
482
483 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
484 sunxi_mmc_dump_errinfo(host);
485 mrq->cmd->error = -ETIMEDOUT;
486
487 if (data) {
488 data->error = -ETIMEDOUT;
489 host->manual_stop_mrq = mrq;
490 }
491
492 if (mrq->stop)
493 mrq->stop->error = -ETIMEDOUT;
494 } else {
495 if (mrq->cmd->flags & MMC_RSP_136) {
496 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
497 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
498 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
499 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
500 } else {
501 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
502 }
503
504 if (data)
505 data->bytes_xfered = data->blocks * data->blksz;
506 }
507
508 if (data) {
509 mmc_writel(host, REG_IDST, 0x337);
510 mmc_writel(host, REG_DMAC, 0);
511 rval = mmc_readl(host, REG_GCTRL);
512 rval |= SDXC_DMA_RESET;
513 mmc_writel(host, REG_GCTRL, rval);
514 rval &= ~SDXC_DMA_ENABLE_BIT;
515 mmc_writel(host, REG_GCTRL, rval);
516 rval |= SDXC_FIFO_RESET;
517 mmc_writel(host, REG_GCTRL, rval);
518 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
519 sunxi_mmc_get_dma_dir(data));
520 }
521
522 mmc_writel(host, REG_RINTR, 0xffff);
523
524 host->mrq = NULL;
525 host->int_sum = 0;
526 host->wait_dma = false;
527
528 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
529}
530
531static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
532{
533 struct sunxi_mmc_host *host = dev_id;
534 struct mmc_request *mrq;
535 u32 msk_int, idma_int;
536 bool finalize = false;
537 bool sdio_int = false;
538 irqreturn_t ret = IRQ_HANDLED;
539
540 spin_lock(&host->lock);
541
542 idma_int = mmc_readl(host, REG_IDST);
543 msk_int = mmc_readl(host, REG_MISTA);
544
545 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
546 host->mrq, msk_int, idma_int);
547
548 mrq = host->mrq;
549 if (mrq) {
550 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
551 host->wait_dma = false;
552
553 host->int_sum |= msk_int;
554
555 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
556 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
557 !(host->int_sum & SDXC_COMMAND_DONE))
558 mmc_writel(host, REG_IMASK,
559 host->sdio_imask | SDXC_COMMAND_DONE);
560 /* Don't wait for dma on error */
561 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
562 finalize = true;
563 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
564 !host->wait_dma)
565 finalize = true;
566 }
567
568 if (msk_int & SDXC_SDIO_INTERRUPT)
569 sdio_int = true;
570
571 mmc_writel(host, REG_RINTR, msk_int);
572 mmc_writel(host, REG_IDST, idma_int);
573
574 if (finalize)
575 ret = sunxi_mmc_finalize_request(host);
576
577 spin_unlock(&host->lock);
578
579 if (finalize && ret == IRQ_HANDLED)
580 mmc_request_done(host->mmc, mrq);
581
582 if (sdio_int)
583 mmc_signal_sdio_irq(host->mmc);
584
585 return ret;
586}
587
588static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
589{
590 struct sunxi_mmc_host *host = dev_id;
591 struct mmc_request *mrq;
592 unsigned long iflags;
593
594 spin_lock_irqsave(&host->lock, iflags);
595 mrq = host->manual_stop_mrq;
596 spin_unlock_irqrestore(&host->lock, iflags);
597
598 if (!mrq) {
599 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
600 return IRQ_HANDLED;
601 }
602
603 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
604
605 /*
606 * We will never have more than one outstanding request,
607 * and we do not complete the request until after
608 * we've cleared host->manual_stop_mrq so we do not need to
609 * spin lock this function.
610 * Additionally we have wait states within this function
611 * so having it in a lock is a very bad idea.
612 */
613 sunxi_mmc_send_manual_stop(host, mrq);
614
615 spin_lock_irqsave(&host->lock, iflags);
616 host->manual_stop_mrq = NULL;
617 spin_unlock_irqrestore(&host->lock, iflags);
618
619 mmc_request_done(host->mmc, mrq);
620
621 return IRQ_HANDLED;
622}
623
624static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
625{
626 unsigned long expire = jiffies + msecs_to_jiffies(750);
627 u32 rval;
628
629 rval = mmc_readl(host, REG_CLKCR);
630 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
631
632 if (oclk_en)
633 rval |= SDXC_CARD_CLOCK_ON;
634
635 mmc_writel(host, REG_CLKCR, rval);
636
637 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
638 mmc_writel(host, REG_CMDR, rval);
639
640 do {
641 rval = mmc_readl(host, REG_CMDR);
642 } while (time_before(jiffies, expire) && (rval & SDXC_START));
643
644 /* clear irq status bits set by the command */
645 mmc_writel(host, REG_RINTR,
646 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
647
648 if (rval & SDXC_START) {
649 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
650 return -EIO;
651 }
652
653 return 0;
654}
655
656static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
657 struct mmc_ios *ios)
658{
659 u32 rate, oclk_dly, rval, sclk_dly;
660 u32 clock = ios->clock;
661 int ret;
662
663 /* 8 bit DDR requires a higher module clock */
664 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
665 ios->bus_width == MMC_BUS_WIDTH_8)
666 clock <<= 1;
667
668 rate = clk_round_rate(host->clk_mmc, clock);
669 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
670 clock, rate);
671
672 /* setting clock rate */
673 ret = clk_set_rate(host->clk_mmc, rate);
674 if (ret) {
675 dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
676 rate, ret);
677 return ret;
678 }
679
680 ret = sunxi_mmc_oclk_onoff(host, 0);
681 if (ret)
682 return ret;
683
684 /* clear internal divider */
685 rval = mmc_readl(host, REG_CLKCR);
686 rval &= ~0xff;
687 /* set internal divider for 8 bit eMMC DDR, so card clock is right */
688 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
689 ios->bus_width == MMC_BUS_WIDTH_8) {
690 rval |= 1;
691 rate >>= 1;
692 }
693 mmc_writel(host, REG_CLKCR, rval);
694
695 /* determine delays */
696 if (rate <= 400000) {
697 oclk_dly = host->clk_delays[SDXC_CLK_400K].output;
698 sclk_dly = host->clk_delays[SDXC_CLK_400K].sample;
699 } else if (rate <= 25000000) {
700 oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
701 sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
702 } else if (rate <= 52000000) {
703 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
704 ios->timing != MMC_TIMING_MMC_DDR52) {
705 oclk_dly = host->clk_delays[SDXC_CLK_50M].output;
706 sclk_dly = host->clk_delays[SDXC_CLK_50M].sample;
707 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
708 oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].output;
709 sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].sample;
710 } else {
711 oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
712 sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
713 }
714 } else {
715 return -EINVAL;
716 }
717
718 clk_set_phase(host->clk_sample, sclk_dly);
719 clk_set_phase(host->clk_output, oclk_dly);
720
721 return sunxi_mmc_oclk_onoff(host, 1);
722}
723
724static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
725{
726 struct sunxi_mmc_host *host = mmc_priv(mmc);
727 u32 rval;
728
729 /* Set the power state */
730 switch (ios->power_mode) {
731 case MMC_POWER_ON:
732 break;
733
734 case MMC_POWER_UP:
735 host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
736 ios->vdd);
737 if (host->ferror)
738 return;
739
740 if (!IS_ERR(mmc->supply.vqmmc)) {
741 host->ferror = regulator_enable(mmc->supply.vqmmc);
742 if (host->ferror) {
743 dev_err(mmc_dev(mmc),
744 "failed to enable vqmmc\n");
745 return;
746 }
747 host->vqmmc_enabled = true;
748 }
749
750 host->ferror = sunxi_mmc_init_host(mmc);
751 if (host->ferror)
752 return;
753
754 dev_dbg(mmc_dev(mmc), "power on!\n");
755 break;
756
757 case MMC_POWER_OFF:
758 dev_dbg(mmc_dev(mmc), "power off!\n");
759 sunxi_mmc_reset_host(host);
760 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
761 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
762 regulator_disable(mmc->supply.vqmmc);
763 host->vqmmc_enabled = false;
764 break;
765 }
766
767 /* set bus width */
768 switch (ios->bus_width) {
769 case MMC_BUS_WIDTH_1:
770 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
771 break;
772 case MMC_BUS_WIDTH_4:
773 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
774 break;
775 case MMC_BUS_WIDTH_8:
776 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
777 break;
778 }
779
780 /* set ddr mode */
781 rval = mmc_readl(host, REG_GCTRL);
782 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
783 ios->timing == MMC_TIMING_MMC_DDR52)
784 rval |= SDXC_DDR_MODE;
785 else
786 rval &= ~SDXC_DDR_MODE;
787 mmc_writel(host, REG_GCTRL, rval);
788
789 /* set up clock */
790 if (ios->clock && ios->power_mode) {
791 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
792 /* Android code had a usleep_range(50000, 55000); here */
793 }
794}
795
796static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
797{
798 /* vqmmc regulator is available */
799 if (!IS_ERR(mmc->supply.vqmmc))
800 return mmc_regulator_set_vqmmc(mmc, ios);
801
802 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
803 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
804 return 0;
805
806 return -EINVAL;
807}
808
809static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
810{
811 struct sunxi_mmc_host *host = mmc_priv(mmc);
812 unsigned long flags;
813 u32 imask;
814
815 spin_lock_irqsave(&host->lock, flags);
816
817 imask = mmc_readl(host, REG_IMASK);
818 if (enable) {
819 host->sdio_imask = SDXC_SDIO_INTERRUPT;
820 imask |= SDXC_SDIO_INTERRUPT;
821 } else {
822 host->sdio_imask = 0;
823 imask &= ~SDXC_SDIO_INTERRUPT;
824 }
825 mmc_writel(host, REG_IMASK, imask);
826 spin_unlock_irqrestore(&host->lock, flags);
827}
828
829static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
830{
831 struct sunxi_mmc_host *host = mmc_priv(mmc);
832 mmc_writel(host, REG_HWRST, 0);
833 udelay(10);
834 mmc_writel(host, REG_HWRST, 1);
835 udelay(300);
836}
837
838static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
839{
840 struct sunxi_mmc_host *host = mmc_priv(mmc);
841 struct mmc_command *cmd = mrq->cmd;
842 struct mmc_data *data = mrq->data;
843 unsigned long iflags;
844 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
845 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
846 bool wait_dma = host->wait_dma;
847 int ret;
848
849 /* Check for set_ios errors (should never happen) */
850 if (host->ferror) {
851 mrq->cmd->error = host->ferror;
852 mmc_request_done(mmc, mrq);
853 return;
854 }
855
856 if (data) {
857 ret = sunxi_mmc_map_dma(host, data);
858 if (ret < 0) {
859 dev_err(mmc_dev(mmc), "map DMA failed\n");
860 cmd->error = ret;
861 data->error = ret;
862 mmc_request_done(mmc, mrq);
863 return;
864 }
865 }
866
867 if (cmd->opcode == MMC_GO_IDLE_STATE) {
868 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
869 imask |= SDXC_COMMAND_DONE;
870 }
871
872 if (cmd->flags & MMC_RSP_PRESENT) {
873 cmd_val |= SDXC_RESP_EXPIRE;
874 if (cmd->flags & MMC_RSP_136)
875 cmd_val |= SDXC_LONG_RESPONSE;
876 if (cmd->flags & MMC_RSP_CRC)
877 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
878
879 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
880 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
881
882 if (cmd->data->stop) {
883 imask |= SDXC_AUTO_COMMAND_DONE;
884 cmd_val |= SDXC_SEND_AUTO_STOP;
885 } else {
886 imask |= SDXC_DATA_OVER;
887 }
888
889 if (cmd->data->flags & MMC_DATA_WRITE)
890 cmd_val |= SDXC_WRITE;
891 else
892 wait_dma = true;
893 } else {
894 imask |= SDXC_COMMAND_DONE;
895 }
896 } else {
897 imask |= SDXC_COMMAND_DONE;
898 }
899
900 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
901 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
902 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
903
904 spin_lock_irqsave(&host->lock, iflags);
905
906 if (host->mrq || host->manual_stop_mrq) {
907 spin_unlock_irqrestore(&host->lock, iflags);
908
909 if (data)
910 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
911 sunxi_mmc_get_dma_dir(data));
912
913 dev_err(mmc_dev(mmc), "request already pending\n");
914 mrq->cmd->error = -EBUSY;
915 mmc_request_done(mmc, mrq);
916 return;
917 }
918
919 if (data) {
920 mmc_writel(host, REG_BLKSZ, data->blksz);
921 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
922 sunxi_mmc_start_dma(host, data);
923 }
924
925 host->mrq = mrq;
926 host->wait_dma = wait_dma;
927 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
928 mmc_writel(host, REG_CARG, cmd->arg);
929 mmc_writel(host, REG_CMDR, cmd_val);
930
931 spin_unlock_irqrestore(&host->lock, iflags);
932}
933
934static int sunxi_mmc_card_busy(struct mmc_host *mmc)
935{
936 struct sunxi_mmc_host *host = mmc_priv(mmc);
937
938 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
939}
940
941static const struct of_device_id sunxi_mmc_of_match[] = {
942 { .compatible = "allwinner,sun4i-a10-mmc", },
943 { .compatible = "allwinner,sun5i-a13-mmc", },
944 { .compatible = "allwinner,sun9i-a80-mmc", },
945 { /* sentinel */ }
946};
947MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
948
949static struct mmc_host_ops sunxi_mmc_ops = {
950 .request = sunxi_mmc_request,
951 .set_ios = sunxi_mmc_set_ios,
952 .get_ro = mmc_gpio_get_ro,
953 .get_cd = mmc_gpio_get_cd,
954 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
955 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
956 .hw_reset = sunxi_mmc_hw_reset,
957 .card_busy = sunxi_mmc_card_busy,
958};
959
960static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
961 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
962 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
963 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
964 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
965 /* Value from A83T "new timing mode". Works but might not be right. */
966 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
967};
968
969static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
970 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
971 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
972 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
973 [SDXC_CLK_50M_DDR] = { .output = 90, .sample = 120 },
974 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 120 },
975};
976
977static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
978 struct platform_device *pdev)
979{
980 struct device_node *np = pdev->dev.of_node;
981 int ret;
982
983 if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
984 host->idma_des_size_bits = 13;
985 else
986 host->idma_des_size_bits = 16;
987
988 if (of_device_is_compatible(np, "allwinner,sun9i-a80-mmc"))
989 host->clk_delays = sun9i_mmc_clk_delays;
990 else
991 host->clk_delays = sunxi_mmc_clk_delays;
992
993 ret = mmc_regulator_get_supply(host->mmc);
994 if (ret) {
995 if (ret != -EPROBE_DEFER)
996 dev_err(&pdev->dev, "Could not get vmmc supply\n");
997 return ret;
998 }
999
1000 host->reg_base = devm_ioremap_resource(&pdev->dev,
1001 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1002 if (IS_ERR(host->reg_base))
1003 return PTR_ERR(host->reg_base);
1004
1005 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1006 if (IS_ERR(host->clk_ahb)) {
1007 dev_err(&pdev->dev, "Could not get ahb clock\n");
1008 return PTR_ERR(host->clk_ahb);
1009 }
1010
1011 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1012 if (IS_ERR(host->clk_mmc)) {
1013 dev_err(&pdev->dev, "Could not get mmc clock\n");
1014 return PTR_ERR(host->clk_mmc);
1015 }
1016
1017 host->clk_output = devm_clk_get(&pdev->dev, "output");
1018 if (IS_ERR(host->clk_output)) {
1019 dev_err(&pdev->dev, "Could not get output clock\n");
1020 return PTR_ERR(host->clk_output);
1021 }
1022
1023 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1024 if (IS_ERR(host->clk_sample)) {
1025 dev_err(&pdev->dev, "Could not get sample clock\n");
1026 return PTR_ERR(host->clk_sample);
1027 }
1028
1029 host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1030 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1031 return PTR_ERR(host->reset);
1032
1033 ret = clk_prepare_enable(host->clk_ahb);
1034 if (ret) {
1035 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1036 return ret;
1037 }
1038
1039 ret = clk_prepare_enable(host->clk_mmc);
1040 if (ret) {
1041 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1042 goto error_disable_clk_ahb;
1043 }
1044
1045 ret = clk_prepare_enable(host->clk_output);
1046 if (ret) {
1047 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1048 goto error_disable_clk_mmc;
1049 }
1050
1051 ret = clk_prepare_enable(host->clk_sample);
1052 if (ret) {
1053 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1054 goto error_disable_clk_output;
1055 }
1056
1057 if (!IS_ERR(host->reset)) {
1058 ret = reset_control_deassert(host->reset);
1059 if (ret) {
1060 dev_err(&pdev->dev, "reset err %d\n", ret);
1061 goto error_disable_clk_sample;
1062 }
1063 }
1064
1065 /*
1066 * Sometimes the controller asserts the irq on boot for some reason,
1067 * make sure the controller is in a sane state before enabling irqs.
1068 */
1069 ret = sunxi_mmc_reset_host(host);
1070 if (ret)
1071 goto error_assert_reset;
1072
1073 host->irq = platform_get_irq(pdev, 0);
1074 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1075 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1076
1077error_assert_reset:
1078 if (!IS_ERR(host->reset))
1079 reset_control_assert(host->reset);
1080error_disable_clk_sample:
1081 clk_disable_unprepare(host->clk_sample);
1082error_disable_clk_output:
1083 clk_disable_unprepare(host->clk_output);
1084error_disable_clk_mmc:
1085 clk_disable_unprepare(host->clk_mmc);
1086error_disable_clk_ahb:
1087 clk_disable_unprepare(host->clk_ahb);
1088 return ret;
1089}
1090
1091static int sunxi_mmc_probe(struct platform_device *pdev)
1092{
1093 struct sunxi_mmc_host *host;
1094 struct mmc_host *mmc;
1095 int ret;
1096
1097 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1098 if (!mmc) {
1099 dev_err(&pdev->dev, "mmc alloc host failed\n");
1100 return -ENOMEM;
1101 }
1102
1103 host = mmc_priv(mmc);
1104 host->mmc = mmc;
1105 spin_lock_init(&host->lock);
1106
1107 ret = sunxi_mmc_resource_request(host, pdev);
1108 if (ret)
1109 goto error_free_host;
1110
1111 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1112 &host->sg_dma, GFP_KERNEL);
1113 if (!host->sg_cpu) {
1114 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1115 ret = -ENOMEM;
1116 goto error_free_host;
1117 }
1118
1119 mmc->ops = &sunxi_mmc_ops;
1120 mmc->max_blk_count = 8192;
1121 mmc->max_blk_size = 4096;
1122 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1123 mmc->max_seg_size = (1 << host->idma_des_size_bits);
1124 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
1125 /* 400kHz ~ 52MHz */
1126 mmc->f_min = 400000;
1127 mmc->f_max = 52000000;
1128 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1129 MMC_CAP_1_8V_DDR |
1130 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1131
1132 /* TODO MMC DDR is not working on A80 */
1133 if (of_device_is_compatible(pdev->dev.of_node,
1134 "allwinner,sun9i-a80-mmc"))
1135 mmc->caps &= ~MMC_CAP_1_8V_DDR;
1136
1137 ret = mmc_of_parse(mmc);
1138 if (ret)
1139 goto error_free_dma;
1140
1141 ret = mmc_add_host(mmc);
1142 if (ret)
1143 goto error_free_dma;
1144
1145 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1146 platform_set_drvdata(pdev, mmc);
1147 return 0;
1148
1149error_free_dma:
1150 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1151error_free_host:
1152 mmc_free_host(mmc);
1153 return ret;
1154}
1155
1156static int sunxi_mmc_remove(struct platform_device *pdev)
1157{
1158 struct mmc_host *mmc = platform_get_drvdata(pdev);
1159 struct sunxi_mmc_host *host = mmc_priv(mmc);
1160
1161 mmc_remove_host(mmc);
1162 disable_irq(host->irq);
1163 sunxi_mmc_reset_host(host);
1164
1165 if (!IS_ERR(host->reset))
1166 reset_control_assert(host->reset);
1167
1168 clk_disable_unprepare(host->clk_mmc);
1169 clk_disable_unprepare(host->clk_ahb);
1170
1171 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1172 mmc_free_host(mmc);
1173
1174 return 0;
1175}
1176
1177static struct platform_driver sunxi_mmc_driver = {
1178 .driver = {
1179 .name = "sunxi-mmc",
1180 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1181 },
1182 .probe = sunxi_mmc_probe,
1183 .remove = sunxi_mmc_remove,
1184};
1185module_platform_driver(sunxi_mmc_driver);
1186
1187MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1188MODULE_LICENSE("GPL v2");
1189MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1190MODULE_ALIAS("platform:sunxi-mmc");
1/*
2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/io.h>
18#include <linux/device.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22
23#include <linux/clk.h>
24#include <linux/gpio.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27#include <linux/scatterlist.h>
28#include <linux/dma-mapping.h>
29#include <linux/slab.h>
30#include <linux/reset.h>
31#include <linux/regulator/consumer.h>
32
33#include <linux/of_address.h>
34#include <linux/of_gpio.h>
35#include <linux/of_platform.h>
36
37#include <linux/mmc/host.h>
38#include <linux/mmc/sd.h>
39#include <linux/mmc/sdio.h>
40#include <linux/mmc/mmc.h>
41#include <linux/mmc/core.h>
42#include <linux/mmc/card.h>
43#include <linux/mmc/slot-gpio.h>
44
45/* register offset definitions */
46#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
47#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
48#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
49#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
50#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
51#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
52#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
53#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
54#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
55#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
56#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
57#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
58#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
59#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
60#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
61#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
62#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
63#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
64#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
65#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
66#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
67#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
68#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
69#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
70#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
71#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
72#define SDXC_REG_CHDA (0x90)
73#define SDXC_REG_CBDA (0x94)
74
75/* New registers introduced in A64 */
76#define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */
77#define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */
78#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
79#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
80#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
81
82#define mmc_readl(host, reg) \
83 readl((host)->reg_base + SDXC_##reg)
84#define mmc_writel(host, reg, value) \
85 writel((value), (host)->reg_base + SDXC_##reg)
86
87/* global control register bits */
88#define SDXC_SOFT_RESET BIT(0)
89#define SDXC_FIFO_RESET BIT(1)
90#define SDXC_DMA_RESET BIT(2)
91#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
92#define SDXC_DMA_ENABLE_BIT BIT(5)
93#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
94#define SDXC_POSEDGE_LATCH_DATA BIT(9)
95#define SDXC_DDR_MODE BIT(10)
96#define SDXC_MEMORY_ACCESS_DONE BIT(29)
97#define SDXC_ACCESS_DONE_DIRECT BIT(30)
98#define SDXC_ACCESS_BY_AHB BIT(31)
99#define SDXC_ACCESS_BY_DMA (0 << 31)
100#define SDXC_HARDWARE_RESET \
101 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
102
103/* clock control bits */
104#define SDXC_CARD_CLOCK_ON BIT(16)
105#define SDXC_LOW_POWER_ON BIT(17)
106
107/* bus width */
108#define SDXC_WIDTH1 0
109#define SDXC_WIDTH4 1
110#define SDXC_WIDTH8 2
111
112/* smc command bits */
113#define SDXC_RESP_EXPIRE BIT(6)
114#define SDXC_LONG_RESPONSE BIT(7)
115#define SDXC_CHECK_RESPONSE_CRC BIT(8)
116#define SDXC_DATA_EXPIRE BIT(9)
117#define SDXC_WRITE BIT(10)
118#define SDXC_SEQUENCE_MODE BIT(11)
119#define SDXC_SEND_AUTO_STOP BIT(12)
120#define SDXC_WAIT_PRE_OVER BIT(13)
121#define SDXC_STOP_ABORT_CMD BIT(14)
122#define SDXC_SEND_INIT_SEQUENCE BIT(15)
123#define SDXC_UPCLK_ONLY BIT(21)
124#define SDXC_READ_CEATA_DEV BIT(22)
125#define SDXC_CCS_EXPIRE BIT(23)
126#define SDXC_ENABLE_BIT_BOOT BIT(24)
127#define SDXC_ALT_BOOT_OPTIONS BIT(25)
128#define SDXC_BOOT_ACK_EXPIRE BIT(26)
129#define SDXC_BOOT_ABORT BIT(27)
130#define SDXC_VOLTAGE_SWITCH BIT(28)
131#define SDXC_USE_HOLD_REGISTER BIT(29)
132#define SDXC_START BIT(31)
133
134/* interrupt bits */
135#define SDXC_RESP_ERROR BIT(1)
136#define SDXC_COMMAND_DONE BIT(2)
137#define SDXC_DATA_OVER BIT(3)
138#define SDXC_TX_DATA_REQUEST BIT(4)
139#define SDXC_RX_DATA_REQUEST BIT(5)
140#define SDXC_RESP_CRC_ERROR BIT(6)
141#define SDXC_DATA_CRC_ERROR BIT(7)
142#define SDXC_RESP_TIMEOUT BIT(8)
143#define SDXC_DATA_TIMEOUT BIT(9)
144#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
145#define SDXC_FIFO_RUN_ERROR BIT(11)
146#define SDXC_HARD_WARE_LOCKED BIT(12)
147#define SDXC_START_BIT_ERROR BIT(13)
148#define SDXC_AUTO_COMMAND_DONE BIT(14)
149#define SDXC_END_BIT_ERROR BIT(15)
150#define SDXC_SDIO_INTERRUPT BIT(16)
151#define SDXC_CARD_INSERT BIT(30)
152#define SDXC_CARD_REMOVE BIT(31)
153#define SDXC_INTERRUPT_ERROR_BIT \
154 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
155 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
156 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
157#define SDXC_INTERRUPT_DONE_BIT \
158 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
159 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
160
161/* status */
162#define SDXC_RXWL_FLAG BIT(0)
163#define SDXC_TXWL_FLAG BIT(1)
164#define SDXC_FIFO_EMPTY BIT(2)
165#define SDXC_FIFO_FULL BIT(3)
166#define SDXC_CARD_PRESENT BIT(8)
167#define SDXC_CARD_DATA_BUSY BIT(9)
168#define SDXC_DATA_FSM_BUSY BIT(10)
169#define SDXC_DMA_REQUEST BIT(31)
170#define SDXC_FIFO_SIZE 16
171
172/* Function select */
173#define SDXC_CEATA_ON (0xceaa << 16)
174#define SDXC_SEND_IRQ_RESPONSE BIT(0)
175#define SDXC_SDIO_READ_WAIT BIT(1)
176#define SDXC_ABORT_READ_DATA BIT(2)
177#define SDXC_SEND_CCSD BIT(8)
178#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
179#define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
180
181/* IDMA controller bus mod bit field */
182#define SDXC_IDMAC_SOFT_RESET BIT(0)
183#define SDXC_IDMAC_FIX_BURST BIT(1)
184#define SDXC_IDMAC_IDMA_ON BIT(7)
185#define SDXC_IDMAC_REFETCH_DES BIT(31)
186
187/* IDMA status bit field */
188#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
189#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
190#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
191#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
192#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
193#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
194#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
195#define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
196#define SDXC_IDMAC_IDLE (0 << 13)
197#define SDXC_IDMAC_SUSPEND (1 << 13)
198#define SDXC_IDMAC_DESC_READ (2 << 13)
199#define SDXC_IDMAC_DESC_CHECK (3 << 13)
200#define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
201#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
202#define SDXC_IDMAC_READ (6 << 13)
203#define SDXC_IDMAC_WRITE (7 << 13)
204#define SDXC_IDMAC_DESC_CLOSE (8 << 13)
205
206/*
207* If the idma-des-size-bits of property is ie 13, bufsize bits are:
208* Bits 0-12: buf1 size
209* Bits 13-25: buf2 size
210* Bits 26-31: not used
211* Since we only ever set buf1 size, we can simply store it directly.
212*/
213#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
214#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
215#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
216#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
217#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
218#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
219#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
220
221#define SDXC_CLK_400K 0
222#define SDXC_CLK_25M 1
223#define SDXC_CLK_50M 2
224#define SDXC_CLK_50M_DDR 3
225#define SDXC_CLK_50M_DDR_8BIT 4
226
227#define SDXC_2X_TIMING_MODE BIT(31)
228
229#define SDXC_CAL_START BIT(15)
230#define SDXC_CAL_DONE BIT(14)
231#define SDXC_CAL_DL_SHIFT 8
232#define SDXC_CAL_DL_SW_EN BIT(7)
233#define SDXC_CAL_DL_SW_SHIFT 0
234#define SDXC_CAL_DL_MASK 0x3f
235
236#define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
237
238struct sunxi_mmc_clk_delay {
239 u32 output;
240 u32 sample;
241};
242
243struct sunxi_idma_des {
244 __le32 config;
245 __le32 buf_size;
246 __le32 buf_addr_ptr1;
247 __le32 buf_addr_ptr2;
248};
249
250struct sunxi_mmc_cfg {
251 u32 idma_des_size_bits;
252 const struct sunxi_mmc_clk_delay *clk_delays;
253
254 /* does the IP block support autocalibration? */
255 bool can_calibrate;
256};
257
258struct sunxi_mmc_host {
259 struct mmc_host *mmc;
260 struct reset_control *reset;
261 const struct sunxi_mmc_cfg *cfg;
262
263 /* IO mapping base */
264 void __iomem *reg_base;
265
266 /* clock management */
267 struct clk *clk_ahb;
268 struct clk *clk_mmc;
269 struct clk *clk_sample;
270 struct clk *clk_output;
271
272 /* irq */
273 spinlock_t lock;
274 int irq;
275 u32 int_sum;
276 u32 sdio_imask;
277
278 /* dma */
279 dma_addr_t sg_dma;
280 void *sg_cpu;
281 bool wait_dma;
282
283 struct mmc_request *mrq;
284 struct mmc_request *manual_stop_mrq;
285 int ferror;
286
287 /* vqmmc */
288 bool vqmmc_enabled;
289};
290
291static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
292{
293 unsigned long expire = jiffies + msecs_to_jiffies(250);
294 u32 rval;
295
296 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
297 do {
298 rval = mmc_readl(host, REG_GCTRL);
299 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
300
301 if (rval & SDXC_HARDWARE_RESET) {
302 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
303 return -EIO;
304 }
305
306 return 0;
307}
308
309static int sunxi_mmc_init_host(struct mmc_host *mmc)
310{
311 u32 rval;
312 struct sunxi_mmc_host *host = mmc_priv(mmc);
313
314 if (sunxi_mmc_reset_host(host))
315 return -EIO;
316
317 /*
318 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
319 *
320 * TODO: sun9i has a larger FIFO and supports higher trigger values
321 */
322 mmc_writel(host, REG_FTRGL, 0x20070008);
323 /* Maximum timeout value */
324 mmc_writel(host, REG_TMOUT, 0xffffffff);
325 /* Unmask SDIO interrupt if needed */
326 mmc_writel(host, REG_IMASK, host->sdio_imask);
327 /* Clear all pending interrupts */
328 mmc_writel(host, REG_RINTR, 0xffffffff);
329 /* Debug register? undocumented */
330 mmc_writel(host, REG_DBGC, 0xdeb);
331 /* Enable CEATA support */
332 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
333 /* Set DMA descriptor list base address */
334 mmc_writel(host, REG_DLBA, host->sg_dma);
335
336 rval = mmc_readl(host, REG_GCTRL);
337 rval |= SDXC_INTERRUPT_ENABLE_BIT;
338 /* Undocumented, but found in Allwinner code */
339 rval &= ~SDXC_ACCESS_DONE_DIRECT;
340 mmc_writel(host, REG_GCTRL, rval);
341
342 return 0;
343}
344
345static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
346 struct mmc_data *data)
347{
348 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
349 dma_addr_t next_desc = host->sg_dma;
350 int i, max_len = (1 << host->cfg->idma_des_size_bits);
351
352 for (i = 0; i < data->sg_len; i++) {
353 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
354 SDXC_IDMAC_DES0_OWN |
355 SDXC_IDMAC_DES0_DIC);
356
357 if (data->sg[i].length == max_len)
358 pdes[i].buf_size = 0; /* 0 == max_len */
359 else
360 pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
361
362 next_desc += sizeof(struct sunxi_idma_des);
363 pdes[i].buf_addr_ptr1 =
364 cpu_to_le32(sg_dma_address(&data->sg[i]));
365 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
366 }
367
368 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
369 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
370 SDXC_IDMAC_DES0_ER);
371 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
372 pdes[i - 1].buf_addr_ptr2 = 0;
373
374 /*
375 * Avoid the io-store starting the idmac hitting io-mem before the
376 * descriptors hit the main-mem.
377 */
378 wmb();
379}
380
381static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
382{
383 if (data->flags & MMC_DATA_WRITE)
384 return DMA_TO_DEVICE;
385 else
386 return DMA_FROM_DEVICE;
387}
388
389static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
390 struct mmc_data *data)
391{
392 u32 i, dma_len;
393 struct scatterlist *sg;
394
395 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
396 sunxi_mmc_get_dma_dir(data));
397 if (dma_len == 0) {
398 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
399 return -ENOMEM;
400 }
401
402 for_each_sg(data->sg, sg, data->sg_len, i) {
403 if (sg->offset & 3 || sg->length & 3) {
404 dev_err(mmc_dev(host->mmc),
405 "unaligned scatterlist: os %x length %d\n",
406 sg->offset, sg->length);
407 return -EINVAL;
408 }
409 }
410
411 return 0;
412}
413
414static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
415 struct mmc_data *data)
416{
417 u32 rval;
418
419 sunxi_mmc_init_idma_des(host, data);
420
421 rval = mmc_readl(host, REG_GCTRL);
422 rval |= SDXC_DMA_ENABLE_BIT;
423 mmc_writel(host, REG_GCTRL, rval);
424 rval |= SDXC_DMA_RESET;
425 mmc_writel(host, REG_GCTRL, rval);
426
427 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
428
429 if (!(data->flags & MMC_DATA_WRITE))
430 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
431
432 mmc_writel(host, REG_DMAC,
433 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
434}
435
436static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
437 struct mmc_request *req)
438{
439 u32 arg, cmd_val, ri;
440 unsigned long expire = jiffies + msecs_to_jiffies(1000);
441
442 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
443 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
444
445 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
446 cmd_val |= SD_IO_RW_DIRECT;
447 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
448 ((req->cmd->arg >> 28) & 0x7);
449 } else {
450 cmd_val |= MMC_STOP_TRANSMISSION;
451 arg = 0;
452 }
453
454 mmc_writel(host, REG_CARG, arg);
455 mmc_writel(host, REG_CMDR, cmd_val);
456
457 do {
458 ri = mmc_readl(host, REG_RINTR);
459 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
460 time_before(jiffies, expire));
461
462 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
463 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
464 if (req->stop)
465 req->stop->resp[0] = -ETIMEDOUT;
466 } else {
467 if (req->stop)
468 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
469 }
470
471 mmc_writel(host, REG_RINTR, 0xffff);
472}
473
474static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
475{
476 struct mmc_command *cmd = host->mrq->cmd;
477 struct mmc_data *data = host->mrq->data;
478
479 /* For some cmds timeout is normal with sd/mmc cards */
480 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
481 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
482 cmd->opcode == SD_IO_RW_DIRECT))
483 return;
484
485 dev_err(mmc_dev(host->mmc),
486 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
487 host->mmc->index, cmd->opcode,
488 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
489 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
490 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
491 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
492 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
493 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
494 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
495 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
496 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
497 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
498 );
499}
500
501/* Called in interrupt context! */
502static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
503{
504 struct mmc_request *mrq = host->mrq;
505 struct mmc_data *data = mrq->data;
506 u32 rval;
507
508 mmc_writel(host, REG_IMASK, host->sdio_imask);
509 mmc_writel(host, REG_IDIE, 0);
510
511 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
512 sunxi_mmc_dump_errinfo(host);
513 mrq->cmd->error = -ETIMEDOUT;
514
515 if (data) {
516 data->error = -ETIMEDOUT;
517 host->manual_stop_mrq = mrq;
518 }
519
520 if (mrq->stop)
521 mrq->stop->error = -ETIMEDOUT;
522 } else {
523 if (mrq->cmd->flags & MMC_RSP_136) {
524 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
525 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
526 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
527 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
528 } else {
529 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
530 }
531
532 if (data)
533 data->bytes_xfered = data->blocks * data->blksz;
534 }
535
536 if (data) {
537 mmc_writel(host, REG_IDST, 0x337);
538 mmc_writel(host, REG_DMAC, 0);
539 rval = mmc_readl(host, REG_GCTRL);
540 rval |= SDXC_DMA_RESET;
541 mmc_writel(host, REG_GCTRL, rval);
542 rval &= ~SDXC_DMA_ENABLE_BIT;
543 mmc_writel(host, REG_GCTRL, rval);
544 rval |= SDXC_FIFO_RESET;
545 mmc_writel(host, REG_GCTRL, rval);
546 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
547 sunxi_mmc_get_dma_dir(data));
548 }
549
550 mmc_writel(host, REG_RINTR, 0xffff);
551
552 host->mrq = NULL;
553 host->int_sum = 0;
554 host->wait_dma = false;
555
556 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
557}
558
559static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
560{
561 struct sunxi_mmc_host *host = dev_id;
562 struct mmc_request *mrq;
563 u32 msk_int, idma_int;
564 bool finalize = false;
565 bool sdio_int = false;
566 irqreturn_t ret = IRQ_HANDLED;
567
568 spin_lock(&host->lock);
569
570 idma_int = mmc_readl(host, REG_IDST);
571 msk_int = mmc_readl(host, REG_MISTA);
572
573 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
574 host->mrq, msk_int, idma_int);
575
576 mrq = host->mrq;
577 if (mrq) {
578 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
579 host->wait_dma = false;
580
581 host->int_sum |= msk_int;
582
583 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
584 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
585 !(host->int_sum & SDXC_COMMAND_DONE))
586 mmc_writel(host, REG_IMASK,
587 host->sdio_imask | SDXC_COMMAND_DONE);
588 /* Don't wait for dma on error */
589 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
590 finalize = true;
591 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
592 !host->wait_dma)
593 finalize = true;
594 }
595
596 if (msk_int & SDXC_SDIO_INTERRUPT)
597 sdio_int = true;
598
599 mmc_writel(host, REG_RINTR, msk_int);
600 mmc_writel(host, REG_IDST, idma_int);
601
602 if (finalize)
603 ret = sunxi_mmc_finalize_request(host);
604
605 spin_unlock(&host->lock);
606
607 if (finalize && ret == IRQ_HANDLED)
608 mmc_request_done(host->mmc, mrq);
609
610 if (sdio_int)
611 mmc_signal_sdio_irq(host->mmc);
612
613 return ret;
614}
615
616static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
617{
618 struct sunxi_mmc_host *host = dev_id;
619 struct mmc_request *mrq;
620 unsigned long iflags;
621
622 spin_lock_irqsave(&host->lock, iflags);
623 mrq = host->manual_stop_mrq;
624 spin_unlock_irqrestore(&host->lock, iflags);
625
626 if (!mrq) {
627 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
628 return IRQ_HANDLED;
629 }
630
631 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
632
633 /*
634 * We will never have more than one outstanding request,
635 * and we do not complete the request until after
636 * we've cleared host->manual_stop_mrq so we do not need to
637 * spin lock this function.
638 * Additionally we have wait states within this function
639 * so having it in a lock is a very bad idea.
640 */
641 sunxi_mmc_send_manual_stop(host, mrq);
642
643 spin_lock_irqsave(&host->lock, iflags);
644 host->manual_stop_mrq = NULL;
645 spin_unlock_irqrestore(&host->lock, iflags);
646
647 mmc_request_done(host->mmc, mrq);
648
649 return IRQ_HANDLED;
650}
651
652static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
653{
654 unsigned long expire = jiffies + msecs_to_jiffies(750);
655 u32 rval;
656
657 rval = mmc_readl(host, REG_CLKCR);
658 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
659
660 if (oclk_en)
661 rval |= SDXC_CARD_CLOCK_ON;
662
663 mmc_writel(host, REG_CLKCR, rval);
664
665 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
666 mmc_writel(host, REG_CMDR, rval);
667
668 do {
669 rval = mmc_readl(host, REG_CMDR);
670 } while (time_before(jiffies, expire) && (rval & SDXC_START));
671
672 /* clear irq status bits set by the command */
673 mmc_writel(host, REG_RINTR,
674 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
675
676 if (rval & SDXC_START) {
677 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
678 return -EIO;
679 }
680
681 return 0;
682}
683
684static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
685{
686 u32 reg = readl(host->reg_base + reg_off);
687 u32 delay;
688 unsigned long timeout;
689
690 if (!host->cfg->can_calibrate)
691 return 0;
692
693 reg &= ~(SDXC_CAL_DL_MASK << SDXC_CAL_DL_SW_SHIFT);
694 reg &= ~SDXC_CAL_DL_SW_EN;
695
696 writel(reg | SDXC_CAL_START, host->reg_base + reg_off);
697
698 dev_dbg(mmc_dev(host->mmc), "calibration started\n");
699
700 timeout = jiffies + HZ * SDXC_CAL_TIMEOUT;
701
702 while (!((reg = readl(host->reg_base + reg_off)) & SDXC_CAL_DONE)) {
703 if (time_before(jiffies, timeout))
704 cpu_relax();
705 else {
706 reg &= ~SDXC_CAL_START;
707 writel(reg, host->reg_base + reg_off);
708
709 return -ETIMEDOUT;
710 }
711 }
712
713 delay = (reg >> SDXC_CAL_DL_SHIFT) & SDXC_CAL_DL_MASK;
714
715 reg &= ~SDXC_CAL_START;
716 reg |= (delay << SDXC_CAL_DL_SW_SHIFT) | SDXC_CAL_DL_SW_EN;
717
718 writel(reg, host->reg_base + reg_off);
719
720 dev_dbg(mmc_dev(host->mmc), "calibration ended, reg is 0x%x\n", reg);
721
722 return 0;
723}
724
725static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
726 struct mmc_ios *ios, u32 rate)
727{
728 int index;
729
730 if (!host->cfg->clk_delays)
731 return 0;
732
733 /* determine delays */
734 if (rate <= 400000) {
735 index = SDXC_CLK_400K;
736 } else if (rate <= 25000000) {
737 index = SDXC_CLK_25M;
738 } else if (rate <= 52000000) {
739 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
740 ios->timing != MMC_TIMING_MMC_DDR52) {
741 index = SDXC_CLK_50M;
742 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
743 index = SDXC_CLK_50M_DDR_8BIT;
744 } else {
745 index = SDXC_CLK_50M_DDR;
746 }
747 } else {
748 return -EINVAL;
749 }
750
751 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
752 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
753
754 return 0;
755}
756
757static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
758 struct mmc_ios *ios)
759{
760 long rate;
761 u32 rval, clock = ios->clock;
762 int ret;
763
764 /* 8 bit DDR requires a higher module clock */
765 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
766 ios->bus_width == MMC_BUS_WIDTH_8)
767 clock <<= 1;
768
769 rate = clk_round_rate(host->clk_mmc, clock);
770 if (rate < 0) {
771 dev_err(mmc_dev(host->mmc), "error rounding clk to %d: %ld\n",
772 clock, rate);
773 return rate;
774 }
775 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %ld\n",
776 clock, rate);
777
778 /* setting clock rate */
779 ret = clk_set_rate(host->clk_mmc, rate);
780 if (ret) {
781 dev_err(mmc_dev(host->mmc), "error setting clk to %ld: %d\n",
782 rate, ret);
783 return ret;
784 }
785
786 ret = sunxi_mmc_oclk_onoff(host, 0);
787 if (ret)
788 return ret;
789
790 /* clear internal divider */
791 rval = mmc_readl(host, REG_CLKCR);
792 rval &= ~0xff;
793 /* set internal divider for 8 bit eMMC DDR, so card clock is right */
794 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
795 ios->bus_width == MMC_BUS_WIDTH_8) {
796 rval |= 1;
797 rate >>= 1;
798 }
799 mmc_writel(host, REG_CLKCR, rval);
800
801 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
802 if (ret)
803 return ret;
804
805 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
806 if (ret)
807 return ret;
808
809 /* TODO: enable calibrate on sdc2 SDXC_REG_DS_DL_REG of A64 */
810
811 return sunxi_mmc_oclk_onoff(host, 1);
812}
813
814static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
815{
816 struct sunxi_mmc_host *host = mmc_priv(mmc);
817 u32 rval;
818
819 /* Set the power state */
820 switch (ios->power_mode) {
821 case MMC_POWER_ON:
822 break;
823
824 case MMC_POWER_UP:
825 if (!IS_ERR(mmc->supply.vmmc)) {
826 host->ferror = mmc_regulator_set_ocr(mmc,
827 mmc->supply.vmmc,
828 ios->vdd);
829 if (host->ferror)
830 return;
831 }
832
833 if (!IS_ERR(mmc->supply.vqmmc)) {
834 host->ferror = regulator_enable(mmc->supply.vqmmc);
835 if (host->ferror) {
836 dev_err(mmc_dev(mmc),
837 "failed to enable vqmmc\n");
838 return;
839 }
840 host->vqmmc_enabled = true;
841 }
842
843 host->ferror = sunxi_mmc_init_host(mmc);
844 if (host->ferror)
845 return;
846
847 dev_dbg(mmc_dev(mmc), "power on!\n");
848 break;
849
850 case MMC_POWER_OFF:
851 dev_dbg(mmc_dev(mmc), "power off!\n");
852 sunxi_mmc_reset_host(host);
853 if (!IS_ERR(mmc->supply.vmmc))
854 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
855
856 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
857 regulator_disable(mmc->supply.vqmmc);
858 host->vqmmc_enabled = false;
859 break;
860 }
861
862 /* set bus width */
863 switch (ios->bus_width) {
864 case MMC_BUS_WIDTH_1:
865 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
866 break;
867 case MMC_BUS_WIDTH_4:
868 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
869 break;
870 case MMC_BUS_WIDTH_8:
871 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
872 break;
873 }
874
875 /* set ddr mode */
876 rval = mmc_readl(host, REG_GCTRL);
877 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
878 ios->timing == MMC_TIMING_MMC_DDR52)
879 rval |= SDXC_DDR_MODE;
880 else
881 rval &= ~SDXC_DDR_MODE;
882 mmc_writel(host, REG_GCTRL, rval);
883
884 /* set up clock */
885 if (ios->clock && ios->power_mode) {
886 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
887 /* Android code had a usleep_range(50000, 55000); here */
888 }
889}
890
891static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
892{
893 /* vqmmc regulator is available */
894 if (!IS_ERR(mmc->supply.vqmmc))
895 return mmc_regulator_set_vqmmc(mmc, ios);
896
897 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
898 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
899 return 0;
900
901 return -EINVAL;
902}
903
904static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
905{
906 struct sunxi_mmc_host *host = mmc_priv(mmc);
907 unsigned long flags;
908 u32 imask;
909
910 spin_lock_irqsave(&host->lock, flags);
911
912 imask = mmc_readl(host, REG_IMASK);
913 if (enable) {
914 host->sdio_imask = SDXC_SDIO_INTERRUPT;
915 imask |= SDXC_SDIO_INTERRUPT;
916 } else {
917 host->sdio_imask = 0;
918 imask &= ~SDXC_SDIO_INTERRUPT;
919 }
920 mmc_writel(host, REG_IMASK, imask);
921 spin_unlock_irqrestore(&host->lock, flags);
922}
923
924static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
925{
926 struct sunxi_mmc_host *host = mmc_priv(mmc);
927 mmc_writel(host, REG_HWRST, 0);
928 udelay(10);
929 mmc_writel(host, REG_HWRST, 1);
930 udelay(300);
931}
932
933static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
934{
935 struct sunxi_mmc_host *host = mmc_priv(mmc);
936 struct mmc_command *cmd = mrq->cmd;
937 struct mmc_data *data = mrq->data;
938 unsigned long iflags;
939 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
940 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
941 bool wait_dma = host->wait_dma;
942 int ret;
943
944 /* Check for set_ios errors (should never happen) */
945 if (host->ferror) {
946 mrq->cmd->error = host->ferror;
947 mmc_request_done(mmc, mrq);
948 return;
949 }
950
951 if (data) {
952 ret = sunxi_mmc_map_dma(host, data);
953 if (ret < 0) {
954 dev_err(mmc_dev(mmc), "map DMA failed\n");
955 cmd->error = ret;
956 data->error = ret;
957 mmc_request_done(mmc, mrq);
958 return;
959 }
960 }
961
962 if (cmd->opcode == MMC_GO_IDLE_STATE) {
963 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
964 imask |= SDXC_COMMAND_DONE;
965 }
966
967 if (cmd->flags & MMC_RSP_PRESENT) {
968 cmd_val |= SDXC_RESP_EXPIRE;
969 if (cmd->flags & MMC_RSP_136)
970 cmd_val |= SDXC_LONG_RESPONSE;
971 if (cmd->flags & MMC_RSP_CRC)
972 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
973
974 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
975 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
976
977 if (cmd->data->stop) {
978 imask |= SDXC_AUTO_COMMAND_DONE;
979 cmd_val |= SDXC_SEND_AUTO_STOP;
980 } else {
981 imask |= SDXC_DATA_OVER;
982 }
983
984 if (cmd->data->flags & MMC_DATA_WRITE)
985 cmd_val |= SDXC_WRITE;
986 else
987 wait_dma = true;
988 } else {
989 imask |= SDXC_COMMAND_DONE;
990 }
991 } else {
992 imask |= SDXC_COMMAND_DONE;
993 }
994
995 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
996 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
997 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
998
999 spin_lock_irqsave(&host->lock, iflags);
1000
1001 if (host->mrq || host->manual_stop_mrq) {
1002 spin_unlock_irqrestore(&host->lock, iflags);
1003
1004 if (data)
1005 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1006 sunxi_mmc_get_dma_dir(data));
1007
1008 dev_err(mmc_dev(mmc), "request already pending\n");
1009 mrq->cmd->error = -EBUSY;
1010 mmc_request_done(mmc, mrq);
1011 return;
1012 }
1013
1014 if (data) {
1015 mmc_writel(host, REG_BLKSZ, data->blksz);
1016 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1017 sunxi_mmc_start_dma(host, data);
1018 }
1019
1020 host->mrq = mrq;
1021 host->wait_dma = wait_dma;
1022 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1023 mmc_writel(host, REG_CARG, cmd->arg);
1024 mmc_writel(host, REG_CMDR, cmd_val);
1025
1026 spin_unlock_irqrestore(&host->lock, iflags);
1027}
1028
1029static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1030{
1031 struct sunxi_mmc_host *host = mmc_priv(mmc);
1032
1033 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1034}
1035
1036static struct mmc_host_ops sunxi_mmc_ops = {
1037 .request = sunxi_mmc_request,
1038 .set_ios = sunxi_mmc_set_ios,
1039 .get_ro = mmc_gpio_get_ro,
1040 .get_cd = mmc_gpio_get_cd,
1041 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1042 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
1043 .hw_reset = sunxi_mmc_hw_reset,
1044 .card_busy = sunxi_mmc_card_busy,
1045};
1046
1047static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1048 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1049 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1050 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
1051 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
1052 /* Value from A83T "new timing mode". Works but might not be right. */
1053 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
1054};
1055
1056static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1057 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1058 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1059 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
1060 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
1061 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
1062};
1063
1064static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1065 .idma_des_size_bits = 13,
1066 .clk_delays = NULL,
1067 .can_calibrate = false,
1068};
1069
1070static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
1071 .idma_des_size_bits = 16,
1072 .clk_delays = NULL,
1073 .can_calibrate = false,
1074};
1075
1076static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
1077 .idma_des_size_bits = 16,
1078 .clk_delays = sunxi_mmc_clk_delays,
1079 .can_calibrate = false,
1080};
1081
1082static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1083 .idma_des_size_bits = 16,
1084 .clk_delays = sun9i_mmc_clk_delays,
1085 .can_calibrate = false,
1086};
1087
1088static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1089 .idma_des_size_bits = 16,
1090 .clk_delays = NULL,
1091 .can_calibrate = true,
1092};
1093
1094static const struct of_device_id sunxi_mmc_of_match[] = {
1095 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1096 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1097 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1098 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1099 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1100 { /* sentinel */ }
1101};
1102MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1103
1104static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1105 struct platform_device *pdev)
1106{
1107 int ret;
1108
1109 host->cfg = of_device_get_match_data(&pdev->dev);
1110 if (!host->cfg)
1111 return -EINVAL;
1112
1113 ret = mmc_regulator_get_supply(host->mmc);
1114 if (ret) {
1115 if (ret != -EPROBE_DEFER)
1116 dev_err(&pdev->dev, "Could not get vmmc supply\n");
1117 return ret;
1118 }
1119
1120 host->reg_base = devm_ioremap_resource(&pdev->dev,
1121 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1122 if (IS_ERR(host->reg_base))
1123 return PTR_ERR(host->reg_base);
1124
1125 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1126 if (IS_ERR(host->clk_ahb)) {
1127 dev_err(&pdev->dev, "Could not get ahb clock\n");
1128 return PTR_ERR(host->clk_ahb);
1129 }
1130
1131 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1132 if (IS_ERR(host->clk_mmc)) {
1133 dev_err(&pdev->dev, "Could not get mmc clock\n");
1134 return PTR_ERR(host->clk_mmc);
1135 }
1136
1137 if (host->cfg->clk_delays) {
1138 host->clk_output = devm_clk_get(&pdev->dev, "output");
1139 if (IS_ERR(host->clk_output)) {
1140 dev_err(&pdev->dev, "Could not get output clock\n");
1141 return PTR_ERR(host->clk_output);
1142 }
1143
1144 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1145 if (IS_ERR(host->clk_sample)) {
1146 dev_err(&pdev->dev, "Could not get sample clock\n");
1147 return PTR_ERR(host->clk_sample);
1148 }
1149 }
1150
1151 host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1152 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1153 return PTR_ERR(host->reset);
1154
1155 ret = clk_prepare_enable(host->clk_ahb);
1156 if (ret) {
1157 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1158 return ret;
1159 }
1160
1161 ret = clk_prepare_enable(host->clk_mmc);
1162 if (ret) {
1163 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1164 goto error_disable_clk_ahb;
1165 }
1166
1167 ret = clk_prepare_enable(host->clk_output);
1168 if (ret) {
1169 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1170 goto error_disable_clk_mmc;
1171 }
1172
1173 ret = clk_prepare_enable(host->clk_sample);
1174 if (ret) {
1175 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1176 goto error_disable_clk_output;
1177 }
1178
1179 if (!IS_ERR(host->reset)) {
1180 ret = reset_control_deassert(host->reset);
1181 if (ret) {
1182 dev_err(&pdev->dev, "reset err %d\n", ret);
1183 goto error_disable_clk_sample;
1184 }
1185 }
1186
1187 /*
1188 * Sometimes the controller asserts the irq on boot for some reason,
1189 * make sure the controller is in a sane state before enabling irqs.
1190 */
1191 ret = sunxi_mmc_reset_host(host);
1192 if (ret)
1193 goto error_assert_reset;
1194
1195 host->irq = platform_get_irq(pdev, 0);
1196 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1197 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1198
1199error_assert_reset:
1200 if (!IS_ERR(host->reset))
1201 reset_control_assert(host->reset);
1202error_disable_clk_sample:
1203 clk_disable_unprepare(host->clk_sample);
1204error_disable_clk_output:
1205 clk_disable_unprepare(host->clk_output);
1206error_disable_clk_mmc:
1207 clk_disable_unprepare(host->clk_mmc);
1208error_disable_clk_ahb:
1209 clk_disable_unprepare(host->clk_ahb);
1210 return ret;
1211}
1212
1213static int sunxi_mmc_probe(struct platform_device *pdev)
1214{
1215 struct sunxi_mmc_host *host;
1216 struct mmc_host *mmc;
1217 int ret;
1218
1219 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1220 if (!mmc) {
1221 dev_err(&pdev->dev, "mmc alloc host failed\n");
1222 return -ENOMEM;
1223 }
1224
1225 host = mmc_priv(mmc);
1226 host->mmc = mmc;
1227 spin_lock_init(&host->lock);
1228
1229 ret = sunxi_mmc_resource_request(host, pdev);
1230 if (ret)
1231 goto error_free_host;
1232
1233 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1234 &host->sg_dma, GFP_KERNEL);
1235 if (!host->sg_cpu) {
1236 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1237 ret = -ENOMEM;
1238 goto error_free_host;
1239 }
1240
1241 mmc->ops = &sunxi_mmc_ops;
1242 mmc->max_blk_count = 8192;
1243 mmc->max_blk_size = 4096;
1244 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1245 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
1246 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
1247 /* 400kHz ~ 52MHz */
1248 mmc->f_min = 400000;
1249 mmc->f_max = 52000000;
1250 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1251 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1252
1253 if (host->cfg->clk_delays)
1254 mmc->caps |= MMC_CAP_1_8V_DDR;
1255
1256 ret = mmc_of_parse(mmc);
1257 if (ret)
1258 goto error_free_dma;
1259
1260 ret = mmc_add_host(mmc);
1261 if (ret)
1262 goto error_free_dma;
1263
1264 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1265 platform_set_drvdata(pdev, mmc);
1266 return 0;
1267
1268error_free_dma:
1269 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1270error_free_host:
1271 mmc_free_host(mmc);
1272 return ret;
1273}
1274
1275static int sunxi_mmc_remove(struct platform_device *pdev)
1276{
1277 struct mmc_host *mmc = platform_get_drvdata(pdev);
1278 struct sunxi_mmc_host *host = mmc_priv(mmc);
1279
1280 mmc_remove_host(mmc);
1281 disable_irq(host->irq);
1282 sunxi_mmc_reset_host(host);
1283
1284 if (!IS_ERR(host->reset))
1285 reset_control_assert(host->reset);
1286
1287 clk_disable_unprepare(host->clk_sample);
1288 clk_disable_unprepare(host->clk_output);
1289 clk_disable_unprepare(host->clk_mmc);
1290 clk_disable_unprepare(host->clk_ahb);
1291
1292 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1293 mmc_free_host(mmc);
1294
1295 return 0;
1296}
1297
1298static struct platform_driver sunxi_mmc_driver = {
1299 .driver = {
1300 .name = "sunxi-mmc",
1301 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1302 },
1303 .probe = sunxi_mmc_probe,
1304 .remove = sunxi_mmc_remove,
1305};
1306module_platform_driver(sunxi_mmc_driver);
1307
1308MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1309MODULE_LICENSE("GPL v2");
1310MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1311MODULE_ALIAS("platform:sunxi-mmc");