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1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SD/MMC controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/mmc/host.h>
17#include <linux/mmc/slot-gpio.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/delay.h>
25#include <linux/scatterlist.h>
26#include <linux/clk.h>
27
28#include <linux/bitops.h>
29#include <linux/gpio.h>
30#include <asm/mach-jz4740/gpio.h>
31#include <asm/cacheflush.h>
32#include <linux/dma-mapping.h>
33#include <linux/dmaengine.h>
34
35#include <asm/mach-jz4740/dma.h>
36#include <asm/mach-jz4740/jz4740_mmc.h>
37
38#define JZ_REG_MMC_STRPCL 0x00
39#define JZ_REG_MMC_STATUS 0x04
40#define JZ_REG_MMC_CLKRT 0x08
41#define JZ_REG_MMC_CMDAT 0x0C
42#define JZ_REG_MMC_RESTO 0x10
43#define JZ_REG_MMC_RDTO 0x14
44#define JZ_REG_MMC_BLKLEN 0x18
45#define JZ_REG_MMC_NOB 0x1C
46#define JZ_REG_MMC_SNOB 0x20
47#define JZ_REG_MMC_IMASK 0x24
48#define JZ_REG_MMC_IREG 0x28
49#define JZ_REG_MMC_CMD 0x2C
50#define JZ_REG_MMC_ARG 0x30
51#define JZ_REG_MMC_RESP_FIFO 0x34
52#define JZ_REG_MMC_RXFIFO 0x38
53#define JZ_REG_MMC_TXFIFO 0x3C
54
55#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
56#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
57#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
58#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
59#define JZ_MMC_STRPCL_RESET BIT(3)
60#define JZ_MMC_STRPCL_START_OP BIT(2)
61#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
62#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
63#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
64
65
66#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
67#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
68#define JZ_MMC_STATUS_PRG_DONE BIT(13)
69#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
70#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
71#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
72#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
73#define JZ_MMC_STATUS_CLK_EN BIT(8)
74#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
75#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
76#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
77#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
78#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
79#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
80#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
81#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
82
83#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
84#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
85
86
87#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
88#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
89#define JZ_MMC_CMDAT_DMA_EN BIT(8)
90#define JZ_MMC_CMDAT_INIT BIT(7)
91#define JZ_MMC_CMDAT_BUSY BIT(6)
92#define JZ_MMC_CMDAT_STREAM BIT(5)
93#define JZ_MMC_CMDAT_WRITE BIT(4)
94#define JZ_MMC_CMDAT_DATA_EN BIT(3)
95#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
96#define JZ_MMC_CMDAT_RSP_R1 1
97#define JZ_MMC_CMDAT_RSP_R2 2
98#define JZ_MMC_CMDAT_RSP_R3 3
99
100#define JZ_MMC_IRQ_SDIO BIT(7)
101#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
102#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
103#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
104#define JZ_MMC_IRQ_PRG_DONE BIT(1)
105#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
106
107
108#define JZ_MMC_CLK_RATE 24000000
109
110enum jz4740_mmc_state {
111 JZ4740_MMC_STATE_READ_RESPONSE,
112 JZ4740_MMC_STATE_TRANSFER_DATA,
113 JZ4740_MMC_STATE_SEND_STOP,
114 JZ4740_MMC_STATE_DONE,
115};
116
117struct jz4740_mmc_host_next {
118 int sg_len;
119 s32 cookie;
120};
121
122struct jz4740_mmc_host {
123 struct mmc_host *mmc;
124 struct platform_device *pdev;
125 struct jz4740_mmc_platform_data *pdata;
126 struct clk *clk;
127
128 int irq;
129 int card_detect_irq;
130
131 void __iomem *base;
132 struct resource *mem_res;
133 struct mmc_request *req;
134 struct mmc_command *cmd;
135
136 unsigned long waiting;
137
138 uint32_t cmdat;
139
140 uint16_t irq_mask;
141
142 spinlock_t lock;
143
144 struct timer_list timeout_timer;
145 struct sg_mapping_iter miter;
146 enum jz4740_mmc_state state;
147
148 /* DMA support */
149 struct dma_chan *dma_rx;
150 struct dma_chan *dma_tx;
151 struct jz4740_mmc_host_next next_data;
152 bool use_dma;
153 int sg_len;
154
155/* The DMA trigger level is 8 words, that is to say, the DMA read
156 * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write
157 * trigger is when data words in MSC_TXFIFO is < 8.
158 */
159#define JZ4740_MMC_FIFO_HALF_SIZE 8
160};
161
162/*----------------------------------------------------------------------------*/
163/* DMA infrastructure */
164
165static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
166{
167 if (!host->use_dma)
168 return;
169
170 dma_release_channel(host->dma_tx);
171 dma_release_channel(host->dma_rx);
172}
173
174static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
175{
176 dma_cap_mask_t mask;
177
178 dma_cap_zero(mask);
179 dma_cap_set(DMA_SLAVE, mask);
180
181 host->dma_tx = dma_request_channel(mask, NULL, host);
182 if (!host->dma_tx) {
183 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
184 return -ENODEV;
185 }
186
187 host->dma_rx = dma_request_channel(mask, NULL, host);
188 if (!host->dma_rx) {
189 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
190 goto free_master_write;
191 }
192
193 /* Initialize DMA pre request cookie */
194 host->next_data.cookie = 1;
195
196 return 0;
197
198free_master_write:
199 dma_release_channel(host->dma_tx);
200 return -ENODEV;
201}
202
203static inline int jz4740_mmc_get_dma_dir(struct mmc_data *data)
204{
205 return (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
206}
207
208static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host,
209 struct mmc_data *data)
210{
211 return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx;
212}
213
214static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
215 struct mmc_data *data)
216{
217 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
218 enum dma_data_direction dir = jz4740_mmc_get_dma_dir(data);
219
220 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
221}
222
223/* Prepares DMA data for current/next transfer, returns non-zero on failure */
224static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host,
225 struct mmc_data *data,
226 struct jz4740_mmc_host_next *next,
227 struct dma_chan *chan)
228{
229 struct jz4740_mmc_host_next *next_data = &host->next_data;
230 enum dma_data_direction dir = jz4740_mmc_get_dma_dir(data);
231 int sg_len;
232
233 if (!next && data->host_cookie &&
234 data->host_cookie != host->next_data.cookie) {
235 dev_warn(mmc_dev(host->mmc),
236 "[%s] invalid cookie: data->host_cookie %d host->next_data.cookie %d\n",
237 __func__,
238 data->host_cookie,
239 host->next_data.cookie);
240 data->host_cookie = 0;
241 }
242
243 /* Check if next job is already prepared */
244 if (next || data->host_cookie != host->next_data.cookie) {
245 sg_len = dma_map_sg(chan->device->dev,
246 data->sg,
247 data->sg_len,
248 dir);
249
250 } else {
251 sg_len = next_data->sg_len;
252 next_data->sg_len = 0;
253 }
254
255 if (sg_len <= 0) {
256 dev_err(mmc_dev(host->mmc),
257 "Failed to map scatterlist for DMA operation\n");
258 return -EINVAL;
259 }
260
261 if (next) {
262 next->sg_len = sg_len;
263 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
264 } else
265 host->sg_len = sg_len;
266
267 return 0;
268}
269
270static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
271 struct mmc_data *data)
272{
273 int ret;
274 struct dma_chan *chan;
275 struct dma_async_tx_descriptor *desc;
276 struct dma_slave_config conf = {
277 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
278 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
279 .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
280 .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
281 };
282
283 if (data->flags & MMC_DATA_WRITE) {
284 conf.direction = DMA_MEM_TO_DEV;
285 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
286 conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT;
287 chan = host->dma_tx;
288 } else {
289 conf.direction = DMA_DEV_TO_MEM;
290 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
291 conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE;
292 chan = host->dma_rx;
293 }
294
295 ret = jz4740_mmc_prepare_dma_data(host, data, NULL, chan);
296 if (ret)
297 return ret;
298
299 dmaengine_slave_config(chan, &conf);
300 desc = dmaengine_prep_slave_sg(chan,
301 data->sg,
302 host->sg_len,
303 conf.direction,
304 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
305 if (!desc) {
306 dev_err(mmc_dev(host->mmc),
307 "Failed to allocate DMA %s descriptor",
308 conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX");
309 goto dma_unmap;
310 }
311
312 dmaengine_submit(desc);
313 dma_async_issue_pending(chan);
314
315 return 0;
316
317dma_unmap:
318 jz4740_mmc_dma_unmap(host, data);
319 return -ENOMEM;
320}
321
322static void jz4740_mmc_pre_request(struct mmc_host *mmc,
323 struct mmc_request *mrq,
324 bool is_first_req)
325{
326 struct jz4740_mmc_host *host = mmc_priv(mmc);
327 struct mmc_data *data = mrq->data;
328 struct jz4740_mmc_host_next *next_data = &host->next_data;
329
330 BUG_ON(data->host_cookie);
331
332 if (host->use_dma) {
333 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
334
335 if (jz4740_mmc_prepare_dma_data(host, data, next_data, chan))
336 data->host_cookie = 0;
337 }
338}
339
340static void jz4740_mmc_post_request(struct mmc_host *mmc,
341 struct mmc_request *mrq,
342 int err)
343{
344 struct jz4740_mmc_host *host = mmc_priv(mmc);
345 struct mmc_data *data = mrq->data;
346
347 if (host->use_dma && data->host_cookie) {
348 jz4740_mmc_dma_unmap(host, data);
349 data->host_cookie = 0;
350 }
351
352 if (err) {
353 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
354
355 dmaengine_terminate_all(chan);
356 }
357}
358
359/*----------------------------------------------------------------------------*/
360
361static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
362 unsigned int irq, bool enabled)
363{
364 unsigned long flags;
365
366 spin_lock_irqsave(&host->lock, flags);
367 if (enabled)
368 host->irq_mask &= ~irq;
369 else
370 host->irq_mask |= irq;
371 spin_unlock_irqrestore(&host->lock, flags);
372
373 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
374}
375
376static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
377 bool start_transfer)
378{
379 uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
380
381 if (start_transfer)
382 val |= JZ_MMC_STRPCL_START_OP;
383
384 writew(val, host->base + JZ_REG_MMC_STRPCL);
385}
386
387static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
388{
389 uint32_t status;
390 unsigned int timeout = 1000;
391
392 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
393 do {
394 status = readl(host->base + JZ_REG_MMC_STATUS);
395 } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
396}
397
398static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
399{
400 uint32_t status;
401 unsigned int timeout = 1000;
402
403 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
404 udelay(10);
405 do {
406 status = readl(host->base + JZ_REG_MMC_STATUS);
407 } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
408}
409
410static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
411{
412 struct mmc_request *req;
413
414 req = host->req;
415 host->req = NULL;
416
417 mmc_request_done(host->mmc, req);
418}
419
420static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
421 unsigned int irq)
422{
423 unsigned int timeout = 0x800;
424 uint16_t status;
425
426 do {
427 status = readw(host->base + JZ_REG_MMC_IREG);
428 } while (!(status & irq) && --timeout);
429
430 if (timeout == 0) {
431 set_bit(0, &host->waiting);
432 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
433 jz4740_mmc_set_irq_enabled(host, irq, true);
434 return true;
435 }
436
437 return false;
438}
439
440static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
441 struct mmc_data *data)
442{
443 int status;
444
445 status = readl(host->base + JZ_REG_MMC_STATUS);
446 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
447 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
448 host->req->cmd->error = -ETIMEDOUT;
449 data->error = -ETIMEDOUT;
450 } else {
451 host->req->cmd->error = -EIO;
452 data->error = -EIO;
453 }
454 } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
455 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
456 host->req->cmd->error = -ETIMEDOUT;
457 data->error = -ETIMEDOUT;
458 } else {
459 host->req->cmd->error = -EIO;
460 data->error = -EIO;
461 }
462 }
463}
464
465static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
466 struct mmc_data *data)
467{
468 struct sg_mapping_iter *miter = &host->miter;
469 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
470 uint32_t *buf;
471 bool timeout;
472 size_t i, j;
473
474 while (sg_miter_next(miter)) {
475 buf = miter->addr;
476 i = miter->length / 4;
477 j = i / 8;
478 i = i & 0x7;
479 while (j) {
480 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
481 if (unlikely(timeout))
482 goto poll_timeout;
483
484 writel(buf[0], fifo_addr);
485 writel(buf[1], fifo_addr);
486 writel(buf[2], fifo_addr);
487 writel(buf[3], fifo_addr);
488 writel(buf[4], fifo_addr);
489 writel(buf[5], fifo_addr);
490 writel(buf[6], fifo_addr);
491 writel(buf[7], fifo_addr);
492 buf += 8;
493 --j;
494 }
495 if (unlikely(i)) {
496 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
497 if (unlikely(timeout))
498 goto poll_timeout;
499
500 while (i) {
501 writel(*buf, fifo_addr);
502 ++buf;
503 --i;
504 }
505 }
506 data->bytes_xfered += miter->length;
507 }
508 sg_miter_stop(miter);
509
510 return false;
511
512poll_timeout:
513 miter->consumed = (void *)buf - miter->addr;
514 data->bytes_xfered += miter->consumed;
515 sg_miter_stop(miter);
516
517 return true;
518}
519
520static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
521 struct mmc_data *data)
522{
523 struct sg_mapping_iter *miter = &host->miter;
524 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
525 uint32_t *buf;
526 uint32_t d;
527 uint16_t status;
528 size_t i, j;
529 unsigned int timeout;
530
531 while (sg_miter_next(miter)) {
532 buf = miter->addr;
533 i = miter->length;
534 j = i / 32;
535 i = i & 0x1f;
536 while (j) {
537 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
538 if (unlikely(timeout))
539 goto poll_timeout;
540
541 buf[0] = readl(fifo_addr);
542 buf[1] = readl(fifo_addr);
543 buf[2] = readl(fifo_addr);
544 buf[3] = readl(fifo_addr);
545 buf[4] = readl(fifo_addr);
546 buf[5] = readl(fifo_addr);
547 buf[6] = readl(fifo_addr);
548 buf[7] = readl(fifo_addr);
549
550 buf += 8;
551 --j;
552 }
553
554 if (unlikely(i)) {
555 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
556 if (unlikely(timeout))
557 goto poll_timeout;
558
559 while (i >= 4) {
560 *buf++ = readl(fifo_addr);
561 i -= 4;
562 }
563 if (unlikely(i > 0)) {
564 d = readl(fifo_addr);
565 memcpy(buf, &d, i);
566 }
567 }
568 data->bytes_xfered += miter->length;
569
570 /* This can go away once MIPS implements
571 * flush_kernel_dcache_page */
572 flush_dcache_page(miter->page);
573 }
574 sg_miter_stop(miter);
575
576 /* For whatever reason there is sometime one word more in the fifo then
577 * requested */
578 timeout = 1000;
579 status = readl(host->base + JZ_REG_MMC_STATUS);
580 while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
581 d = readl(fifo_addr);
582 status = readl(host->base + JZ_REG_MMC_STATUS);
583 }
584
585 return false;
586
587poll_timeout:
588 miter->consumed = (void *)buf - miter->addr;
589 data->bytes_xfered += miter->consumed;
590 sg_miter_stop(miter);
591
592 return true;
593}
594
595static void jz4740_mmc_timeout(unsigned long data)
596{
597 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
598
599 if (!test_and_clear_bit(0, &host->waiting))
600 return;
601
602 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
603
604 host->req->cmd->error = -ETIMEDOUT;
605 jz4740_mmc_request_done(host);
606}
607
608static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
609 struct mmc_command *cmd)
610{
611 int i;
612 uint16_t tmp;
613 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
614
615 if (cmd->flags & MMC_RSP_136) {
616 tmp = readw(fifo_addr);
617 for (i = 0; i < 4; ++i) {
618 cmd->resp[i] = tmp << 24;
619 tmp = readw(fifo_addr);
620 cmd->resp[i] |= tmp << 8;
621 tmp = readw(fifo_addr);
622 cmd->resp[i] |= tmp >> 8;
623 }
624 } else {
625 cmd->resp[0] = readw(fifo_addr) << 24;
626 cmd->resp[0] |= readw(fifo_addr) << 8;
627 cmd->resp[0] |= readw(fifo_addr) & 0xff;
628 }
629}
630
631static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
632 struct mmc_command *cmd)
633{
634 uint32_t cmdat = host->cmdat;
635
636 host->cmdat &= ~JZ_MMC_CMDAT_INIT;
637 jz4740_mmc_clock_disable(host);
638
639 host->cmd = cmd;
640
641 if (cmd->flags & MMC_RSP_BUSY)
642 cmdat |= JZ_MMC_CMDAT_BUSY;
643
644 switch (mmc_resp_type(cmd)) {
645 case MMC_RSP_R1B:
646 case MMC_RSP_R1:
647 cmdat |= JZ_MMC_CMDAT_RSP_R1;
648 break;
649 case MMC_RSP_R2:
650 cmdat |= JZ_MMC_CMDAT_RSP_R2;
651 break;
652 case MMC_RSP_R3:
653 cmdat |= JZ_MMC_CMDAT_RSP_R3;
654 break;
655 default:
656 break;
657 }
658
659 if (cmd->data) {
660 cmdat |= JZ_MMC_CMDAT_DATA_EN;
661 if (cmd->data->flags & MMC_DATA_WRITE)
662 cmdat |= JZ_MMC_CMDAT_WRITE;
663 if (host->use_dma)
664 cmdat |= JZ_MMC_CMDAT_DMA_EN;
665
666 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
667 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
668 }
669
670 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
671 writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
672 writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
673
674 jz4740_mmc_clock_enable(host, 1);
675}
676
677static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
678{
679 struct mmc_command *cmd = host->req->cmd;
680 struct mmc_data *data = cmd->data;
681 int direction;
682
683 if (data->flags & MMC_DATA_READ)
684 direction = SG_MITER_TO_SG;
685 else
686 direction = SG_MITER_FROM_SG;
687
688 sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
689}
690
691
692static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
693{
694 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
695 struct mmc_command *cmd = host->req->cmd;
696 struct mmc_request *req = host->req;
697 struct mmc_data *data = cmd->data;
698 bool timeout = false;
699
700 if (cmd->error)
701 host->state = JZ4740_MMC_STATE_DONE;
702
703 switch (host->state) {
704 case JZ4740_MMC_STATE_READ_RESPONSE:
705 if (cmd->flags & MMC_RSP_PRESENT)
706 jz4740_mmc_read_response(host, cmd);
707
708 if (!data)
709 break;
710
711 jz_mmc_prepare_data_transfer(host);
712
713 case JZ4740_MMC_STATE_TRANSFER_DATA:
714 if (host->use_dma) {
715 /* Use DMA if enabled.
716 * Data transfer direction is defined later by
717 * relying on data flags in
718 * jz4740_mmc_prepare_dma_data() and
719 * jz4740_mmc_start_dma_transfer().
720 */
721 timeout = jz4740_mmc_start_dma_transfer(host, data);
722 data->bytes_xfered = data->blocks * data->blksz;
723 } else if (data->flags & MMC_DATA_READ)
724 /* Use PIO if DMA is not enabled.
725 * Data transfer direction was defined before
726 * by relying on data flags in
727 * jz_mmc_prepare_data_transfer().
728 */
729 timeout = jz4740_mmc_read_data(host, data);
730 else
731 timeout = jz4740_mmc_write_data(host, data);
732
733 if (unlikely(timeout)) {
734 host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
735 break;
736 }
737
738 jz4740_mmc_transfer_check_state(host, data);
739
740 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
741 if (unlikely(timeout)) {
742 host->state = JZ4740_MMC_STATE_SEND_STOP;
743 break;
744 }
745 writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
746
747 case JZ4740_MMC_STATE_SEND_STOP:
748 if (!req->stop)
749 break;
750
751 jz4740_mmc_send_command(host, req->stop);
752
753 if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) {
754 timeout = jz4740_mmc_poll_irq(host,
755 JZ_MMC_IRQ_PRG_DONE);
756 if (timeout) {
757 host->state = JZ4740_MMC_STATE_DONE;
758 break;
759 }
760 }
761 case JZ4740_MMC_STATE_DONE:
762 break;
763 }
764
765 if (!timeout)
766 jz4740_mmc_request_done(host);
767
768 return IRQ_HANDLED;
769}
770
771static irqreturn_t jz_mmc_irq(int irq, void *devid)
772{
773 struct jz4740_mmc_host *host = devid;
774 struct mmc_command *cmd = host->cmd;
775 uint16_t irq_reg, status, tmp;
776
777 irq_reg = readw(host->base + JZ_REG_MMC_IREG);
778
779 tmp = irq_reg;
780 irq_reg &= ~host->irq_mask;
781
782 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
783 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
784
785 if (tmp != irq_reg)
786 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
787
788 if (irq_reg & JZ_MMC_IRQ_SDIO) {
789 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
790 mmc_signal_sdio_irq(host->mmc);
791 irq_reg &= ~JZ_MMC_IRQ_SDIO;
792 }
793
794 if (host->req && cmd && irq_reg) {
795 if (test_and_clear_bit(0, &host->waiting)) {
796 del_timer(&host->timeout_timer);
797
798 status = readl(host->base + JZ_REG_MMC_STATUS);
799
800 if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
801 cmd->error = -ETIMEDOUT;
802 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
803 cmd->error = -EIO;
804 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
805 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
806 if (cmd->data)
807 cmd->data->error = -EIO;
808 cmd->error = -EIO;
809 }
810
811 jz4740_mmc_set_irq_enabled(host, irq_reg, false);
812 writew(irq_reg, host->base + JZ_REG_MMC_IREG);
813
814 return IRQ_WAKE_THREAD;
815 }
816 }
817
818 return IRQ_HANDLED;
819}
820
821static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
822{
823 int div = 0;
824 int real_rate;
825
826 jz4740_mmc_clock_disable(host);
827 clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
828
829 real_rate = clk_get_rate(host->clk);
830
831 while (real_rate > rate && div < 7) {
832 ++div;
833 real_rate >>= 1;
834 }
835
836 writew(div, host->base + JZ_REG_MMC_CLKRT);
837 return real_rate;
838}
839
840static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
841{
842 struct jz4740_mmc_host *host = mmc_priv(mmc);
843
844 host->req = req;
845
846 writew(0xffff, host->base + JZ_REG_MMC_IREG);
847
848 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
849 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
850
851 host->state = JZ4740_MMC_STATE_READ_RESPONSE;
852 set_bit(0, &host->waiting);
853 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
854 jz4740_mmc_send_command(host, req->cmd);
855}
856
857static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
858{
859 struct jz4740_mmc_host *host = mmc_priv(mmc);
860 if (ios->clock)
861 jz4740_mmc_set_clock_rate(host, ios->clock);
862
863 switch (ios->power_mode) {
864 case MMC_POWER_UP:
865 jz4740_mmc_reset(host);
866 if (gpio_is_valid(host->pdata->gpio_power))
867 gpio_set_value(host->pdata->gpio_power,
868 !host->pdata->power_active_low);
869 host->cmdat |= JZ_MMC_CMDAT_INIT;
870 clk_prepare_enable(host->clk);
871 break;
872 case MMC_POWER_ON:
873 break;
874 default:
875 if (gpio_is_valid(host->pdata->gpio_power))
876 gpio_set_value(host->pdata->gpio_power,
877 host->pdata->power_active_low);
878 clk_disable_unprepare(host->clk);
879 break;
880 }
881
882 switch (ios->bus_width) {
883 case MMC_BUS_WIDTH_1:
884 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
885 break;
886 case MMC_BUS_WIDTH_4:
887 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
888 break;
889 default:
890 break;
891 }
892}
893
894static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
895{
896 struct jz4740_mmc_host *host = mmc_priv(mmc);
897 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
898}
899
900static const struct mmc_host_ops jz4740_mmc_ops = {
901 .request = jz4740_mmc_request,
902 .pre_req = jz4740_mmc_pre_request,
903 .post_req = jz4740_mmc_post_request,
904 .set_ios = jz4740_mmc_set_ios,
905 .get_ro = mmc_gpio_get_ro,
906 .get_cd = mmc_gpio_get_cd,
907 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
908};
909
910static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
911 JZ_GPIO_BULK_PIN(MSC_CMD),
912 JZ_GPIO_BULK_PIN(MSC_CLK),
913 JZ_GPIO_BULK_PIN(MSC_DATA0),
914 JZ_GPIO_BULK_PIN(MSC_DATA1),
915 JZ_GPIO_BULK_PIN(MSC_DATA2),
916 JZ_GPIO_BULK_PIN(MSC_DATA3),
917};
918
919static int jz4740_mmc_request_gpio(struct device *dev, int gpio,
920 const char *name, bool output, int value)
921{
922 int ret;
923
924 if (!gpio_is_valid(gpio))
925 return 0;
926
927 ret = gpio_request(gpio, name);
928 if (ret) {
929 dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
930 return ret;
931 }
932
933 if (output)
934 gpio_direction_output(gpio, value);
935 else
936 gpio_direction_input(gpio);
937
938 return 0;
939}
940
941static int jz4740_mmc_request_gpios(struct mmc_host *mmc,
942 struct platform_device *pdev)
943{
944 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
945 int ret = 0;
946
947 if (!pdata)
948 return 0;
949
950 if (!pdata->card_detect_active_low)
951 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
952 if (!pdata->read_only_active_low)
953 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
954
955 if (gpio_is_valid(pdata->gpio_card_detect)) {
956 ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0);
957 if (ret)
958 return ret;
959 }
960
961 if (gpio_is_valid(pdata->gpio_read_only)) {
962 ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only);
963 if (ret)
964 return ret;
965 }
966
967 return jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
968 "MMC read only", true, pdata->power_active_low);
969}
970
971static void jz4740_mmc_free_gpios(struct platform_device *pdev)
972{
973 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
974
975 if (!pdata)
976 return;
977
978 if (gpio_is_valid(pdata->gpio_power))
979 gpio_free(pdata->gpio_power);
980}
981
982static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
983{
984 size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
985 if (host->pdata && host->pdata->data_1bit)
986 num_pins -= 3;
987
988 return num_pins;
989}
990
991static int jz4740_mmc_probe(struct platform_device* pdev)
992{
993 int ret;
994 struct mmc_host *mmc;
995 struct jz4740_mmc_host *host;
996 struct jz4740_mmc_platform_data *pdata;
997
998 pdata = pdev->dev.platform_data;
999
1000 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
1001 if (!mmc) {
1002 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
1003 return -ENOMEM;
1004 }
1005
1006 host = mmc_priv(mmc);
1007 host->pdata = pdata;
1008
1009 host->irq = platform_get_irq(pdev, 0);
1010 if (host->irq < 0) {
1011 ret = host->irq;
1012 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
1013 goto err_free_host;
1014 }
1015
1016 host->clk = devm_clk_get(&pdev->dev, "mmc");
1017 if (IS_ERR(host->clk)) {
1018 ret = PTR_ERR(host->clk);
1019 dev_err(&pdev->dev, "Failed to get mmc clock\n");
1020 goto err_free_host;
1021 }
1022
1023 host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1024 host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
1025 if (IS_ERR(host->base)) {
1026 ret = PTR_ERR(host->base);
1027 dev_err(&pdev->dev, "Failed to ioremap base memory\n");
1028 goto err_free_host;
1029 }
1030
1031 ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1032 if (ret) {
1033 dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
1034 goto err_free_host;
1035 }
1036
1037 ret = jz4740_mmc_request_gpios(mmc, pdev);
1038 if (ret)
1039 goto err_gpio_bulk_free;
1040
1041 mmc->ops = &jz4740_mmc_ops;
1042 mmc->f_min = JZ_MMC_CLK_RATE / 128;
1043 mmc->f_max = JZ_MMC_CLK_RATE;
1044 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1045 mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
1046 mmc->caps |= MMC_CAP_SDIO_IRQ;
1047
1048 mmc->max_blk_size = (1 << 10) - 1;
1049 mmc->max_blk_count = (1 << 15) - 1;
1050 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1051
1052 mmc->max_segs = 128;
1053 mmc->max_seg_size = mmc->max_req_size;
1054
1055 host->mmc = mmc;
1056 host->pdev = pdev;
1057 spin_lock_init(&host->lock);
1058 host->irq_mask = 0xffff;
1059
1060 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
1061 dev_name(&pdev->dev), host);
1062 if (ret) {
1063 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1064 goto err_free_gpios;
1065 }
1066
1067 jz4740_mmc_reset(host);
1068 jz4740_mmc_clock_disable(host);
1069 setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
1070 (unsigned long)host);
1071 /* It is not important when it times out, it just needs to timeout. */
1072 set_timer_slack(&host->timeout_timer, HZ);
1073
1074 host->use_dma = true;
1075 if (host->use_dma && jz4740_mmc_acquire_dma_channels(host) != 0)
1076 host->use_dma = false;
1077
1078 platform_set_drvdata(pdev, host);
1079 ret = mmc_add_host(mmc);
1080
1081 if (ret) {
1082 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
1083 goto err_free_irq;
1084 }
1085 dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
1086
1087 dev_info(&pdev->dev, "Using %s, %d-bit mode\n",
1088 host->use_dma ? "DMA" : "PIO",
1089 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1090
1091 return 0;
1092
1093err_free_irq:
1094 free_irq(host->irq, host);
1095err_free_gpios:
1096 jz4740_mmc_free_gpios(pdev);
1097err_gpio_bulk_free:
1098 if (host->use_dma)
1099 jz4740_mmc_release_dma_channels(host);
1100 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1101err_free_host:
1102 mmc_free_host(mmc);
1103
1104 return ret;
1105}
1106
1107static int jz4740_mmc_remove(struct platform_device *pdev)
1108{
1109 struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
1110
1111 del_timer_sync(&host->timeout_timer);
1112 jz4740_mmc_set_irq_enabled(host, 0xff, false);
1113 jz4740_mmc_reset(host);
1114
1115 mmc_remove_host(host->mmc);
1116
1117 free_irq(host->irq, host);
1118
1119 jz4740_mmc_free_gpios(pdev);
1120 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1121
1122 if (host->use_dma)
1123 jz4740_mmc_release_dma_channels(host);
1124
1125 mmc_free_host(host->mmc);
1126
1127 return 0;
1128}
1129
1130#ifdef CONFIG_PM_SLEEP
1131
1132static int jz4740_mmc_suspend(struct device *dev)
1133{
1134 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1135
1136 jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1137
1138 return 0;
1139}
1140
1141static int jz4740_mmc_resume(struct device *dev)
1142{
1143 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1144
1145 jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1146
1147 return 0;
1148}
1149
1150static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
1151 jz4740_mmc_resume);
1152#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
1153#else
1154#define JZ4740_MMC_PM_OPS NULL
1155#endif
1156
1157static struct platform_driver jz4740_mmc_driver = {
1158 .probe = jz4740_mmc_probe,
1159 .remove = jz4740_mmc_remove,
1160 .driver = {
1161 .name = "jz4740-mmc",
1162 .pm = JZ4740_MMC_PM_OPS,
1163 },
1164};
1165
1166module_platform_driver(jz4740_mmc_driver);
1167
1168MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
1169MODULE_LICENSE("GPL");
1170MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SD/MMC controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/mmc/host.h>
17#include <linux/mmc/slot-gpio.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/delay.h>
25#include <linux/scatterlist.h>
26#include <linux/clk.h>
27
28#include <linux/bitops.h>
29#include <linux/gpio.h>
30#include <asm/mach-jz4740/gpio.h>
31#include <asm/cacheflush.h>
32#include <linux/dma-mapping.h>
33#include <linux/dmaengine.h>
34
35#include <asm/mach-jz4740/dma.h>
36#include <asm/mach-jz4740/jz4740_mmc.h>
37
38#define JZ_REG_MMC_STRPCL 0x00
39#define JZ_REG_MMC_STATUS 0x04
40#define JZ_REG_MMC_CLKRT 0x08
41#define JZ_REG_MMC_CMDAT 0x0C
42#define JZ_REG_MMC_RESTO 0x10
43#define JZ_REG_MMC_RDTO 0x14
44#define JZ_REG_MMC_BLKLEN 0x18
45#define JZ_REG_MMC_NOB 0x1C
46#define JZ_REG_MMC_SNOB 0x20
47#define JZ_REG_MMC_IMASK 0x24
48#define JZ_REG_MMC_IREG 0x28
49#define JZ_REG_MMC_CMD 0x2C
50#define JZ_REG_MMC_ARG 0x30
51#define JZ_REG_MMC_RESP_FIFO 0x34
52#define JZ_REG_MMC_RXFIFO 0x38
53#define JZ_REG_MMC_TXFIFO 0x3C
54
55#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
56#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
57#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
58#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
59#define JZ_MMC_STRPCL_RESET BIT(3)
60#define JZ_MMC_STRPCL_START_OP BIT(2)
61#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
62#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
63#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
64
65
66#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
67#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
68#define JZ_MMC_STATUS_PRG_DONE BIT(13)
69#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
70#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
71#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
72#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
73#define JZ_MMC_STATUS_CLK_EN BIT(8)
74#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
75#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
76#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
77#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
78#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
79#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
80#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
81#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
82
83#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
84#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
85
86
87#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
88#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
89#define JZ_MMC_CMDAT_DMA_EN BIT(8)
90#define JZ_MMC_CMDAT_INIT BIT(7)
91#define JZ_MMC_CMDAT_BUSY BIT(6)
92#define JZ_MMC_CMDAT_STREAM BIT(5)
93#define JZ_MMC_CMDAT_WRITE BIT(4)
94#define JZ_MMC_CMDAT_DATA_EN BIT(3)
95#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
96#define JZ_MMC_CMDAT_RSP_R1 1
97#define JZ_MMC_CMDAT_RSP_R2 2
98#define JZ_MMC_CMDAT_RSP_R3 3
99
100#define JZ_MMC_IRQ_SDIO BIT(7)
101#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
102#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
103#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
104#define JZ_MMC_IRQ_PRG_DONE BIT(1)
105#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
106
107
108#define JZ_MMC_CLK_RATE 24000000
109
110enum jz4740_mmc_state {
111 JZ4740_MMC_STATE_READ_RESPONSE,
112 JZ4740_MMC_STATE_TRANSFER_DATA,
113 JZ4740_MMC_STATE_SEND_STOP,
114 JZ4740_MMC_STATE_DONE,
115};
116
117struct jz4740_mmc_host_next {
118 int sg_len;
119 s32 cookie;
120};
121
122struct jz4740_mmc_host {
123 struct mmc_host *mmc;
124 struct platform_device *pdev;
125 struct jz4740_mmc_platform_data *pdata;
126 struct clk *clk;
127
128 int irq;
129 int card_detect_irq;
130
131 void __iomem *base;
132 struct resource *mem_res;
133 struct mmc_request *req;
134 struct mmc_command *cmd;
135
136 unsigned long waiting;
137
138 uint32_t cmdat;
139
140 uint16_t irq_mask;
141
142 spinlock_t lock;
143
144 struct timer_list timeout_timer;
145 struct sg_mapping_iter miter;
146 enum jz4740_mmc_state state;
147
148 /* DMA support */
149 struct dma_chan *dma_rx;
150 struct dma_chan *dma_tx;
151 struct jz4740_mmc_host_next next_data;
152 bool use_dma;
153 int sg_len;
154
155/* The DMA trigger level is 8 words, that is to say, the DMA read
156 * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write
157 * trigger is when data words in MSC_TXFIFO is < 8.
158 */
159#define JZ4740_MMC_FIFO_HALF_SIZE 8
160};
161
162/*----------------------------------------------------------------------------*/
163/* DMA infrastructure */
164
165static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
166{
167 if (!host->use_dma)
168 return;
169
170 dma_release_channel(host->dma_tx);
171 dma_release_channel(host->dma_rx);
172}
173
174static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
175{
176 dma_cap_mask_t mask;
177
178 dma_cap_zero(mask);
179 dma_cap_set(DMA_SLAVE, mask);
180
181 host->dma_tx = dma_request_channel(mask, NULL, host);
182 if (!host->dma_tx) {
183 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
184 return -ENODEV;
185 }
186
187 host->dma_rx = dma_request_channel(mask, NULL, host);
188 if (!host->dma_rx) {
189 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
190 goto free_master_write;
191 }
192
193 /* Initialize DMA pre request cookie */
194 host->next_data.cookie = 1;
195
196 return 0;
197
198free_master_write:
199 dma_release_channel(host->dma_tx);
200 return -ENODEV;
201}
202
203static inline int jz4740_mmc_get_dma_dir(struct mmc_data *data)
204{
205 return (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
206}
207
208static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host,
209 struct mmc_data *data)
210{
211 return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx;
212}
213
214static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
215 struct mmc_data *data)
216{
217 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
218 enum dma_data_direction dir = jz4740_mmc_get_dma_dir(data);
219
220 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
221}
222
223/* Prepares DMA data for current/next transfer, returns non-zero on failure */
224static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host,
225 struct mmc_data *data,
226 struct jz4740_mmc_host_next *next,
227 struct dma_chan *chan)
228{
229 struct jz4740_mmc_host_next *next_data = &host->next_data;
230 enum dma_data_direction dir = jz4740_mmc_get_dma_dir(data);
231 int sg_len;
232
233 if (!next && data->host_cookie &&
234 data->host_cookie != host->next_data.cookie) {
235 dev_warn(mmc_dev(host->mmc),
236 "[%s] invalid cookie: data->host_cookie %d host->next_data.cookie %d\n",
237 __func__,
238 data->host_cookie,
239 host->next_data.cookie);
240 data->host_cookie = 0;
241 }
242
243 /* Check if next job is already prepared */
244 if (next || data->host_cookie != host->next_data.cookie) {
245 sg_len = dma_map_sg(chan->device->dev,
246 data->sg,
247 data->sg_len,
248 dir);
249
250 } else {
251 sg_len = next_data->sg_len;
252 next_data->sg_len = 0;
253 }
254
255 if (sg_len <= 0) {
256 dev_err(mmc_dev(host->mmc),
257 "Failed to map scatterlist for DMA operation\n");
258 return -EINVAL;
259 }
260
261 if (next) {
262 next->sg_len = sg_len;
263 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
264 } else
265 host->sg_len = sg_len;
266
267 return 0;
268}
269
270static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
271 struct mmc_data *data)
272{
273 int ret;
274 struct dma_chan *chan;
275 struct dma_async_tx_descriptor *desc;
276 struct dma_slave_config conf = {
277 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
278 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
279 .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
280 .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
281 };
282
283 if (data->flags & MMC_DATA_WRITE) {
284 conf.direction = DMA_MEM_TO_DEV;
285 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
286 conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT;
287 chan = host->dma_tx;
288 } else {
289 conf.direction = DMA_DEV_TO_MEM;
290 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
291 conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE;
292 chan = host->dma_rx;
293 }
294
295 ret = jz4740_mmc_prepare_dma_data(host, data, NULL, chan);
296 if (ret)
297 return ret;
298
299 dmaengine_slave_config(chan, &conf);
300 desc = dmaengine_prep_slave_sg(chan,
301 data->sg,
302 host->sg_len,
303 conf.direction,
304 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
305 if (!desc) {
306 dev_err(mmc_dev(host->mmc),
307 "Failed to allocate DMA %s descriptor",
308 conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX");
309 goto dma_unmap;
310 }
311
312 dmaengine_submit(desc);
313 dma_async_issue_pending(chan);
314
315 return 0;
316
317dma_unmap:
318 jz4740_mmc_dma_unmap(host, data);
319 return -ENOMEM;
320}
321
322static void jz4740_mmc_pre_request(struct mmc_host *mmc,
323 struct mmc_request *mrq)
324{
325 struct jz4740_mmc_host *host = mmc_priv(mmc);
326 struct mmc_data *data = mrq->data;
327 struct jz4740_mmc_host_next *next_data = &host->next_data;
328
329 BUG_ON(data->host_cookie);
330
331 if (host->use_dma) {
332 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
333
334 if (jz4740_mmc_prepare_dma_data(host, data, next_data, chan))
335 data->host_cookie = 0;
336 }
337}
338
339static void jz4740_mmc_post_request(struct mmc_host *mmc,
340 struct mmc_request *mrq,
341 int err)
342{
343 struct jz4740_mmc_host *host = mmc_priv(mmc);
344 struct mmc_data *data = mrq->data;
345
346 if (host->use_dma && data->host_cookie) {
347 jz4740_mmc_dma_unmap(host, data);
348 data->host_cookie = 0;
349 }
350
351 if (err) {
352 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
353
354 dmaengine_terminate_all(chan);
355 }
356}
357
358/*----------------------------------------------------------------------------*/
359
360static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
361 unsigned int irq, bool enabled)
362{
363 unsigned long flags;
364
365 spin_lock_irqsave(&host->lock, flags);
366 if (enabled)
367 host->irq_mask &= ~irq;
368 else
369 host->irq_mask |= irq;
370 spin_unlock_irqrestore(&host->lock, flags);
371
372 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
373}
374
375static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
376 bool start_transfer)
377{
378 uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
379
380 if (start_transfer)
381 val |= JZ_MMC_STRPCL_START_OP;
382
383 writew(val, host->base + JZ_REG_MMC_STRPCL);
384}
385
386static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
387{
388 uint32_t status;
389 unsigned int timeout = 1000;
390
391 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
392 do {
393 status = readl(host->base + JZ_REG_MMC_STATUS);
394 } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
395}
396
397static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
398{
399 uint32_t status;
400 unsigned int timeout = 1000;
401
402 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
403 udelay(10);
404 do {
405 status = readl(host->base + JZ_REG_MMC_STATUS);
406 } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
407}
408
409static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
410{
411 struct mmc_request *req;
412
413 req = host->req;
414 host->req = NULL;
415
416 mmc_request_done(host->mmc, req);
417}
418
419static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
420 unsigned int irq)
421{
422 unsigned int timeout = 0x800;
423 uint16_t status;
424
425 do {
426 status = readw(host->base + JZ_REG_MMC_IREG);
427 } while (!(status & irq) && --timeout);
428
429 if (timeout == 0) {
430 set_bit(0, &host->waiting);
431 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
432 jz4740_mmc_set_irq_enabled(host, irq, true);
433 return true;
434 }
435
436 return false;
437}
438
439static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
440 struct mmc_data *data)
441{
442 int status;
443
444 status = readl(host->base + JZ_REG_MMC_STATUS);
445 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
446 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
447 host->req->cmd->error = -ETIMEDOUT;
448 data->error = -ETIMEDOUT;
449 } else {
450 host->req->cmd->error = -EIO;
451 data->error = -EIO;
452 }
453 } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
454 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
455 host->req->cmd->error = -ETIMEDOUT;
456 data->error = -ETIMEDOUT;
457 } else {
458 host->req->cmd->error = -EIO;
459 data->error = -EIO;
460 }
461 }
462}
463
464static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
465 struct mmc_data *data)
466{
467 struct sg_mapping_iter *miter = &host->miter;
468 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
469 uint32_t *buf;
470 bool timeout;
471 size_t i, j;
472
473 while (sg_miter_next(miter)) {
474 buf = miter->addr;
475 i = miter->length / 4;
476 j = i / 8;
477 i = i & 0x7;
478 while (j) {
479 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
480 if (unlikely(timeout))
481 goto poll_timeout;
482
483 writel(buf[0], fifo_addr);
484 writel(buf[1], fifo_addr);
485 writel(buf[2], fifo_addr);
486 writel(buf[3], fifo_addr);
487 writel(buf[4], fifo_addr);
488 writel(buf[5], fifo_addr);
489 writel(buf[6], fifo_addr);
490 writel(buf[7], fifo_addr);
491 buf += 8;
492 --j;
493 }
494 if (unlikely(i)) {
495 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
496 if (unlikely(timeout))
497 goto poll_timeout;
498
499 while (i) {
500 writel(*buf, fifo_addr);
501 ++buf;
502 --i;
503 }
504 }
505 data->bytes_xfered += miter->length;
506 }
507 sg_miter_stop(miter);
508
509 return false;
510
511poll_timeout:
512 miter->consumed = (void *)buf - miter->addr;
513 data->bytes_xfered += miter->consumed;
514 sg_miter_stop(miter);
515
516 return true;
517}
518
519static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
520 struct mmc_data *data)
521{
522 struct sg_mapping_iter *miter = &host->miter;
523 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
524 uint32_t *buf;
525 uint32_t d;
526 uint16_t status;
527 size_t i, j;
528 unsigned int timeout;
529
530 while (sg_miter_next(miter)) {
531 buf = miter->addr;
532 i = miter->length;
533 j = i / 32;
534 i = i & 0x1f;
535 while (j) {
536 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
537 if (unlikely(timeout))
538 goto poll_timeout;
539
540 buf[0] = readl(fifo_addr);
541 buf[1] = readl(fifo_addr);
542 buf[2] = readl(fifo_addr);
543 buf[3] = readl(fifo_addr);
544 buf[4] = readl(fifo_addr);
545 buf[5] = readl(fifo_addr);
546 buf[6] = readl(fifo_addr);
547 buf[7] = readl(fifo_addr);
548
549 buf += 8;
550 --j;
551 }
552
553 if (unlikely(i)) {
554 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
555 if (unlikely(timeout))
556 goto poll_timeout;
557
558 while (i >= 4) {
559 *buf++ = readl(fifo_addr);
560 i -= 4;
561 }
562 if (unlikely(i > 0)) {
563 d = readl(fifo_addr);
564 memcpy(buf, &d, i);
565 }
566 }
567 data->bytes_xfered += miter->length;
568
569 /* This can go away once MIPS implements
570 * flush_kernel_dcache_page */
571 flush_dcache_page(miter->page);
572 }
573 sg_miter_stop(miter);
574
575 /* For whatever reason there is sometime one word more in the fifo then
576 * requested */
577 timeout = 1000;
578 status = readl(host->base + JZ_REG_MMC_STATUS);
579 while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
580 d = readl(fifo_addr);
581 status = readl(host->base + JZ_REG_MMC_STATUS);
582 }
583
584 return false;
585
586poll_timeout:
587 miter->consumed = (void *)buf - miter->addr;
588 data->bytes_xfered += miter->consumed;
589 sg_miter_stop(miter);
590
591 return true;
592}
593
594static void jz4740_mmc_timeout(unsigned long data)
595{
596 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
597
598 if (!test_and_clear_bit(0, &host->waiting))
599 return;
600
601 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
602
603 host->req->cmd->error = -ETIMEDOUT;
604 jz4740_mmc_request_done(host);
605}
606
607static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
608 struct mmc_command *cmd)
609{
610 int i;
611 uint16_t tmp;
612 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
613
614 if (cmd->flags & MMC_RSP_136) {
615 tmp = readw(fifo_addr);
616 for (i = 0; i < 4; ++i) {
617 cmd->resp[i] = tmp << 24;
618 tmp = readw(fifo_addr);
619 cmd->resp[i] |= tmp << 8;
620 tmp = readw(fifo_addr);
621 cmd->resp[i] |= tmp >> 8;
622 }
623 } else {
624 cmd->resp[0] = readw(fifo_addr) << 24;
625 cmd->resp[0] |= readw(fifo_addr) << 8;
626 cmd->resp[0] |= readw(fifo_addr) & 0xff;
627 }
628}
629
630static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
631 struct mmc_command *cmd)
632{
633 uint32_t cmdat = host->cmdat;
634
635 host->cmdat &= ~JZ_MMC_CMDAT_INIT;
636 jz4740_mmc_clock_disable(host);
637
638 host->cmd = cmd;
639
640 if (cmd->flags & MMC_RSP_BUSY)
641 cmdat |= JZ_MMC_CMDAT_BUSY;
642
643 switch (mmc_resp_type(cmd)) {
644 case MMC_RSP_R1B:
645 case MMC_RSP_R1:
646 cmdat |= JZ_MMC_CMDAT_RSP_R1;
647 break;
648 case MMC_RSP_R2:
649 cmdat |= JZ_MMC_CMDAT_RSP_R2;
650 break;
651 case MMC_RSP_R3:
652 cmdat |= JZ_MMC_CMDAT_RSP_R3;
653 break;
654 default:
655 break;
656 }
657
658 if (cmd->data) {
659 cmdat |= JZ_MMC_CMDAT_DATA_EN;
660 if (cmd->data->flags & MMC_DATA_WRITE)
661 cmdat |= JZ_MMC_CMDAT_WRITE;
662 if (host->use_dma)
663 cmdat |= JZ_MMC_CMDAT_DMA_EN;
664
665 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
666 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
667 }
668
669 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
670 writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
671 writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
672
673 jz4740_mmc_clock_enable(host, 1);
674}
675
676static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
677{
678 struct mmc_command *cmd = host->req->cmd;
679 struct mmc_data *data = cmd->data;
680 int direction;
681
682 if (data->flags & MMC_DATA_READ)
683 direction = SG_MITER_TO_SG;
684 else
685 direction = SG_MITER_FROM_SG;
686
687 sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
688}
689
690
691static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
692{
693 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
694 struct mmc_command *cmd = host->req->cmd;
695 struct mmc_request *req = host->req;
696 struct mmc_data *data = cmd->data;
697 bool timeout = false;
698
699 if (cmd->error)
700 host->state = JZ4740_MMC_STATE_DONE;
701
702 switch (host->state) {
703 case JZ4740_MMC_STATE_READ_RESPONSE:
704 if (cmd->flags & MMC_RSP_PRESENT)
705 jz4740_mmc_read_response(host, cmd);
706
707 if (!data)
708 break;
709
710 jz_mmc_prepare_data_transfer(host);
711
712 case JZ4740_MMC_STATE_TRANSFER_DATA:
713 if (host->use_dma) {
714 /* Use DMA if enabled.
715 * Data transfer direction is defined later by
716 * relying on data flags in
717 * jz4740_mmc_prepare_dma_data() and
718 * jz4740_mmc_start_dma_transfer().
719 */
720 timeout = jz4740_mmc_start_dma_transfer(host, data);
721 data->bytes_xfered = data->blocks * data->blksz;
722 } else if (data->flags & MMC_DATA_READ)
723 /* Use PIO if DMA is not enabled.
724 * Data transfer direction was defined before
725 * by relying on data flags in
726 * jz_mmc_prepare_data_transfer().
727 */
728 timeout = jz4740_mmc_read_data(host, data);
729 else
730 timeout = jz4740_mmc_write_data(host, data);
731
732 if (unlikely(timeout)) {
733 host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
734 break;
735 }
736
737 jz4740_mmc_transfer_check_state(host, data);
738
739 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
740 if (unlikely(timeout)) {
741 host->state = JZ4740_MMC_STATE_SEND_STOP;
742 break;
743 }
744 writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
745
746 case JZ4740_MMC_STATE_SEND_STOP:
747 if (!req->stop)
748 break;
749
750 jz4740_mmc_send_command(host, req->stop);
751
752 if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) {
753 timeout = jz4740_mmc_poll_irq(host,
754 JZ_MMC_IRQ_PRG_DONE);
755 if (timeout) {
756 host->state = JZ4740_MMC_STATE_DONE;
757 break;
758 }
759 }
760 case JZ4740_MMC_STATE_DONE:
761 break;
762 }
763
764 if (!timeout)
765 jz4740_mmc_request_done(host);
766
767 return IRQ_HANDLED;
768}
769
770static irqreturn_t jz_mmc_irq(int irq, void *devid)
771{
772 struct jz4740_mmc_host *host = devid;
773 struct mmc_command *cmd = host->cmd;
774 uint16_t irq_reg, status, tmp;
775
776 irq_reg = readw(host->base + JZ_REG_MMC_IREG);
777
778 tmp = irq_reg;
779 irq_reg &= ~host->irq_mask;
780
781 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
782 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
783
784 if (tmp != irq_reg)
785 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
786
787 if (irq_reg & JZ_MMC_IRQ_SDIO) {
788 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
789 mmc_signal_sdio_irq(host->mmc);
790 irq_reg &= ~JZ_MMC_IRQ_SDIO;
791 }
792
793 if (host->req && cmd && irq_reg) {
794 if (test_and_clear_bit(0, &host->waiting)) {
795 del_timer(&host->timeout_timer);
796
797 status = readl(host->base + JZ_REG_MMC_STATUS);
798
799 if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
800 cmd->error = -ETIMEDOUT;
801 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
802 cmd->error = -EIO;
803 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
804 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
805 if (cmd->data)
806 cmd->data->error = -EIO;
807 cmd->error = -EIO;
808 }
809
810 jz4740_mmc_set_irq_enabled(host, irq_reg, false);
811 writew(irq_reg, host->base + JZ_REG_MMC_IREG);
812
813 return IRQ_WAKE_THREAD;
814 }
815 }
816
817 return IRQ_HANDLED;
818}
819
820static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
821{
822 int div = 0;
823 int real_rate;
824
825 jz4740_mmc_clock_disable(host);
826 clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
827
828 real_rate = clk_get_rate(host->clk);
829
830 while (real_rate > rate && div < 7) {
831 ++div;
832 real_rate >>= 1;
833 }
834
835 writew(div, host->base + JZ_REG_MMC_CLKRT);
836 return real_rate;
837}
838
839static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
840{
841 struct jz4740_mmc_host *host = mmc_priv(mmc);
842
843 host->req = req;
844
845 writew(0xffff, host->base + JZ_REG_MMC_IREG);
846
847 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
848 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
849
850 host->state = JZ4740_MMC_STATE_READ_RESPONSE;
851 set_bit(0, &host->waiting);
852 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
853 jz4740_mmc_send_command(host, req->cmd);
854}
855
856static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
857{
858 struct jz4740_mmc_host *host = mmc_priv(mmc);
859 if (ios->clock)
860 jz4740_mmc_set_clock_rate(host, ios->clock);
861
862 switch (ios->power_mode) {
863 case MMC_POWER_UP:
864 jz4740_mmc_reset(host);
865 if (gpio_is_valid(host->pdata->gpio_power))
866 gpio_set_value(host->pdata->gpio_power,
867 !host->pdata->power_active_low);
868 host->cmdat |= JZ_MMC_CMDAT_INIT;
869 clk_prepare_enable(host->clk);
870 break;
871 case MMC_POWER_ON:
872 break;
873 default:
874 if (gpio_is_valid(host->pdata->gpio_power))
875 gpio_set_value(host->pdata->gpio_power,
876 host->pdata->power_active_low);
877 clk_disable_unprepare(host->clk);
878 break;
879 }
880
881 switch (ios->bus_width) {
882 case MMC_BUS_WIDTH_1:
883 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
884 break;
885 case MMC_BUS_WIDTH_4:
886 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
887 break;
888 default:
889 break;
890 }
891}
892
893static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
894{
895 struct jz4740_mmc_host *host = mmc_priv(mmc);
896 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
897}
898
899static const struct mmc_host_ops jz4740_mmc_ops = {
900 .request = jz4740_mmc_request,
901 .pre_req = jz4740_mmc_pre_request,
902 .post_req = jz4740_mmc_post_request,
903 .set_ios = jz4740_mmc_set_ios,
904 .get_ro = mmc_gpio_get_ro,
905 .get_cd = mmc_gpio_get_cd,
906 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
907};
908
909static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
910 JZ_GPIO_BULK_PIN(MSC_CMD),
911 JZ_GPIO_BULK_PIN(MSC_CLK),
912 JZ_GPIO_BULK_PIN(MSC_DATA0),
913 JZ_GPIO_BULK_PIN(MSC_DATA1),
914 JZ_GPIO_BULK_PIN(MSC_DATA2),
915 JZ_GPIO_BULK_PIN(MSC_DATA3),
916};
917
918static int jz4740_mmc_request_gpio(struct device *dev, int gpio,
919 const char *name, bool output, int value)
920{
921 int ret;
922
923 if (!gpio_is_valid(gpio))
924 return 0;
925
926 ret = gpio_request(gpio, name);
927 if (ret) {
928 dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
929 return ret;
930 }
931
932 if (output)
933 gpio_direction_output(gpio, value);
934 else
935 gpio_direction_input(gpio);
936
937 return 0;
938}
939
940static int jz4740_mmc_request_gpios(struct mmc_host *mmc,
941 struct platform_device *pdev)
942{
943 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
944 int ret = 0;
945
946 if (!pdata)
947 return 0;
948
949 if (!pdata->card_detect_active_low)
950 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
951 if (!pdata->read_only_active_low)
952 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
953
954 if (gpio_is_valid(pdata->gpio_card_detect)) {
955 ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0);
956 if (ret)
957 return ret;
958 }
959
960 if (gpio_is_valid(pdata->gpio_read_only)) {
961 ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only);
962 if (ret)
963 return ret;
964 }
965
966 return jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
967 "MMC read only", true, pdata->power_active_low);
968}
969
970static void jz4740_mmc_free_gpios(struct platform_device *pdev)
971{
972 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
973
974 if (!pdata)
975 return;
976
977 if (gpio_is_valid(pdata->gpio_power))
978 gpio_free(pdata->gpio_power);
979}
980
981static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
982{
983 size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
984 if (host->pdata && host->pdata->data_1bit)
985 num_pins -= 3;
986
987 return num_pins;
988}
989
990static int jz4740_mmc_probe(struct platform_device* pdev)
991{
992 int ret;
993 struct mmc_host *mmc;
994 struct jz4740_mmc_host *host;
995 struct jz4740_mmc_platform_data *pdata;
996
997 pdata = pdev->dev.platform_data;
998
999 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
1000 if (!mmc) {
1001 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
1002 return -ENOMEM;
1003 }
1004
1005 host = mmc_priv(mmc);
1006 host->pdata = pdata;
1007
1008 host->irq = platform_get_irq(pdev, 0);
1009 if (host->irq < 0) {
1010 ret = host->irq;
1011 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
1012 goto err_free_host;
1013 }
1014
1015 host->clk = devm_clk_get(&pdev->dev, "mmc");
1016 if (IS_ERR(host->clk)) {
1017 ret = PTR_ERR(host->clk);
1018 dev_err(&pdev->dev, "Failed to get mmc clock\n");
1019 goto err_free_host;
1020 }
1021
1022 host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1023 host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
1024 if (IS_ERR(host->base)) {
1025 ret = PTR_ERR(host->base);
1026 dev_err(&pdev->dev, "Failed to ioremap base memory\n");
1027 goto err_free_host;
1028 }
1029
1030 ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1031 if (ret) {
1032 dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
1033 goto err_free_host;
1034 }
1035
1036 ret = jz4740_mmc_request_gpios(mmc, pdev);
1037 if (ret)
1038 goto err_gpio_bulk_free;
1039
1040 mmc->ops = &jz4740_mmc_ops;
1041 mmc->f_min = JZ_MMC_CLK_RATE / 128;
1042 mmc->f_max = JZ_MMC_CLK_RATE;
1043 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1044 mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
1045 mmc->caps |= MMC_CAP_SDIO_IRQ;
1046
1047 mmc->max_blk_size = (1 << 10) - 1;
1048 mmc->max_blk_count = (1 << 15) - 1;
1049 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1050
1051 mmc->max_segs = 128;
1052 mmc->max_seg_size = mmc->max_req_size;
1053
1054 host->mmc = mmc;
1055 host->pdev = pdev;
1056 spin_lock_init(&host->lock);
1057 host->irq_mask = 0xffff;
1058
1059 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
1060 dev_name(&pdev->dev), host);
1061 if (ret) {
1062 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1063 goto err_free_gpios;
1064 }
1065
1066 jz4740_mmc_reset(host);
1067 jz4740_mmc_clock_disable(host);
1068 setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
1069 (unsigned long)host);
1070
1071 host->use_dma = true;
1072 if (host->use_dma && jz4740_mmc_acquire_dma_channels(host) != 0)
1073 host->use_dma = false;
1074
1075 platform_set_drvdata(pdev, host);
1076 ret = mmc_add_host(mmc);
1077
1078 if (ret) {
1079 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
1080 goto err_free_irq;
1081 }
1082 dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
1083
1084 dev_info(&pdev->dev, "Using %s, %d-bit mode\n",
1085 host->use_dma ? "DMA" : "PIO",
1086 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1087
1088 return 0;
1089
1090err_free_irq:
1091 free_irq(host->irq, host);
1092err_free_gpios:
1093 jz4740_mmc_free_gpios(pdev);
1094err_gpio_bulk_free:
1095 if (host->use_dma)
1096 jz4740_mmc_release_dma_channels(host);
1097 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1098err_free_host:
1099 mmc_free_host(mmc);
1100
1101 return ret;
1102}
1103
1104static int jz4740_mmc_remove(struct platform_device *pdev)
1105{
1106 struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
1107
1108 del_timer_sync(&host->timeout_timer);
1109 jz4740_mmc_set_irq_enabled(host, 0xff, false);
1110 jz4740_mmc_reset(host);
1111
1112 mmc_remove_host(host->mmc);
1113
1114 free_irq(host->irq, host);
1115
1116 jz4740_mmc_free_gpios(pdev);
1117 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1118
1119 if (host->use_dma)
1120 jz4740_mmc_release_dma_channels(host);
1121
1122 mmc_free_host(host->mmc);
1123
1124 return 0;
1125}
1126
1127#ifdef CONFIG_PM_SLEEP
1128
1129static int jz4740_mmc_suspend(struct device *dev)
1130{
1131 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1132
1133 jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1134
1135 return 0;
1136}
1137
1138static int jz4740_mmc_resume(struct device *dev)
1139{
1140 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1141
1142 jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1143
1144 return 0;
1145}
1146
1147static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
1148 jz4740_mmc_resume);
1149#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
1150#else
1151#define JZ4740_MMC_PM_OPS NULL
1152#endif
1153
1154static struct platform_driver jz4740_mmc_driver = {
1155 .probe = jz4740_mmc_probe,
1156 .remove = jz4740_mmc_remove,
1157 .driver = {
1158 .name = "jz4740-mmc",
1159 .pm = JZ4740_MMC_PM_OPS,
1160 },
1161};
1162
1163module_platform_driver(jz4740_mmc_driver);
1164
1165MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
1166MODULE_LICENSE("GPL");
1167MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");