1/*
  2 * Copyright (c) 2015 MediaTek Inc.
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 *
  8 * This program is distributed in the hope that it will be useful,
  9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11 * GNU General Public License for more details.
 12 */
 13
 14#include <asm/barrier.h>
 15#include <drm/drmP.h>
 16#include <drm/drm_atomic_helper.h>
 17#include <drm/drm_crtc_helper.h>
 18#include <drm/drm_plane_helper.h>
 19#include <linux/clk.h>
 20#include <linux/pm_runtime.h>
 21#include <soc/mediatek/smi.h>
 22
 23#include "mtk_drm_drv.h"
 24#include "mtk_drm_crtc.h"
 25#include "mtk_drm_ddp.h"
 26#include "mtk_drm_ddp_comp.h"
 27#include "mtk_drm_gem.h"
 28#include "mtk_drm_plane.h"
 29
 30/**
 31 * struct mtk_drm_crtc - MediaTek specific crtc structure.
 32 * @base: crtc object.
 33 * @enabled: records whether crtc_enable succeeded
 34 * @planes: array of 4 drm_plane structures, one for each overlay plane
 35 * @pending_planes: whether any plane has pending changes to be applied
 36 * @config_regs: memory mapped mmsys configuration register space
 37 * @mutex: handle to one of the ten disp_mutex streams
 38 * @ddp_comp_nr: number of components in ddp_comp
 39 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
 40 */
 41struct mtk_drm_crtc {
 42	struct drm_crtc			base;
 43	bool				enabled;
 44
 45	bool				pending_needs_vblank;
 46	struct drm_pending_vblank_event	*event;
 47
 48	struct drm_plane		planes[OVL_LAYER_NR];
 49	bool				pending_planes;
 50
 51	void __iomem			*config_regs;
 52	struct mtk_disp_mutex		*mutex;
 53	unsigned int			ddp_comp_nr;
 54	struct mtk_ddp_comp		**ddp_comp;
 55};
 56
 57struct mtk_crtc_state {
 58	struct drm_crtc_state		base;
 59
 60	bool				pending_config;
 61	unsigned int			pending_width;
 62	unsigned int			pending_height;
 63	unsigned int			pending_vrefresh;
 64};
 65
 66static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
 67{
 68	return container_of(c, struct mtk_drm_crtc, base);
 69}
 70
 71static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
 72{
 73	return container_of(s, struct mtk_crtc_state, base);
 74}
 75
 76static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
 77{
 78	struct drm_crtc *crtc = &mtk_crtc->base;
 79	unsigned long flags;
 80
 81	spin_lock_irqsave(&crtc->dev->event_lock, flags);
 82	drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
 83	drm_crtc_vblank_put(crtc);
 84	mtk_crtc->event = NULL;
 85	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 86}
 87
 88static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
 89{
 90	drm_crtc_handle_vblank(&mtk_crtc->base);
 91	if (mtk_crtc->pending_needs_vblank) {
 92		mtk_drm_crtc_finish_page_flip(mtk_crtc);
 93		mtk_crtc->pending_needs_vblank = false;
 94	}
 95}
 96
 97static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
 98{
 99	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
100	int i;
101
102	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
103		clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
104
105	mtk_disp_mutex_put(mtk_crtc->mutex);
106
107	drm_crtc_cleanup(crtc);
108}
109
110static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
111{
112	struct mtk_crtc_state *state;
113
114	if (crtc->state) {
115		__drm_atomic_helper_crtc_destroy_state(crtc->state);
116
117		state = to_mtk_crtc_state(crtc->state);
118		memset(state, 0, sizeof(*state));
119	} else {
120		state = kzalloc(sizeof(*state), GFP_KERNEL);
121		if (!state)
122			return;
123		crtc->state = &state->base;
124	}
125
126	state->base.crtc = crtc;
127}
128
129static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
130{
131	struct mtk_crtc_state *state;
132
133	state = kzalloc(sizeof(*state), GFP_KERNEL);
134	if (!state)
135		return NULL;
136
137	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
138
139	WARN_ON(state->base.crtc != crtc);
140	state->base.crtc = crtc;
141
142	return &state->base;
143}
144
145static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
146				       struct drm_crtc_state *state)
147{
148	__drm_atomic_helper_crtc_destroy_state(state);
149	kfree(to_mtk_crtc_state(state));
150}
151
152static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
153				    const struct drm_display_mode *mode,
154				    struct drm_display_mode *adjusted_mode)
155{
156	/* Nothing to do here, but this callback is mandatory. */
157	return true;
158}
159
160static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
161{
162	struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
163
164	state->pending_width = crtc->mode.hdisplay;
165	state->pending_height = crtc->mode.vdisplay;
166	state->pending_vrefresh = crtc->mode.vrefresh;
167	wmb();	/* Make sure the above parameters are set before update */
168	state->pending_config = true;
169}
170
171int mtk_drm_crtc_enable_vblank(struct drm_device *drm, unsigned int pipe)
172{
173	struct mtk_drm_private *priv = drm->dev_private;
174	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(priv->crtc[pipe]);
175	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
176
177	mtk_ddp_comp_enable_vblank(ovl, &mtk_crtc->base);
178
179	return 0;
180}
181
182void mtk_drm_crtc_disable_vblank(struct drm_device *drm, unsigned int pipe)
183{
184	struct mtk_drm_private *priv = drm->dev_private;
185	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(priv->crtc[pipe]);
186	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
187
188	mtk_ddp_comp_disable_vblank(ovl);
189}
190
191static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
192{
193	int ret;
194	int i;
195
196	DRM_DEBUG_DRIVER("%s\n", __func__);
197	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
198		ret = clk_enable(mtk_crtc->ddp_comp[i]->clk);
199		if (ret) {
200			DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
201			goto err;
202		}
203	}
204
205	return 0;
206err:
207	while (--i >= 0)
208		clk_disable(mtk_crtc->ddp_comp[i]->clk);
209	return ret;
210}
211
212static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
213{
214	int i;
215
216	DRM_DEBUG_DRIVER("%s\n", __func__);
217	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
218		clk_disable(mtk_crtc->ddp_comp[i]->clk);
219}
220
221static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
222{
223	struct drm_crtc *crtc = &mtk_crtc->base;
224	struct drm_connector *connector;
225	struct drm_encoder *encoder;
226	unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
227	int ret;
228	int i;
229
230	DRM_DEBUG_DRIVER("%s\n", __func__);
231	if (WARN_ON(!crtc->state))
232		return -EINVAL;
233
234	width = crtc->state->adjusted_mode.hdisplay;
235	height = crtc->state->adjusted_mode.vdisplay;
236	vrefresh = crtc->state->adjusted_mode.vrefresh;
237
238	drm_for_each_encoder(encoder, crtc->dev) {
239		if (encoder->crtc != crtc)
240			continue;
241
242		drm_for_each_connector(connector, crtc->dev) {
243			if (connector->encoder != encoder)
244				continue;
245			if (connector->display_info.bpc != 0 &&
246			    bpc > connector->display_info.bpc)
247				bpc = connector->display_info.bpc;
248		}
249	}
250
251	ret = pm_runtime_get_sync(crtc->dev->dev);
252	if (ret < 0) {
253		DRM_ERROR("Failed to enable power domain: %d\n", ret);
254		return ret;
255	}
256
257	ret = mtk_disp_mutex_prepare(mtk_crtc->mutex);
258	if (ret < 0) {
259		DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
260		goto err_pm_runtime_put;
261	}
262
263	ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
264	if (ret < 0) {
265		DRM_ERROR("Failed to enable component clocks: %d\n", ret);
266		goto err_mutex_unprepare;
267	}
268
269	DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
270	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
271		mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
272					 mtk_crtc->ddp_comp[i]->id,
273					 mtk_crtc->ddp_comp[i + 1]->id);
274		mtk_disp_mutex_add_comp(mtk_crtc->mutex,
275					mtk_crtc->ddp_comp[i]->id);
276	}
277	mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
278	mtk_disp_mutex_enable(mtk_crtc->mutex);
279
280	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
281		struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
282
283		mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
284		mtk_ddp_comp_start(comp);
285	}
286
287	/* Initially configure all planes */
288	for (i = 0; i < OVL_LAYER_NR; i++) {
289		struct drm_plane *plane = &mtk_crtc->planes[i];
290		struct mtk_plane_state *plane_state;
291
292		plane_state = to_mtk_plane_state(plane->state);
293		mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[0], i,
294					  plane_state);
295	}
296
297	return 0;
298
299err_mutex_unprepare:
300	mtk_disp_mutex_unprepare(mtk_crtc->mutex);
301err_pm_runtime_put:
302	pm_runtime_put(crtc->dev->dev);
303	return ret;
304}
305
306static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
307{
308	struct drm_device *drm = mtk_crtc->base.dev;
309	int i;
310
311	DRM_DEBUG_DRIVER("%s\n", __func__);
312	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
313		mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
314	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
315		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
316					   mtk_crtc->ddp_comp[i]->id);
317	mtk_disp_mutex_disable(mtk_crtc->mutex);
318	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
319		mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
320					      mtk_crtc->ddp_comp[i]->id,
321					      mtk_crtc->ddp_comp[i + 1]->id);
322		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
323					   mtk_crtc->ddp_comp[i]->id);
324	}
325	mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
326	mtk_crtc_ddp_clk_disable(mtk_crtc);
327	mtk_disp_mutex_unprepare(mtk_crtc->mutex);
328
329	pm_runtime_put(drm->dev);
330}
331
332static void mtk_drm_crtc_enable(struct drm_crtc *crtc)
333{
334	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
335	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
336	int ret;
337
338	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
339
340	ret = mtk_smi_larb_get(ovl->larb_dev);
341	if (ret) {
342		DRM_ERROR("Failed to get larb: %d\n", ret);
343		return;
344	}
345
346	ret = mtk_crtc_ddp_hw_init(mtk_crtc);
347	if (ret) {
348		mtk_smi_larb_put(ovl->larb_dev);
349		return;
350	}
351
352	drm_crtc_vblank_on(crtc);
353	mtk_crtc->enabled = true;
354}
355
356static void mtk_drm_crtc_disable(struct drm_crtc *crtc)
357{
358	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
359	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
360	int i;
361
362	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
363	if (!mtk_crtc->enabled)
364		return;
365
366	/* Set all pending plane state to disabled */
367	for (i = 0; i < OVL_LAYER_NR; i++) {
368		struct drm_plane *plane = &mtk_crtc->planes[i];
369		struct mtk_plane_state *plane_state;
370
371		plane_state = to_mtk_plane_state(plane->state);
372		plane_state->pending.enable = false;
373		plane_state->pending.config = true;
374	}
375	mtk_crtc->pending_planes = true;
376
377	/* Wait for planes to be disabled */
378	drm_crtc_wait_one_vblank(crtc);
379
380	drm_crtc_vblank_off(crtc);
381	mtk_crtc_ddp_hw_fini(mtk_crtc);
382	mtk_smi_larb_put(ovl->larb_dev);
383
384	mtk_crtc->enabled = false;
385}
386
387static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
388				      struct drm_crtc_state *old_crtc_state)
389{
390	struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
391	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
392
393	if (mtk_crtc->event && state->base.event)
394		DRM_ERROR("new event while there is still a pending event\n");
395
396	if (state->base.event) {
397		state->base.event->pipe = drm_crtc_index(crtc);
398		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
399		mtk_crtc->event = state->base.event;
400		state->base.event = NULL;
401	}
402}
403
404static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
405				      struct drm_crtc_state *old_crtc_state)
406{
407	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
408	unsigned int pending_planes = 0;
409	int i;
410
411	if (mtk_crtc->event)
412		mtk_crtc->pending_needs_vblank = true;
413	for (i = 0; i < OVL_LAYER_NR; i++) {
414		struct drm_plane *plane = &mtk_crtc->planes[i];
415		struct mtk_plane_state *plane_state;
416
417		plane_state = to_mtk_plane_state(plane->state);
418		if (plane_state->pending.dirty) {
419			plane_state->pending.config = true;
420			plane_state->pending.dirty = false;
421			pending_planes |= BIT(i);
422		}
423	}
424	if (pending_planes)
425		mtk_crtc->pending_planes = true;
426	if (crtc->state->color_mgmt_changed)
427		for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
428			mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
429}
430
431static const struct drm_crtc_funcs mtk_crtc_funcs = {
432	.set_config		= drm_atomic_helper_set_config,
433	.page_flip		= drm_atomic_helper_page_flip,
434	.destroy		= mtk_drm_crtc_destroy,
435	.reset			= mtk_drm_crtc_reset,
436	.atomic_duplicate_state	= mtk_drm_crtc_duplicate_state,
437	.atomic_destroy_state	= mtk_drm_crtc_destroy_state,
438	.gamma_set		= drm_atomic_helper_legacy_gamma_set,
439};
440
441static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
442	.mode_fixup	= mtk_drm_crtc_mode_fixup,
443	.mode_set_nofb	= mtk_drm_crtc_mode_set_nofb,
444	.enable		= mtk_drm_crtc_enable,
445	.disable	= mtk_drm_crtc_disable,
446	.atomic_begin	= mtk_drm_crtc_atomic_begin,
447	.atomic_flush	= mtk_drm_crtc_atomic_flush,
448};
449
450static int mtk_drm_crtc_init(struct drm_device *drm,
451			     struct mtk_drm_crtc *mtk_crtc,
452			     struct drm_plane *primary,
453			     struct drm_plane *cursor, unsigned int pipe)
454{
455	int ret;
456
457	ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
458					&mtk_crtc_funcs, NULL);
459	if (ret)
460		goto err_cleanup_crtc;
461
462	drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
463
464	return 0;
465
466err_cleanup_crtc:
467	drm_crtc_cleanup(&mtk_crtc->base);
468	return ret;
469}
470
471void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
472{
473	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
474	struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
475	unsigned int i;
476
477	/*
478	 * TODO: instead of updating the registers here, we should prepare
479	 * working registers in atomic_commit and let the hardware command
480	 * queue update module registers on vblank.
481	 */
482	if (state->pending_config) {
483		mtk_ddp_comp_config(ovl, state->pending_width,
484				    state->pending_height,
485				    state->pending_vrefresh, 0);
486
487		state->pending_config = false;
488	}
489
490	if (mtk_crtc->pending_planes) {
491		for (i = 0; i < OVL_LAYER_NR; i++) {
492			struct drm_plane *plane = &mtk_crtc->planes[i];
493			struct mtk_plane_state *plane_state;
494
495			plane_state = to_mtk_plane_state(plane->state);
496
497			if (plane_state->pending.config) {
498				mtk_ddp_comp_layer_config(ovl, i, plane_state);
499				plane_state->pending.config = false;
500			}
501		}
502		mtk_crtc->pending_planes = false;
503	}
504
505	mtk_drm_finish_page_flip(mtk_crtc);
506}
507
508int mtk_drm_crtc_create(struct drm_device *drm_dev,
509			const enum mtk_ddp_comp_id *path, unsigned int path_len)
510{
511	struct mtk_drm_private *priv = drm_dev->dev_private;
512	struct device *dev = drm_dev->dev;
513	struct mtk_drm_crtc *mtk_crtc;
514	enum drm_plane_type type;
515	unsigned int zpos;
516	int pipe = priv->num_pipes;
517	int ret;
518	int i;
519
520	for (i = 0; i < path_len; i++) {
521		enum mtk_ddp_comp_id comp_id = path[i];
522		struct device_node *node;
523
524		node = priv->comp_node[comp_id];
525		if (!node) {
526			dev_info(dev,
527				 "Not creating crtc %d because component %d is disabled or missing\n",
528				 pipe, comp_id);
529			return 0;
530		}
531	}
532
533	mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
534	if (!mtk_crtc)
535		return -ENOMEM;
536
537	mtk_crtc->config_regs = priv->config_regs;
538	mtk_crtc->ddp_comp_nr = path_len;
539	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
540						sizeof(*mtk_crtc->ddp_comp),
541						GFP_KERNEL);
542
543	mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe);
544	if (IS_ERR(mtk_crtc->mutex)) {
545		ret = PTR_ERR(mtk_crtc->mutex);
546		dev_err(dev, "Failed to get mutex: %d\n", ret);
547		return ret;
548	}
549
550	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
551		enum mtk_ddp_comp_id comp_id = path[i];
552		struct mtk_ddp_comp *comp;
553		struct device_node *node;
554
555		node = priv->comp_node[comp_id];
556		comp = priv->ddp_comp[comp_id];
557		if (!comp) {
558			dev_err(dev, "Component %s not initialized\n",
559				node->full_name);
560			ret = -ENODEV;
561			goto unprepare;
562		}
563
564		ret = clk_prepare(comp->clk);
565		if (ret) {
566			dev_err(dev,
567				"Failed to prepare clock for component %s: %d\n",
568				node->full_name, ret);
569			goto unprepare;
570		}
571
572		mtk_crtc->ddp_comp[i] = comp;
573	}
574
575	for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) {
576		type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :
577				(zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
578						DRM_PLANE_TYPE_OVERLAY;
579		ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
580				     BIT(pipe), type);
581		if (ret)
582			goto unprepare;
583	}
584
585	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
586				&mtk_crtc->planes[1], pipe);
587	if (ret < 0)
588		goto unprepare;
589	drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
590	drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
591	priv->crtc[pipe] = &mtk_crtc->base;
592	priv->num_pipes++;
593
594	return 0;
595
596unprepare:
597	while (--i >= 0)
598		clk_unprepare(mtk_crtc->ddp_comp[i]->clk);
599
600	return ret;
601}