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1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/component.h>
19#include <linux/hdmi.h>
20#include <linux/module.h>
21#include <linux/irq.h>
22#include <sound/asoundef.h>
23
24#include <drm/drmP.h>
25#include <drm/drm_atomic_helper.h>
26#include <drm/drm_crtc_helper.h>
27#include <drm/drm_edid.h>
28#include <drm/drm_of.h>
29#include <drm/i2c/tda998x.h>
30
31#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
32
33struct tda998x_priv {
34 struct i2c_client *cec;
35 struct i2c_client *hdmi;
36 struct mutex mutex;
37 u16 rev;
38 u8 current_page;
39 int dpms;
40 bool is_hdmi_sink;
41 u8 vip_cntrl_0;
42 u8 vip_cntrl_1;
43 u8 vip_cntrl_2;
44 struct tda998x_encoder_params params;
45
46 wait_queue_head_t wq_edid;
47 volatile int wq_edid_wait;
48
49 struct work_struct detect_work;
50 struct timer_list edid_delay_timer;
51 wait_queue_head_t edid_delay_waitq;
52 bool edid_delay_active;
53
54 struct drm_encoder encoder;
55 struct drm_connector connector;
56};
57
58#define conn_to_tda998x_priv(x) \
59 container_of(x, struct tda998x_priv, connector)
60
61#define enc_to_tda998x_priv(x) \
62 container_of(x, struct tda998x_priv, encoder)
63
64/* The TDA9988 series of devices use a paged register scheme.. to simplify
65 * things we encode the page # in upper bits of the register #. To read/
66 * write a given register, we need to make sure CURPAGE register is set
67 * appropriately. Which implies reads/writes are not atomic. Fun!
68 */
69
70#define REG(page, addr) (((page) << 8) | (addr))
71#define REG2ADDR(reg) ((reg) & 0xff)
72#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
73
74#define REG_CURPAGE 0xff /* write */
75
76
77/* Page 00h: General Control */
78#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
79#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
80# define MAIN_CNTRL0_SR (1 << 0)
81# define MAIN_CNTRL0_DECS (1 << 1)
82# define MAIN_CNTRL0_DEHS (1 << 2)
83# define MAIN_CNTRL0_CECS (1 << 3)
84# define MAIN_CNTRL0_CEHS (1 << 4)
85# define MAIN_CNTRL0_SCALER (1 << 7)
86#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
87#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
88# define SOFTRESET_AUDIO (1 << 0)
89# define SOFTRESET_I2C_MASTER (1 << 1)
90#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
91#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
92#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
93# define I2C_MASTER_DIS_MM (1 << 0)
94# define I2C_MASTER_DIS_FILT (1 << 1)
95# define I2C_MASTER_APP_STRT_LAT (1 << 2)
96#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
97# define FEAT_POWERDOWN_SPDIF (1 << 3)
98#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
99#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
100#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
101# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
102#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
103#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
104#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
105#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
106#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
107#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
108# define VIP_CNTRL_0_MIRR_A (1 << 7)
109# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
110# define VIP_CNTRL_0_MIRR_B (1 << 3)
111# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
112#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
113# define VIP_CNTRL_1_MIRR_C (1 << 7)
114# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
115# define VIP_CNTRL_1_MIRR_D (1 << 3)
116# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
117#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
118# define VIP_CNTRL_2_MIRR_E (1 << 7)
119# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
120# define VIP_CNTRL_2_MIRR_F (1 << 3)
121# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
122#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
123# define VIP_CNTRL_3_X_TGL (1 << 0)
124# define VIP_CNTRL_3_H_TGL (1 << 1)
125# define VIP_CNTRL_3_V_TGL (1 << 2)
126# define VIP_CNTRL_3_EMB (1 << 3)
127# define VIP_CNTRL_3_SYNC_DE (1 << 4)
128# define VIP_CNTRL_3_SYNC_HS (1 << 5)
129# define VIP_CNTRL_3_DE_INT (1 << 6)
130# define VIP_CNTRL_3_EDGE (1 << 7)
131#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
132# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
133# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
134# define VIP_CNTRL_4_CCIR656 (1 << 4)
135# define VIP_CNTRL_4_656_ALT (1 << 5)
136# define VIP_CNTRL_4_TST_656 (1 << 6)
137# define VIP_CNTRL_4_TST_PAT (1 << 7)
138#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
139# define VIP_CNTRL_5_CKCASE (1 << 0)
140# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
141#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
142# define MUX_AP_SELECT_I2S 0x64
143# define MUX_AP_SELECT_SPDIF 0x40
144#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
145#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
146# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
147# define MAT_CONTRL_MAT_BP (1 << 2)
148#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
149#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
150#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
151#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
152#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
153#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
154#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
155#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
156#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
157#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
158#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
159#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
160#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
161#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
162#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
163#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
164#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
165#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
166#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
167#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
168#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
169#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
170#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
171#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
172#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
173#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
174#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
175#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
176#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
177#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
178#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
179#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
180#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
181#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
182#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
183#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
184#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
185#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
186#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
187#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
188#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
189#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
190# define TBG_CNTRL_0_TOP_TGL (1 << 0)
191# define TBG_CNTRL_0_TOP_SEL (1 << 1)
192# define TBG_CNTRL_0_DE_EXT (1 << 2)
193# define TBG_CNTRL_0_TOP_EXT (1 << 3)
194# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
195# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
196# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
197#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
198# define TBG_CNTRL_1_H_TGL (1 << 0)
199# define TBG_CNTRL_1_V_TGL (1 << 1)
200# define TBG_CNTRL_1_TGL_EN (1 << 2)
201# define TBG_CNTRL_1_X_EXT (1 << 3)
202# define TBG_CNTRL_1_H_EXT (1 << 4)
203# define TBG_CNTRL_1_V_EXT (1 << 5)
204# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
205#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
206#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
207# define HVF_CNTRL_0_SM (1 << 7)
208# define HVF_CNTRL_0_RWB (1 << 6)
209# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
210# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
211#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
212# define HVF_CNTRL_1_FOR (1 << 0)
213# define HVF_CNTRL_1_YUVBLK (1 << 1)
214# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
215# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
216# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
217#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
218#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
219# define I2S_FORMAT(x) (((x) & 3) << 0)
220#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
221# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
222# define AIP_CLKSEL_AIP_I2S (1 << 3)
223# define AIP_CLKSEL_FS_ACLK (0 << 0)
224# define AIP_CLKSEL_FS_MCLK (1 << 0)
225# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
226
227/* Page 02h: PLL settings */
228#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
229# define PLL_SERIAL_1_SRL_FDN (1 << 0)
230# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
231# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
232#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
233# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
234# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
235#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
236# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
237# define PLL_SERIAL_3_SRL_DE (1 << 2)
238# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
239#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
240#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
241#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
242#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
243#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
244#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
245#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
246#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
247#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
248# define AUDIO_DIV_SERCLK_1 0
249# define AUDIO_DIV_SERCLK_2 1
250# define AUDIO_DIV_SERCLK_4 2
251# define AUDIO_DIV_SERCLK_8 3
252# define AUDIO_DIV_SERCLK_16 4
253# define AUDIO_DIV_SERCLK_32 5
254#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
255# define SEL_CLK_SEL_CLK1 (1 << 0)
256# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
257# define SEL_CLK_ENA_SC_CLK (1 << 3)
258#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
259
260
261/* Page 09h: EDID Control */
262#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
263/* next 127 successive registers are the EDID block */
264#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
265#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
266#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
267#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
268#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
269
270
271/* Page 10h: information frames and packets */
272#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
273#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
274#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
275#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
276#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
277
278
279/* Page 11h: audio settings and content info packets */
280#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
281# define AIP_CNTRL_0_RST_FIFO (1 << 0)
282# define AIP_CNTRL_0_SWAP (1 << 1)
283# define AIP_CNTRL_0_LAYOUT (1 << 2)
284# define AIP_CNTRL_0_ACR_MAN (1 << 5)
285# define AIP_CNTRL_0_RST_CTS (1 << 6)
286#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
287# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
288# define CA_I2S_HBR_CHSTAT (1 << 6)
289#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
290#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
291#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
292#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
293#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
294#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
295#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
296#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
297# define CTS_N_K(x) (((x) & 7) << 0)
298# define CTS_N_M(x) (((x) & 3) << 4)
299#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
300# define ENC_CNTRL_RST_ENC (1 << 0)
301# define ENC_CNTRL_RST_SEL (1 << 1)
302# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
303#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
304# define DIP_FLAGS_ACR (1 << 0)
305# define DIP_FLAGS_GC (1 << 1)
306#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
307# define DIP_IF_FLAGS_IF1 (1 << 1)
308# define DIP_IF_FLAGS_IF2 (1 << 2)
309# define DIP_IF_FLAGS_IF3 (1 << 3)
310# define DIP_IF_FLAGS_IF4 (1 << 4)
311# define DIP_IF_FLAGS_IF5 (1 << 5)
312#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
313
314
315/* Page 12h: HDCP and OTP */
316#define REG_TX3 REG(0x12, 0x9a) /* read/write */
317#define REG_TX4 REG(0x12, 0x9b) /* read/write */
318# define TX4_PD_RAM (1 << 1)
319#define REG_TX33 REG(0x12, 0xb8) /* read/write */
320# define TX33_HDMI (1 << 1)
321
322
323/* Page 13h: Gamut related metadata packets */
324
325
326
327/* CEC registers: (not paged)
328 */
329#define REG_CEC_INTSTATUS 0xee /* read */
330# define CEC_INTSTATUS_CEC (1 << 0)
331# define CEC_INTSTATUS_HDMI (1 << 1)
332#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
333# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
334# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
335# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
336# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
337#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
338#define REG_CEC_RXSHPDINT 0xfd /* read */
339# define CEC_RXSHPDINT_RXSENS BIT(0)
340# define CEC_RXSHPDINT_HPD BIT(1)
341#define REG_CEC_RXSHPDLEV 0xfe /* read */
342# define CEC_RXSHPDLEV_RXSENS (1 << 0)
343# define CEC_RXSHPDLEV_HPD (1 << 1)
344
345#define REG_CEC_ENAMODS 0xff /* read/write */
346# define CEC_ENAMODS_DIS_FRO (1 << 6)
347# define CEC_ENAMODS_DIS_CCLK (1 << 5)
348# define CEC_ENAMODS_EN_RXSENS (1 << 2)
349# define CEC_ENAMODS_EN_HDMI (1 << 1)
350# define CEC_ENAMODS_EN_CEC (1 << 0)
351
352
353/* Device versions: */
354#define TDA9989N2 0x0101
355#define TDA19989 0x0201
356#define TDA19989N2 0x0202
357#define TDA19988 0x0301
358
359static void
360cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
361{
362 struct i2c_client *client = priv->cec;
363 u8 buf[] = {addr, val};
364 int ret;
365
366 ret = i2c_master_send(client, buf, sizeof(buf));
367 if (ret < 0)
368 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
369}
370
371static u8
372cec_read(struct tda998x_priv *priv, u8 addr)
373{
374 struct i2c_client *client = priv->cec;
375 u8 val;
376 int ret;
377
378 ret = i2c_master_send(client, &addr, sizeof(addr));
379 if (ret < 0)
380 goto fail;
381
382 ret = i2c_master_recv(client, &val, sizeof(val));
383 if (ret < 0)
384 goto fail;
385
386 return val;
387
388fail:
389 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
390 return 0;
391}
392
393static int
394set_page(struct tda998x_priv *priv, u16 reg)
395{
396 if (REG2PAGE(reg) != priv->current_page) {
397 struct i2c_client *client = priv->hdmi;
398 u8 buf[] = {
399 REG_CURPAGE, REG2PAGE(reg)
400 };
401 int ret = i2c_master_send(client, buf, sizeof(buf));
402 if (ret < 0) {
403 dev_err(&client->dev, "%s %04x err %d\n", __func__,
404 reg, ret);
405 return ret;
406 }
407
408 priv->current_page = REG2PAGE(reg);
409 }
410 return 0;
411}
412
413static int
414reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
415{
416 struct i2c_client *client = priv->hdmi;
417 u8 addr = REG2ADDR(reg);
418 int ret;
419
420 mutex_lock(&priv->mutex);
421 ret = set_page(priv, reg);
422 if (ret < 0)
423 goto out;
424
425 ret = i2c_master_send(client, &addr, sizeof(addr));
426 if (ret < 0)
427 goto fail;
428
429 ret = i2c_master_recv(client, buf, cnt);
430 if (ret < 0)
431 goto fail;
432
433 goto out;
434
435fail:
436 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
437out:
438 mutex_unlock(&priv->mutex);
439 return ret;
440}
441
442static void
443reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
444{
445 struct i2c_client *client = priv->hdmi;
446 u8 buf[cnt+1];
447 int ret;
448
449 buf[0] = REG2ADDR(reg);
450 memcpy(&buf[1], p, cnt);
451
452 mutex_lock(&priv->mutex);
453 ret = set_page(priv, reg);
454 if (ret < 0)
455 goto out;
456
457 ret = i2c_master_send(client, buf, cnt + 1);
458 if (ret < 0)
459 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
460out:
461 mutex_unlock(&priv->mutex);
462}
463
464static int
465reg_read(struct tda998x_priv *priv, u16 reg)
466{
467 u8 val = 0;
468 int ret;
469
470 ret = reg_read_range(priv, reg, &val, sizeof(val));
471 if (ret < 0)
472 return ret;
473 return val;
474}
475
476static void
477reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
478{
479 struct i2c_client *client = priv->hdmi;
480 u8 buf[] = {REG2ADDR(reg), val};
481 int ret;
482
483 mutex_lock(&priv->mutex);
484 ret = set_page(priv, reg);
485 if (ret < 0)
486 goto out;
487
488 ret = i2c_master_send(client, buf, sizeof(buf));
489 if (ret < 0)
490 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
491out:
492 mutex_unlock(&priv->mutex);
493}
494
495static void
496reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
497{
498 struct i2c_client *client = priv->hdmi;
499 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
500 int ret;
501
502 mutex_lock(&priv->mutex);
503 ret = set_page(priv, reg);
504 if (ret < 0)
505 goto out;
506
507 ret = i2c_master_send(client, buf, sizeof(buf));
508 if (ret < 0)
509 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
510out:
511 mutex_unlock(&priv->mutex);
512}
513
514static void
515reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
516{
517 int old_val;
518
519 old_val = reg_read(priv, reg);
520 if (old_val >= 0)
521 reg_write(priv, reg, old_val | val);
522}
523
524static void
525reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
526{
527 int old_val;
528
529 old_val = reg_read(priv, reg);
530 if (old_val >= 0)
531 reg_write(priv, reg, old_val & ~val);
532}
533
534static void
535tda998x_reset(struct tda998x_priv *priv)
536{
537 /* reset audio and i2c master: */
538 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
539 msleep(50);
540 reg_write(priv, REG_SOFTRESET, 0);
541 msleep(50);
542
543 /* reset transmitter: */
544 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
545 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
546
547 /* PLL registers common configuration */
548 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
549 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
550 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
551 reg_write(priv, REG_SERIALIZER, 0x00);
552 reg_write(priv, REG_BUFFER_OUT, 0x00);
553 reg_write(priv, REG_PLL_SCG1, 0x00);
554 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
555 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
556 reg_write(priv, REG_PLL_SCGN1, 0xfa);
557 reg_write(priv, REG_PLL_SCGN2, 0x00);
558 reg_write(priv, REG_PLL_SCGR1, 0x5b);
559 reg_write(priv, REG_PLL_SCGR2, 0x00);
560 reg_write(priv, REG_PLL_SCG2, 0x10);
561
562 /* Write the default value MUX register */
563 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
564}
565
566/*
567 * The TDA998x has a problem when trying to read the EDID close to a
568 * HPD assertion: it needs a delay of 100ms to avoid timing out while
569 * trying to read EDID data.
570 *
571 * However, tda998x_encoder_get_modes() may be called at any moment
572 * after tda998x_connector_detect() indicates that we are connected, so
573 * we need to delay probing modes in tda998x_encoder_get_modes() after
574 * we have seen a HPD inactive->active transition. This code implements
575 * that delay.
576 */
577static void tda998x_edid_delay_done(unsigned long data)
578{
579 struct tda998x_priv *priv = (struct tda998x_priv *)data;
580
581 priv->edid_delay_active = false;
582 wake_up(&priv->edid_delay_waitq);
583 schedule_work(&priv->detect_work);
584}
585
586static void tda998x_edid_delay_start(struct tda998x_priv *priv)
587{
588 priv->edid_delay_active = true;
589 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
590}
591
592static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
593{
594 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
595}
596
597/*
598 * We need to run the KMS hotplug event helper outside of our threaded
599 * interrupt routine as this can call back into our get_modes method,
600 * which will want to make use of interrupts.
601 */
602static void tda998x_detect_work(struct work_struct *work)
603{
604 struct tda998x_priv *priv =
605 container_of(work, struct tda998x_priv, detect_work);
606 struct drm_device *dev = priv->encoder.dev;
607
608 if (dev)
609 drm_kms_helper_hotplug_event(dev);
610}
611
612/*
613 * only 2 interrupts may occur: screen plug/unplug and EDID read
614 */
615static irqreturn_t tda998x_irq_thread(int irq, void *data)
616{
617 struct tda998x_priv *priv = data;
618 u8 sta, cec, lvl, flag0, flag1, flag2;
619 bool handled = false;
620
621 sta = cec_read(priv, REG_CEC_INTSTATUS);
622 cec = cec_read(priv, REG_CEC_RXSHPDINT);
623 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
624 flag0 = reg_read(priv, REG_INT_FLAGS_0);
625 flag1 = reg_read(priv, REG_INT_FLAGS_1);
626 flag2 = reg_read(priv, REG_INT_FLAGS_2);
627 DRM_DEBUG_DRIVER(
628 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
629 sta, cec, lvl, flag0, flag1, flag2);
630
631 if (cec & CEC_RXSHPDINT_HPD) {
632 if (lvl & CEC_RXSHPDLEV_HPD)
633 tda998x_edid_delay_start(priv);
634 else
635 schedule_work(&priv->detect_work);
636
637 handled = true;
638 }
639
640 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
641 priv->wq_edid_wait = 0;
642 wake_up(&priv->wq_edid);
643 handled = true;
644 }
645
646 return IRQ_RETVAL(handled);
647}
648
649static void
650tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
651 union hdmi_infoframe *frame)
652{
653 u8 buf[32];
654 ssize_t len;
655
656 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
657 if (len < 0) {
658 dev_err(&priv->hdmi->dev,
659 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
660 frame->any.type, len);
661 return;
662 }
663
664 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
665 reg_write_range(priv, addr, buf, len);
666 reg_set(priv, REG_DIP_IF_FLAGS, bit);
667}
668
669static void
670tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
671{
672 union hdmi_infoframe frame;
673
674 hdmi_audio_infoframe_init(&frame.audio);
675
676 frame.audio.channels = p->audio_frame[1] & 0x07;
677 frame.audio.channel_allocation = p->audio_frame[4];
678 frame.audio.level_shift_value = (p->audio_frame[5] & 0x78) >> 3;
679 frame.audio.downmix_inhibit = (p->audio_frame[5] & 0x80) >> 7;
680
681 /*
682 * L-PCM and IEC61937 compressed audio shall always set sample
683 * frequency to "refer to stream". For others, see the HDMI
684 * specification.
685 */
686 frame.audio.sample_frequency = (p->audio_frame[2] & 0x1c) >> 2;
687
688 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
689}
690
691static void
692tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
693{
694 union hdmi_infoframe frame;
695
696 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
697 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
698
699 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
700}
701
702static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
703{
704 if (on) {
705 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
706 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
707 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
708 } else {
709 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
710 }
711}
712
713static void
714tda998x_configure_audio(struct tda998x_priv *priv,
715 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
716{
717 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
718 u32 n;
719
720 /* Enable audio ports */
721 reg_write(priv, REG_ENA_AP, p->audio_cfg);
722 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
723
724 /* Set audio input source */
725 switch (p->audio_format) {
726 case AFMT_SPDIF:
727 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
728 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
729 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
730 cts_n = CTS_N_M(3) | CTS_N_K(3);
731 break;
732
733 case AFMT_I2S:
734 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
735 clksel_aip = AIP_CLKSEL_AIP_I2S;
736 clksel_fs = AIP_CLKSEL_FS_ACLK;
737 cts_n = CTS_N_M(3) | CTS_N_K(3);
738 break;
739
740 default:
741 BUG();
742 return;
743 }
744
745 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
746 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
747 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
748 reg_write(priv, REG_CTS_N, cts_n);
749
750 /*
751 * Audio input somehow depends on HDMI line rate which is
752 * related to pixclk. Testing showed that modes with pixclk
753 * >100MHz need a larger divider while <40MHz need the default.
754 * There is no detailed info in the datasheet, so we just
755 * assume 100MHz requires larger divider.
756 */
757 adiv = AUDIO_DIV_SERCLK_8;
758 if (mode->clock > 100000)
759 adiv++; /* AUDIO_DIV_SERCLK_16 */
760
761 /* S/PDIF asks for a larger divider */
762 if (p->audio_format == AFMT_SPDIF)
763 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
764
765 reg_write(priv, REG_AUDIO_DIV, adiv);
766
767 /*
768 * This is the approximate value of N, which happens to be
769 * the recommended values for non-coherent clocks.
770 */
771 n = 128 * p->audio_sample_rate / 1000;
772
773 /* Write the CTS and N values */
774 buf[0] = 0x44;
775 buf[1] = 0x42;
776 buf[2] = 0x01;
777 buf[3] = n;
778 buf[4] = n >> 8;
779 buf[5] = n >> 16;
780 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
781
782 /* Set CTS clock reference */
783 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
784
785 /* Reset CTS generator */
786 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
787 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
788
789 /* Write the channel status */
790 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
791 buf[1] = 0x00;
792 buf[2] = IEC958_AES3_CON_FS_NOTID;
793 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
794 IEC958_AES4_CON_MAX_WORDLEN_24;
795 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
796
797 tda998x_audio_mute(priv, true);
798 msleep(20);
799 tda998x_audio_mute(priv, false);
800
801 /* Write the audio information packet */
802 tda998x_write_aif(priv, p);
803}
804
805/* DRM encoder functions */
806
807static void tda998x_encoder_set_config(struct tda998x_priv *priv,
808 const struct tda998x_encoder_params *p)
809{
810 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
811 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
812 VIP_CNTRL_0_SWAP_B(p->swap_b) |
813 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
814 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
815 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
816 VIP_CNTRL_1_SWAP_D(p->swap_d) |
817 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
818 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
819 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
820 VIP_CNTRL_2_SWAP_F(p->swap_f) |
821 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
822
823 priv->params = *p;
824}
825
826static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
827{
828 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
829
830 /* we only care about on or off: */
831 if (mode != DRM_MODE_DPMS_ON)
832 mode = DRM_MODE_DPMS_OFF;
833
834 if (mode == priv->dpms)
835 return;
836
837 switch (mode) {
838 case DRM_MODE_DPMS_ON:
839 /* enable video ports, audio will be enabled later */
840 reg_write(priv, REG_ENA_VP_0, 0xff);
841 reg_write(priv, REG_ENA_VP_1, 0xff);
842 reg_write(priv, REG_ENA_VP_2, 0xff);
843 /* set muxing after enabling ports: */
844 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
845 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
846 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
847 break;
848 case DRM_MODE_DPMS_OFF:
849 /* disable video ports */
850 reg_write(priv, REG_ENA_VP_0, 0x00);
851 reg_write(priv, REG_ENA_VP_1, 0x00);
852 reg_write(priv, REG_ENA_VP_2, 0x00);
853 break;
854 }
855
856 priv->dpms = mode;
857}
858
859static int tda998x_connector_mode_valid(struct drm_connector *connector,
860 struct drm_display_mode *mode)
861{
862 /* TDA19988 dotclock can go up to 165MHz */
863 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
864
865 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
866 return MODE_CLOCK_HIGH;
867 if (mode->htotal >= BIT(13))
868 return MODE_BAD_HVALUE;
869 if (mode->vtotal >= BIT(11))
870 return MODE_BAD_VVALUE;
871 return MODE_OK;
872}
873
874static void
875tda998x_encoder_mode_set(struct drm_encoder *encoder,
876 struct drm_display_mode *mode,
877 struct drm_display_mode *adjusted_mode)
878{
879 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
880 u16 ref_pix, ref_line, n_pix, n_line;
881 u16 hs_pix_s, hs_pix_e;
882 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
883 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
884 u16 vwin1_line_s, vwin1_line_e;
885 u16 vwin2_line_s, vwin2_line_e;
886 u16 de_pix_s, de_pix_e;
887 u8 reg, div, rep;
888
889 /*
890 * Internally TDA998x is using ITU-R BT.656 style sync but
891 * we get VESA style sync. TDA998x is using a reference pixel
892 * relative to ITU to sync to the input frame and for output
893 * sync generation. Currently, we are using reference detection
894 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
895 * which is position of rising VS with coincident rising HS.
896 *
897 * Now there is some issues to take care of:
898 * - HDMI data islands require sync-before-active
899 * - TDA998x register values must be > 0 to be enabled
900 * - REFLINE needs an additional offset of +1
901 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
902 *
903 * So we add +1 to all horizontal and vertical register values,
904 * plus an additional +3 for REFPIX as we are using RGB input only.
905 */
906 n_pix = mode->htotal;
907 n_line = mode->vtotal;
908
909 hs_pix_e = mode->hsync_end - mode->hdisplay;
910 hs_pix_s = mode->hsync_start - mode->hdisplay;
911 de_pix_e = mode->htotal;
912 de_pix_s = mode->htotal - mode->hdisplay;
913 ref_pix = 3 + hs_pix_s;
914
915 /*
916 * Attached LCD controllers may generate broken sync. Allow
917 * those to adjust the position of the rising VS edge by adding
918 * HSKEW to ref_pix.
919 */
920 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
921 ref_pix += adjusted_mode->hskew;
922
923 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
924 ref_line = 1 + mode->vsync_start - mode->vdisplay;
925 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
926 vwin1_line_e = vwin1_line_s + mode->vdisplay;
927 vs1_pix_s = vs1_pix_e = hs_pix_s;
928 vs1_line_s = mode->vsync_start - mode->vdisplay;
929 vs1_line_e = vs1_line_s +
930 mode->vsync_end - mode->vsync_start;
931 vwin2_line_s = vwin2_line_e = 0;
932 vs2_pix_s = vs2_pix_e = 0;
933 vs2_line_s = vs2_line_e = 0;
934 } else {
935 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
936 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
937 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
938 vs1_pix_s = vs1_pix_e = hs_pix_s;
939 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
940 vs1_line_e = vs1_line_s +
941 (mode->vsync_end - mode->vsync_start)/2;
942 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
943 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
944 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
945 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
946 vs2_line_e = vs2_line_s +
947 (mode->vsync_end - mode->vsync_start)/2;
948 }
949
950 div = 148500 / mode->clock;
951 if (div != 0) {
952 div--;
953 if (div > 3)
954 div = 3;
955 }
956
957 /* mute the audio FIFO: */
958 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
959
960 /* set HDMI HDCP mode off: */
961 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
962 reg_clear(priv, REG_TX33, TX33_HDMI);
963 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
964
965 /* no pre-filter or interpolator: */
966 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
967 HVF_CNTRL_0_INTPOL(0));
968 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
969 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
970 VIP_CNTRL_4_BLC(0));
971
972 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
973 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
974 PLL_SERIAL_3_SRL_DE);
975 reg_write(priv, REG_SERIALIZER, 0);
976 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
977
978 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
979 rep = 0;
980 reg_write(priv, REG_RPT_CNTRL, 0);
981 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
982 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
983
984 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
985 PLL_SERIAL_2_SRL_PR(rep));
986
987 /* set color matrix bypass flag: */
988 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
989 MAT_CONTRL_MAT_SC(1));
990
991 /* set BIAS tmds value: */
992 reg_write(priv, REG_ANA_GENERAL, 0x09);
993
994 /*
995 * Sync on rising HSYNC/VSYNC
996 */
997 reg = VIP_CNTRL_3_SYNC_HS;
998
999 /*
1000 * TDA19988 requires high-active sync at input stage,
1001 * so invert low-active sync provided by master encoder here
1002 */
1003 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1004 reg |= VIP_CNTRL_3_H_TGL;
1005 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1006 reg |= VIP_CNTRL_3_V_TGL;
1007 reg_write(priv, REG_VIP_CNTRL_3, reg);
1008
1009 reg_write(priv, REG_VIDFORMAT, 0x00);
1010 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1011 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1012 reg_write16(priv, REG_NPIX_MSB, n_pix);
1013 reg_write16(priv, REG_NLINE_MSB, n_line);
1014 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1015 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1016 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1017 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1018 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1019 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1020 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1021 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1022 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1023 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1024 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1025 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1026 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1027 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1028 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1029 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1030
1031 if (priv->rev == TDA19988) {
1032 /* let incoming pixels fill the active space (if any) */
1033 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1034 }
1035
1036 /*
1037 * Always generate sync polarity relative to input sync and
1038 * revert input stage toggled sync at output stage
1039 */
1040 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1041 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1042 reg |= TBG_CNTRL_1_H_TGL;
1043 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1044 reg |= TBG_CNTRL_1_V_TGL;
1045 reg_write(priv, REG_TBG_CNTRL_1, reg);
1046
1047 /* must be last register set: */
1048 reg_write(priv, REG_TBG_CNTRL_0, 0);
1049
1050 /* Only setup the info frames if the sink is HDMI */
1051 if (priv->is_hdmi_sink) {
1052 /* We need to turn HDMI HDCP stuff on to get audio through */
1053 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1054 reg_write(priv, REG_TBG_CNTRL_1, reg);
1055 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1056 reg_set(priv, REG_TX33, TX33_HDMI);
1057
1058 tda998x_write_avi(priv, adjusted_mode);
1059
1060 if (priv->params.audio_cfg)
1061 tda998x_configure_audio(priv, adjusted_mode,
1062 &priv->params);
1063 }
1064}
1065
1066static enum drm_connector_status
1067tda998x_connector_detect(struct drm_connector *connector, bool force)
1068{
1069 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1070 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1071
1072 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1073 connector_status_disconnected;
1074}
1075
1076static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1077{
1078 struct tda998x_priv *priv = data;
1079 u8 offset, segptr;
1080 int ret, i;
1081
1082 offset = (blk & 1) ? 128 : 0;
1083 segptr = blk / 2;
1084
1085 reg_write(priv, REG_DDC_ADDR, 0xa0);
1086 reg_write(priv, REG_DDC_OFFS, offset);
1087 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1088 reg_write(priv, REG_DDC_SEGM, segptr);
1089
1090 /* enable reading EDID: */
1091 priv->wq_edid_wait = 1;
1092 reg_write(priv, REG_EDID_CTRL, 0x1);
1093
1094 /* flag must be cleared by sw: */
1095 reg_write(priv, REG_EDID_CTRL, 0x0);
1096
1097 /* wait for block read to complete: */
1098 if (priv->hdmi->irq) {
1099 i = wait_event_timeout(priv->wq_edid,
1100 !priv->wq_edid_wait,
1101 msecs_to_jiffies(100));
1102 if (i < 0) {
1103 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1104 return i;
1105 }
1106 } else {
1107 for (i = 100; i > 0; i--) {
1108 msleep(1);
1109 ret = reg_read(priv, REG_INT_FLAGS_2);
1110 if (ret < 0)
1111 return ret;
1112 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1113 break;
1114 }
1115 }
1116
1117 if (i == 0) {
1118 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1119 return -ETIMEDOUT;
1120 }
1121
1122 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1123 if (ret != length) {
1124 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1125 blk, ret);
1126 return ret;
1127 }
1128
1129 return 0;
1130}
1131
1132static int tda998x_connector_get_modes(struct drm_connector *connector)
1133{
1134 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1135 struct edid *edid;
1136 int n;
1137
1138 /*
1139 * If we get killed while waiting for the HPD timeout, return
1140 * no modes found: we are not in a restartable path, so we
1141 * can't handle signals gracefully.
1142 */
1143 if (tda998x_edid_delay_wait(priv))
1144 return 0;
1145
1146 if (priv->rev == TDA19988)
1147 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1148
1149 edid = drm_do_get_edid(connector, read_edid_block, priv);
1150
1151 if (priv->rev == TDA19988)
1152 reg_set(priv, REG_TX4, TX4_PD_RAM);
1153
1154 if (!edid) {
1155 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1156 return 0;
1157 }
1158
1159 drm_mode_connector_update_edid_property(connector, edid);
1160 n = drm_add_edid_modes(connector, edid);
1161 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1162 kfree(edid);
1163
1164 return n;
1165}
1166
1167static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1168 struct drm_connector *connector)
1169{
1170 if (priv->hdmi->irq)
1171 connector->polled = DRM_CONNECTOR_POLL_HPD;
1172 else
1173 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1174 DRM_CONNECTOR_POLL_DISCONNECT;
1175}
1176
1177static void tda998x_destroy(struct tda998x_priv *priv)
1178{
1179 /* disable all IRQs and free the IRQ handler */
1180 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1181 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1182
1183 if (priv->hdmi->irq)
1184 free_irq(priv->hdmi->irq, priv);
1185
1186 del_timer_sync(&priv->edid_delay_timer);
1187 cancel_work_sync(&priv->detect_work);
1188
1189 i2c_unregister_device(priv->cec);
1190}
1191
1192/* I2C driver functions */
1193
1194static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1195{
1196 struct device_node *np = client->dev.of_node;
1197 u32 video;
1198 int rev_lo, rev_hi, ret;
1199 unsigned short cec_addr;
1200
1201 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1202 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1203 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1204
1205 priv->current_page = 0xff;
1206 priv->hdmi = client;
1207 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1208 cec_addr = 0x34 + (client->addr & 0x03);
1209 priv->cec = i2c_new_dummy(client->adapter, cec_addr);
1210 if (!priv->cec)
1211 return -ENODEV;
1212
1213 priv->dpms = DRM_MODE_DPMS_OFF;
1214
1215 mutex_init(&priv->mutex); /* protect the page access */
1216 init_waitqueue_head(&priv->edid_delay_waitq);
1217 setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1218 (unsigned long)priv);
1219 INIT_WORK(&priv->detect_work, tda998x_detect_work);
1220
1221 /* wake up the device: */
1222 cec_write(priv, REG_CEC_ENAMODS,
1223 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1224
1225 tda998x_reset(priv);
1226
1227 /* read version: */
1228 rev_lo = reg_read(priv, REG_VERSION_LSB);
1229 rev_hi = reg_read(priv, REG_VERSION_MSB);
1230 if (rev_lo < 0 || rev_hi < 0) {
1231 ret = rev_lo < 0 ? rev_lo : rev_hi;
1232 goto fail;
1233 }
1234
1235 priv->rev = rev_lo | rev_hi << 8;
1236
1237 /* mask off feature bits: */
1238 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1239
1240 switch (priv->rev) {
1241 case TDA9989N2:
1242 dev_info(&client->dev, "found TDA9989 n2");
1243 break;
1244 case TDA19989:
1245 dev_info(&client->dev, "found TDA19989");
1246 break;
1247 case TDA19989N2:
1248 dev_info(&client->dev, "found TDA19989 n2");
1249 break;
1250 case TDA19988:
1251 dev_info(&client->dev, "found TDA19988");
1252 break;
1253 default:
1254 dev_err(&client->dev, "found unsupported device: %04x\n",
1255 priv->rev);
1256 goto fail;
1257 }
1258
1259 /* after reset, enable DDC: */
1260 reg_write(priv, REG_DDC_DISABLE, 0x00);
1261
1262 /* set clock on DDC channel: */
1263 reg_write(priv, REG_TX3, 39);
1264
1265 /* if necessary, disable multi-master: */
1266 if (priv->rev == TDA19989)
1267 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1268
1269 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1270 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1271
1272 /* initialize the optional IRQ */
1273 if (client->irq) {
1274 int irqf_trigger;
1275
1276 /* init read EDID waitqueue and HDP work */
1277 init_waitqueue_head(&priv->wq_edid);
1278
1279 /* clear pending interrupts */
1280 reg_read(priv, REG_INT_FLAGS_0);
1281 reg_read(priv, REG_INT_FLAGS_1);
1282 reg_read(priv, REG_INT_FLAGS_2);
1283
1284 irqf_trigger =
1285 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1286 ret = request_threaded_irq(client->irq, NULL,
1287 tda998x_irq_thread,
1288 irqf_trigger | IRQF_ONESHOT,
1289 "tda998x", priv);
1290 if (ret) {
1291 dev_err(&client->dev,
1292 "failed to request IRQ#%u: %d\n",
1293 client->irq, ret);
1294 goto fail;
1295 }
1296
1297 /* enable HPD irq */
1298 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1299 }
1300
1301 /* enable EDID read irq: */
1302 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1303
1304 if (!np)
1305 return 0; /* non-DT */
1306
1307 /* get the optional video properties */
1308 ret = of_property_read_u32(np, "video-ports", &video);
1309 if (ret == 0) {
1310 priv->vip_cntrl_0 = video >> 16;
1311 priv->vip_cntrl_1 = video >> 8;
1312 priv->vip_cntrl_2 = video;
1313 }
1314
1315 return 0;
1316
1317fail:
1318 /* if encoder_init fails, the encoder slave is never registered,
1319 * so cleanup here:
1320 */
1321 if (priv->cec)
1322 i2c_unregister_device(priv->cec);
1323 return -ENXIO;
1324}
1325
1326static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1327{
1328 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1329}
1330
1331static void tda998x_encoder_commit(struct drm_encoder *encoder)
1332{
1333 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1334}
1335
1336static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1337 .dpms = tda998x_encoder_dpms,
1338 .prepare = tda998x_encoder_prepare,
1339 .commit = tda998x_encoder_commit,
1340 .mode_set = tda998x_encoder_mode_set,
1341};
1342
1343static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1344{
1345 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1346
1347 tda998x_destroy(priv);
1348 drm_encoder_cleanup(encoder);
1349}
1350
1351static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1352 .destroy = tda998x_encoder_destroy,
1353};
1354
1355static struct drm_encoder *
1356tda998x_connector_best_encoder(struct drm_connector *connector)
1357{
1358 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1359
1360 return &priv->encoder;
1361}
1362
1363static
1364const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1365 .get_modes = tda998x_connector_get_modes,
1366 .mode_valid = tda998x_connector_mode_valid,
1367 .best_encoder = tda998x_connector_best_encoder,
1368};
1369
1370static void tda998x_connector_destroy(struct drm_connector *connector)
1371{
1372 drm_connector_unregister(connector);
1373 drm_connector_cleanup(connector);
1374}
1375
1376static int tda998x_connector_dpms(struct drm_connector *connector, int mode)
1377{
1378 if (drm_core_check_feature(connector->dev, DRIVER_ATOMIC))
1379 return drm_atomic_helper_connector_dpms(connector, mode);
1380 else
1381 return drm_helper_connector_dpms(connector, mode);
1382}
1383
1384static const struct drm_connector_funcs tda998x_connector_funcs = {
1385 .dpms = tda998x_connector_dpms,
1386 .reset = drm_atomic_helper_connector_reset,
1387 .fill_modes = drm_helper_probe_single_connector_modes,
1388 .detect = tda998x_connector_detect,
1389 .destroy = tda998x_connector_destroy,
1390 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1391 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1392};
1393
1394static int tda998x_bind(struct device *dev, struct device *master, void *data)
1395{
1396 struct tda998x_encoder_params *params = dev->platform_data;
1397 struct i2c_client *client = to_i2c_client(dev);
1398 struct drm_device *drm = data;
1399 struct tda998x_priv *priv;
1400 u32 crtcs = 0;
1401 int ret;
1402
1403 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1404 if (!priv)
1405 return -ENOMEM;
1406
1407 dev_set_drvdata(dev, priv);
1408
1409 if (dev->of_node)
1410 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1411
1412 /* If no CRTCs were found, fall back to our old behaviour */
1413 if (crtcs == 0) {
1414 dev_warn(dev, "Falling back to first CRTC\n");
1415 crtcs = 1 << 0;
1416 }
1417
1418 priv->connector.interlace_allowed = 1;
1419 priv->encoder.possible_crtcs = crtcs;
1420
1421 ret = tda998x_create(client, priv);
1422 if (ret)
1423 return ret;
1424
1425 if (!dev->of_node && params)
1426 tda998x_encoder_set_config(priv, params);
1427
1428 tda998x_encoder_set_polling(priv, &priv->connector);
1429
1430 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1431 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1432 DRM_MODE_ENCODER_TMDS, NULL);
1433 if (ret)
1434 goto err_encoder;
1435
1436 drm_connector_helper_add(&priv->connector,
1437 &tda998x_connector_helper_funcs);
1438 ret = drm_connector_init(drm, &priv->connector,
1439 &tda998x_connector_funcs,
1440 DRM_MODE_CONNECTOR_HDMIA);
1441 if (ret)
1442 goto err_connector;
1443
1444 ret = drm_connector_register(&priv->connector);
1445 if (ret)
1446 goto err_sysfs;
1447
1448 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1449
1450 return 0;
1451
1452err_sysfs:
1453 drm_connector_cleanup(&priv->connector);
1454err_connector:
1455 drm_encoder_cleanup(&priv->encoder);
1456err_encoder:
1457 tda998x_destroy(priv);
1458 return ret;
1459}
1460
1461static void tda998x_unbind(struct device *dev, struct device *master,
1462 void *data)
1463{
1464 struct tda998x_priv *priv = dev_get_drvdata(dev);
1465
1466 drm_connector_unregister(&priv->connector);
1467 drm_connector_cleanup(&priv->connector);
1468 drm_encoder_cleanup(&priv->encoder);
1469 tda998x_destroy(priv);
1470}
1471
1472static const struct component_ops tda998x_ops = {
1473 .bind = tda998x_bind,
1474 .unbind = tda998x_unbind,
1475};
1476
1477static int
1478tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1479{
1480 return component_add(&client->dev, &tda998x_ops);
1481}
1482
1483static int tda998x_remove(struct i2c_client *client)
1484{
1485 component_del(&client->dev, &tda998x_ops);
1486 return 0;
1487}
1488
1489#ifdef CONFIG_OF
1490static const struct of_device_id tda998x_dt_ids[] = {
1491 { .compatible = "nxp,tda998x", },
1492 { }
1493};
1494MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1495#endif
1496
1497static struct i2c_device_id tda998x_ids[] = {
1498 { "tda998x", 0 },
1499 { }
1500};
1501MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1502
1503static struct i2c_driver tda998x_driver = {
1504 .probe = tda998x_probe,
1505 .remove = tda998x_remove,
1506 .driver = {
1507 .name = "tda998x",
1508 .of_match_table = of_match_ptr(tda998x_dt_ids),
1509 },
1510 .id_table = tda998x_ids,
1511};
1512
1513module_i2c_driver(tda998x_driver);
1514
1515MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1516MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1517MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/component.h>
19#include <linux/hdmi.h>
20#include <linux/module.h>
21#include <linux/irq.h>
22#include <sound/asoundef.h>
23#include <sound/hdmi-codec.h>
24
25#include <drm/drmP.h>
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/drm_edid.h>
29#include <drm/drm_of.h>
30#include <drm/i2c/tda998x.h>
31
32#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
33
34struct tda998x_audio_port {
35 u8 format; /* AFMT_xxx */
36 u8 config; /* AP value */
37};
38
39struct tda998x_priv {
40 struct i2c_client *cec;
41 struct i2c_client *hdmi;
42 struct mutex mutex;
43 u16 rev;
44 u8 cec_addr;
45 u8 current_page;
46 bool is_on;
47 bool supports_infoframes;
48 bool sink_has_audio;
49 u8 vip_cntrl_0;
50 u8 vip_cntrl_1;
51 u8 vip_cntrl_2;
52 unsigned long tmds_clock;
53 struct tda998x_audio_params audio_params;
54
55 struct platform_device *audio_pdev;
56 struct mutex audio_mutex;
57
58 wait_queue_head_t wq_edid;
59 volatile int wq_edid_wait;
60
61 struct work_struct detect_work;
62 struct timer_list edid_delay_timer;
63 wait_queue_head_t edid_delay_waitq;
64 bool edid_delay_active;
65
66 struct drm_encoder encoder;
67 struct drm_connector connector;
68
69 struct tda998x_audio_port audio_port[2];
70};
71
72#define conn_to_tda998x_priv(x) \
73 container_of(x, struct tda998x_priv, connector)
74
75#define enc_to_tda998x_priv(x) \
76 container_of(x, struct tda998x_priv, encoder)
77
78/* The TDA9988 series of devices use a paged register scheme.. to simplify
79 * things we encode the page # in upper bits of the register #. To read/
80 * write a given register, we need to make sure CURPAGE register is set
81 * appropriately. Which implies reads/writes are not atomic. Fun!
82 */
83
84#define REG(page, addr) (((page) << 8) | (addr))
85#define REG2ADDR(reg) ((reg) & 0xff)
86#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
87
88#define REG_CURPAGE 0xff /* write */
89
90
91/* Page 00h: General Control */
92#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
93#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
94# define MAIN_CNTRL0_SR (1 << 0)
95# define MAIN_CNTRL0_DECS (1 << 1)
96# define MAIN_CNTRL0_DEHS (1 << 2)
97# define MAIN_CNTRL0_CECS (1 << 3)
98# define MAIN_CNTRL0_CEHS (1 << 4)
99# define MAIN_CNTRL0_SCALER (1 << 7)
100#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
101#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
102# define SOFTRESET_AUDIO (1 << 0)
103# define SOFTRESET_I2C_MASTER (1 << 1)
104#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
105#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
106#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
107# define I2C_MASTER_DIS_MM (1 << 0)
108# define I2C_MASTER_DIS_FILT (1 << 1)
109# define I2C_MASTER_APP_STRT_LAT (1 << 2)
110#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
111# define FEAT_POWERDOWN_PREFILT BIT(0)
112# define FEAT_POWERDOWN_CSC BIT(1)
113# define FEAT_POWERDOWN_SPDIF (1 << 3)
114#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
115#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
116#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
117# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
118#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
119#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
120#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
121#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
122#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
123#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
124# define VIP_CNTRL_0_MIRR_A (1 << 7)
125# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
126# define VIP_CNTRL_0_MIRR_B (1 << 3)
127# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
128#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
129# define VIP_CNTRL_1_MIRR_C (1 << 7)
130# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
131# define VIP_CNTRL_1_MIRR_D (1 << 3)
132# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
133#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
134# define VIP_CNTRL_2_MIRR_E (1 << 7)
135# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
136# define VIP_CNTRL_2_MIRR_F (1 << 3)
137# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
138#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
139# define VIP_CNTRL_3_X_TGL (1 << 0)
140# define VIP_CNTRL_3_H_TGL (1 << 1)
141# define VIP_CNTRL_3_V_TGL (1 << 2)
142# define VIP_CNTRL_3_EMB (1 << 3)
143# define VIP_CNTRL_3_SYNC_DE (1 << 4)
144# define VIP_CNTRL_3_SYNC_HS (1 << 5)
145# define VIP_CNTRL_3_DE_INT (1 << 6)
146# define VIP_CNTRL_3_EDGE (1 << 7)
147#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
148# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
149# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
150# define VIP_CNTRL_4_CCIR656 (1 << 4)
151# define VIP_CNTRL_4_656_ALT (1 << 5)
152# define VIP_CNTRL_4_TST_656 (1 << 6)
153# define VIP_CNTRL_4_TST_PAT (1 << 7)
154#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
155# define VIP_CNTRL_5_CKCASE (1 << 0)
156# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
157#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
158# define MUX_AP_SELECT_I2S 0x64
159# define MUX_AP_SELECT_SPDIF 0x40
160#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
161#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
162# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
163# define MAT_CONTRL_MAT_BP (1 << 2)
164#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
165#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
166#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
167#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
168#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
169#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
170#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
171#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
172#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
173#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
174#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
175#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
176#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
177#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
178#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
179#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
180#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
181#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
182#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
183#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
184#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
185#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
186#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
187#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
188#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
189#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
190#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
191#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
192#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
193#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
194#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
195#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
196#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
197#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
198#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
199#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
200#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
201#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
202#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
203#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
204#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
205#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
206# define TBG_CNTRL_0_TOP_TGL (1 << 0)
207# define TBG_CNTRL_0_TOP_SEL (1 << 1)
208# define TBG_CNTRL_0_DE_EXT (1 << 2)
209# define TBG_CNTRL_0_TOP_EXT (1 << 3)
210# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
211# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
212# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
213#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
214# define TBG_CNTRL_1_H_TGL (1 << 0)
215# define TBG_CNTRL_1_V_TGL (1 << 1)
216# define TBG_CNTRL_1_TGL_EN (1 << 2)
217# define TBG_CNTRL_1_X_EXT (1 << 3)
218# define TBG_CNTRL_1_H_EXT (1 << 4)
219# define TBG_CNTRL_1_V_EXT (1 << 5)
220# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
221#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
222#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
223# define HVF_CNTRL_0_SM (1 << 7)
224# define HVF_CNTRL_0_RWB (1 << 6)
225# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
226# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
227#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
228# define HVF_CNTRL_1_FOR (1 << 0)
229# define HVF_CNTRL_1_YUVBLK (1 << 1)
230# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
231# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
232# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
233#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
234#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
235# define I2S_FORMAT(x) (((x) & 3) << 0)
236#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
237# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
238# define AIP_CLKSEL_AIP_I2S (1 << 3)
239# define AIP_CLKSEL_FS_ACLK (0 << 0)
240# define AIP_CLKSEL_FS_MCLK (1 << 0)
241# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
242
243/* Page 02h: PLL settings */
244#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
245# define PLL_SERIAL_1_SRL_FDN (1 << 0)
246# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
247# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
248#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
249# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
250# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
251#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
252# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
253# define PLL_SERIAL_3_SRL_DE (1 << 2)
254# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
255#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
256#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
257#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
258#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
259#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
260#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
261#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
262#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
263#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
264# define AUDIO_DIV_SERCLK_1 0
265# define AUDIO_DIV_SERCLK_2 1
266# define AUDIO_DIV_SERCLK_4 2
267# define AUDIO_DIV_SERCLK_8 3
268# define AUDIO_DIV_SERCLK_16 4
269# define AUDIO_DIV_SERCLK_32 5
270#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
271# define SEL_CLK_SEL_CLK1 (1 << 0)
272# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
273# define SEL_CLK_ENA_SC_CLK (1 << 3)
274#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
275
276
277/* Page 09h: EDID Control */
278#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
279/* next 127 successive registers are the EDID block */
280#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
281#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
282#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
283#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
284#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
285
286
287/* Page 10h: information frames and packets */
288#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
289#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
290#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
291#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
292#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
293
294
295/* Page 11h: audio settings and content info packets */
296#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
297# define AIP_CNTRL_0_RST_FIFO (1 << 0)
298# define AIP_CNTRL_0_SWAP (1 << 1)
299# define AIP_CNTRL_0_LAYOUT (1 << 2)
300# define AIP_CNTRL_0_ACR_MAN (1 << 5)
301# define AIP_CNTRL_0_RST_CTS (1 << 6)
302#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
303# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
304# define CA_I2S_HBR_CHSTAT (1 << 6)
305#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
306#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
307#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
308#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
309#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
310#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
311#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
312#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
313# define CTS_N_K(x) (((x) & 7) << 0)
314# define CTS_N_M(x) (((x) & 3) << 4)
315#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
316# define ENC_CNTRL_RST_ENC (1 << 0)
317# define ENC_CNTRL_RST_SEL (1 << 1)
318# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
319#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
320# define DIP_FLAGS_ACR (1 << 0)
321# define DIP_FLAGS_GC (1 << 1)
322#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
323# define DIP_IF_FLAGS_IF1 (1 << 1)
324# define DIP_IF_FLAGS_IF2 (1 << 2)
325# define DIP_IF_FLAGS_IF3 (1 << 3)
326# define DIP_IF_FLAGS_IF4 (1 << 4)
327# define DIP_IF_FLAGS_IF5 (1 << 5)
328#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
329
330
331/* Page 12h: HDCP and OTP */
332#define REG_TX3 REG(0x12, 0x9a) /* read/write */
333#define REG_TX4 REG(0x12, 0x9b) /* read/write */
334# define TX4_PD_RAM (1 << 1)
335#define REG_TX33 REG(0x12, 0xb8) /* read/write */
336# define TX33_HDMI (1 << 1)
337
338
339/* Page 13h: Gamut related metadata packets */
340
341
342
343/* CEC registers: (not paged)
344 */
345#define REG_CEC_INTSTATUS 0xee /* read */
346# define CEC_INTSTATUS_CEC (1 << 0)
347# define CEC_INTSTATUS_HDMI (1 << 1)
348#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
349# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
350# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
351# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
352# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
353#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
354#define REG_CEC_RXSHPDINT 0xfd /* read */
355# define CEC_RXSHPDINT_RXSENS BIT(0)
356# define CEC_RXSHPDINT_HPD BIT(1)
357#define REG_CEC_RXSHPDLEV 0xfe /* read */
358# define CEC_RXSHPDLEV_RXSENS (1 << 0)
359# define CEC_RXSHPDLEV_HPD (1 << 1)
360
361#define REG_CEC_ENAMODS 0xff /* read/write */
362# define CEC_ENAMODS_DIS_FRO (1 << 6)
363# define CEC_ENAMODS_DIS_CCLK (1 << 5)
364# define CEC_ENAMODS_EN_RXSENS (1 << 2)
365# define CEC_ENAMODS_EN_HDMI (1 << 1)
366# define CEC_ENAMODS_EN_CEC (1 << 0)
367
368
369/* Device versions: */
370#define TDA9989N2 0x0101
371#define TDA19989 0x0201
372#define TDA19989N2 0x0202
373#define TDA19988 0x0301
374
375static void
376cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
377{
378 u8 buf[] = {addr, val};
379 struct i2c_msg msg = {
380 .addr = priv->cec_addr,
381 .len = 2,
382 .buf = buf,
383 };
384 int ret;
385
386 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
387 if (ret < 0)
388 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
389 ret, addr);
390}
391
392static u8
393cec_read(struct tda998x_priv *priv, u8 addr)
394{
395 u8 val;
396 struct i2c_msg msg[2] = {
397 {
398 .addr = priv->cec_addr,
399 .len = 1,
400 .buf = &addr,
401 }, {
402 .addr = priv->cec_addr,
403 .flags = I2C_M_RD,
404 .len = 1,
405 .buf = &val,
406 },
407 };
408 int ret;
409
410 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
411 if (ret < 0) {
412 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
413 ret, addr);
414 val = 0;
415 }
416
417 return val;
418}
419
420static int
421set_page(struct tda998x_priv *priv, u16 reg)
422{
423 if (REG2PAGE(reg) != priv->current_page) {
424 struct i2c_client *client = priv->hdmi;
425 u8 buf[] = {
426 REG_CURPAGE, REG2PAGE(reg)
427 };
428 int ret = i2c_master_send(client, buf, sizeof(buf));
429 if (ret < 0) {
430 dev_err(&client->dev, "%s %04x err %d\n", __func__,
431 reg, ret);
432 return ret;
433 }
434
435 priv->current_page = REG2PAGE(reg);
436 }
437 return 0;
438}
439
440static int
441reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
442{
443 struct i2c_client *client = priv->hdmi;
444 u8 addr = REG2ADDR(reg);
445 int ret;
446
447 mutex_lock(&priv->mutex);
448 ret = set_page(priv, reg);
449 if (ret < 0)
450 goto out;
451
452 ret = i2c_master_send(client, &addr, sizeof(addr));
453 if (ret < 0)
454 goto fail;
455
456 ret = i2c_master_recv(client, buf, cnt);
457 if (ret < 0)
458 goto fail;
459
460 goto out;
461
462fail:
463 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
464out:
465 mutex_unlock(&priv->mutex);
466 return ret;
467}
468
469static void
470reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
471{
472 struct i2c_client *client = priv->hdmi;
473 u8 buf[cnt+1];
474 int ret;
475
476 buf[0] = REG2ADDR(reg);
477 memcpy(&buf[1], p, cnt);
478
479 mutex_lock(&priv->mutex);
480 ret = set_page(priv, reg);
481 if (ret < 0)
482 goto out;
483
484 ret = i2c_master_send(client, buf, cnt + 1);
485 if (ret < 0)
486 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
487out:
488 mutex_unlock(&priv->mutex);
489}
490
491static int
492reg_read(struct tda998x_priv *priv, u16 reg)
493{
494 u8 val = 0;
495 int ret;
496
497 ret = reg_read_range(priv, reg, &val, sizeof(val));
498 if (ret < 0)
499 return ret;
500 return val;
501}
502
503static void
504reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
505{
506 struct i2c_client *client = priv->hdmi;
507 u8 buf[] = {REG2ADDR(reg), val};
508 int ret;
509
510 mutex_lock(&priv->mutex);
511 ret = set_page(priv, reg);
512 if (ret < 0)
513 goto out;
514
515 ret = i2c_master_send(client, buf, sizeof(buf));
516 if (ret < 0)
517 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
518out:
519 mutex_unlock(&priv->mutex);
520}
521
522static void
523reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
524{
525 struct i2c_client *client = priv->hdmi;
526 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
527 int ret;
528
529 mutex_lock(&priv->mutex);
530 ret = set_page(priv, reg);
531 if (ret < 0)
532 goto out;
533
534 ret = i2c_master_send(client, buf, sizeof(buf));
535 if (ret < 0)
536 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
537out:
538 mutex_unlock(&priv->mutex);
539}
540
541static void
542reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
543{
544 int old_val;
545
546 old_val = reg_read(priv, reg);
547 if (old_val >= 0)
548 reg_write(priv, reg, old_val | val);
549}
550
551static void
552reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
553{
554 int old_val;
555
556 old_val = reg_read(priv, reg);
557 if (old_val >= 0)
558 reg_write(priv, reg, old_val & ~val);
559}
560
561static void
562tda998x_reset(struct tda998x_priv *priv)
563{
564 /* reset audio and i2c master: */
565 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
566 msleep(50);
567 reg_write(priv, REG_SOFTRESET, 0);
568 msleep(50);
569
570 /* reset transmitter: */
571 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
572 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
573
574 /* PLL registers common configuration */
575 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
576 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
577 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
578 reg_write(priv, REG_SERIALIZER, 0x00);
579 reg_write(priv, REG_BUFFER_OUT, 0x00);
580 reg_write(priv, REG_PLL_SCG1, 0x00);
581 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
582 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
583 reg_write(priv, REG_PLL_SCGN1, 0xfa);
584 reg_write(priv, REG_PLL_SCGN2, 0x00);
585 reg_write(priv, REG_PLL_SCGR1, 0x5b);
586 reg_write(priv, REG_PLL_SCGR2, 0x00);
587 reg_write(priv, REG_PLL_SCG2, 0x10);
588
589 /* Write the default value MUX register */
590 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
591}
592
593/*
594 * The TDA998x has a problem when trying to read the EDID close to a
595 * HPD assertion: it needs a delay of 100ms to avoid timing out while
596 * trying to read EDID data.
597 *
598 * However, tda998x_connector_get_modes() may be called at any moment
599 * after tda998x_connector_detect() indicates that we are connected, so
600 * we need to delay probing modes in tda998x_connector_get_modes() after
601 * we have seen a HPD inactive->active transition. This code implements
602 * that delay.
603 */
604static void tda998x_edid_delay_done(unsigned long data)
605{
606 struct tda998x_priv *priv = (struct tda998x_priv *)data;
607
608 priv->edid_delay_active = false;
609 wake_up(&priv->edid_delay_waitq);
610 schedule_work(&priv->detect_work);
611}
612
613static void tda998x_edid_delay_start(struct tda998x_priv *priv)
614{
615 priv->edid_delay_active = true;
616 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
617}
618
619static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
620{
621 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
622}
623
624/*
625 * We need to run the KMS hotplug event helper outside of our threaded
626 * interrupt routine as this can call back into our get_modes method,
627 * which will want to make use of interrupts.
628 */
629static void tda998x_detect_work(struct work_struct *work)
630{
631 struct tda998x_priv *priv =
632 container_of(work, struct tda998x_priv, detect_work);
633 struct drm_device *dev = priv->encoder.dev;
634
635 if (dev)
636 drm_kms_helper_hotplug_event(dev);
637}
638
639/*
640 * only 2 interrupts may occur: screen plug/unplug and EDID read
641 */
642static irqreturn_t tda998x_irq_thread(int irq, void *data)
643{
644 struct tda998x_priv *priv = data;
645 u8 sta, cec, lvl, flag0, flag1, flag2;
646 bool handled = false;
647
648 sta = cec_read(priv, REG_CEC_INTSTATUS);
649 if (sta & CEC_INTSTATUS_HDMI) {
650 cec = cec_read(priv, REG_CEC_RXSHPDINT);
651 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
652 flag0 = reg_read(priv, REG_INT_FLAGS_0);
653 flag1 = reg_read(priv, REG_INT_FLAGS_1);
654 flag2 = reg_read(priv, REG_INT_FLAGS_2);
655 DRM_DEBUG_DRIVER(
656 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
657 sta, cec, lvl, flag0, flag1, flag2);
658
659 if (cec & CEC_RXSHPDINT_HPD) {
660 if (lvl & CEC_RXSHPDLEV_HPD)
661 tda998x_edid_delay_start(priv);
662 else
663 schedule_work(&priv->detect_work);
664
665 handled = true;
666 }
667
668 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
669 priv->wq_edid_wait = 0;
670 wake_up(&priv->wq_edid);
671 handled = true;
672 }
673 }
674
675 return IRQ_RETVAL(handled);
676}
677
678static void
679tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
680 union hdmi_infoframe *frame)
681{
682 u8 buf[32];
683 ssize_t len;
684
685 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
686 if (len < 0) {
687 dev_err(&priv->hdmi->dev,
688 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
689 frame->any.type, len);
690 return;
691 }
692
693 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
694 reg_write_range(priv, addr, buf, len);
695 reg_set(priv, REG_DIP_IF_FLAGS, bit);
696}
697
698static int tda998x_write_aif(struct tda998x_priv *priv,
699 struct hdmi_audio_infoframe *cea)
700{
701 union hdmi_infoframe frame;
702
703 frame.audio = *cea;
704
705 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
706
707 return 0;
708}
709
710static void
711tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
712{
713 union hdmi_infoframe frame;
714
715 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
716 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
717
718 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
719}
720
721/* Audio support */
722
723static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
724{
725 if (on) {
726 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
727 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
728 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
729 } else {
730 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
731 }
732}
733
734static int
735tda998x_configure_audio(struct tda998x_priv *priv,
736 struct tda998x_audio_params *params)
737{
738 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
739 u32 n;
740
741 /* Enable audio ports */
742 reg_write(priv, REG_ENA_AP, params->config);
743
744 /* Set audio input source */
745 switch (params->format) {
746 case AFMT_SPDIF:
747 reg_write(priv, REG_ENA_ACLK, 0);
748 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
749 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
750 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
751 cts_n = CTS_N_M(3) | CTS_N_K(3);
752 break;
753
754 case AFMT_I2S:
755 reg_write(priv, REG_ENA_ACLK, 1);
756 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
757 clksel_aip = AIP_CLKSEL_AIP_I2S;
758 clksel_fs = AIP_CLKSEL_FS_ACLK;
759 switch (params->sample_width) {
760 case 16:
761 cts_n = CTS_N_M(3) | CTS_N_K(1);
762 break;
763 case 18:
764 case 20:
765 case 24:
766 cts_n = CTS_N_M(3) | CTS_N_K(2);
767 break;
768 default:
769 case 32:
770 cts_n = CTS_N_M(3) | CTS_N_K(3);
771 break;
772 }
773 break;
774
775 default:
776 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n");
777 return -EINVAL;
778 }
779
780 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
781 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
782 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
783 reg_write(priv, REG_CTS_N, cts_n);
784
785 /*
786 * Audio input somehow depends on HDMI line rate which is
787 * related to pixclk. Testing showed that modes with pixclk
788 * >100MHz need a larger divider while <40MHz need the default.
789 * There is no detailed info in the datasheet, so we just
790 * assume 100MHz requires larger divider.
791 */
792 adiv = AUDIO_DIV_SERCLK_8;
793 if (priv->tmds_clock > 100000)
794 adiv++; /* AUDIO_DIV_SERCLK_16 */
795
796 /* S/PDIF asks for a larger divider */
797 if (params->format == AFMT_SPDIF)
798 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
799
800 reg_write(priv, REG_AUDIO_DIV, adiv);
801
802 /*
803 * This is the approximate value of N, which happens to be
804 * the recommended values for non-coherent clocks.
805 */
806 n = 128 * params->sample_rate / 1000;
807
808 /* Write the CTS and N values */
809 buf[0] = 0x44;
810 buf[1] = 0x42;
811 buf[2] = 0x01;
812 buf[3] = n;
813 buf[4] = n >> 8;
814 buf[5] = n >> 16;
815 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
816
817 /* Set CTS clock reference */
818 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
819
820 /* Reset CTS generator */
821 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
822 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
823
824 /* Write the channel status
825 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
826 * there is a separate register for each I2S wire.
827 */
828 buf[0] = params->status[0];
829 buf[1] = params->status[1];
830 buf[2] = params->status[3];
831 buf[3] = params->status[4];
832 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
833
834 tda998x_audio_mute(priv, true);
835 msleep(20);
836 tda998x_audio_mute(priv, false);
837
838 return tda998x_write_aif(priv, ¶ms->cea);
839}
840
841static int tda998x_audio_hw_params(struct device *dev, void *data,
842 struct hdmi_codec_daifmt *daifmt,
843 struct hdmi_codec_params *params)
844{
845 struct tda998x_priv *priv = dev_get_drvdata(dev);
846 int i, ret;
847 struct tda998x_audio_params audio = {
848 .sample_width = params->sample_width,
849 .sample_rate = params->sample_rate,
850 .cea = params->cea,
851 };
852
853 memcpy(audio.status, params->iec.status,
854 min(sizeof(audio.status), sizeof(params->iec.status)));
855
856 switch (daifmt->fmt) {
857 case HDMI_I2S:
858 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
859 daifmt->bit_clk_master || daifmt->frame_clk_master) {
860 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
861 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
862 daifmt->bit_clk_master,
863 daifmt->frame_clk_master);
864 return -EINVAL;
865 }
866 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
867 if (priv->audio_port[i].format == AFMT_I2S)
868 audio.config = priv->audio_port[i].config;
869 audio.format = AFMT_I2S;
870 break;
871 case HDMI_SPDIF:
872 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
873 if (priv->audio_port[i].format == AFMT_SPDIF)
874 audio.config = priv->audio_port[i].config;
875 audio.format = AFMT_SPDIF;
876 break;
877 default:
878 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
879 return -EINVAL;
880 }
881
882 if (audio.config == 0) {
883 dev_err(dev, "%s: No audio configuration found\n", __func__);
884 return -EINVAL;
885 }
886
887 mutex_lock(&priv->audio_mutex);
888 if (priv->supports_infoframes && priv->sink_has_audio)
889 ret = tda998x_configure_audio(priv, &audio);
890 else
891 ret = 0;
892
893 if (ret == 0)
894 priv->audio_params = audio;
895 mutex_unlock(&priv->audio_mutex);
896
897 return ret;
898}
899
900static void tda998x_audio_shutdown(struct device *dev, void *data)
901{
902 struct tda998x_priv *priv = dev_get_drvdata(dev);
903
904 mutex_lock(&priv->audio_mutex);
905
906 reg_write(priv, REG_ENA_AP, 0);
907
908 priv->audio_params.format = AFMT_UNUSED;
909
910 mutex_unlock(&priv->audio_mutex);
911}
912
913int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
914{
915 struct tda998x_priv *priv = dev_get_drvdata(dev);
916
917 mutex_lock(&priv->audio_mutex);
918
919 tda998x_audio_mute(priv, enable);
920
921 mutex_unlock(&priv->audio_mutex);
922 return 0;
923}
924
925static int tda998x_audio_get_eld(struct device *dev, void *data,
926 uint8_t *buf, size_t len)
927{
928 struct tda998x_priv *priv = dev_get_drvdata(dev);
929
930 mutex_lock(&priv->audio_mutex);
931 memcpy(buf, priv->connector.eld,
932 min(sizeof(priv->connector.eld), len));
933 mutex_unlock(&priv->audio_mutex);
934
935 return 0;
936}
937
938static const struct hdmi_codec_ops audio_codec_ops = {
939 .hw_params = tda998x_audio_hw_params,
940 .audio_shutdown = tda998x_audio_shutdown,
941 .digital_mute = tda998x_audio_digital_mute,
942 .get_eld = tda998x_audio_get_eld,
943};
944
945static int tda998x_audio_codec_init(struct tda998x_priv *priv,
946 struct device *dev)
947{
948 struct hdmi_codec_pdata codec_data = {
949 .ops = &audio_codec_ops,
950 .max_i2s_channels = 2,
951 };
952 int i;
953
954 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) {
955 if (priv->audio_port[i].format == AFMT_I2S &&
956 priv->audio_port[i].config != 0)
957 codec_data.i2s = 1;
958 if (priv->audio_port[i].format == AFMT_SPDIF &&
959 priv->audio_port[i].config != 0)
960 codec_data.spdif = 1;
961 }
962
963 priv->audio_pdev = platform_device_register_data(
964 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
965 &codec_data, sizeof(codec_data));
966
967 return PTR_ERR_OR_ZERO(priv->audio_pdev);
968}
969
970/* DRM connector functions */
971
972static int tda998x_connector_dpms(struct drm_connector *connector, int mode)
973{
974 if (drm_core_check_feature(connector->dev, DRIVER_ATOMIC))
975 return drm_atomic_helper_connector_dpms(connector, mode);
976 else
977 return drm_helper_connector_dpms(connector, mode);
978}
979
980static int tda998x_connector_fill_modes(struct drm_connector *connector,
981 uint32_t maxX, uint32_t maxY)
982{
983 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
984 int ret;
985
986 mutex_lock(&priv->audio_mutex);
987 ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
988
989 if (connector->edid_blob_ptr) {
990 struct edid *edid = (void *)connector->edid_blob_ptr->data;
991
992 priv->sink_has_audio = drm_detect_monitor_audio(edid);
993 } else {
994 priv->sink_has_audio = false;
995 }
996 mutex_unlock(&priv->audio_mutex);
997
998 return ret;
999}
1000
1001static enum drm_connector_status
1002tda998x_connector_detect(struct drm_connector *connector, bool force)
1003{
1004 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1005 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1006
1007 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1008 connector_status_disconnected;
1009}
1010
1011static void tda998x_connector_destroy(struct drm_connector *connector)
1012{
1013 drm_connector_cleanup(connector);
1014}
1015
1016static const struct drm_connector_funcs tda998x_connector_funcs = {
1017 .dpms = tda998x_connector_dpms,
1018 .reset = drm_atomic_helper_connector_reset,
1019 .fill_modes = tda998x_connector_fill_modes,
1020 .detect = tda998x_connector_detect,
1021 .destroy = tda998x_connector_destroy,
1022 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1023 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1024};
1025
1026static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1027{
1028 struct tda998x_priv *priv = data;
1029 u8 offset, segptr;
1030 int ret, i;
1031
1032 offset = (blk & 1) ? 128 : 0;
1033 segptr = blk / 2;
1034
1035 reg_write(priv, REG_DDC_ADDR, 0xa0);
1036 reg_write(priv, REG_DDC_OFFS, offset);
1037 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1038 reg_write(priv, REG_DDC_SEGM, segptr);
1039
1040 /* enable reading EDID: */
1041 priv->wq_edid_wait = 1;
1042 reg_write(priv, REG_EDID_CTRL, 0x1);
1043
1044 /* flag must be cleared by sw: */
1045 reg_write(priv, REG_EDID_CTRL, 0x0);
1046
1047 /* wait for block read to complete: */
1048 if (priv->hdmi->irq) {
1049 i = wait_event_timeout(priv->wq_edid,
1050 !priv->wq_edid_wait,
1051 msecs_to_jiffies(100));
1052 if (i < 0) {
1053 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1054 return i;
1055 }
1056 } else {
1057 for (i = 100; i > 0; i--) {
1058 msleep(1);
1059 ret = reg_read(priv, REG_INT_FLAGS_2);
1060 if (ret < 0)
1061 return ret;
1062 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1063 break;
1064 }
1065 }
1066
1067 if (i == 0) {
1068 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1069 return -ETIMEDOUT;
1070 }
1071
1072 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1073 if (ret != length) {
1074 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1075 blk, ret);
1076 return ret;
1077 }
1078
1079 return 0;
1080}
1081
1082static int tda998x_connector_get_modes(struct drm_connector *connector)
1083{
1084 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1085 struct edid *edid;
1086 int n;
1087
1088 /*
1089 * If we get killed while waiting for the HPD timeout, return
1090 * no modes found: we are not in a restartable path, so we
1091 * can't handle signals gracefully.
1092 */
1093 if (tda998x_edid_delay_wait(priv))
1094 return 0;
1095
1096 if (priv->rev == TDA19988)
1097 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1098
1099 edid = drm_do_get_edid(connector, read_edid_block, priv);
1100
1101 if (priv->rev == TDA19988)
1102 reg_set(priv, REG_TX4, TX4_PD_RAM);
1103
1104 if (!edid) {
1105 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1106 return 0;
1107 }
1108
1109 drm_mode_connector_update_edid_property(connector, edid);
1110 n = drm_add_edid_modes(connector, edid);
1111 drm_edid_to_eld(connector, edid);
1112
1113 kfree(edid);
1114
1115 return n;
1116}
1117
1118static int tda998x_connector_mode_valid(struct drm_connector *connector,
1119 struct drm_display_mode *mode)
1120{
1121 /* TDA19988 dotclock can go up to 165MHz */
1122 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1123
1124 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1125 return MODE_CLOCK_HIGH;
1126 if (mode->htotal >= BIT(13))
1127 return MODE_BAD_HVALUE;
1128 if (mode->vtotal >= BIT(11))
1129 return MODE_BAD_VVALUE;
1130 return MODE_OK;
1131}
1132
1133static struct drm_encoder *
1134tda998x_connector_best_encoder(struct drm_connector *connector)
1135{
1136 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1137
1138 return &priv->encoder;
1139}
1140
1141static
1142const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1143 .get_modes = tda998x_connector_get_modes,
1144 .mode_valid = tda998x_connector_mode_valid,
1145 .best_encoder = tda998x_connector_best_encoder,
1146};
1147
1148static int tda998x_connector_init(struct tda998x_priv *priv,
1149 struct drm_device *drm)
1150{
1151 struct drm_connector *connector = &priv->connector;
1152 int ret;
1153
1154 connector->interlace_allowed = 1;
1155
1156 if (priv->hdmi->irq)
1157 connector->polled = DRM_CONNECTOR_POLL_HPD;
1158 else
1159 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1160 DRM_CONNECTOR_POLL_DISCONNECT;
1161
1162 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1163 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1164 DRM_MODE_CONNECTOR_HDMIA);
1165 if (ret)
1166 return ret;
1167
1168 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1169
1170 return 0;
1171}
1172
1173/* DRM encoder functions */
1174
1175static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
1176{
1177 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1178 bool on;
1179
1180 /* we only care about on or off: */
1181 on = mode == DRM_MODE_DPMS_ON;
1182
1183 if (on == priv->is_on)
1184 return;
1185
1186 if (on) {
1187 /* enable video ports, audio will be enabled later */
1188 reg_write(priv, REG_ENA_VP_0, 0xff);
1189 reg_write(priv, REG_ENA_VP_1, 0xff);
1190 reg_write(priv, REG_ENA_VP_2, 0xff);
1191 /* set muxing after enabling ports: */
1192 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1193 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1194 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1195
1196 priv->is_on = true;
1197 } else {
1198 /* disable video ports */
1199 reg_write(priv, REG_ENA_VP_0, 0x00);
1200 reg_write(priv, REG_ENA_VP_1, 0x00);
1201 reg_write(priv, REG_ENA_VP_2, 0x00);
1202
1203 priv->is_on = false;
1204 }
1205}
1206
1207static void
1208tda998x_encoder_mode_set(struct drm_encoder *encoder,
1209 struct drm_display_mode *mode,
1210 struct drm_display_mode *adjusted_mode)
1211{
1212 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1213 u16 ref_pix, ref_line, n_pix, n_line;
1214 u16 hs_pix_s, hs_pix_e;
1215 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1216 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1217 u16 vwin1_line_s, vwin1_line_e;
1218 u16 vwin2_line_s, vwin2_line_e;
1219 u16 de_pix_s, de_pix_e;
1220 u8 reg, div, rep;
1221
1222 /*
1223 * Internally TDA998x is using ITU-R BT.656 style sync but
1224 * we get VESA style sync. TDA998x is using a reference pixel
1225 * relative to ITU to sync to the input frame and for output
1226 * sync generation. Currently, we are using reference detection
1227 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1228 * which is position of rising VS with coincident rising HS.
1229 *
1230 * Now there is some issues to take care of:
1231 * - HDMI data islands require sync-before-active
1232 * - TDA998x register values must be > 0 to be enabled
1233 * - REFLINE needs an additional offset of +1
1234 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1235 *
1236 * So we add +1 to all horizontal and vertical register values,
1237 * plus an additional +3 for REFPIX as we are using RGB input only.
1238 */
1239 n_pix = mode->htotal;
1240 n_line = mode->vtotal;
1241
1242 hs_pix_e = mode->hsync_end - mode->hdisplay;
1243 hs_pix_s = mode->hsync_start - mode->hdisplay;
1244 de_pix_e = mode->htotal;
1245 de_pix_s = mode->htotal - mode->hdisplay;
1246 ref_pix = 3 + hs_pix_s;
1247
1248 /*
1249 * Attached LCD controllers may generate broken sync. Allow
1250 * those to adjust the position of the rising VS edge by adding
1251 * HSKEW to ref_pix.
1252 */
1253 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1254 ref_pix += adjusted_mode->hskew;
1255
1256 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1257 ref_line = 1 + mode->vsync_start - mode->vdisplay;
1258 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1259 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1260 vs1_pix_s = vs1_pix_e = hs_pix_s;
1261 vs1_line_s = mode->vsync_start - mode->vdisplay;
1262 vs1_line_e = vs1_line_s +
1263 mode->vsync_end - mode->vsync_start;
1264 vwin2_line_s = vwin2_line_e = 0;
1265 vs2_pix_s = vs2_pix_e = 0;
1266 vs2_line_s = vs2_line_e = 0;
1267 } else {
1268 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
1269 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1270 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1271 vs1_pix_s = vs1_pix_e = hs_pix_s;
1272 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
1273 vs1_line_e = vs1_line_s +
1274 (mode->vsync_end - mode->vsync_start)/2;
1275 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1276 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1277 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
1278 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
1279 vs2_line_e = vs2_line_s +
1280 (mode->vsync_end - mode->vsync_start)/2;
1281 }
1282
1283 div = 148500 / mode->clock;
1284 if (div != 0) {
1285 div--;
1286 if (div > 3)
1287 div = 3;
1288 }
1289
1290 mutex_lock(&priv->audio_mutex);
1291
1292 /* mute the audio FIFO: */
1293 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1294
1295 /* set HDMI HDCP mode off: */
1296 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1297 reg_clear(priv, REG_TX33, TX33_HDMI);
1298 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1299
1300 /* no pre-filter or interpolator: */
1301 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1302 HVF_CNTRL_0_INTPOL(0));
1303 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1304 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1305 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1306 VIP_CNTRL_4_BLC(0));
1307
1308 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1309 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1310 PLL_SERIAL_3_SRL_DE);
1311 reg_write(priv, REG_SERIALIZER, 0);
1312 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1313
1314 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
1315 rep = 0;
1316 reg_write(priv, REG_RPT_CNTRL, 0);
1317 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
1318 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1319
1320 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1321 PLL_SERIAL_2_SRL_PR(rep));
1322
1323 /* set color matrix bypass flag: */
1324 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1325 MAT_CONTRL_MAT_SC(1));
1326 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1327
1328 /* set BIAS tmds value: */
1329 reg_write(priv, REG_ANA_GENERAL, 0x09);
1330
1331 /*
1332 * Sync on rising HSYNC/VSYNC
1333 */
1334 reg = VIP_CNTRL_3_SYNC_HS;
1335
1336 /*
1337 * TDA19988 requires high-active sync at input stage,
1338 * so invert low-active sync provided by master encoder here
1339 */
1340 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1341 reg |= VIP_CNTRL_3_H_TGL;
1342 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1343 reg |= VIP_CNTRL_3_V_TGL;
1344 reg_write(priv, REG_VIP_CNTRL_3, reg);
1345
1346 reg_write(priv, REG_VIDFORMAT, 0x00);
1347 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1348 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1349 reg_write16(priv, REG_NPIX_MSB, n_pix);
1350 reg_write16(priv, REG_NLINE_MSB, n_line);
1351 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1352 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1353 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1354 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1355 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1356 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1357 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1358 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1359 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1360 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1361 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1362 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1363 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1364 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1365 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1366 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1367
1368 if (priv->rev == TDA19988) {
1369 /* let incoming pixels fill the active space (if any) */
1370 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1371 }
1372
1373 /*
1374 * Always generate sync polarity relative to input sync and
1375 * revert input stage toggled sync at output stage
1376 */
1377 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1378 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1379 reg |= TBG_CNTRL_1_H_TGL;
1380 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1381 reg |= TBG_CNTRL_1_V_TGL;
1382 reg_write(priv, REG_TBG_CNTRL_1, reg);
1383
1384 /* must be last register set: */
1385 reg_write(priv, REG_TBG_CNTRL_0, 0);
1386
1387 priv->tmds_clock = adjusted_mode->clock;
1388
1389 /* CEA-861B section 6 says that:
1390 * CEA version 1 (CEA-861) has no support for infoframes.
1391 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1392 * and optional basic audio.
1393 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1394 * and optional digital audio, with audio infoframes.
1395 *
1396 * Since we only support generation of version 2 AVI infoframes,
1397 * ignore CEA version 2 and below (iow, behave as if we're a
1398 * CEA-861 source.)
1399 */
1400 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1401
1402 if (priv->supports_infoframes) {
1403 /* We need to turn HDMI HDCP stuff on to get audio through */
1404 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1405 reg_write(priv, REG_TBG_CNTRL_1, reg);
1406 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1407 reg_set(priv, REG_TX33, TX33_HDMI);
1408
1409 tda998x_write_avi(priv, adjusted_mode);
1410
1411 if (priv->audio_params.format != AFMT_UNUSED &&
1412 priv->sink_has_audio)
1413 tda998x_configure_audio(priv, &priv->audio_params);
1414 }
1415
1416 mutex_unlock(&priv->audio_mutex);
1417}
1418
1419static void tda998x_destroy(struct tda998x_priv *priv)
1420{
1421 /* disable all IRQs and free the IRQ handler */
1422 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1423 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1424
1425 if (priv->audio_pdev)
1426 platform_device_unregister(priv->audio_pdev);
1427
1428 if (priv->hdmi->irq)
1429 free_irq(priv->hdmi->irq, priv);
1430
1431 del_timer_sync(&priv->edid_delay_timer);
1432 cancel_work_sync(&priv->detect_work);
1433
1434 i2c_unregister_device(priv->cec);
1435}
1436
1437/* I2C driver functions */
1438
1439static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1440 struct device_node *np)
1441{
1442 const u32 *port_data;
1443 u32 size;
1444 int i;
1445
1446 port_data = of_get_property(np, "audio-ports", &size);
1447 if (!port_data)
1448 return 0;
1449
1450 size /= sizeof(u32);
1451 if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) {
1452 dev_err(&priv->hdmi->dev,
1453 "Bad number of elements in audio-ports dt-property\n");
1454 return -EINVAL;
1455 }
1456
1457 size /= 2;
1458
1459 for (i = 0; i < size; i++) {
1460 u8 afmt = be32_to_cpup(&port_data[2*i]);
1461 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1462
1463 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) {
1464 dev_err(&priv->hdmi->dev,
1465 "Bad audio format %u\n", afmt);
1466 return -EINVAL;
1467 }
1468
1469 priv->audio_port[i].format = afmt;
1470 priv->audio_port[i].config = ena_ap;
1471 }
1472
1473 if (priv->audio_port[0].format == priv->audio_port[1].format) {
1474 dev_err(&priv->hdmi->dev,
1475 "There can only be on I2S port and one SPDIF port\n");
1476 return -EINVAL;
1477 }
1478 return 0;
1479}
1480
1481static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1482{
1483 struct device_node *np = client->dev.of_node;
1484 u32 video;
1485 int rev_lo, rev_hi, ret;
1486
1487 mutex_init(&priv->audio_mutex); /* Protect access from audio thread */
1488
1489 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1490 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1491 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1492
1493 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1494 priv->cec_addr = 0x34 + (client->addr & 0x03);
1495 priv->current_page = 0xff;
1496 priv->hdmi = client;
1497 priv->cec = i2c_new_dummy(client->adapter, priv->cec_addr);
1498 if (!priv->cec)
1499 return -ENODEV;
1500
1501 mutex_init(&priv->mutex); /* protect the page access */
1502 init_waitqueue_head(&priv->edid_delay_waitq);
1503 setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1504 (unsigned long)priv);
1505 INIT_WORK(&priv->detect_work, tda998x_detect_work);
1506
1507 /* wake up the device: */
1508 cec_write(priv, REG_CEC_ENAMODS,
1509 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1510
1511 tda998x_reset(priv);
1512
1513 /* read version: */
1514 rev_lo = reg_read(priv, REG_VERSION_LSB);
1515 rev_hi = reg_read(priv, REG_VERSION_MSB);
1516 if (rev_lo < 0 || rev_hi < 0) {
1517 ret = rev_lo < 0 ? rev_lo : rev_hi;
1518 goto fail;
1519 }
1520
1521 priv->rev = rev_lo | rev_hi << 8;
1522
1523 /* mask off feature bits: */
1524 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1525
1526 switch (priv->rev) {
1527 case TDA9989N2:
1528 dev_info(&client->dev, "found TDA9989 n2");
1529 break;
1530 case TDA19989:
1531 dev_info(&client->dev, "found TDA19989");
1532 break;
1533 case TDA19989N2:
1534 dev_info(&client->dev, "found TDA19989 n2");
1535 break;
1536 case TDA19988:
1537 dev_info(&client->dev, "found TDA19988");
1538 break;
1539 default:
1540 dev_err(&client->dev, "found unsupported device: %04x\n",
1541 priv->rev);
1542 goto fail;
1543 }
1544
1545 /* after reset, enable DDC: */
1546 reg_write(priv, REG_DDC_DISABLE, 0x00);
1547
1548 /* set clock on DDC channel: */
1549 reg_write(priv, REG_TX3, 39);
1550
1551 /* if necessary, disable multi-master: */
1552 if (priv->rev == TDA19989)
1553 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1554
1555 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1556 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1557
1558 /* initialize the optional IRQ */
1559 if (client->irq) {
1560 unsigned long irq_flags;
1561
1562 /* init read EDID waitqueue and HDP work */
1563 init_waitqueue_head(&priv->wq_edid);
1564
1565 /* clear pending interrupts */
1566 reg_read(priv, REG_INT_FLAGS_0);
1567 reg_read(priv, REG_INT_FLAGS_1);
1568 reg_read(priv, REG_INT_FLAGS_2);
1569
1570 irq_flags =
1571 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1572 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1573 ret = request_threaded_irq(client->irq, NULL,
1574 tda998x_irq_thread, irq_flags,
1575 "tda998x", priv);
1576 if (ret) {
1577 dev_err(&client->dev,
1578 "failed to request IRQ#%u: %d\n",
1579 client->irq, ret);
1580 goto fail;
1581 }
1582
1583 /* enable HPD irq */
1584 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1585 }
1586
1587 /* enable EDID read irq: */
1588 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1589
1590 if (!np)
1591 return 0; /* non-DT */
1592
1593 /* get the device tree parameters */
1594 ret = of_property_read_u32(np, "video-ports", &video);
1595 if (ret == 0) {
1596 priv->vip_cntrl_0 = video >> 16;
1597 priv->vip_cntrl_1 = video >> 8;
1598 priv->vip_cntrl_2 = video;
1599 }
1600
1601 ret = tda998x_get_audio_ports(priv, np);
1602 if (ret)
1603 goto fail;
1604
1605 if (priv->audio_port[0].format != AFMT_UNUSED)
1606 tda998x_audio_codec_init(priv, &client->dev);
1607
1608 return 0;
1609fail:
1610 /* if encoder_init fails, the encoder slave is never registered,
1611 * so cleanup here:
1612 */
1613 if (priv->cec)
1614 i2c_unregister_device(priv->cec);
1615 return -ENXIO;
1616}
1617
1618static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1619{
1620 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1621}
1622
1623static void tda998x_encoder_commit(struct drm_encoder *encoder)
1624{
1625 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1626}
1627
1628static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1629 .dpms = tda998x_encoder_dpms,
1630 .prepare = tda998x_encoder_prepare,
1631 .commit = tda998x_encoder_commit,
1632 .mode_set = tda998x_encoder_mode_set,
1633};
1634
1635static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1636{
1637 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1638
1639 tda998x_destroy(priv);
1640 drm_encoder_cleanup(encoder);
1641}
1642
1643static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1644 .destroy = tda998x_encoder_destroy,
1645};
1646
1647static void tda998x_set_config(struct tda998x_priv *priv,
1648 const struct tda998x_encoder_params *p)
1649{
1650 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1651 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1652 VIP_CNTRL_0_SWAP_B(p->swap_b) |
1653 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1654 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1655 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1656 VIP_CNTRL_1_SWAP_D(p->swap_d) |
1657 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1658 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1659 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1660 VIP_CNTRL_2_SWAP_F(p->swap_f) |
1661 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1662
1663 priv->audio_params = p->audio_params;
1664}
1665
1666static int tda998x_bind(struct device *dev, struct device *master, void *data)
1667{
1668 struct tda998x_encoder_params *params = dev->platform_data;
1669 struct i2c_client *client = to_i2c_client(dev);
1670 struct drm_device *drm = data;
1671 struct tda998x_priv *priv;
1672 u32 crtcs = 0;
1673 int ret;
1674
1675 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1676 if (!priv)
1677 return -ENOMEM;
1678
1679 dev_set_drvdata(dev, priv);
1680
1681 if (dev->of_node)
1682 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1683
1684 /* If no CRTCs were found, fall back to our old behaviour */
1685 if (crtcs == 0) {
1686 dev_warn(dev, "Falling back to first CRTC\n");
1687 crtcs = 1 << 0;
1688 }
1689
1690 priv->encoder.possible_crtcs = crtcs;
1691
1692 ret = tda998x_create(client, priv);
1693 if (ret)
1694 return ret;
1695
1696 if (!dev->of_node && params)
1697 tda998x_set_config(priv, params);
1698
1699 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1700 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1701 DRM_MODE_ENCODER_TMDS, NULL);
1702 if (ret)
1703 goto err_encoder;
1704
1705 ret = tda998x_connector_init(priv, drm);
1706 if (ret)
1707 goto err_connector;
1708
1709 return 0;
1710
1711err_connector:
1712 drm_encoder_cleanup(&priv->encoder);
1713err_encoder:
1714 tda998x_destroy(priv);
1715 return ret;
1716}
1717
1718static void tda998x_unbind(struct device *dev, struct device *master,
1719 void *data)
1720{
1721 struct tda998x_priv *priv = dev_get_drvdata(dev);
1722
1723 drm_connector_cleanup(&priv->connector);
1724 drm_encoder_cleanup(&priv->encoder);
1725 tda998x_destroy(priv);
1726}
1727
1728static const struct component_ops tda998x_ops = {
1729 .bind = tda998x_bind,
1730 .unbind = tda998x_unbind,
1731};
1732
1733static int
1734tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1735{
1736 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1737 dev_warn(&client->dev, "adapter does not support I2C\n");
1738 return -EIO;
1739 }
1740 return component_add(&client->dev, &tda998x_ops);
1741}
1742
1743static int tda998x_remove(struct i2c_client *client)
1744{
1745 component_del(&client->dev, &tda998x_ops);
1746 return 0;
1747}
1748
1749#ifdef CONFIG_OF
1750static const struct of_device_id tda998x_dt_ids[] = {
1751 { .compatible = "nxp,tda998x", },
1752 { }
1753};
1754MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1755#endif
1756
1757static struct i2c_device_id tda998x_ids[] = {
1758 { "tda998x", 0 },
1759 { }
1760};
1761MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1762
1763static struct i2c_driver tda998x_driver = {
1764 .probe = tda998x_probe,
1765 .remove = tda998x_remove,
1766 .driver = {
1767 .name = "tda998x",
1768 .of_match_table = of_match_ptr(tda998x_dt_ids),
1769 },
1770 .id_table = tda998x_ids,
1771};
1772
1773module_i2c_driver(tda998x_driver);
1774
1775MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1776MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1777MODULE_LICENSE("GPL");