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1/*
2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
3 * Author: Lin Huang <hl@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/arm-smccc.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/devfreq.h>
19#include <linux/devfreq-event.h>
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pm_opp.h>
25#include <linux/regulator/consumer.h>
26#include <linux/rwsem.h>
27#include <linux/suspend.h>
28
29#include <soc/rockchip/rockchip_sip.h>
30
31struct dram_timing {
32 unsigned int ddr3_speed_bin;
33 unsigned int pd_idle;
34 unsigned int sr_idle;
35 unsigned int sr_mc_gate_idle;
36 unsigned int srpd_lite_idle;
37 unsigned int standby_idle;
38 unsigned int auto_pd_dis_freq;
39 unsigned int dram_dll_dis_freq;
40 unsigned int phy_dll_dis_freq;
41 unsigned int ddr3_odt_dis_freq;
42 unsigned int ddr3_drv;
43 unsigned int ddr3_odt;
44 unsigned int phy_ddr3_ca_drv;
45 unsigned int phy_ddr3_dq_drv;
46 unsigned int phy_ddr3_odt;
47 unsigned int lpddr3_odt_dis_freq;
48 unsigned int lpddr3_drv;
49 unsigned int lpddr3_odt;
50 unsigned int phy_lpddr3_ca_drv;
51 unsigned int phy_lpddr3_dq_drv;
52 unsigned int phy_lpddr3_odt;
53 unsigned int lpddr4_odt_dis_freq;
54 unsigned int lpddr4_drv;
55 unsigned int lpddr4_dq_odt;
56 unsigned int lpddr4_ca_odt;
57 unsigned int phy_lpddr4_ca_drv;
58 unsigned int phy_lpddr4_ck_cs_drv;
59 unsigned int phy_lpddr4_dq_drv;
60 unsigned int phy_lpddr4_odt;
61};
62
63struct rk3399_dmcfreq {
64 struct device *dev;
65 struct devfreq *devfreq;
66 struct devfreq_simple_ondemand_data ondemand_data;
67 struct clk *dmc_clk;
68 struct devfreq_event_dev *edev;
69 struct mutex lock;
70 struct dram_timing timing;
71
72 /*
73 * DDR Converser of Frequency (DCF) is used to implement DDR frequency
74 * conversion without the participation of CPU, we will implement and
75 * control it in arm trust firmware.
76 */
77 wait_queue_head_t wait_dcf_queue;
78 int irq;
79 int wait_dcf_flag;
80 struct regulator *vdd_center;
81 unsigned long rate, target_rate;
82 unsigned long volt, target_volt;
83};
84
85static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
86 u32 flags)
87{
88 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
89 struct dev_pm_opp *opp;
90 unsigned long old_clk_rate = dmcfreq->rate;
91 unsigned long target_volt, target_rate;
92 int err;
93
94 rcu_read_lock();
95 opp = devfreq_recommended_opp(dev, freq, flags);
96 if (IS_ERR(opp)) {
97 rcu_read_unlock();
98 return PTR_ERR(opp);
99 }
100
101 target_rate = dev_pm_opp_get_freq(opp);
102 target_volt = dev_pm_opp_get_voltage(opp);
103
104 rcu_read_unlock();
105
106 if (dmcfreq->rate == target_rate)
107 return 0;
108
109 mutex_lock(&dmcfreq->lock);
110
111 /*
112 * If frequency scaling from low to high, adjust voltage first.
113 * If frequency scaling from high to low, adjust frequency first.
114 */
115 if (old_clk_rate < target_rate) {
116 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
117 target_volt);
118 if (err) {
119 dev_err(dev, "Cannot to set voltage %lu uV\n",
120 target_volt);
121 goto out;
122 }
123 }
124 dmcfreq->wait_dcf_flag = 1;
125
126 err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
127 if (err) {
128 dev_err(dev, "Cannot to set frequency %lu (%d)\n",
129 target_rate, err);
130 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
131 dmcfreq->volt);
132 goto out;
133 }
134
135 /*
136 * Wait until bcf irq happen, it means freq scaling finish in
137 * arm trust firmware, use 100ms as timeout time.
138 */
139 if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
140 !dmcfreq->wait_dcf_flag, HZ / 10))
141 dev_warn(dev, "Timeout waiting for dcf interrupt\n");
142
143 /*
144 * Check the dpll rate,
145 * There only two result we will get,
146 * 1. Ddr frequency scaling fail, we still get the old rate.
147 * 2. Ddr frequency scaling sucessful, we get the rate we set.
148 */
149 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
150
151 /* If get the incorrect rate, set voltage to old value. */
152 if (dmcfreq->rate != target_rate) {
153 dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
154 Current frequency %lu\n", target_rate, dmcfreq->rate);
155 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
156 dmcfreq->volt);
157 goto out;
158 } else if (old_clk_rate > target_rate)
159 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
160 target_volt);
161 if (err)
162 dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
163
164 dmcfreq->rate = target_rate;
165 dmcfreq->volt = target_volt;
166
167out:
168 mutex_unlock(&dmcfreq->lock);
169 return err;
170}
171
172static int rk3399_dmcfreq_get_dev_status(struct device *dev,
173 struct devfreq_dev_status *stat)
174{
175 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
176 struct devfreq_event_data edata;
177 int ret = 0;
178
179 ret = devfreq_event_get_event(dmcfreq->edev, &edata);
180 if (ret < 0)
181 return ret;
182
183 stat->current_frequency = dmcfreq->rate;
184 stat->busy_time = edata.load_count;
185 stat->total_time = edata.total_count;
186
187 return ret;
188}
189
190static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
191{
192 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
193
194 *freq = dmcfreq->rate;
195
196 return 0;
197}
198
199static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
200 .polling_ms = 200,
201 .target = rk3399_dmcfreq_target,
202 .get_dev_status = rk3399_dmcfreq_get_dev_status,
203 .get_cur_freq = rk3399_dmcfreq_get_cur_freq,
204};
205
206static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
207{
208 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
209 int ret = 0;
210
211 ret = devfreq_event_disable_edev(dmcfreq->edev);
212 if (ret < 0) {
213 dev_err(dev, "failed to disable the devfreq-event devices\n");
214 return ret;
215 }
216
217 ret = devfreq_suspend_device(dmcfreq->devfreq);
218 if (ret < 0) {
219 dev_err(dev, "failed to suspend the devfreq devices\n");
220 return ret;
221 }
222
223 return 0;
224}
225
226static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
227{
228 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
229 int ret = 0;
230
231 ret = devfreq_event_enable_edev(dmcfreq->edev);
232 if (ret < 0) {
233 dev_err(dev, "failed to enable the devfreq-event devices\n");
234 return ret;
235 }
236
237 ret = devfreq_resume_device(dmcfreq->devfreq);
238 if (ret < 0) {
239 dev_err(dev, "failed to resume the devfreq devices\n");
240 return ret;
241 }
242 return ret;
243}
244
245static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
246 rk3399_dmcfreq_resume);
247
248static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
249{
250 struct rk3399_dmcfreq *dmcfreq = dev_id;
251 struct arm_smccc_res res;
252
253 dmcfreq->wait_dcf_flag = 0;
254 wake_up(&dmcfreq->wait_dcf_queue);
255
256 /* Clear the DCF interrupt */
257 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
258 ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
259 0, 0, 0, 0, &res);
260
261 return IRQ_HANDLED;
262}
263
264static int of_get_ddr_timings(struct dram_timing *timing,
265 struct device_node *np)
266{
267 int ret = 0;
268
269 ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
270 &timing->ddr3_speed_bin);
271 ret |= of_property_read_u32(np, "rockchip,pd_idle",
272 &timing->pd_idle);
273 ret |= of_property_read_u32(np, "rockchip,sr_idle",
274 &timing->sr_idle);
275 ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
276 &timing->sr_mc_gate_idle);
277 ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
278 &timing->srpd_lite_idle);
279 ret |= of_property_read_u32(np, "rockchip,standby_idle",
280 &timing->standby_idle);
281 ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
282 &timing->auto_pd_dis_freq);
283 ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
284 &timing->dram_dll_dis_freq);
285 ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
286 &timing->phy_dll_dis_freq);
287 ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
288 &timing->ddr3_odt_dis_freq);
289 ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
290 &timing->ddr3_drv);
291 ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
292 &timing->ddr3_odt);
293 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
294 &timing->phy_ddr3_ca_drv);
295 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
296 &timing->phy_ddr3_dq_drv);
297 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
298 &timing->phy_ddr3_odt);
299 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
300 &timing->lpddr3_odt_dis_freq);
301 ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
302 &timing->lpddr3_drv);
303 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
304 &timing->lpddr3_odt);
305 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
306 &timing->phy_lpddr3_ca_drv);
307 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
308 &timing->phy_lpddr3_dq_drv);
309 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
310 &timing->phy_lpddr3_odt);
311 ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
312 &timing->lpddr4_odt_dis_freq);
313 ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
314 &timing->lpddr4_drv);
315 ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
316 &timing->lpddr4_dq_odt);
317 ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
318 &timing->lpddr4_ca_odt);
319 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
320 &timing->phy_lpddr4_ca_drv);
321 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
322 &timing->phy_lpddr4_ck_cs_drv);
323 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
324 &timing->phy_lpddr4_dq_drv);
325 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
326 &timing->phy_lpddr4_odt);
327
328 return ret;
329}
330
331static int rk3399_dmcfreq_probe(struct platform_device *pdev)
332{
333 struct arm_smccc_res res;
334 struct device *dev = &pdev->dev;
335 struct device_node *np = pdev->dev.of_node;
336 struct rk3399_dmcfreq *data;
337 int ret, irq, index, size;
338 uint32_t *timing;
339 struct dev_pm_opp *opp;
340
341 irq = platform_get_irq(pdev, 0);
342 if (irq < 0) {
343 dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
344 return -EINVAL;
345 }
346 data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
347 if (!data)
348 return -ENOMEM;
349
350 mutex_init(&data->lock);
351
352 data->vdd_center = devm_regulator_get(dev, "center");
353 if (IS_ERR(data->vdd_center)) {
354 dev_err(dev, "Cannot get the regulator \"center\"\n");
355 return PTR_ERR(data->vdd_center);
356 }
357
358 data->dmc_clk = devm_clk_get(dev, "dmc_clk");
359 if (IS_ERR(data->dmc_clk)) {
360 dev_err(dev, "Cannot get the clk dmc_clk\n");
361 return PTR_ERR(data->dmc_clk);
362 };
363
364 data->irq = irq;
365 ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
366 dev_name(dev), data);
367 if (ret) {
368 dev_err(dev, "Failed to request dmc irq: %d\n", ret);
369 return ret;
370 }
371
372 init_waitqueue_head(&data->wait_dcf_queue);
373 data->wait_dcf_flag = 0;
374
375 data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
376 if (IS_ERR(data->edev))
377 return -EPROBE_DEFER;
378
379 ret = devfreq_event_enable_edev(data->edev);
380 if (ret < 0) {
381 dev_err(dev, "failed to enable devfreq-event devices\n");
382 return ret;
383 }
384
385 /*
386 * Get dram timing and pass it to arm trust firmware,
387 * the dram drvier in arm trust firmware will get these
388 * timing and to do dram initial.
389 */
390 if (!of_get_ddr_timings(&data->timing, np)) {
391 timing = &data->timing.ddr3_speed_bin;
392 size = sizeof(struct dram_timing) / 4;
393 for (index = 0; index < size; index++) {
394 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
395 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
396 0, 0, 0, 0, &res);
397 if (res.a0) {
398 dev_err(dev, "Failed to set dram param: %ld\n",
399 res.a0);
400 return -EINVAL;
401 }
402 }
403 }
404
405 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
406 ROCKCHIP_SIP_CONFIG_DRAM_INIT,
407 0, 0, 0, 0, &res);
408
409 /*
410 * We add a devfreq driver to our parent since it has a device tree node
411 * with operating points.
412 */
413 if (dev_pm_opp_of_add_table(dev)) {
414 dev_err(dev, "Invalid operating-points in device tree.\n");
415 return -EINVAL;
416 }
417
418 of_property_read_u32(np, "upthreshold",
419 &data->ondemand_data.upthreshold);
420 of_property_read_u32(np, "downdifferential",
421 &data->ondemand_data.downdifferential);
422
423 data->rate = clk_get_rate(data->dmc_clk);
424
425 rcu_read_lock();
426 opp = devfreq_recommended_opp(dev, &data->rate, 0);
427 if (IS_ERR(opp)) {
428 rcu_read_unlock();
429 return PTR_ERR(opp);
430 }
431 data->rate = dev_pm_opp_get_freq(opp);
432 data->volt = dev_pm_opp_get_voltage(opp);
433 rcu_read_unlock();
434
435 rk3399_devfreq_dmc_profile.initial_freq = data->rate;
436
437 data->devfreq = devm_devfreq_add_device(dev,
438 &rk3399_devfreq_dmc_profile,
439 "simple_ondemand",
440 &data->ondemand_data);
441 if (IS_ERR(data->devfreq))
442 return PTR_ERR(data->devfreq);
443 devm_devfreq_register_opp_notifier(dev, data->devfreq);
444
445 data->dev = dev;
446 platform_set_drvdata(pdev, data);
447
448 return 0;
449}
450
451static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
452 { .compatible = "rockchip,rk3399-dmc" },
453 { },
454};
455MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
456
457static struct platform_driver rk3399_dmcfreq_driver = {
458 .probe = rk3399_dmcfreq_probe,
459 .driver = {
460 .name = "rk3399-dmc-freq",
461 .pm = &rk3399_dmcfreq_pm,
462 .of_match_table = rk3399dmc_devfreq_of_match,
463 },
464};
465module_platform_driver(rk3399_dmcfreq_driver);
466
467MODULE_LICENSE("GPL v2");
468MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
469MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");