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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1997, 1998 Ralf Baechle
7 * Copyright (C) 1999 SuSE GmbH
8 * Copyright (C) 1999-2001 Hewlett-Packard Company
9 * Copyright (C) 1999-2001 Grant Grundler
10 */
11#include <linux/eisa.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/types.h>
17
18#include <asm/io.h>
19#include <asm/superio.h>
20
21#define DEBUG_RESOURCES 0
22#define DEBUG_CONFIG 0
23
24#if DEBUG_CONFIG
25# define DBGC(x...) printk(KERN_DEBUG x)
26#else
27# define DBGC(x...)
28#endif
29
30
31#if DEBUG_RESOURCES
32#define DBG_RES(x...) printk(KERN_DEBUG x)
33#else
34#define DBG_RES(x...)
35#endif
36
37/* To be used as: mdelay(pci_post_reset_delay);
38 *
39 * post_reset is the time the kernel should stall to prevent anyone from
40 * accessing the PCI bus once #RESET is de-asserted.
41 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
42 * this makes the boot time much longer than necessary.
43 * 20ms seems to work for all the HP PCI implementations to date.
44 *
45 * #define pci_post_reset_delay 50
46 */
47
48struct pci_port_ops *pci_port __read_mostly;
49struct pci_bios_ops *pci_bios __read_mostly;
50
51static int pci_hba_count __read_mostly;
52
53/* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */
54#define PCI_HBA_MAX 32
55static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly;
56
57
58/********************************************************************
59**
60** I/O port space support
61**
62*********************************************************************/
63
64/* EISA port numbers and PCI port numbers share the same interface. Some
65 * machines have both EISA and PCI adapters installed. Rather than turn
66 * pci_port into an array, we reserve bus 0 for EISA and call the EISA
67 * routines if the access is to a port on bus 0. We don't want to fix
68 * EISA and ISA drivers which assume port space is <= 0xffff.
69 */
70
71#ifdef CONFIG_EISA
72#define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
73#define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
74#else
75#define EISA_IN(size)
76#define EISA_OUT(size)
77#endif
78
79#define PCI_PORT_IN(type, size) \
80u##size in##type (int addr) \
81{ \
82 int b = PCI_PORT_HBA(addr); \
83 EISA_IN(size); \
84 if (!parisc_pci_hba[b]) return (u##size) -1; \
85 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
86} \
87EXPORT_SYMBOL(in##type);
88
89PCI_PORT_IN(b, 8)
90PCI_PORT_IN(w, 16)
91PCI_PORT_IN(l, 32)
92
93
94#define PCI_PORT_OUT(type, size) \
95void out##type (u##size d, int addr) \
96{ \
97 int b = PCI_PORT_HBA(addr); \
98 EISA_OUT(size); \
99 if (!parisc_pci_hba[b]) return; \
100 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
101} \
102EXPORT_SYMBOL(out##type);
103
104PCI_PORT_OUT(b, 8)
105PCI_PORT_OUT(w, 16)
106PCI_PORT_OUT(l, 32)
107
108
109
110/*
111 * BIOS32 replacement.
112 */
113static int __init pcibios_init(void)
114{
115 if (!pci_bios)
116 return -1;
117
118 if (pci_bios->init) {
119 pci_bios->init();
120 } else {
121 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
122 }
123
124 /* Set the CLS for PCI as early as possible. */
125 pci_cache_line_size = pci_dfl_cache_line_size;
126
127 return 0;
128}
129
130
131/* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
132void pcibios_fixup_bus(struct pci_bus *bus)
133{
134 if (pci_bios->fixup_bus) {
135 pci_bios->fixup_bus(bus);
136 } else {
137 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
138 }
139}
140
141
142/*
143 * Called by pci_set_master() - a driver interface.
144 *
145 * Legacy PDC guarantees to set:
146 * Map Memory BAR's into PA IO space.
147 * Map Expansion ROM BAR into one common PA IO space per bus.
148 * Map IO BAR's into PCI IO space.
149 * Command (see below)
150 * Cache Line Size
151 * Latency Timer
152 * Interrupt Line
153 * PPB: secondary latency timer, io/mmio base/limit,
154 * bus numbers, bridge control
155 *
156 */
157void pcibios_set_master(struct pci_dev *dev)
158{
159 u8 lat;
160
161 /* If someone already mucked with this, don't touch it. */
162 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
163 if (lat >= 16) return;
164
165 /*
166 ** HP generally has fewer devices on the bus than other architectures.
167 ** upper byte is PCI_LATENCY_TIMER.
168 */
169 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
170 (0x80 << 8) | pci_cache_line_size);
171}
172
173/*
174 * pcibios_init_bridge() initializes cache line and default latency
175 * for pci controllers and pci-pci bridges
176 */
177void __init pcibios_init_bridge(struct pci_dev *dev)
178{
179 unsigned short bridge_ctl, bridge_ctl_new;
180
181 /* We deal only with pci controllers and pci-pci bridges. */
182 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
183 return;
184
185 /* PCI-PCI bridge - set the cache line and default latency
186 * (32) for primary and secondary buses.
187 */
188 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
189
190 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
191
192 bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY |
193 PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT;
194 dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n",
195 bridge_ctl, bridge_ctl_new);
196
197 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new);
198}
199
200/*
201 * pcibios align resources() is called every time generic PCI code
202 * wants to generate a new address. The process of looking for
203 * an available address, each candidate is first "aligned" and
204 * then checked if the resource is available until a match is found.
205 *
206 * Since we are just checking candidates, don't use any fields other
207 * than res->start.
208 */
209resource_size_t pcibios_align_resource(void *data, const struct resource *res,
210 resource_size_t size, resource_size_t alignment)
211{
212 resource_size_t mask, align, start = res->start;
213
214 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
215 pci_name(((struct pci_dev *) data)),
216 res->parent, res->start, res->end,
217 (int) res->flags, size, alignment);
218
219 /* If it's not IO, then it's gotta be MEM */
220 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
221
222 /* Align to largest of MIN or input size */
223 mask = max(alignment, align) - 1;
224 start += mask;
225 start &= ~mask;
226
227 return start;
228}
229
230
231int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
232 enum pci_mmap_state mmap_state, int write_combine)
233{
234 unsigned long prot;
235
236 /*
237 * I/O space can be accessed via normal processor loads and stores on
238 * this platform but for now we elect not to do this and portable
239 * drivers should not do this anyway.
240 */
241 if (mmap_state == pci_mmap_io)
242 return -EINVAL;
243
244 if (write_combine)
245 return -EINVAL;
246
247 /*
248 * Ignore write-combine; for now only return uncached mappings.
249 */
250 prot = pgprot_val(vma->vm_page_prot);
251 prot |= _PAGE_NO_CACHE;
252 vma->vm_page_prot = __pgprot(prot);
253
254 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
255 vma->vm_end - vma->vm_start, vma->vm_page_prot);
256}
257
258/*
259 * A driver is enabling the device. We make sure that all the appropriate
260 * bits are set to allow the device to operate as the driver is expecting.
261 * We enable the port IO and memory IO bits if the device has any BARs of
262 * that type, and we enable the PERR and SERR bits unconditionally.
263 * Drivers that do not need parity (eg graphics and possibly networking)
264 * can clear these bits if they want.
265 */
266int pcibios_enable_device(struct pci_dev *dev, int mask)
267{
268 int err;
269 u16 cmd, old_cmd;
270
271 err = pci_enable_resources(dev, mask);
272 if (err < 0)
273 return err;
274
275 pci_read_config_word(dev, PCI_COMMAND, &cmd);
276 old_cmd = cmd;
277
278 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
279
280#if 0
281 /* If bridge/bus controller has FBB enabled, child must too. */
282 if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
283 cmd |= PCI_COMMAND_FAST_BACK;
284#endif
285
286 if (cmd != old_cmd) {
287 dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
288 old_cmd, cmd);
289 pci_write_config_word(dev, PCI_COMMAND, cmd);
290 }
291 return 0;
292}
293
294
295/* PA-RISC specific */
296void pcibios_register_hba(struct pci_hba_data *hba)
297{
298 if (pci_hba_count >= PCI_HBA_MAX) {
299 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
300 return;
301 }
302
303 parisc_pci_hba[pci_hba_count] = hba;
304 hba->hba_num = pci_hba_count++;
305}
306
307subsys_initcall(pcibios_init);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1997, 1998 Ralf Baechle
7 * Copyright (C) 1999 SuSE GmbH
8 * Copyright (C) 1999-2001 Hewlett-Packard Company
9 * Copyright (C) 1999-2001 Grant Grundler
10 */
11#include <linux/eisa.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/types.h>
17
18#include <asm/io.h>
19#include <asm/superio.h>
20
21#define DEBUG_RESOURCES 0
22#define DEBUG_CONFIG 0
23
24#if DEBUG_CONFIG
25# define DBGC(x...) printk(KERN_DEBUG x)
26#else
27# define DBGC(x...)
28#endif
29
30
31#if DEBUG_RESOURCES
32#define DBG_RES(x...) printk(KERN_DEBUG x)
33#else
34#define DBG_RES(x...)
35#endif
36
37/* To be used as: mdelay(pci_post_reset_delay);
38 *
39 * post_reset is the time the kernel should stall to prevent anyone from
40 * accessing the PCI bus once #RESET is de-asserted.
41 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
42 * this makes the boot time much longer than necessary.
43 * 20ms seems to work for all the HP PCI implementations to date.
44 *
45 * #define pci_post_reset_delay 50
46 */
47
48struct pci_port_ops *pci_port __read_mostly;
49struct pci_bios_ops *pci_bios __read_mostly;
50
51static int pci_hba_count __read_mostly;
52
53/* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */
54#define PCI_HBA_MAX 32
55static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly;
56
57
58/********************************************************************
59**
60** I/O port space support
61**
62*********************************************************************/
63
64/* EISA port numbers and PCI port numbers share the same interface. Some
65 * machines have both EISA and PCI adapters installed. Rather than turn
66 * pci_port into an array, we reserve bus 0 for EISA and call the EISA
67 * routines if the access is to a port on bus 0. We don't want to fix
68 * EISA and ISA drivers which assume port space is <= 0xffff.
69 */
70
71#ifdef CONFIG_EISA
72#define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
73#define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
74#else
75#define EISA_IN(size)
76#define EISA_OUT(size)
77#endif
78
79#define PCI_PORT_IN(type, size) \
80u##size in##type (int addr) \
81{ \
82 int b = PCI_PORT_HBA(addr); \
83 EISA_IN(size); \
84 if (!parisc_pci_hba[b]) return (u##size) -1; \
85 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
86} \
87EXPORT_SYMBOL(in##type);
88
89PCI_PORT_IN(b, 8)
90PCI_PORT_IN(w, 16)
91PCI_PORT_IN(l, 32)
92
93
94#define PCI_PORT_OUT(type, size) \
95void out##type (u##size d, int addr) \
96{ \
97 int b = PCI_PORT_HBA(addr); \
98 EISA_OUT(size); \
99 if (!parisc_pci_hba[b]) return; \
100 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
101} \
102EXPORT_SYMBOL(out##type);
103
104PCI_PORT_OUT(b, 8)
105PCI_PORT_OUT(w, 16)
106PCI_PORT_OUT(l, 32)
107
108
109
110/*
111 * BIOS32 replacement.
112 */
113static int __init pcibios_init(void)
114{
115 if (!pci_bios)
116 return -1;
117
118 if (pci_bios->init) {
119 pci_bios->init();
120 } else {
121 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
122 }
123
124 /* Set the CLS for PCI as early as possible. */
125 pci_cache_line_size = pci_dfl_cache_line_size;
126
127 return 0;
128}
129
130
131/* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
132void pcibios_fixup_bus(struct pci_bus *bus)
133{
134 if (pci_bios->fixup_bus) {
135 pci_bios->fixup_bus(bus);
136 } else {
137 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
138 }
139}
140
141
142/*
143 * Called by pci_set_master() - a driver interface.
144 *
145 * Legacy PDC guarantees to set:
146 * Map Memory BAR's into PA IO space.
147 * Map Expansion ROM BAR into one common PA IO space per bus.
148 * Map IO BAR's into PCI IO space.
149 * Command (see below)
150 * Cache Line Size
151 * Latency Timer
152 * Interrupt Line
153 * PPB: secondary latency timer, io/mmio base/limit,
154 * bus numbers, bridge control
155 *
156 */
157void pcibios_set_master(struct pci_dev *dev)
158{
159 u8 lat;
160
161 /* If someone already mucked with this, don't touch it. */
162 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
163 if (lat >= 16) return;
164
165 /*
166 ** HP generally has fewer devices on the bus than other architectures.
167 ** upper byte is PCI_LATENCY_TIMER.
168 */
169 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
170 (0x80 << 8) | pci_cache_line_size);
171}
172
173/*
174 * pcibios_init_bridge() initializes cache line and default latency
175 * for pci controllers and pci-pci bridges
176 */
177void __init pcibios_init_bridge(struct pci_dev *dev)
178{
179 unsigned short bridge_ctl, bridge_ctl_new;
180
181 /* We deal only with pci controllers and pci-pci bridges. */
182 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
183 return;
184
185 /* PCI-PCI bridge - set the cache line and default latency
186 * (32) for primary and secondary buses.
187 */
188 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
189
190 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
191
192 bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY |
193 PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT;
194 dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n",
195 bridge_ctl, bridge_ctl_new);
196
197 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new);
198}
199
200/*
201 * pcibios align resources() is called every time generic PCI code
202 * wants to generate a new address. The process of looking for
203 * an available address, each candidate is first "aligned" and
204 * then checked if the resource is available until a match is found.
205 *
206 * Since we are just checking candidates, don't use any fields other
207 * than res->start.
208 */
209resource_size_t pcibios_align_resource(void *data, const struct resource *res,
210 resource_size_t size, resource_size_t alignment)
211{
212 resource_size_t mask, align, start = res->start;
213
214 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
215 pci_name(((struct pci_dev *) data)),
216 res->parent, res->start, res->end,
217 (int) res->flags, size, alignment);
218
219 /* If it's not IO, then it's gotta be MEM */
220 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
221
222 /* Align to largest of MIN or input size */
223 mask = max(alignment, align) - 1;
224 start += mask;
225 start &= ~mask;
226
227 return start;
228}
229
230
231int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
232 enum pci_mmap_state mmap_state, int write_combine)
233{
234 unsigned long prot;
235
236 /*
237 * I/O space can be accessed via normal processor loads and stores on
238 * this platform but for now we elect not to do this and portable
239 * drivers should not do this anyway.
240 */
241 if (mmap_state == pci_mmap_io)
242 return -EINVAL;
243
244 if (write_combine)
245 return -EINVAL;
246
247 /*
248 * Ignore write-combine; for now only return uncached mappings.
249 */
250 prot = pgprot_val(vma->vm_page_prot);
251 prot |= _PAGE_NO_CACHE;
252 vma->vm_page_prot = __pgprot(prot);
253
254 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
255 vma->vm_end - vma->vm_start, vma->vm_page_prot);
256}
257
258/*
259 * A driver is enabling the device. We make sure that all the appropriate
260 * bits are set to allow the device to operate as the driver is expecting.
261 * We enable the port IO and memory IO bits if the device has any BARs of
262 * that type, and we enable the PERR and SERR bits unconditionally.
263 * Drivers that do not need parity (eg graphics and possibly networking)
264 * can clear these bits if they want.
265 */
266int pcibios_enable_device(struct pci_dev *dev, int mask)
267{
268 int err;
269 u16 cmd, old_cmd;
270
271 err = pci_enable_resources(dev, mask);
272 if (err < 0)
273 return err;
274
275 pci_read_config_word(dev, PCI_COMMAND, &cmd);
276 old_cmd = cmd;
277
278 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
279
280#if 0
281 /* If bridge/bus controller has FBB enabled, child must too. */
282 if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
283 cmd |= PCI_COMMAND_FAST_BACK;
284#endif
285
286 if (cmd != old_cmd) {
287 dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
288 old_cmd, cmd);
289 pci_write_config_word(dev, PCI_COMMAND, cmd);
290 }
291 return 0;
292}
293
294
295/* PA-RISC specific */
296void pcibios_register_hba(struct pci_hba_data *hba)
297{
298 if (pci_hba_count >= PCI_HBA_MAX) {
299 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
300 return;
301 }
302
303 parisc_pci_hba[pci_hba_count] = hba;
304 hba->hba_num = pci_hba_count++;
305}
306
307subsys_initcall(pcibios_init);