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1/*
2 * Copyright (C) 2015 Free Electrons
3 * Copyright (C) 2015 NextThing Co
4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <drm/drmP.h>
14#include <drm/drm_atomic_helper.h>
15#include <drm/drm_crtc.h>
16#include <drm/drm_crtc_helper.h>
17#include <drm/drm_fb_cma_helper.h>
18#include <drm/drm_gem_cma_helper.h>
19#include <drm/drm_plane_helper.h>
20
21#include <linux/component.h>
22#include <linux/reset.h>
23
24#include "sun4i_backend.h"
25#include "sun4i_drv.h"
26
27static u32 sunxi_rgb2yuv_coef[12] = {
28 0x00000107, 0x00000204, 0x00000064, 0x00000108,
29 0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
30 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
31};
32
33void sun4i_backend_apply_color_correction(struct sun4i_backend *backend)
34{
35 int i;
36
37 DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
38
39 /* Set color correction */
40 regmap_write(backend->regs, SUN4I_BACKEND_OCCTL_REG,
41 SUN4I_BACKEND_OCCTL_ENABLE);
42
43 for (i = 0; i < 12; i++)
44 regmap_write(backend->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
45 sunxi_rgb2yuv_coef[i]);
46}
47EXPORT_SYMBOL(sun4i_backend_apply_color_correction);
48
49void sun4i_backend_disable_color_correction(struct sun4i_backend *backend)
50{
51 DRM_DEBUG_DRIVER("Disabling color correction\n");
52
53 /* Disable color correction */
54 regmap_update_bits(backend->regs, SUN4I_BACKEND_OCCTL_REG,
55 SUN4I_BACKEND_OCCTL_ENABLE, 0);
56}
57EXPORT_SYMBOL(sun4i_backend_disable_color_correction);
58
59void sun4i_backend_commit(struct sun4i_backend *backend)
60{
61 DRM_DEBUG_DRIVER("Committing changes\n");
62
63 regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
64 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
65 SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
66}
67EXPORT_SYMBOL(sun4i_backend_commit);
68
69void sun4i_backend_layer_enable(struct sun4i_backend *backend,
70 int layer, bool enable)
71{
72 u32 val;
73
74 DRM_DEBUG_DRIVER("Enabling layer %d\n", layer);
75
76 if (enable)
77 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
78 else
79 val = 0;
80
81 regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
82 SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
83}
84EXPORT_SYMBOL(sun4i_backend_layer_enable);
85
86static int sun4i_backend_drm_format_to_layer(struct drm_plane *plane,
87 u32 format, u32 *mode)
88{
89 if ((plane->type == DRM_PLANE_TYPE_PRIMARY) &&
90 (format == DRM_FORMAT_ARGB8888))
91 format = DRM_FORMAT_XRGB8888;
92
93 switch (format) {
94 case DRM_FORMAT_ARGB8888:
95 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
96 break;
97
98 case DRM_FORMAT_ARGB4444:
99 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
100 break;
101
102 case DRM_FORMAT_ARGB1555:
103 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
104 break;
105
106 case DRM_FORMAT_RGBA5551:
107 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
108 break;
109
110 case DRM_FORMAT_RGBA4444:
111 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
112 break;
113
114 case DRM_FORMAT_XRGB8888:
115 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
116 break;
117
118 case DRM_FORMAT_RGB888:
119 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
120 break;
121
122 case DRM_FORMAT_RGB565:
123 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
124 break;
125
126 default:
127 return -EINVAL;
128 }
129
130 return 0;
131}
132
133int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
134 int layer, struct drm_plane *plane)
135{
136 struct drm_plane_state *state = plane->state;
137 struct drm_framebuffer *fb = state->fb;
138
139 DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
140
141 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
142 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
143 state->crtc_w, state->crtc_h);
144 regmap_write(backend->regs, SUN4I_BACKEND_DISSIZE_REG,
145 SUN4I_BACKEND_DISSIZE(state->crtc_w,
146 state->crtc_h));
147 }
148
149 /* Set the line width */
150 DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
151 regmap_write(backend->regs, SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
152 fb->pitches[0] * 8);
153
154 /* Set height and width */
155 DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
156 state->crtc_w, state->crtc_h);
157 regmap_write(backend->regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
158 SUN4I_BACKEND_LAYSIZE(state->crtc_w,
159 state->crtc_h));
160
161 /* Set base coordinates */
162 DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
163 state->crtc_x, state->crtc_y);
164 regmap_write(backend->regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
165 SUN4I_BACKEND_LAYCOOR(state->crtc_x,
166 state->crtc_y));
167
168 return 0;
169}
170EXPORT_SYMBOL(sun4i_backend_update_layer_coord);
171
172int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
173 int layer, struct drm_plane *plane)
174{
175 struct drm_plane_state *state = plane->state;
176 struct drm_framebuffer *fb = state->fb;
177 bool interlaced = false;
178 u32 val;
179 int ret;
180
181 if (plane->state->crtc)
182 interlaced = plane->state->crtc->state->adjusted_mode.flags
183 & DRM_MODE_FLAG_INTERLACE;
184
185 regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
186 SUN4I_BACKEND_MODCTL_ITLMOD_EN,
187 interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
188
189 DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
190 interlaced ? "on" : "off");
191
192 ret = sun4i_backend_drm_format_to_layer(plane, fb->pixel_format, &val);
193 if (ret) {
194 DRM_DEBUG_DRIVER("Invalid format\n");
195 return val;
196 }
197
198 regmap_update_bits(backend->regs, SUN4I_BACKEND_ATTCTL_REG1(layer),
199 SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
200
201 return 0;
202}
203EXPORT_SYMBOL(sun4i_backend_update_layer_formats);
204
205int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
206 int layer, struct drm_plane *plane)
207{
208 struct drm_plane_state *state = plane->state;
209 struct drm_framebuffer *fb = state->fb;
210 struct drm_gem_cma_object *gem;
211 u32 lo_paddr, hi_paddr;
212 dma_addr_t paddr;
213 int bpp;
214
215 /* Get the physical address of the buffer in memory */
216 gem = drm_fb_cma_get_gem_obj(fb, 0);
217
218 DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
219
220 /* Compute the start of the displayed memory */
221 bpp = drm_format_plane_cpp(fb->pixel_format, 0);
222 paddr = gem->paddr + fb->offsets[0];
223 paddr += (state->src_x >> 16) * bpp;
224 paddr += (state->src_y >> 16) * fb->pitches[0];
225
226 DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
227
228 /* Write the 32 lower bits of the address (in bits) */
229 lo_paddr = paddr << 3;
230 DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
231 regmap_write(backend->regs, SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
232 lo_paddr);
233
234 /* And the upper bits */
235 hi_paddr = paddr >> 29;
236 DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
237 regmap_update_bits(backend->regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
238 SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
239 SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
240
241 return 0;
242}
243EXPORT_SYMBOL(sun4i_backend_update_layer_buffer);
244
245static int sun4i_backend_init_sat(struct device *dev) {
246 struct sun4i_backend *backend = dev_get_drvdata(dev);
247 int ret;
248
249 backend->sat_reset = devm_reset_control_get(dev, "sat");
250 if (IS_ERR(backend->sat_reset)) {
251 dev_err(dev, "Couldn't get the SAT reset line\n");
252 return PTR_ERR(backend->sat_reset);
253 }
254
255 ret = reset_control_deassert(backend->sat_reset);
256 if (ret) {
257 dev_err(dev, "Couldn't deassert the SAT reset line\n");
258 return ret;
259 }
260
261 backend->sat_clk = devm_clk_get(dev, "sat");
262 if (IS_ERR(backend->sat_clk)) {
263 dev_err(dev, "Couldn't get our SAT clock\n");
264 ret = PTR_ERR(backend->sat_clk);
265 goto err_assert_reset;
266 }
267
268 ret = clk_prepare_enable(backend->sat_clk);
269 if (ret) {
270 dev_err(dev, "Couldn't enable the SAT clock\n");
271 return ret;
272 }
273
274 return 0;
275
276err_assert_reset:
277 reset_control_assert(backend->sat_reset);
278 return ret;
279}
280
281static int sun4i_backend_free_sat(struct device *dev) {
282 struct sun4i_backend *backend = dev_get_drvdata(dev);
283
284 clk_disable_unprepare(backend->sat_clk);
285 reset_control_assert(backend->sat_reset);
286
287 return 0;
288}
289
290static struct regmap_config sun4i_backend_regmap_config = {
291 .reg_bits = 32,
292 .val_bits = 32,
293 .reg_stride = 4,
294 .max_register = 0x5800,
295};
296
297static int sun4i_backend_bind(struct device *dev, struct device *master,
298 void *data)
299{
300 struct platform_device *pdev = to_platform_device(dev);
301 struct drm_device *drm = data;
302 struct sun4i_drv *drv = drm->dev_private;
303 struct sun4i_backend *backend;
304 struct resource *res;
305 void __iomem *regs;
306 int i, ret;
307
308 backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
309 if (!backend)
310 return -ENOMEM;
311 dev_set_drvdata(dev, backend);
312 drv->backend = backend;
313
314 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
315 regs = devm_ioremap_resource(dev, res);
316 if (IS_ERR(regs))
317 return PTR_ERR(regs);
318
319 backend->regs = devm_regmap_init_mmio(dev, regs,
320 &sun4i_backend_regmap_config);
321 if (IS_ERR(backend->regs)) {
322 dev_err(dev, "Couldn't create the backend0 regmap\n");
323 return PTR_ERR(backend->regs);
324 }
325
326 backend->reset = devm_reset_control_get(dev, NULL);
327 if (IS_ERR(backend->reset)) {
328 dev_err(dev, "Couldn't get our reset line\n");
329 return PTR_ERR(backend->reset);
330 }
331
332 ret = reset_control_deassert(backend->reset);
333 if (ret) {
334 dev_err(dev, "Couldn't deassert our reset line\n");
335 return ret;
336 }
337
338 backend->bus_clk = devm_clk_get(dev, "ahb");
339 if (IS_ERR(backend->bus_clk)) {
340 dev_err(dev, "Couldn't get the backend bus clock\n");
341 ret = PTR_ERR(backend->bus_clk);
342 goto err_assert_reset;
343 }
344 clk_prepare_enable(backend->bus_clk);
345
346 backend->mod_clk = devm_clk_get(dev, "mod");
347 if (IS_ERR(backend->mod_clk)) {
348 dev_err(dev, "Couldn't get the backend module clock\n");
349 ret = PTR_ERR(backend->mod_clk);
350 goto err_disable_bus_clk;
351 }
352 clk_prepare_enable(backend->mod_clk);
353
354 backend->ram_clk = devm_clk_get(dev, "ram");
355 if (IS_ERR(backend->ram_clk)) {
356 dev_err(dev, "Couldn't get the backend RAM clock\n");
357 ret = PTR_ERR(backend->ram_clk);
358 goto err_disable_mod_clk;
359 }
360 clk_prepare_enable(backend->ram_clk);
361
362 if (of_device_is_compatible(dev->of_node,
363 "allwinner,sun8i-a33-display-backend")) {
364 ret = sun4i_backend_init_sat(dev);
365 if (ret) {
366 dev_err(dev, "Couldn't init SAT resources\n");
367 goto err_disable_ram_clk;
368 }
369 }
370
371 /* Reset the registers */
372 for (i = 0x800; i < 0x1000; i += 4)
373 regmap_write(backend->regs, i, 0);
374
375 /* Disable registers autoloading */
376 regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
377 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
378
379 /* Enable the backend */
380 regmap_write(backend->regs, SUN4I_BACKEND_MODCTL_REG,
381 SUN4I_BACKEND_MODCTL_DEBE_EN |
382 SUN4I_BACKEND_MODCTL_START_CTL);
383
384 return 0;
385
386err_disable_ram_clk:
387 clk_disable_unprepare(backend->ram_clk);
388err_disable_mod_clk:
389 clk_disable_unprepare(backend->mod_clk);
390err_disable_bus_clk:
391 clk_disable_unprepare(backend->bus_clk);
392err_assert_reset:
393 reset_control_assert(backend->reset);
394 return ret;
395}
396
397static void sun4i_backend_unbind(struct device *dev, struct device *master,
398 void *data)
399{
400 struct sun4i_backend *backend = dev_get_drvdata(dev);
401
402 if (of_device_is_compatible(dev->of_node,
403 "allwinner,sun8i-a33-display-backend"))
404 sun4i_backend_free_sat(dev);
405
406 clk_disable_unprepare(backend->ram_clk);
407 clk_disable_unprepare(backend->mod_clk);
408 clk_disable_unprepare(backend->bus_clk);
409 reset_control_assert(backend->reset);
410}
411
412static const struct component_ops sun4i_backend_ops = {
413 .bind = sun4i_backend_bind,
414 .unbind = sun4i_backend_unbind,
415};
416
417static int sun4i_backend_probe(struct platform_device *pdev)
418{
419 return component_add(&pdev->dev, &sun4i_backend_ops);
420}
421
422static int sun4i_backend_remove(struct platform_device *pdev)
423{
424 component_del(&pdev->dev, &sun4i_backend_ops);
425
426 return 0;
427}
428
429static const struct of_device_id sun4i_backend_of_table[] = {
430 { .compatible = "allwinner,sun5i-a13-display-backend" },
431 { .compatible = "allwinner,sun6i-a31-display-backend" },
432 { .compatible = "allwinner,sun8i-a33-display-backend" },
433 { }
434};
435MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
436
437static struct platform_driver sun4i_backend_platform_driver = {
438 .probe = sun4i_backend_probe,
439 .remove = sun4i_backend_remove,
440 .driver = {
441 .name = "sun4i-backend",
442 .of_match_table = sun4i_backend_of_table,
443 },
444};
445module_platform_driver(sun4i_backend_platform_driver);
446
447MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
448MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
449MODULE_LICENSE("GPL");