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1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/export.h>
29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
35#include <linux/hardirq.h>
36#include <linux/platform_device.h>
37#include <linux/pm_runtime.h>
38#include <linux/sizes.h>
39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
42#include <linux/component.h>
43
44#include <video/omapdss.h>
45
46#include "dss.h"
47#include "dss_features.h"
48#include "dispc.h"
49
50/* DISPC */
51#define DISPC_SZ_REGS SZ_4K
52
53enum omap_burst_size {
54 BURST_SIZE_X2 = 0,
55 BURST_SIZE_X4 = 1,
56 BURST_SIZE_X8 = 2,
57};
58
59#define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
61
62#define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
64
65struct dispc_features {
66 u8 sw_start;
67 u8 fp_start;
68 u8 bp_start;
69 u16 sw_max;
70 u16 vp_max;
71 u16 hp_max;
72 u8 mgr_width_start;
73 u8 mgr_height_start;
74 u16 mgr_width_max;
75 u16 mgr_height_max;
76 unsigned long max_lcd_pclk;
77 unsigned long max_tv_pclk;
78 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
79 const struct omap_video_timings *mgr_timings,
80 u16 width, u16 height, u16 out_width, u16 out_height,
81 enum omap_color_mode color_mode, bool *five_taps,
82 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
83 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
84 unsigned long (*calc_core_clk) (unsigned long pclk,
85 u16 width, u16 height, u16 out_width, u16 out_height,
86 bool mem_to_mem);
87 u8 num_fifos;
88
89 /* swap GFX & WB fifos */
90 bool gfx_fifo_workaround:1;
91
92 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
93 bool no_framedone_tv:1;
94
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
96 bool mstandby_workaround:1;
97
98 bool set_max_preload:1;
99
100 /* PIXEL_INC is not added to the last pixel of a line */
101 bool last_pixel_inc_missing:1;
102
103 /* POL_FREQ has ALIGN bit */
104 bool supports_sync_align:1;
105
106 bool has_writeback:1;
107
108 bool supports_double_pixel:1;
109
110 /*
111 * Field order for VENC is different than HDMI. We should handle this in
112 * some intelligent manner, but as the SoCs have either HDMI or VENC,
113 * never both, we can just use this flag for now.
114 */
115 bool reverse_ilace_field_order:1;
116};
117
118#define DISPC_MAX_NR_FIFOS 5
119
120static struct {
121 struct platform_device *pdev;
122 void __iomem *base;
123
124 int irq;
125 irq_handler_t user_handler;
126 void *user_data;
127
128 unsigned long core_clk_rate;
129 unsigned long tv_pclk_rate;
130
131 u32 fifo_size[DISPC_MAX_NR_FIFOS];
132 /* maps which plane is using a fifo. fifo-id -> plane-id */
133 int fifo_assignment[DISPC_MAX_NR_FIFOS];
134
135 bool ctx_valid;
136 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
137
138 const struct dispc_features *feat;
139
140 bool is_enabled;
141
142 struct regmap *syscon_pol;
143 u32 syscon_pol_offset;
144
145 /* DISPC_CONTROL & DISPC_CONFIG lock*/
146 spinlock_t control_lock;
147} dispc;
148
149enum omap_color_component {
150 /* used for all color formats for OMAP3 and earlier
151 * and for RGB and Y color component on OMAP4
152 */
153 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
154 /* used for UV component for
155 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
156 * color formats on OMAP4
157 */
158 DISPC_COLOR_COMPONENT_UV = 1 << 1,
159};
160
161enum mgr_reg_fields {
162 DISPC_MGR_FLD_ENABLE,
163 DISPC_MGR_FLD_STNTFT,
164 DISPC_MGR_FLD_GO,
165 DISPC_MGR_FLD_TFTDATALINES,
166 DISPC_MGR_FLD_STALLMODE,
167 DISPC_MGR_FLD_TCKENABLE,
168 DISPC_MGR_FLD_TCKSELECTION,
169 DISPC_MGR_FLD_CPR,
170 DISPC_MGR_FLD_FIFOHANDCHECK,
171 /* used to maintain a count of the above fields */
172 DISPC_MGR_FLD_NUM,
173};
174
175struct dispc_reg_field {
176 u16 reg;
177 u8 high;
178 u8 low;
179};
180
181static const struct {
182 const char *name;
183 u32 vsync_irq;
184 u32 framedone_irq;
185 u32 sync_lost_irq;
186 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
187} mgr_desc[] = {
188 [OMAP_DSS_CHANNEL_LCD] = {
189 .name = "LCD",
190 .vsync_irq = DISPC_IRQ_VSYNC,
191 .framedone_irq = DISPC_IRQ_FRAMEDONE,
192 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
193 .reg_desc = {
194 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
195 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
196 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
197 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
198 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
199 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
200 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
201 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
202 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
203 },
204 },
205 [OMAP_DSS_CHANNEL_DIGIT] = {
206 .name = "DIGIT",
207 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
208 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
209 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
210 .reg_desc = {
211 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
212 [DISPC_MGR_FLD_STNTFT] = { },
213 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
214 [DISPC_MGR_FLD_TFTDATALINES] = { },
215 [DISPC_MGR_FLD_STALLMODE] = { },
216 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
217 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
218 [DISPC_MGR_FLD_CPR] = { },
219 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
220 },
221 },
222 [OMAP_DSS_CHANNEL_LCD2] = {
223 .name = "LCD2",
224 .vsync_irq = DISPC_IRQ_VSYNC2,
225 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
226 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
227 .reg_desc = {
228 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
229 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
230 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
231 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
232 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
233 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
234 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
235 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
236 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
237 },
238 },
239 [OMAP_DSS_CHANNEL_LCD3] = {
240 .name = "LCD3",
241 .vsync_irq = DISPC_IRQ_VSYNC3,
242 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
243 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
244 .reg_desc = {
245 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
246 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
247 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
248 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
249 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
250 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
251 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
252 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
253 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
254 },
255 },
256};
257
258struct color_conv_coef {
259 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
260 int full_range;
261};
262
263static unsigned long dispc_fclk_rate(void);
264static unsigned long dispc_core_clk_rate(void);
265static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
266static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
267
268static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
269static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
270
271static inline void dispc_write_reg(const u16 idx, u32 val)
272{
273 __raw_writel(val, dispc.base + idx);
274}
275
276static inline u32 dispc_read_reg(const u16 idx)
277{
278 return __raw_readl(dispc.base + idx);
279}
280
281static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
282{
283 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
284 return REG_GET(rfld.reg, rfld.high, rfld.low);
285}
286
287static void mgr_fld_write(enum omap_channel channel,
288 enum mgr_reg_fields regfld, int val) {
289 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
290 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
291 unsigned long flags;
292
293 if (need_lock)
294 spin_lock_irqsave(&dispc.control_lock, flags);
295
296 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
297
298 if (need_lock)
299 spin_unlock_irqrestore(&dispc.control_lock, flags);
300}
301
302#define SR(reg) \
303 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
304#define RR(reg) \
305 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
306
307static void dispc_save_context(void)
308{
309 int i, j;
310
311 DSSDBG("dispc_save_context\n");
312
313 SR(IRQENABLE);
314 SR(CONTROL);
315 SR(CONFIG);
316 SR(LINE_NUMBER);
317 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
318 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
319 SR(GLOBAL_ALPHA);
320 if (dss_has_feature(FEAT_MGR_LCD2)) {
321 SR(CONTROL2);
322 SR(CONFIG2);
323 }
324 if (dss_has_feature(FEAT_MGR_LCD3)) {
325 SR(CONTROL3);
326 SR(CONFIG3);
327 }
328
329 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
330 SR(DEFAULT_COLOR(i));
331 SR(TRANS_COLOR(i));
332 SR(SIZE_MGR(i));
333 if (i == OMAP_DSS_CHANNEL_DIGIT)
334 continue;
335 SR(TIMING_H(i));
336 SR(TIMING_V(i));
337 SR(POL_FREQ(i));
338 SR(DIVISORo(i));
339
340 SR(DATA_CYCLE1(i));
341 SR(DATA_CYCLE2(i));
342 SR(DATA_CYCLE3(i));
343
344 if (dss_has_feature(FEAT_CPR)) {
345 SR(CPR_COEF_R(i));
346 SR(CPR_COEF_G(i));
347 SR(CPR_COEF_B(i));
348 }
349 }
350
351 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
352 SR(OVL_BA0(i));
353 SR(OVL_BA1(i));
354 SR(OVL_POSITION(i));
355 SR(OVL_SIZE(i));
356 SR(OVL_ATTRIBUTES(i));
357 SR(OVL_FIFO_THRESHOLD(i));
358 SR(OVL_ROW_INC(i));
359 SR(OVL_PIXEL_INC(i));
360 if (dss_has_feature(FEAT_PRELOAD))
361 SR(OVL_PRELOAD(i));
362 if (i == OMAP_DSS_GFX) {
363 SR(OVL_WINDOW_SKIP(i));
364 SR(OVL_TABLE_BA(i));
365 continue;
366 }
367 SR(OVL_FIR(i));
368 SR(OVL_PICTURE_SIZE(i));
369 SR(OVL_ACCU0(i));
370 SR(OVL_ACCU1(i));
371
372 for (j = 0; j < 8; j++)
373 SR(OVL_FIR_COEF_H(i, j));
374
375 for (j = 0; j < 8; j++)
376 SR(OVL_FIR_COEF_HV(i, j));
377
378 for (j = 0; j < 5; j++)
379 SR(OVL_CONV_COEF(i, j));
380
381 if (dss_has_feature(FEAT_FIR_COEF_V)) {
382 for (j = 0; j < 8; j++)
383 SR(OVL_FIR_COEF_V(i, j));
384 }
385
386 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
387 SR(OVL_BA0_UV(i));
388 SR(OVL_BA1_UV(i));
389 SR(OVL_FIR2(i));
390 SR(OVL_ACCU2_0(i));
391 SR(OVL_ACCU2_1(i));
392
393 for (j = 0; j < 8; j++)
394 SR(OVL_FIR_COEF_H2(i, j));
395
396 for (j = 0; j < 8; j++)
397 SR(OVL_FIR_COEF_HV2(i, j));
398
399 for (j = 0; j < 8; j++)
400 SR(OVL_FIR_COEF_V2(i, j));
401 }
402 if (dss_has_feature(FEAT_ATTR2))
403 SR(OVL_ATTRIBUTES2(i));
404 }
405
406 if (dss_has_feature(FEAT_CORE_CLK_DIV))
407 SR(DIVISOR);
408
409 dispc.ctx_valid = true;
410
411 DSSDBG("context saved\n");
412}
413
414static void dispc_restore_context(void)
415{
416 int i, j;
417
418 DSSDBG("dispc_restore_context\n");
419
420 if (!dispc.ctx_valid)
421 return;
422
423 /*RR(IRQENABLE);*/
424 /*RR(CONTROL);*/
425 RR(CONFIG);
426 RR(LINE_NUMBER);
427 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
428 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
429 RR(GLOBAL_ALPHA);
430 if (dss_has_feature(FEAT_MGR_LCD2))
431 RR(CONFIG2);
432 if (dss_has_feature(FEAT_MGR_LCD3))
433 RR(CONFIG3);
434
435 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
436 RR(DEFAULT_COLOR(i));
437 RR(TRANS_COLOR(i));
438 RR(SIZE_MGR(i));
439 if (i == OMAP_DSS_CHANNEL_DIGIT)
440 continue;
441 RR(TIMING_H(i));
442 RR(TIMING_V(i));
443 RR(POL_FREQ(i));
444 RR(DIVISORo(i));
445
446 RR(DATA_CYCLE1(i));
447 RR(DATA_CYCLE2(i));
448 RR(DATA_CYCLE3(i));
449
450 if (dss_has_feature(FEAT_CPR)) {
451 RR(CPR_COEF_R(i));
452 RR(CPR_COEF_G(i));
453 RR(CPR_COEF_B(i));
454 }
455 }
456
457 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
458 RR(OVL_BA0(i));
459 RR(OVL_BA1(i));
460 RR(OVL_POSITION(i));
461 RR(OVL_SIZE(i));
462 RR(OVL_ATTRIBUTES(i));
463 RR(OVL_FIFO_THRESHOLD(i));
464 RR(OVL_ROW_INC(i));
465 RR(OVL_PIXEL_INC(i));
466 if (dss_has_feature(FEAT_PRELOAD))
467 RR(OVL_PRELOAD(i));
468 if (i == OMAP_DSS_GFX) {
469 RR(OVL_WINDOW_SKIP(i));
470 RR(OVL_TABLE_BA(i));
471 continue;
472 }
473 RR(OVL_FIR(i));
474 RR(OVL_PICTURE_SIZE(i));
475 RR(OVL_ACCU0(i));
476 RR(OVL_ACCU1(i));
477
478 for (j = 0; j < 8; j++)
479 RR(OVL_FIR_COEF_H(i, j));
480
481 for (j = 0; j < 8; j++)
482 RR(OVL_FIR_COEF_HV(i, j));
483
484 for (j = 0; j < 5; j++)
485 RR(OVL_CONV_COEF(i, j));
486
487 if (dss_has_feature(FEAT_FIR_COEF_V)) {
488 for (j = 0; j < 8; j++)
489 RR(OVL_FIR_COEF_V(i, j));
490 }
491
492 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
493 RR(OVL_BA0_UV(i));
494 RR(OVL_BA1_UV(i));
495 RR(OVL_FIR2(i));
496 RR(OVL_ACCU2_0(i));
497 RR(OVL_ACCU2_1(i));
498
499 for (j = 0; j < 8; j++)
500 RR(OVL_FIR_COEF_H2(i, j));
501
502 for (j = 0; j < 8; j++)
503 RR(OVL_FIR_COEF_HV2(i, j));
504
505 for (j = 0; j < 8; j++)
506 RR(OVL_FIR_COEF_V2(i, j));
507 }
508 if (dss_has_feature(FEAT_ATTR2))
509 RR(OVL_ATTRIBUTES2(i));
510 }
511
512 if (dss_has_feature(FEAT_CORE_CLK_DIV))
513 RR(DIVISOR);
514
515 /* enable last, because LCD & DIGIT enable are here */
516 RR(CONTROL);
517 if (dss_has_feature(FEAT_MGR_LCD2))
518 RR(CONTROL2);
519 if (dss_has_feature(FEAT_MGR_LCD3))
520 RR(CONTROL3);
521 /* clear spurious SYNC_LOST_DIGIT interrupts */
522 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
523
524 /*
525 * enable last so IRQs won't trigger before
526 * the context is fully restored
527 */
528 RR(IRQENABLE);
529
530 DSSDBG("context restored\n");
531}
532
533#undef SR
534#undef RR
535
536int dispc_runtime_get(void)
537{
538 int r;
539
540 DSSDBG("dispc_runtime_get\n");
541
542 r = pm_runtime_get_sync(&dispc.pdev->dev);
543 WARN_ON(r < 0);
544 return r < 0 ? r : 0;
545}
546EXPORT_SYMBOL(dispc_runtime_get);
547
548void dispc_runtime_put(void)
549{
550 int r;
551
552 DSSDBG("dispc_runtime_put\n");
553
554 r = pm_runtime_put_sync(&dispc.pdev->dev);
555 WARN_ON(r < 0 && r != -ENOSYS);
556}
557EXPORT_SYMBOL(dispc_runtime_put);
558
559u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
560{
561 return mgr_desc[channel].vsync_irq;
562}
563EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
564
565u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
566{
567 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
568 return 0;
569
570 return mgr_desc[channel].framedone_irq;
571}
572EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
573
574u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
575{
576 return mgr_desc[channel].sync_lost_irq;
577}
578EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
579
580u32 dispc_wb_get_framedone_irq(void)
581{
582 return DISPC_IRQ_FRAMEDONEWB;
583}
584
585bool dispc_mgr_go_busy(enum omap_channel channel)
586{
587 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
588}
589EXPORT_SYMBOL(dispc_mgr_go_busy);
590
591void dispc_mgr_go(enum omap_channel channel)
592{
593 WARN_ON(!dispc_mgr_is_enabled(channel));
594 WARN_ON(dispc_mgr_go_busy(channel));
595
596 DSSDBG("GO %s\n", mgr_desc[channel].name);
597
598 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
599}
600EXPORT_SYMBOL(dispc_mgr_go);
601
602bool dispc_wb_go_busy(void)
603{
604 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
605}
606
607void dispc_wb_go(void)
608{
609 enum omap_plane plane = OMAP_DSS_WB;
610 bool enable, go;
611
612 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
613
614 if (!enable)
615 return;
616
617 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
618 if (go) {
619 DSSERR("GO bit not down for WB\n");
620 return;
621 }
622
623 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
624}
625
626static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
627{
628 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
629}
630
631static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
632{
633 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
634}
635
636static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
637{
638 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
639}
640
641static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
642{
643 BUG_ON(plane == OMAP_DSS_GFX);
644
645 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
646}
647
648static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
649 u32 value)
650{
651 BUG_ON(plane == OMAP_DSS_GFX);
652
653 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
654}
655
656static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
657{
658 BUG_ON(plane == OMAP_DSS_GFX);
659
660 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
661}
662
663static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
664 int fir_vinc, int five_taps,
665 enum omap_color_component color_comp)
666{
667 const struct dispc_coef *h_coef, *v_coef;
668 int i;
669
670 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
671 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
672
673 for (i = 0; i < 8; i++) {
674 u32 h, hv;
675
676 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
677 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
678 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
679 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
680 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
681 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
682 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
683 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
684
685 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
686 dispc_ovl_write_firh_reg(plane, i, h);
687 dispc_ovl_write_firhv_reg(plane, i, hv);
688 } else {
689 dispc_ovl_write_firh2_reg(plane, i, h);
690 dispc_ovl_write_firhv2_reg(plane, i, hv);
691 }
692
693 }
694
695 if (five_taps) {
696 for (i = 0; i < 8; i++) {
697 u32 v;
698 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
699 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
700 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
701 dispc_ovl_write_firv_reg(plane, i, v);
702 else
703 dispc_ovl_write_firv2_reg(plane, i, v);
704 }
705 }
706}
707
708
709static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
710 const struct color_conv_coef *ct)
711{
712#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
713
714 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
715 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
716 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
717 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
718 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
719
720 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
721
722#undef CVAL
723}
724
725static void dispc_setup_color_conv_coef(void)
726{
727 int i;
728 int num_ovl = dss_feat_get_num_ovls();
729 const struct color_conv_coef ctbl_bt601_5_ovl = {
730 /* YUV -> RGB */
731 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
732 };
733 const struct color_conv_coef ctbl_bt601_5_wb = {
734 /* RGB -> YUV */
735 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
736 };
737
738 for (i = 1; i < num_ovl; i++)
739 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
740
741 if (dispc.feat->has_writeback)
742 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
743}
744
745static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
746{
747 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
748}
749
750static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
751{
752 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
753}
754
755static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
756{
757 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
758}
759
760static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
761{
762 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
763}
764
765static void dispc_ovl_set_pos(enum omap_plane plane,
766 enum omap_overlay_caps caps, int x, int y)
767{
768 u32 val;
769
770 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
771 return;
772
773 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
774
775 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
776}
777
778static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
779 int height)
780{
781 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
782
783 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
784 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
785 else
786 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
787}
788
789static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
790 int height)
791{
792 u32 val;
793
794 BUG_ON(plane == OMAP_DSS_GFX);
795
796 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
797
798 if (plane == OMAP_DSS_WB)
799 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
800 else
801 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
802}
803
804static void dispc_ovl_set_zorder(enum omap_plane plane,
805 enum omap_overlay_caps caps, u8 zorder)
806{
807 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
808 return;
809
810 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
811}
812
813static void dispc_ovl_enable_zorder_planes(void)
814{
815 int i;
816
817 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
818 return;
819
820 for (i = 0; i < dss_feat_get_num_ovls(); i++)
821 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
822}
823
824static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
825 enum omap_overlay_caps caps, bool enable)
826{
827 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
828 return;
829
830 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
831}
832
833static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
834 enum omap_overlay_caps caps, u8 global_alpha)
835{
836 static const unsigned shifts[] = { 0, 8, 16, 24, };
837 int shift;
838
839 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
840 return;
841
842 shift = shifts[plane];
843 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
844}
845
846static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
847{
848 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
849}
850
851static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
852{
853 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
854}
855
856static void dispc_ovl_set_color_mode(enum omap_plane plane,
857 enum omap_color_mode color_mode)
858{
859 u32 m = 0;
860 if (plane != OMAP_DSS_GFX) {
861 switch (color_mode) {
862 case OMAP_DSS_COLOR_NV12:
863 m = 0x0; break;
864 case OMAP_DSS_COLOR_RGBX16:
865 m = 0x1; break;
866 case OMAP_DSS_COLOR_RGBA16:
867 m = 0x2; break;
868 case OMAP_DSS_COLOR_RGB12U:
869 m = 0x4; break;
870 case OMAP_DSS_COLOR_ARGB16:
871 m = 0x5; break;
872 case OMAP_DSS_COLOR_RGB16:
873 m = 0x6; break;
874 case OMAP_DSS_COLOR_ARGB16_1555:
875 m = 0x7; break;
876 case OMAP_DSS_COLOR_RGB24U:
877 m = 0x8; break;
878 case OMAP_DSS_COLOR_RGB24P:
879 m = 0x9; break;
880 case OMAP_DSS_COLOR_YUV2:
881 m = 0xa; break;
882 case OMAP_DSS_COLOR_UYVY:
883 m = 0xb; break;
884 case OMAP_DSS_COLOR_ARGB32:
885 m = 0xc; break;
886 case OMAP_DSS_COLOR_RGBA32:
887 m = 0xd; break;
888 case OMAP_DSS_COLOR_RGBX32:
889 m = 0xe; break;
890 case OMAP_DSS_COLOR_XRGB16_1555:
891 m = 0xf; break;
892 default:
893 BUG(); return;
894 }
895 } else {
896 switch (color_mode) {
897 case OMAP_DSS_COLOR_CLUT1:
898 m = 0x0; break;
899 case OMAP_DSS_COLOR_CLUT2:
900 m = 0x1; break;
901 case OMAP_DSS_COLOR_CLUT4:
902 m = 0x2; break;
903 case OMAP_DSS_COLOR_CLUT8:
904 m = 0x3; break;
905 case OMAP_DSS_COLOR_RGB12U:
906 m = 0x4; break;
907 case OMAP_DSS_COLOR_ARGB16:
908 m = 0x5; break;
909 case OMAP_DSS_COLOR_RGB16:
910 m = 0x6; break;
911 case OMAP_DSS_COLOR_ARGB16_1555:
912 m = 0x7; break;
913 case OMAP_DSS_COLOR_RGB24U:
914 m = 0x8; break;
915 case OMAP_DSS_COLOR_RGB24P:
916 m = 0x9; break;
917 case OMAP_DSS_COLOR_RGBX16:
918 m = 0xa; break;
919 case OMAP_DSS_COLOR_RGBA16:
920 m = 0xb; break;
921 case OMAP_DSS_COLOR_ARGB32:
922 m = 0xc; break;
923 case OMAP_DSS_COLOR_RGBA32:
924 m = 0xd; break;
925 case OMAP_DSS_COLOR_RGBX32:
926 m = 0xe; break;
927 case OMAP_DSS_COLOR_XRGB16_1555:
928 m = 0xf; break;
929 default:
930 BUG(); return;
931 }
932 }
933
934 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
935}
936
937static void dispc_ovl_configure_burst_type(enum omap_plane plane,
938 enum omap_dss_rotation_type rotation_type)
939{
940 if (dss_has_feature(FEAT_BURST_2D) == 0)
941 return;
942
943 if (rotation_type == OMAP_DSS_ROT_TILER)
944 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
945 else
946 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
947}
948
949void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
950{
951 int shift;
952 u32 val;
953 int chan = 0, chan2 = 0;
954
955 switch (plane) {
956 case OMAP_DSS_GFX:
957 shift = 8;
958 break;
959 case OMAP_DSS_VIDEO1:
960 case OMAP_DSS_VIDEO2:
961 case OMAP_DSS_VIDEO3:
962 shift = 16;
963 break;
964 default:
965 BUG();
966 return;
967 }
968
969 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
970 if (dss_has_feature(FEAT_MGR_LCD2)) {
971 switch (channel) {
972 case OMAP_DSS_CHANNEL_LCD:
973 chan = 0;
974 chan2 = 0;
975 break;
976 case OMAP_DSS_CHANNEL_DIGIT:
977 chan = 1;
978 chan2 = 0;
979 break;
980 case OMAP_DSS_CHANNEL_LCD2:
981 chan = 0;
982 chan2 = 1;
983 break;
984 case OMAP_DSS_CHANNEL_LCD3:
985 if (dss_has_feature(FEAT_MGR_LCD3)) {
986 chan = 0;
987 chan2 = 2;
988 } else {
989 BUG();
990 return;
991 }
992 break;
993 case OMAP_DSS_CHANNEL_WB:
994 chan = 0;
995 chan2 = 3;
996 break;
997 default:
998 BUG();
999 return;
1000 }
1001
1002 val = FLD_MOD(val, chan, shift, shift);
1003 val = FLD_MOD(val, chan2, 31, 30);
1004 } else {
1005 val = FLD_MOD(val, channel, shift, shift);
1006 }
1007 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1008}
1009EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1010
1011static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1012{
1013 int shift;
1014 u32 val;
1015
1016 switch (plane) {
1017 case OMAP_DSS_GFX:
1018 shift = 8;
1019 break;
1020 case OMAP_DSS_VIDEO1:
1021 case OMAP_DSS_VIDEO2:
1022 case OMAP_DSS_VIDEO3:
1023 shift = 16;
1024 break;
1025 default:
1026 BUG();
1027 return 0;
1028 }
1029
1030 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1031
1032 if (FLD_GET(val, shift, shift) == 1)
1033 return OMAP_DSS_CHANNEL_DIGIT;
1034
1035 if (!dss_has_feature(FEAT_MGR_LCD2))
1036 return OMAP_DSS_CHANNEL_LCD;
1037
1038 switch (FLD_GET(val, 31, 30)) {
1039 case 0:
1040 default:
1041 return OMAP_DSS_CHANNEL_LCD;
1042 case 1:
1043 return OMAP_DSS_CHANNEL_LCD2;
1044 case 2:
1045 return OMAP_DSS_CHANNEL_LCD3;
1046 case 3:
1047 return OMAP_DSS_CHANNEL_WB;
1048 }
1049}
1050
1051void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1052{
1053 enum omap_plane plane = OMAP_DSS_WB;
1054
1055 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1056}
1057
1058static void dispc_ovl_set_burst_size(enum omap_plane plane,
1059 enum omap_burst_size burst_size)
1060{
1061 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1062 int shift;
1063
1064 shift = shifts[plane];
1065 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1066}
1067
1068static void dispc_configure_burst_sizes(void)
1069{
1070 int i;
1071 const int burst_size = BURST_SIZE_X8;
1072
1073 /* Configure burst size always to maximum size */
1074 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1075 dispc_ovl_set_burst_size(i, burst_size);
1076 if (dispc.feat->has_writeback)
1077 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1078}
1079
1080static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1081{
1082 unsigned unit = dss_feat_get_burst_size_unit();
1083 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1084 return unit * 8;
1085}
1086
1087void dispc_enable_gamma_table(bool enable)
1088{
1089 /*
1090 * This is partially implemented to support only disabling of
1091 * the gamma table.
1092 */
1093 if (enable) {
1094 DSSWARN("Gamma table enabling for TV not yet supported");
1095 return;
1096 }
1097
1098 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1099}
1100
1101static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1102{
1103 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1104 return;
1105
1106 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1107}
1108
1109static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1110 const struct omap_dss_cpr_coefs *coefs)
1111{
1112 u32 coef_r, coef_g, coef_b;
1113
1114 if (!dss_mgr_is_lcd(channel))
1115 return;
1116
1117 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1118 FLD_VAL(coefs->rb, 9, 0);
1119 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1120 FLD_VAL(coefs->gb, 9, 0);
1121 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1122 FLD_VAL(coefs->bb, 9, 0);
1123
1124 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1125 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1126 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1127}
1128
1129static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1130{
1131 u32 val;
1132
1133 BUG_ON(plane == OMAP_DSS_GFX);
1134
1135 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1136 val = FLD_MOD(val, enable, 9, 9);
1137 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1138}
1139
1140static void dispc_ovl_enable_replication(enum omap_plane plane,
1141 enum omap_overlay_caps caps, bool enable)
1142{
1143 static const unsigned shifts[] = { 5, 10, 10, 10 };
1144 int shift;
1145
1146 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1147 return;
1148
1149 shift = shifts[plane];
1150 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1151}
1152
1153static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1154 u16 height)
1155{
1156 u32 val;
1157
1158 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1159 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1160
1161 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1162}
1163
1164static void dispc_init_fifos(void)
1165{
1166 u32 size;
1167 int fifo;
1168 u8 start, end;
1169 u32 unit;
1170 int i;
1171
1172 unit = dss_feat_get_buffer_size_unit();
1173
1174 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1175
1176 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1177 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1178 size *= unit;
1179 dispc.fifo_size[fifo] = size;
1180
1181 /*
1182 * By default fifos are mapped directly to overlays, fifo 0 to
1183 * ovl 0, fifo 1 to ovl 1, etc.
1184 */
1185 dispc.fifo_assignment[fifo] = fifo;
1186 }
1187
1188 /*
1189 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1190 * causes problems with certain use cases, like using the tiler in 2D
1191 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1192 * giving GFX plane a larger fifo. WB but should work fine with a
1193 * smaller fifo.
1194 */
1195 if (dispc.feat->gfx_fifo_workaround) {
1196 u32 v;
1197
1198 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1199
1200 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1201 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1202 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1203 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1204
1205 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1206
1207 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1208 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1209 }
1210
1211 /*
1212 * Setup default fifo thresholds.
1213 */
1214 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1215 u32 low, high;
1216 const bool use_fifomerge = false;
1217 const bool manual_update = false;
1218
1219 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1220 use_fifomerge, manual_update);
1221
1222 dispc_ovl_set_fifo_threshold(i, low, high);
1223 }
1224
1225 if (dispc.feat->has_writeback) {
1226 u32 low, high;
1227 const bool use_fifomerge = false;
1228 const bool manual_update = false;
1229
1230 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1231 use_fifomerge, manual_update);
1232
1233 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1234 }
1235}
1236
1237static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1238{
1239 int fifo;
1240 u32 size = 0;
1241
1242 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1243 if (dispc.fifo_assignment[fifo] == plane)
1244 size += dispc.fifo_size[fifo];
1245 }
1246
1247 return size;
1248}
1249
1250void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1251{
1252 u8 hi_start, hi_end, lo_start, lo_end;
1253 u32 unit;
1254
1255 unit = dss_feat_get_buffer_size_unit();
1256
1257 WARN_ON(low % unit != 0);
1258 WARN_ON(high % unit != 0);
1259
1260 low /= unit;
1261 high /= unit;
1262
1263 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1264 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1265
1266 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1267 plane,
1268 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1269 lo_start, lo_end) * unit,
1270 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1271 hi_start, hi_end) * unit,
1272 low * unit, high * unit);
1273
1274 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1275 FLD_VAL(high, hi_start, hi_end) |
1276 FLD_VAL(low, lo_start, lo_end));
1277
1278 /*
1279 * configure the preload to the pipeline's high threhold, if HT it's too
1280 * large for the preload field, set the threshold to the maximum value
1281 * that can be held by the preload register
1282 */
1283 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1284 plane != OMAP_DSS_WB)
1285 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1286}
1287
1288void dispc_enable_fifomerge(bool enable)
1289{
1290 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1291 WARN_ON(enable);
1292 return;
1293 }
1294
1295 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1296 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1297}
1298
1299void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1300 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1301 bool manual_update)
1302{
1303 /*
1304 * All sizes are in bytes. Both the buffer and burst are made of
1305 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1306 */
1307
1308 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1309 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1310 int i;
1311
1312 burst_size = dispc_ovl_get_burst_size(plane);
1313 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1314
1315 if (use_fifomerge) {
1316 total_fifo_size = 0;
1317 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1318 total_fifo_size += dispc_ovl_get_fifo_size(i);
1319 } else {
1320 total_fifo_size = ovl_fifo_size;
1321 }
1322
1323 /*
1324 * We use the same low threshold for both fifomerge and non-fifomerge
1325 * cases, but for fifomerge we calculate the high threshold using the
1326 * combined fifo size
1327 */
1328
1329 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1330 *fifo_low = ovl_fifo_size - burst_size * 2;
1331 *fifo_high = total_fifo_size - burst_size;
1332 } else if (plane == OMAP_DSS_WB) {
1333 /*
1334 * Most optimal configuration for writeback is to push out data
1335 * to the interconnect the moment writeback pushes enough pixels
1336 * in the FIFO to form a burst
1337 */
1338 *fifo_low = 0;
1339 *fifo_high = burst_size;
1340 } else {
1341 *fifo_low = ovl_fifo_size - burst_size;
1342 *fifo_high = total_fifo_size - buf_unit;
1343 }
1344}
1345
1346static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1347{
1348 int bit;
1349
1350 if (plane == OMAP_DSS_GFX)
1351 bit = 14;
1352 else
1353 bit = 23;
1354
1355 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1356}
1357
1358static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1359 int low, int high)
1360{
1361 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1362 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1363}
1364
1365static void dispc_init_mflag(void)
1366{
1367 int i;
1368
1369 /*
1370 * HACK: NV12 color format and MFLAG seem to have problems working
1371 * together: using two displays, and having an NV12 overlay on one of
1372 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1373 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1374 * remove the errors, but there doesn't seem to be a clear logic on
1375 * which values work and which not.
1376 *
1377 * As a work-around, set force MFLAG to always on.
1378 */
1379 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1380 (1 << 0) | /* MFLAG_CTRL = force always on */
1381 (0 << 2)); /* MFLAG_START = disable */
1382
1383 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1384 u32 size = dispc_ovl_get_fifo_size(i);
1385 u32 unit = dss_feat_get_buffer_size_unit();
1386 u32 low, high;
1387
1388 dispc_ovl_set_mflag(i, true);
1389
1390 /*
1391 * Simulation team suggests below thesholds:
1392 * HT = fifosize * 5 / 8;
1393 * LT = fifosize * 4 / 8;
1394 */
1395
1396 low = size * 4 / 8 / unit;
1397 high = size * 5 / 8 / unit;
1398
1399 dispc_ovl_set_mflag_threshold(i, low, high);
1400 }
1401
1402 if (dispc.feat->has_writeback) {
1403 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1404 u32 unit = dss_feat_get_buffer_size_unit();
1405 u32 low, high;
1406
1407 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1408
1409 /*
1410 * Simulation team suggests below thesholds:
1411 * HT = fifosize * 5 / 8;
1412 * LT = fifosize * 4 / 8;
1413 */
1414
1415 low = size * 4 / 8 / unit;
1416 high = size * 5 / 8 / unit;
1417
1418 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1419 }
1420}
1421
1422static void dispc_ovl_set_fir(enum omap_plane plane,
1423 int hinc, int vinc,
1424 enum omap_color_component color_comp)
1425{
1426 u32 val;
1427
1428 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1429 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1430
1431 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1432 &hinc_start, &hinc_end);
1433 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1434 &vinc_start, &vinc_end);
1435 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1436 FLD_VAL(hinc, hinc_start, hinc_end);
1437
1438 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1439 } else {
1440 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1441 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1442 }
1443}
1444
1445static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1446{
1447 u32 val;
1448 u8 hor_start, hor_end, vert_start, vert_end;
1449
1450 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1451 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1452
1453 val = FLD_VAL(vaccu, vert_start, vert_end) |
1454 FLD_VAL(haccu, hor_start, hor_end);
1455
1456 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1457}
1458
1459static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1460{
1461 u32 val;
1462 u8 hor_start, hor_end, vert_start, vert_end;
1463
1464 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1465 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1466
1467 val = FLD_VAL(vaccu, vert_start, vert_end) |
1468 FLD_VAL(haccu, hor_start, hor_end);
1469
1470 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1471}
1472
1473static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1474 int vaccu)
1475{
1476 u32 val;
1477
1478 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1479 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1480}
1481
1482static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1483 int vaccu)
1484{
1485 u32 val;
1486
1487 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1488 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1489}
1490
1491static void dispc_ovl_set_scale_param(enum omap_plane plane,
1492 u16 orig_width, u16 orig_height,
1493 u16 out_width, u16 out_height,
1494 bool five_taps, u8 rotation,
1495 enum omap_color_component color_comp)
1496{
1497 int fir_hinc, fir_vinc;
1498
1499 fir_hinc = 1024 * orig_width / out_width;
1500 fir_vinc = 1024 * orig_height / out_height;
1501
1502 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1503 color_comp);
1504 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1505}
1506
1507static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1508 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1509 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1510{
1511 int h_accu2_0, h_accu2_1;
1512 int v_accu2_0, v_accu2_1;
1513 int chroma_hinc, chroma_vinc;
1514 int idx;
1515
1516 struct accu {
1517 s8 h0_m, h0_n;
1518 s8 h1_m, h1_n;
1519 s8 v0_m, v0_n;
1520 s8 v1_m, v1_n;
1521 };
1522
1523 const struct accu *accu_table;
1524 const struct accu *accu_val;
1525
1526 static const struct accu accu_nv12[4] = {
1527 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1528 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1529 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1530 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1531 };
1532
1533 static const struct accu accu_nv12_ilace[4] = {
1534 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1535 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1536 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1537 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1538 };
1539
1540 static const struct accu accu_yuv[4] = {
1541 { 0, 1, 0, 1, 0, 1, 0, 1 },
1542 { 0, 1, 0, 1, 0, 1, 0, 1 },
1543 { -1, 1, 0, 1, 0, 1, 0, 1 },
1544 { 0, 1, 0, 1, -1, 1, 0, 1 },
1545 };
1546
1547 switch (rotation) {
1548 case OMAP_DSS_ROT_0:
1549 idx = 0;
1550 break;
1551 case OMAP_DSS_ROT_90:
1552 idx = 1;
1553 break;
1554 case OMAP_DSS_ROT_180:
1555 idx = 2;
1556 break;
1557 case OMAP_DSS_ROT_270:
1558 idx = 3;
1559 break;
1560 default:
1561 BUG();
1562 return;
1563 }
1564
1565 switch (color_mode) {
1566 case OMAP_DSS_COLOR_NV12:
1567 if (ilace)
1568 accu_table = accu_nv12_ilace;
1569 else
1570 accu_table = accu_nv12;
1571 break;
1572 case OMAP_DSS_COLOR_YUV2:
1573 case OMAP_DSS_COLOR_UYVY:
1574 accu_table = accu_yuv;
1575 break;
1576 default:
1577 BUG();
1578 return;
1579 }
1580
1581 accu_val = &accu_table[idx];
1582
1583 chroma_hinc = 1024 * orig_width / out_width;
1584 chroma_vinc = 1024 * orig_height / out_height;
1585
1586 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1587 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1588 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1589 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1590
1591 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1592 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1593}
1594
1595static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1596 u16 orig_width, u16 orig_height,
1597 u16 out_width, u16 out_height,
1598 bool ilace, bool five_taps,
1599 bool fieldmode, enum omap_color_mode color_mode,
1600 u8 rotation)
1601{
1602 int accu0 = 0;
1603 int accu1 = 0;
1604 u32 l;
1605
1606 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1607 out_width, out_height, five_taps,
1608 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1609 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1610
1611 /* RESIZEENABLE and VERTICALTAPS */
1612 l &= ~((0x3 << 5) | (0x1 << 21));
1613 l |= (orig_width != out_width) ? (1 << 5) : 0;
1614 l |= (orig_height != out_height) ? (1 << 6) : 0;
1615 l |= five_taps ? (1 << 21) : 0;
1616
1617 /* VRESIZECONF and HRESIZECONF */
1618 if (dss_has_feature(FEAT_RESIZECONF)) {
1619 l &= ~(0x3 << 7);
1620 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1621 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1622 }
1623
1624 /* LINEBUFFERSPLIT */
1625 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1626 l &= ~(0x1 << 22);
1627 l |= five_taps ? (1 << 22) : 0;
1628 }
1629
1630 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1631
1632 /*
1633 * field 0 = even field = bottom field
1634 * field 1 = odd field = top field
1635 */
1636 if (ilace && !fieldmode) {
1637 accu1 = 0;
1638 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1639 if (accu0 >= 1024/2) {
1640 accu1 = 1024/2;
1641 accu0 -= accu1;
1642 }
1643 }
1644
1645 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1646 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1647}
1648
1649static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1650 u16 orig_width, u16 orig_height,
1651 u16 out_width, u16 out_height,
1652 bool ilace, bool five_taps,
1653 bool fieldmode, enum omap_color_mode color_mode,
1654 u8 rotation)
1655{
1656 int scale_x = out_width != orig_width;
1657 int scale_y = out_height != orig_height;
1658 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1659
1660 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1661 return;
1662 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1663 color_mode != OMAP_DSS_COLOR_UYVY &&
1664 color_mode != OMAP_DSS_COLOR_NV12)) {
1665 /* reset chroma resampling for RGB formats */
1666 if (plane != OMAP_DSS_WB)
1667 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1668 return;
1669 }
1670
1671 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1672 out_height, ilace, color_mode, rotation);
1673
1674 switch (color_mode) {
1675 case OMAP_DSS_COLOR_NV12:
1676 if (chroma_upscale) {
1677 /* UV is subsampled by 2 horizontally and vertically */
1678 orig_height >>= 1;
1679 orig_width >>= 1;
1680 } else {
1681 /* UV is downsampled by 2 horizontally and vertically */
1682 orig_height <<= 1;
1683 orig_width <<= 1;
1684 }
1685
1686 break;
1687 case OMAP_DSS_COLOR_YUV2:
1688 case OMAP_DSS_COLOR_UYVY:
1689 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1690 if (rotation == OMAP_DSS_ROT_0 ||
1691 rotation == OMAP_DSS_ROT_180) {
1692 if (chroma_upscale)
1693 /* UV is subsampled by 2 horizontally */
1694 orig_width >>= 1;
1695 else
1696 /* UV is downsampled by 2 horizontally */
1697 orig_width <<= 1;
1698 }
1699
1700 /* must use FIR for YUV422 if rotated */
1701 if (rotation != OMAP_DSS_ROT_0)
1702 scale_x = scale_y = true;
1703
1704 break;
1705 default:
1706 BUG();
1707 return;
1708 }
1709
1710 if (out_width != orig_width)
1711 scale_x = true;
1712 if (out_height != orig_height)
1713 scale_y = true;
1714
1715 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1716 out_width, out_height, five_taps,
1717 rotation, DISPC_COLOR_COMPONENT_UV);
1718
1719 if (plane != OMAP_DSS_WB)
1720 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1721 (scale_x || scale_y) ? 1 : 0, 8, 8);
1722
1723 /* set H scaling */
1724 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1725 /* set V scaling */
1726 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1727}
1728
1729static void dispc_ovl_set_scaling(enum omap_plane plane,
1730 u16 orig_width, u16 orig_height,
1731 u16 out_width, u16 out_height,
1732 bool ilace, bool five_taps,
1733 bool fieldmode, enum omap_color_mode color_mode,
1734 u8 rotation)
1735{
1736 BUG_ON(plane == OMAP_DSS_GFX);
1737
1738 dispc_ovl_set_scaling_common(plane,
1739 orig_width, orig_height,
1740 out_width, out_height,
1741 ilace, five_taps,
1742 fieldmode, color_mode,
1743 rotation);
1744
1745 dispc_ovl_set_scaling_uv(plane,
1746 orig_width, orig_height,
1747 out_width, out_height,
1748 ilace, five_taps,
1749 fieldmode, color_mode,
1750 rotation);
1751}
1752
1753static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1754 enum omap_dss_rotation_type rotation_type,
1755 bool mirroring, enum omap_color_mode color_mode)
1756{
1757 bool row_repeat = false;
1758 int vidrot = 0;
1759
1760 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1761 color_mode == OMAP_DSS_COLOR_UYVY) {
1762
1763 if (mirroring) {
1764 switch (rotation) {
1765 case OMAP_DSS_ROT_0:
1766 vidrot = 2;
1767 break;
1768 case OMAP_DSS_ROT_90:
1769 vidrot = 1;
1770 break;
1771 case OMAP_DSS_ROT_180:
1772 vidrot = 0;
1773 break;
1774 case OMAP_DSS_ROT_270:
1775 vidrot = 3;
1776 break;
1777 }
1778 } else {
1779 switch (rotation) {
1780 case OMAP_DSS_ROT_0:
1781 vidrot = 0;
1782 break;
1783 case OMAP_DSS_ROT_90:
1784 vidrot = 1;
1785 break;
1786 case OMAP_DSS_ROT_180:
1787 vidrot = 2;
1788 break;
1789 case OMAP_DSS_ROT_270:
1790 vidrot = 3;
1791 break;
1792 }
1793 }
1794
1795 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1796 row_repeat = true;
1797 else
1798 row_repeat = false;
1799 }
1800
1801 /*
1802 * OMAP4/5 Errata i631:
1803 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1804 * rows beyond the framebuffer, which may cause OCP error.
1805 */
1806 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1807 rotation_type != OMAP_DSS_ROT_TILER)
1808 vidrot = 1;
1809
1810 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1811 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1812 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1813 row_repeat ? 1 : 0, 18, 18);
1814
1815 if (color_mode == OMAP_DSS_COLOR_NV12) {
1816 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1817 (rotation == OMAP_DSS_ROT_0 ||
1818 rotation == OMAP_DSS_ROT_180);
1819 /* DOUBLESTRIDE */
1820 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1821 }
1822
1823}
1824
1825static int color_mode_to_bpp(enum omap_color_mode color_mode)
1826{
1827 switch (color_mode) {
1828 case OMAP_DSS_COLOR_CLUT1:
1829 return 1;
1830 case OMAP_DSS_COLOR_CLUT2:
1831 return 2;
1832 case OMAP_DSS_COLOR_CLUT4:
1833 return 4;
1834 case OMAP_DSS_COLOR_CLUT8:
1835 case OMAP_DSS_COLOR_NV12:
1836 return 8;
1837 case OMAP_DSS_COLOR_RGB12U:
1838 case OMAP_DSS_COLOR_RGB16:
1839 case OMAP_DSS_COLOR_ARGB16:
1840 case OMAP_DSS_COLOR_YUV2:
1841 case OMAP_DSS_COLOR_UYVY:
1842 case OMAP_DSS_COLOR_RGBA16:
1843 case OMAP_DSS_COLOR_RGBX16:
1844 case OMAP_DSS_COLOR_ARGB16_1555:
1845 case OMAP_DSS_COLOR_XRGB16_1555:
1846 return 16;
1847 case OMAP_DSS_COLOR_RGB24P:
1848 return 24;
1849 case OMAP_DSS_COLOR_RGB24U:
1850 case OMAP_DSS_COLOR_ARGB32:
1851 case OMAP_DSS_COLOR_RGBA32:
1852 case OMAP_DSS_COLOR_RGBX32:
1853 return 32;
1854 default:
1855 BUG();
1856 return 0;
1857 }
1858}
1859
1860static s32 pixinc(int pixels, u8 ps)
1861{
1862 if (pixels == 1)
1863 return 1;
1864 else if (pixels > 1)
1865 return 1 + (pixels - 1) * ps;
1866 else if (pixels < 0)
1867 return 1 - (-pixels + 1) * ps;
1868 else
1869 BUG();
1870 return 0;
1871}
1872
1873static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1874 u16 screen_width,
1875 u16 width, u16 height,
1876 enum omap_color_mode color_mode, bool fieldmode,
1877 unsigned int field_offset,
1878 unsigned *offset0, unsigned *offset1,
1879 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1880{
1881 u8 ps;
1882
1883 /* FIXME CLUT formats */
1884 switch (color_mode) {
1885 case OMAP_DSS_COLOR_CLUT1:
1886 case OMAP_DSS_COLOR_CLUT2:
1887 case OMAP_DSS_COLOR_CLUT4:
1888 case OMAP_DSS_COLOR_CLUT8:
1889 BUG();
1890 return;
1891 case OMAP_DSS_COLOR_YUV2:
1892 case OMAP_DSS_COLOR_UYVY:
1893 ps = 4;
1894 break;
1895 default:
1896 ps = color_mode_to_bpp(color_mode) / 8;
1897 break;
1898 }
1899
1900 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1901 width, height);
1902
1903 /*
1904 * field 0 = even field = bottom field
1905 * field 1 = odd field = top field
1906 */
1907 switch (rotation + mirror * 4) {
1908 case OMAP_DSS_ROT_0:
1909 case OMAP_DSS_ROT_180:
1910 /*
1911 * If the pixel format is YUV or UYVY divide the width
1912 * of the image by 2 for 0 and 180 degree rotation.
1913 */
1914 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1915 color_mode == OMAP_DSS_COLOR_UYVY)
1916 width = width >> 1;
1917 case OMAP_DSS_ROT_90:
1918 case OMAP_DSS_ROT_270:
1919 *offset1 = 0;
1920 if (field_offset)
1921 *offset0 = field_offset * screen_width * ps;
1922 else
1923 *offset0 = 0;
1924
1925 *row_inc = pixinc(1 +
1926 (y_predecim * screen_width - x_predecim * width) +
1927 (fieldmode ? screen_width : 0), ps);
1928 *pix_inc = pixinc(x_predecim, ps);
1929 break;
1930
1931 case OMAP_DSS_ROT_0 + 4:
1932 case OMAP_DSS_ROT_180 + 4:
1933 /* If the pixel format is YUV or UYVY divide the width
1934 * of the image by 2 for 0 degree and 180 degree
1935 */
1936 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1937 color_mode == OMAP_DSS_COLOR_UYVY)
1938 width = width >> 1;
1939 case OMAP_DSS_ROT_90 + 4:
1940 case OMAP_DSS_ROT_270 + 4:
1941 *offset1 = 0;
1942 if (field_offset)
1943 *offset0 = field_offset * screen_width * ps;
1944 else
1945 *offset0 = 0;
1946 *row_inc = pixinc(1 -
1947 (y_predecim * screen_width + x_predecim * width) -
1948 (fieldmode ? screen_width : 0), ps);
1949 *pix_inc = pixinc(x_predecim, ps);
1950 break;
1951
1952 default:
1953 BUG();
1954 return;
1955 }
1956}
1957
1958static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1959 u16 screen_width,
1960 u16 width, u16 height,
1961 enum omap_color_mode color_mode, bool fieldmode,
1962 unsigned int field_offset,
1963 unsigned *offset0, unsigned *offset1,
1964 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1965{
1966 u8 ps;
1967 u16 fbw, fbh;
1968
1969 /* FIXME CLUT formats */
1970 switch (color_mode) {
1971 case OMAP_DSS_COLOR_CLUT1:
1972 case OMAP_DSS_COLOR_CLUT2:
1973 case OMAP_DSS_COLOR_CLUT4:
1974 case OMAP_DSS_COLOR_CLUT8:
1975 BUG();
1976 return;
1977 default:
1978 ps = color_mode_to_bpp(color_mode) / 8;
1979 break;
1980 }
1981
1982 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1983 width, height);
1984
1985 /* width & height are overlay sizes, convert to fb sizes */
1986
1987 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1988 fbw = width;
1989 fbh = height;
1990 } else {
1991 fbw = height;
1992 fbh = width;
1993 }
1994
1995 /*
1996 * field 0 = even field = bottom field
1997 * field 1 = odd field = top field
1998 */
1999 switch (rotation + mirror * 4) {
2000 case OMAP_DSS_ROT_0:
2001 *offset1 = 0;
2002 if (field_offset)
2003 *offset0 = *offset1 + field_offset * screen_width * ps;
2004 else
2005 *offset0 = *offset1;
2006 *row_inc = pixinc(1 +
2007 (y_predecim * screen_width - fbw * x_predecim) +
2008 (fieldmode ? screen_width : 0), ps);
2009 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2010 color_mode == OMAP_DSS_COLOR_UYVY)
2011 *pix_inc = pixinc(x_predecim, 2 * ps);
2012 else
2013 *pix_inc = pixinc(x_predecim, ps);
2014 break;
2015 case OMAP_DSS_ROT_90:
2016 *offset1 = screen_width * (fbh - 1) * ps;
2017 if (field_offset)
2018 *offset0 = *offset1 + field_offset * ps;
2019 else
2020 *offset0 = *offset1;
2021 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2022 y_predecim + (fieldmode ? 1 : 0), ps);
2023 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2024 break;
2025 case OMAP_DSS_ROT_180:
2026 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2027 if (field_offset)
2028 *offset0 = *offset1 - field_offset * screen_width * ps;
2029 else
2030 *offset0 = *offset1;
2031 *row_inc = pixinc(-1 -
2032 (y_predecim * screen_width - fbw * x_predecim) -
2033 (fieldmode ? screen_width : 0), ps);
2034 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2035 color_mode == OMAP_DSS_COLOR_UYVY)
2036 *pix_inc = pixinc(-x_predecim, 2 * ps);
2037 else
2038 *pix_inc = pixinc(-x_predecim, ps);
2039 break;
2040 case OMAP_DSS_ROT_270:
2041 *offset1 = (fbw - 1) * ps;
2042 if (field_offset)
2043 *offset0 = *offset1 - field_offset * ps;
2044 else
2045 *offset0 = *offset1;
2046 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2047 y_predecim - (fieldmode ? 1 : 0), ps);
2048 *pix_inc = pixinc(x_predecim * screen_width, ps);
2049 break;
2050
2051 /* mirroring */
2052 case OMAP_DSS_ROT_0 + 4:
2053 *offset1 = (fbw - 1) * ps;
2054 if (field_offset)
2055 *offset0 = *offset1 + field_offset * screen_width * ps;
2056 else
2057 *offset0 = *offset1;
2058 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2059 (fieldmode ? screen_width : 0),
2060 ps);
2061 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2062 color_mode == OMAP_DSS_COLOR_UYVY)
2063 *pix_inc = pixinc(-x_predecim, 2 * ps);
2064 else
2065 *pix_inc = pixinc(-x_predecim, ps);
2066 break;
2067
2068 case OMAP_DSS_ROT_90 + 4:
2069 *offset1 = 0;
2070 if (field_offset)
2071 *offset0 = *offset1 + field_offset * ps;
2072 else
2073 *offset0 = *offset1;
2074 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2075 y_predecim + (fieldmode ? 1 : 0),
2076 ps);
2077 *pix_inc = pixinc(x_predecim * screen_width, ps);
2078 break;
2079
2080 case OMAP_DSS_ROT_180 + 4:
2081 *offset1 = screen_width * (fbh - 1) * ps;
2082 if (field_offset)
2083 *offset0 = *offset1 - field_offset * screen_width * ps;
2084 else
2085 *offset0 = *offset1;
2086 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2087 (fieldmode ? screen_width : 0),
2088 ps);
2089 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2090 color_mode == OMAP_DSS_COLOR_UYVY)
2091 *pix_inc = pixinc(x_predecim, 2 * ps);
2092 else
2093 *pix_inc = pixinc(x_predecim, ps);
2094 break;
2095
2096 case OMAP_DSS_ROT_270 + 4:
2097 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2098 if (field_offset)
2099 *offset0 = *offset1 - field_offset * ps;
2100 else
2101 *offset0 = *offset1;
2102 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2103 y_predecim - (fieldmode ? 1 : 0),
2104 ps);
2105 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2106 break;
2107
2108 default:
2109 BUG();
2110 return;
2111 }
2112}
2113
2114static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2115 enum omap_color_mode color_mode, bool fieldmode,
2116 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2117 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2118{
2119 u8 ps;
2120
2121 switch (color_mode) {
2122 case OMAP_DSS_COLOR_CLUT1:
2123 case OMAP_DSS_COLOR_CLUT2:
2124 case OMAP_DSS_COLOR_CLUT4:
2125 case OMAP_DSS_COLOR_CLUT8:
2126 BUG();
2127 return;
2128 default:
2129 ps = color_mode_to_bpp(color_mode) / 8;
2130 break;
2131 }
2132
2133 DSSDBG("scrw %d, width %d\n", screen_width, width);
2134
2135 /*
2136 * field 0 = even field = bottom field
2137 * field 1 = odd field = top field
2138 */
2139 *offset1 = 0;
2140 if (field_offset)
2141 *offset0 = *offset1 + field_offset * screen_width * ps;
2142 else
2143 *offset0 = *offset1;
2144 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2145 (fieldmode ? screen_width : 0), ps);
2146 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2147 color_mode == OMAP_DSS_COLOR_UYVY)
2148 *pix_inc = pixinc(x_predecim, 2 * ps);
2149 else
2150 *pix_inc = pixinc(x_predecim, ps);
2151}
2152
2153/*
2154 * This function is used to avoid synclosts in OMAP3, because of some
2155 * undocumented horizontal position and timing related limitations.
2156 */
2157static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2158 const struct omap_video_timings *t, u16 pos_x,
2159 u16 width, u16 height, u16 out_width, u16 out_height,
2160 bool five_taps)
2161{
2162 const int ds = DIV_ROUND_UP(height, out_height);
2163 unsigned long nonactive;
2164 static const u8 limits[3] = { 8, 10, 20 };
2165 u64 val, blank;
2166 int i;
2167
2168 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2169
2170 i = 0;
2171 if (out_height < height)
2172 i++;
2173 if (out_width < width)
2174 i++;
2175 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2176 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2177 if (blank <= limits[i])
2178 return -EINVAL;
2179
2180 /* FIXME add checks for 3-tap filter once the limitations are known */
2181 if (!five_taps)
2182 return 0;
2183
2184 /*
2185 * Pixel data should be prepared before visible display point starts.
2186 * So, atleast DS-2 lines must have already been fetched by DISPC
2187 * during nonactive - pos_x period.
2188 */
2189 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2190 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2191 val, max(0, ds - 2) * width);
2192 if (val < max(0, ds - 2) * width)
2193 return -EINVAL;
2194
2195 /*
2196 * All lines need to be refilled during the nonactive period of which
2197 * only one line can be loaded during the active period. So, atleast
2198 * DS - 1 lines should be loaded during nonactive period.
2199 */
2200 val = div_u64((u64)nonactive * lclk, pclk);
2201 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2202 val, max(0, ds - 1) * width);
2203 if (val < max(0, ds - 1) * width)
2204 return -EINVAL;
2205
2206 return 0;
2207}
2208
2209static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2210 const struct omap_video_timings *mgr_timings, u16 width,
2211 u16 height, u16 out_width, u16 out_height,
2212 enum omap_color_mode color_mode)
2213{
2214 u32 core_clk = 0;
2215 u64 tmp;
2216
2217 if (height <= out_height && width <= out_width)
2218 return (unsigned long) pclk;
2219
2220 if (height > out_height) {
2221 unsigned int ppl = mgr_timings->x_res;
2222
2223 tmp = (u64)pclk * height * out_width;
2224 do_div(tmp, 2 * out_height * ppl);
2225 core_clk = tmp;
2226
2227 if (height > 2 * out_height) {
2228 if (ppl == out_width)
2229 return 0;
2230
2231 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2232 do_div(tmp, 2 * out_height * (ppl - out_width));
2233 core_clk = max_t(u32, core_clk, tmp);
2234 }
2235 }
2236
2237 if (width > out_width) {
2238 tmp = (u64)pclk * width;
2239 do_div(tmp, out_width);
2240 core_clk = max_t(u32, core_clk, tmp);
2241
2242 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2243 core_clk <<= 1;
2244 }
2245
2246 return core_clk;
2247}
2248
2249static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2250 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2251{
2252 if (height > out_height && width > out_width)
2253 return pclk * 4;
2254 else
2255 return pclk * 2;
2256}
2257
2258static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2259 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2260{
2261 unsigned int hf, vf;
2262
2263 /*
2264 * FIXME how to determine the 'A' factor
2265 * for the no downscaling case ?
2266 */
2267
2268 if (width > 3 * out_width)
2269 hf = 4;
2270 else if (width > 2 * out_width)
2271 hf = 3;
2272 else if (width > out_width)
2273 hf = 2;
2274 else
2275 hf = 1;
2276 if (height > out_height)
2277 vf = 2;
2278 else
2279 vf = 1;
2280
2281 return pclk * vf * hf;
2282}
2283
2284static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2285 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2286{
2287 /*
2288 * If the overlay/writeback is in mem to mem mode, there are no
2289 * downscaling limitations with respect to pixel clock, return 1 as
2290 * required core clock to represent that we have sufficient enough
2291 * core clock to do maximum downscaling
2292 */
2293 if (mem_to_mem)
2294 return 1;
2295
2296 if (width > out_width)
2297 return DIV_ROUND_UP(pclk, out_width) * width;
2298 else
2299 return pclk;
2300}
2301
2302static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2303 const struct omap_video_timings *mgr_timings,
2304 u16 width, u16 height, u16 out_width, u16 out_height,
2305 enum omap_color_mode color_mode, bool *five_taps,
2306 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2307 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2308{
2309 int error;
2310 u16 in_width, in_height;
2311 int min_factor = min(*decim_x, *decim_y);
2312 const int maxsinglelinewidth =
2313 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2314
2315 *five_taps = false;
2316
2317 do {
2318 in_height = height / *decim_y;
2319 in_width = width / *decim_x;
2320 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2321 in_height, out_width, out_height, mem_to_mem);
2322 error = (in_width > maxsinglelinewidth || !*core_clk ||
2323 *core_clk > dispc_core_clk_rate());
2324 if (error) {
2325 if (*decim_x == *decim_y) {
2326 *decim_x = min_factor;
2327 ++*decim_y;
2328 } else {
2329 swap(*decim_x, *decim_y);
2330 if (*decim_x < *decim_y)
2331 ++*decim_x;
2332 }
2333 }
2334 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2335
2336 if (error) {
2337 DSSERR("failed to find scaling settings\n");
2338 return -EINVAL;
2339 }
2340
2341 if (in_width > maxsinglelinewidth) {
2342 DSSERR("Cannot scale max input width exceeded");
2343 return -EINVAL;
2344 }
2345 return 0;
2346}
2347
2348static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2349 const struct omap_video_timings *mgr_timings,
2350 u16 width, u16 height, u16 out_width, u16 out_height,
2351 enum omap_color_mode color_mode, bool *five_taps,
2352 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2353 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2354{
2355 int error;
2356 u16 in_width, in_height;
2357 const int maxsinglelinewidth =
2358 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2359
2360 do {
2361 in_height = height / *decim_y;
2362 in_width = width / *decim_x;
2363 *five_taps = in_height > out_height;
2364
2365 if (in_width > maxsinglelinewidth)
2366 if (in_height > out_height &&
2367 in_height < out_height * 2)
2368 *five_taps = false;
2369again:
2370 if (*five_taps)
2371 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2372 in_width, in_height, out_width,
2373 out_height, color_mode);
2374 else
2375 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2376 in_height, out_width, out_height,
2377 mem_to_mem);
2378
2379 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2380 pos_x, in_width, in_height, out_width,
2381 out_height, *five_taps);
2382 if (error && *five_taps) {
2383 *five_taps = false;
2384 goto again;
2385 }
2386
2387 error = (error || in_width > maxsinglelinewidth * 2 ||
2388 (in_width > maxsinglelinewidth && *five_taps) ||
2389 !*core_clk || *core_clk > dispc_core_clk_rate());
2390
2391 if (!error) {
2392 /* verify that we're inside the limits of scaler */
2393 if (in_width / 4 > out_width)
2394 error = 1;
2395
2396 if (*five_taps) {
2397 if (in_height / 4 > out_height)
2398 error = 1;
2399 } else {
2400 if (in_height / 2 > out_height)
2401 error = 1;
2402 }
2403 }
2404
2405 if (error)
2406 ++*decim_y;
2407 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2408
2409 if (error) {
2410 DSSERR("failed to find scaling settings\n");
2411 return -EINVAL;
2412 }
2413
2414 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2415 in_height, out_width, out_height, *five_taps)) {
2416 DSSERR("horizontal timing too tight\n");
2417 return -EINVAL;
2418 }
2419
2420 if (in_width > (maxsinglelinewidth * 2)) {
2421 DSSERR("Cannot setup scaling");
2422 DSSERR("width exceeds maximum width possible");
2423 return -EINVAL;
2424 }
2425
2426 if (in_width > maxsinglelinewidth && *five_taps) {
2427 DSSERR("cannot setup scaling with five taps");
2428 return -EINVAL;
2429 }
2430 return 0;
2431}
2432
2433static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2434 const struct omap_video_timings *mgr_timings,
2435 u16 width, u16 height, u16 out_width, u16 out_height,
2436 enum omap_color_mode color_mode, bool *five_taps,
2437 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2438 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2439{
2440 u16 in_width, in_width_max;
2441 int decim_x_min = *decim_x;
2442 u16 in_height = height / *decim_y;
2443 const int maxsinglelinewidth =
2444 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2445 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2446
2447 if (mem_to_mem) {
2448 in_width_max = out_width * maxdownscale;
2449 } else {
2450 in_width_max = dispc_core_clk_rate() /
2451 DIV_ROUND_UP(pclk, out_width);
2452 }
2453
2454 *decim_x = DIV_ROUND_UP(width, in_width_max);
2455
2456 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2457 if (*decim_x > *x_predecim)
2458 return -EINVAL;
2459
2460 do {
2461 in_width = width / *decim_x;
2462 } while (*decim_x <= *x_predecim &&
2463 in_width > maxsinglelinewidth && ++*decim_x);
2464
2465 if (in_width > maxsinglelinewidth) {
2466 DSSERR("Cannot scale width exceeds max line width");
2467 return -EINVAL;
2468 }
2469
2470 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2471 out_width, out_height, mem_to_mem);
2472 return 0;
2473}
2474
2475#define DIV_FRAC(dividend, divisor) \
2476 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2477
2478static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2479 enum omap_overlay_caps caps,
2480 const struct omap_video_timings *mgr_timings,
2481 u16 width, u16 height, u16 out_width, u16 out_height,
2482 enum omap_color_mode color_mode, bool *five_taps,
2483 int *x_predecim, int *y_predecim, u16 pos_x,
2484 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2485{
2486 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2487 const int max_decim_limit = 16;
2488 unsigned long core_clk = 0;
2489 int decim_x, decim_y, ret;
2490
2491 if (width == out_width && height == out_height)
2492 return 0;
2493
2494 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2495 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2496 return -EINVAL;
2497 }
2498
2499 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2500 return -EINVAL;
2501
2502 if (mem_to_mem) {
2503 *x_predecim = *y_predecim = 1;
2504 } else {
2505 *x_predecim = max_decim_limit;
2506 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2507 dss_has_feature(FEAT_BURST_2D)) ?
2508 2 : max_decim_limit;
2509 }
2510
2511 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2512 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2513 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2514 color_mode == OMAP_DSS_COLOR_CLUT8) {
2515 *x_predecim = 1;
2516 *y_predecim = 1;
2517 *five_taps = false;
2518 return 0;
2519 }
2520
2521 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2522 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2523
2524 if (decim_x > *x_predecim || out_width > width * 8)
2525 return -EINVAL;
2526
2527 if (decim_y > *y_predecim || out_height > height * 8)
2528 return -EINVAL;
2529
2530 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2531 out_width, out_height, color_mode, five_taps,
2532 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2533 mem_to_mem);
2534 if (ret)
2535 return ret;
2536
2537 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2538 width, height,
2539 out_width, out_height,
2540 out_width / width, DIV_FRAC(out_width, width),
2541 out_height / height, DIV_FRAC(out_height, height),
2542
2543 decim_x, decim_y,
2544 width / decim_x, height / decim_y,
2545 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2546 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2547
2548 *five_taps ? 5 : 3,
2549 core_clk, dispc_core_clk_rate());
2550
2551 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2552 DSSERR("failed to set up scaling, "
2553 "required core clk rate = %lu Hz, "
2554 "current core clk rate = %lu Hz\n",
2555 core_clk, dispc_core_clk_rate());
2556 return -EINVAL;
2557 }
2558
2559 *x_predecim = decim_x;
2560 *y_predecim = decim_y;
2561 return 0;
2562}
2563
2564static int dispc_ovl_setup_common(enum omap_plane plane,
2565 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2566 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2567 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2568 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2569 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2570 bool replication, const struct omap_video_timings *mgr_timings,
2571 bool mem_to_mem)
2572{
2573 bool five_taps = true;
2574 bool fieldmode = false;
2575 int r, cconv = 0;
2576 unsigned offset0, offset1;
2577 s32 row_inc;
2578 s32 pix_inc;
2579 u16 frame_width, frame_height;
2580 unsigned int field_offset = 0;
2581 u16 in_height = height;
2582 u16 in_width = width;
2583 int x_predecim = 1, y_predecim = 1;
2584 bool ilace = mgr_timings->interlace;
2585 unsigned long pclk = dispc_plane_pclk_rate(plane);
2586 unsigned long lclk = dispc_plane_lclk_rate(plane);
2587
2588 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2589 return -EINVAL;
2590
2591 switch (color_mode) {
2592 case OMAP_DSS_COLOR_YUV2:
2593 case OMAP_DSS_COLOR_UYVY:
2594 case OMAP_DSS_COLOR_NV12:
2595 if (in_width & 1) {
2596 DSSERR("input width %d is not even for YUV format\n",
2597 in_width);
2598 return -EINVAL;
2599 }
2600 break;
2601
2602 default:
2603 break;
2604 }
2605
2606 out_width = out_width == 0 ? width : out_width;
2607 out_height = out_height == 0 ? height : out_height;
2608
2609 if (ilace && height == out_height)
2610 fieldmode = true;
2611
2612 if (ilace) {
2613 if (fieldmode)
2614 in_height /= 2;
2615 pos_y /= 2;
2616 out_height /= 2;
2617
2618 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2619 "out_height %d\n", in_height, pos_y,
2620 out_height);
2621 }
2622
2623 if (!dss_feat_color_mode_supported(plane, color_mode))
2624 return -EINVAL;
2625
2626 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2627 in_height, out_width, out_height, color_mode,
2628 &five_taps, &x_predecim, &y_predecim, pos_x,
2629 rotation_type, mem_to_mem);
2630 if (r)
2631 return r;
2632
2633 in_width = in_width / x_predecim;
2634 in_height = in_height / y_predecim;
2635
2636 if (x_predecim > 1 || y_predecim > 1)
2637 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2638 x_predecim, y_predecim, in_width, in_height);
2639
2640 switch (color_mode) {
2641 case OMAP_DSS_COLOR_YUV2:
2642 case OMAP_DSS_COLOR_UYVY:
2643 case OMAP_DSS_COLOR_NV12:
2644 if (in_width & 1) {
2645 DSSDBG("predecimated input width is not even for YUV format\n");
2646 DSSDBG("adjusting input width %d -> %d\n",
2647 in_width, in_width & ~1);
2648
2649 in_width &= ~1;
2650 }
2651 break;
2652
2653 default:
2654 break;
2655 }
2656
2657 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2658 color_mode == OMAP_DSS_COLOR_UYVY ||
2659 color_mode == OMAP_DSS_COLOR_NV12)
2660 cconv = 1;
2661
2662 if (ilace && !fieldmode) {
2663 /*
2664 * when downscaling the bottom field may have to start several
2665 * source lines below the top field. Unfortunately ACCUI
2666 * registers will only hold the fractional part of the offset
2667 * so the integer part must be added to the base address of the
2668 * bottom field.
2669 */
2670 if (!in_height || in_height == out_height)
2671 field_offset = 0;
2672 else
2673 field_offset = in_height / out_height / 2;
2674 }
2675
2676 /* Fields are independent but interleaved in memory. */
2677 if (fieldmode)
2678 field_offset = 1;
2679
2680 offset0 = 0;
2681 offset1 = 0;
2682 row_inc = 0;
2683 pix_inc = 0;
2684
2685 if (plane == OMAP_DSS_WB) {
2686 frame_width = out_width;
2687 frame_height = out_height;
2688 } else {
2689 frame_width = in_width;
2690 frame_height = height;
2691 }
2692
2693 if (rotation_type == OMAP_DSS_ROT_TILER)
2694 calc_tiler_rotation_offset(screen_width, frame_width,
2695 color_mode, fieldmode, field_offset,
2696 &offset0, &offset1, &row_inc, &pix_inc,
2697 x_predecim, y_predecim);
2698 else if (rotation_type == OMAP_DSS_ROT_DMA)
2699 calc_dma_rotation_offset(rotation, mirror, screen_width,
2700 frame_width, frame_height,
2701 color_mode, fieldmode, field_offset,
2702 &offset0, &offset1, &row_inc, &pix_inc,
2703 x_predecim, y_predecim);
2704 else
2705 calc_vrfb_rotation_offset(rotation, mirror,
2706 screen_width, frame_width, frame_height,
2707 color_mode, fieldmode, field_offset,
2708 &offset0, &offset1, &row_inc, &pix_inc,
2709 x_predecim, y_predecim);
2710
2711 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2712 offset0, offset1, row_inc, pix_inc);
2713
2714 dispc_ovl_set_color_mode(plane, color_mode);
2715
2716 dispc_ovl_configure_burst_type(plane, rotation_type);
2717
2718 if (dispc.feat->reverse_ilace_field_order)
2719 swap(offset0, offset1);
2720
2721 dispc_ovl_set_ba0(plane, paddr + offset0);
2722 dispc_ovl_set_ba1(plane, paddr + offset1);
2723
2724 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2725 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2726 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2727 }
2728
2729 if (dispc.feat->last_pixel_inc_missing)
2730 row_inc += pix_inc - 1;
2731
2732 dispc_ovl_set_row_inc(plane, row_inc);
2733 dispc_ovl_set_pix_inc(plane, pix_inc);
2734
2735 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2736 in_height, out_width, out_height);
2737
2738 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2739
2740 dispc_ovl_set_input_size(plane, in_width, in_height);
2741
2742 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2743 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2744 out_height, ilace, five_taps, fieldmode,
2745 color_mode, rotation);
2746 dispc_ovl_set_output_size(plane, out_width, out_height);
2747 dispc_ovl_set_vid_color_conv(plane, cconv);
2748 }
2749
2750 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2751 color_mode);
2752
2753 dispc_ovl_set_zorder(plane, caps, zorder);
2754 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2755 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2756
2757 dispc_ovl_enable_replication(plane, caps, replication);
2758
2759 return 0;
2760}
2761
2762int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2763 bool replication, const struct omap_video_timings *mgr_timings,
2764 bool mem_to_mem)
2765{
2766 int r;
2767 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2768 enum omap_channel channel;
2769
2770 channel = dispc_ovl_get_channel_out(plane);
2771
2772 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2773 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2774 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2775 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2776 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2777
2778 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2779 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2780 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2781 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2782 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2783
2784 return r;
2785}
2786EXPORT_SYMBOL(dispc_ovl_setup);
2787
2788int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2789 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2790{
2791 int r;
2792 u32 l;
2793 enum omap_plane plane = OMAP_DSS_WB;
2794 const int pos_x = 0, pos_y = 0;
2795 const u8 zorder = 0, global_alpha = 0;
2796 const bool replication = false;
2797 bool truncation;
2798 int in_width = mgr_timings->x_res;
2799 int in_height = mgr_timings->y_res;
2800 enum omap_overlay_caps caps =
2801 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2802
2803 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2804 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2805 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2806 wi->mirror);
2807
2808 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2809 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2810 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2811 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2812 replication, mgr_timings, mem_to_mem);
2813
2814 switch (wi->color_mode) {
2815 case OMAP_DSS_COLOR_RGB16:
2816 case OMAP_DSS_COLOR_RGB24P:
2817 case OMAP_DSS_COLOR_ARGB16:
2818 case OMAP_DSS_COLOR_RGBA16:
2819 case OMAP_DSS_COLOR_RGB12U:
2820 case OMAP_DSS_COLOR_ARGB16_1555:
2821 case OMAP_DSS_COLOR_XRGB16_1555:
2822 case OMAP_DSS_COLOR_RGBX16:
2823 truncation = true;
2824 break;
2825 default:
2826 truncation = false;
2827 break;
2828 }
2829
2830 /* setup extra DISPC_WB_ATTRIBUTES */
2831 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2832 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2833 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2834 if (mem_to_mem)
2835 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
2836 else
2837 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
2838 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2839
2840 if (mem_to_mem) {
2841 /* WBDELAYCOUNT */
2842 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2843 } else {
2844 int wbdelay;
2845
2846 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2847 mgr_timings->vbp, 255);
2848
2849 /* WBDELAYCOUNT */
2850 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2851 }
2852
2853 return r;
2854}
2855
2856int dispc_ovl_enable(enum omap_plane plane, bool enable)
2857{
2858 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2859
2860 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2861
2862 return 0;
2863}
2864EXPORT_SYMBOL(dispc_ovl_enable);
2865
2866bool dispc_ovl_enabled(enum omap_plane plane)
2867{
2868 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2869}
2870EXPORT_SYMBOL(dispc_ovl_enabled);
2871
2872enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)
2873{
2874 return dss_feat_get_supported_outputs(channel);
2875}
2876EXPORT_SYMBOL(dispc_mgr_get_supported_outputs);
2877
2878void dispc_mgr_enable(enum omap_channel channel, bool enable)
2879{
2880 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2881 /* flush posted write */
2882 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2883}
2884EXPORT_SYMBOL(dispc_mgr_enable);
2885
2886bool dispc_mgr_is_enabled(enum omap_channel channel)
2887{
2888 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2889}
2890EXPORT_SYMBOL(dispc_mgr_is_enabled);
2891
2892void dispc_wb_enable(bool enable)
2893{
2894 dispc_ovl_enable(OMAP_DSS_WB, enable);
2895}
2896
2897bool dispc_wb_is_enabled(void)
2898{
2899 return dispc_ovl_enabled(OMAP_DSS_WB);
2900}
2901
2902static void dispc_lcd_enable_signal_polarity(bool act_high)
2903{
2904 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2905 return;
2906
2907 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2908}
2909
2910void dispc_lcd_enable_signal(bool enable)
2911{
2912 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2913 return;
2914
2915 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2916}
2917
2918void dispc_pck_free_enable(bool enable)
2919{
2920 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2921 return;
2922
2923 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2924}
2925
2926static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2927{
2928 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2929}
2930
2931
2932static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2933{
2934 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2935}
2936
2937static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2938{
2939 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2940}
2941
2942
2943static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2944{
2945 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2946}
2947
2948static void dispc_mgr_set_trans_key(enum omap_channel ch,
2949 enum omap_dss_trans_key_type type,
2950 u32 trans_key)
2951{
2952 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2953
2954 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2955}
2956
2957static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2958{
2959 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2960}
2961
2962static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2963 bool enable)
2964{
2965 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2966 return;
2967
2968 if (ch == OMAP_DSS_CHANNEL_LCD)
2969 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2970 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2971 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2972}
2973
2974void dispc_mgr_setup(enum omap_channel channel,
2975 const struct omap_overlay_manager_info *info)
2976{
2977 dispc_mgr_set_default_color(channel, info->default_color);
2978 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2979 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2980 dispc_mgr_enable_alpha_fixed_zorder(channel,
2981 info->partial_alpha_enabled);
2982 if (dss_has_feature(FEAT_CPR)) {
2983 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2984 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2985 }
2986}
2987EXPORT_SYMBOL(dispc_mgr_setup);
2988
2989static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2990{
2991 int code;
2992
2993 switch (data_lines) {
2994 case 12:
2995 code = 0;
2996 break;
2997 case 16:
2998 code = 1;
2999 break;
3000 case 18:
3001 code = 2;
3002 break;
3003 case 24:
3004 code = 3;
3005 break;
3006 default:
3007 BUG();
3008 return;
3009 }
3010
3011 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3012}
3013
3014static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3015{
3016 u32 l;
3017 int gpout0, gpout1;
3018
3019 switch (mode) {
3020 case DSS_IO_PAD_MODE_RESET:
3021 gpout0 = 0;
3022 gpout1 = 0;
3023 break;
3024 case DSS_IO_PAD_MODE_RFBI:
3025 gpout0 = 1;
3026 gpout1 = 0;
3027 break;
3028 case DSS_IO_PAD_MODE_BYPASS:
3029 gpout0 = 1;
3030 gpout1 = 1;
3031 break;
3032 default:
3033 BUG();
3034 return;
3035 }
3036
3037 l = dispc_read_reg(DISPC_CONTROL);
3038 l = FLD_MOD(l, gpout0, 15, 15);
3039 l = FLD_MOD(l, gpout1, 16, 16);
3040 dispc_write_reg(DISPC_CONTROL, l);
3041}
3042
3043static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3044{
3045 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3046}
3047
3048void dispc_mgr_set_lcd_config(enum omap_channel channel,
3049 const struct dss_lcd_mgr_config *config)
3050{
3051 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3052
3053 dispc_mgr_enable_stallmode(channel, config->stallmode);
3054 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3055
3056 dispc_mgr_set_clock_div(channel, &config->clock_info);
3057
3058 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3059
3060 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3061
3062 dispc_mgr_set_lcd_type_tft(channel);
3063}
3064EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3065
3066static bool _dispc_mgr_size_ok(u16 width, u16 height)
3067{
3068 return width <= dispc.feat->mgr_width_max &&
3069 height <= dispc.feat->mgr_height_max;
3070}
3071
3072static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3073 int vsw, int vfp, int vbp)
3074{
3075 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3076 hfp < 1 || hfp > dispc.feat->hp_max ||
3077 hbp < 1 || hbp > dispc.feat->hp_max ||
3078 vsw < 1 || vsw > dispc.feat->sw_max ||
3079 vfp < 0 || vfp > dispc.feat->vp_max ||
3080 vbp < 0 || vbp > dispc.feat->vp_max)
3081 return false;
3082 return true;
3083}
3084
3085static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3086 unsigned long pclk)
3087{
3088 if (dss_mgr_is_lcd(channel))
3089 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3090 else
3091 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3092}
3093
3094bool dispc_mgr_timings_ok(enum omap_channel channel,
3095 const struct omap_video_timings *timings)
3096{
3097 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3098 return false;
3099
3100 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3101 return false;
3102
3103 if (dss_mgr_is_lcd(channel)) {
3104 /* TODO: OMAP4+ supports interlace for LCD outputs */
3105 if (timings->interlace)
3106 return false;
3107
3108 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3109 timings->hbp, timings->vsw, timings->vfp,
3110 timings->vbp))
3111 return false;
3112 }
3113
3114 return true;
3115}
3116
3117static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3118 int hfp, int hbp, int vsw, int vfp, int vbp,
3119 enum omap_dss_signal_level vsync_level,
3120 enum omap_dss_signal_level hsync_level,
3121 enum omap_dss_signal_edge data_pclk_edge,
3122 enum omap_dss_signal_level de_level,
3123 enum omap_dss_signal_edge sync_pclk_edge)
3124
3125{
3126 u32 timing_h, timing_v, l;
3127 bool onoff, rf, ipc, vs, hs, de;
3128
3129 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3130 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3131 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3132 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3133 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3134 FLD_VAL(vbp, dispc.feat->bp_start, 20);
3135
3136 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3137 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3138
3139 switch (vsync_level) {
3140 case OMAPDSS_SIG_ACTIVE_LOW:
3141 vs = true;
3142 break;
3143 case OMAPDSS_SIG_ACTIVE_HIGH:
3144 vs = false;
3145 break;
3146 default:
3147 BUG();
3148 }
3149
3150 switch (hsync_level) {
3151 case OMAPDSS_SIG_ACTIVE_LOW:
3152 hs = true;
3153 break;
3154 case OMAPDSS_SIG_ACTIVE_HIGH:
3155 hs = false;
3156 break;
3157 default:
3158 BUG();
3159 }
3160
3161 switch (de_level) {
3162 case OMAPDSS_SIG_ACTIVE_LOW:
3163 de = true;
3164 break;
3165 case OMAPDSS_SIG_ACTIVE_HIGH:
3166 de = false;
3167 break;
3168 default:
3169 BUG();
3170 }
3171
3172 switch (data_pclk_edge) {
3173 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3174 ipc = false;
3175 break;
3176 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3177 ipc = true;
3178 break;
3179 default:
3180 BUG();
3181 }
3182
3183 /* always use the 'rf' setting */
3184 onoff = true;
3185
3186 switch (sync_pclk_edge) {
3187 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3188 rf = false;
3189 break;
3190 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3191 rf = true;
3192 break;
3193 default:
3194 BUG();
3195 }
3196
3197 l = FLD_VAL(onoff, 17, 17) |
3198 FLD_VAL(rf, 16, 16) |
3199 FLD_VAL(de, 15, 15) |
3200 FLD_VAL(ipc, 14, 14) |
3201 FLD_VAL(hs, 13, 13) |
3202 FLD_VAL(vs, 12, 12);
3203
3204 /* always set ALIGN bit when available */
3205 if (dispc.feat->supports_sync_align)
3206 l |= (1 << 18);
3207
3208 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3209
3210 if (dispc.syscon_pol) {
3211 const int shifts[] = {
3212 [OMAP_DSS_CHANNEL_LCD] = 0,
3213 [OMAP_DSS_CHANNEL_LCD2] = 1,
3214 [OMAP_DSS_CHANNEL_LCD3] = 2,
3215 };
3216
3217 u32 mask, val;
3218
3219 mask = (1 << 0) | (1 << 3) | (1 << 6);
3220 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3221
3222 mask <<= 16 + shifts[channel];
3223 val <<= 16 + shifts[channel];
3224
3225 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3226 mask, val);
3227 }
3228}
3229
3230/* change name to mode? */
3231void dispc_mgr_set_timings(enum omap_channel channel,
3232 const struct omap_video_timings *timings)
3233{
3234 unsigned xtot, ytot;
3235 unsigned long ht, vt;
3236 struct omap_video_timings t = *timings;
3237
3238 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3239
3240 if (!dispc_mgr_timings_ok(channel, &t)) {
3241 BUG();
3242 return;
3243 }
3244
3245 if (dss_mgr_is_lcd(channel)) {
3246 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3247 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3248 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3249
3250 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3251 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3252
3253 ht = timings->pixelclock / xtot;
3254 vt = timings->pixelclock / xtot / ytot;
3255
3256 DSSDBG("pck %u\n", timings->pixelclock);
3257 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3258 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3259 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3260 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3261 t.de_level, t.sync_pclk_edge);
3262
3263 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3264 } else {
3265 if (t.interlace)
3266 t.y_res /= 2;
3267
3268 if (dispc.feat->supports_double_pixel)
3269 REG_FLD_MOD(DISPC_CONTROL, t.double_pixel ? 1 : 0,
3270 19, 17);
3271 }
3272
3273 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3274}
3275EXPORT_SYMBOL(dispc_mgr_set_timings);
3276
3277static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3278 u16 pck_div)
3279{
3280 BUG_ON(lck_div < 1);
3281 BUG_ON(pck_div < 1);
3282
3283 dispc_write_reg(DISPC_DIVISORo(channel),
3284 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3285
3286 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3287 channel == OMAP_DSS_CHANNEL_LCD)
3288 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3289}
3290
3291static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3292 int *pck_div)
3293{
3294 u32 l;
3295 l = dispc_read_reg(DISPC_DIVISORo(channel));
3296 *lck_div = FLD_GET(l, 23, 16);
3297 *pck_div = FLD_GET(l, 7, 0);
3298}
3299
3300static unsigned long dispc_fclk_rate(void)
3301{
3302 struct dss_pll *pll;
3303 unsigned long r = 0;
3304
3305 switch (dss_get_dispc_clk_source()) {
3306 case OMAP_DSS_CLK_SRC_FCK:
3307 r = dss_get_dispc_clk_rate();
3308 break;
3309 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3310 pll = dss_pll_find("dsi0");
3311 if (!pll)
3312 pll = dss_pll_find("video0");
3313
3314 r = pll->cinfo.clkout[0];
3315 break;
3316 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3317 pll = dss_pll_find("dsi1");
3318 if (!pll)
3319 pll = dss_pll_find("video1");
3320
3321 r = pll->cinfo.clkout[0];
3322 break;
3323 default:
3324 BUG();
3325 return 0;
3326 }
3327
3328 return r;
3329}
3330
3331static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3332{
3333 struct dss_pll *pll;
3334 int lcd;
3335 unsigned long r;
3336 u32 l;
3337
3338 if (dss_mgr_is_lcd(channel)) {
3339 l = dispc_read_reg(DISPC_DIVISORo(channel));
3340
3341 lcd = FLD_GET(l, 23, 16);
3342
3343 switch (dss_get_lcd_clk_source(channel)) {
3344 case OMAP_DSS_CLK_SRC_FCK:
3345 r = dss_get_dispc_clk_rate();
3346 break;
3347 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3348 pll = dss_pll_find("dsi0");
3349 if (!pll)
3350 pll = dss_pll_find("video0");
3351
3352 r = pll->cinfo.clkout[0];
3353 break;
3354 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3355 pll = dss_pll_find("dsi1");
3356 if (!pll)
3357 pll = dss_pll_find("video1");
3358
3359 r = pll->cinfo.clkout[0];
3360 break;
3361 default:
3362 BUG();
3363 return 0;
3364 }
3365
3366 return r / lcd;
3367 } else {
3368 return dispc_fclk_rate();
3369 }
3370}
3371
3372static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3373{
3374 unsigned long r;
3375
3376 if (dss_mgr_is_lcd(channel)) {
3377 int pcd;
3378 u32 l;
3379
3380 l = dispc_read_reg(DISPC_DIVISORo(channel));
3381
3382 pcd = FLD_GET(l, 7, 0);
3383
3384 r = dispc_mgr_lclk_rate(channel);
3385
3386 return r / pcd;
3387 } else {
3388 return dispc.tv_pclk_rate;
3389 }
3390}
3391
3392void dispc_set_tv_pclk(unsigned long pclk)
3393{
3394 dispc.tv_pclk_rate = pclk;
3395}
3396
3397static unsigned long dispc_core_clk_rate(void)
3398{
3399 return dispc.core_clk_rate;
3400}
3401
3402static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3403{
3404 enum omap_channel channel;
3405
3406 if (plane == OMAP_DSS_WB)
3407 return 0;
3408
3409 channel = dispc_ovl_get_channel_out(plane);
3410
3411 return dispc_mgr_pclk_rate(channel);
3412}
3413
3414static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3415{
3416 enum omap_channel channel;
3417
3418 if (plane == OMAP_DSS_WB)
3419 return 0;
3420
3421 channel = dispc_ovl_get_channel_out(plane);
3422
3423 return dispc_mgr_lclk_rate(channel);
3424}
3425
3426static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3427{
3428 int lcd, pcd;
3429 enum omap_dss_clk_source lcd_clk_src;
3430
3431 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3432
3433 lcd_clk_src = dss_get_lcd_clk_source(channel);
3434
3435 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3436 dss_get_generic_clk_source_name(lcd_clk_src),
3437 dss_feat_get_clk_source_name(lcd_clk_src));
3438
3439 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3440
3441 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3442 dispc_mgr_lclk_rate(channel), lcd);
3443 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3444 dispc_mgr_pclk_rate(channel), pcd);
3445}
3446
3447void dispc_dump_clocks(struct seq_file *s)
3448{
3449 int lcd;
3450 u32 l;
3451 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3452
3453 if (dispc_runtime_get())
3454 return;
3455
3456 seq_printf(s, "- DISPC -\n");
3457
3458 seq_printf(s, "dispc fclk source = %s (%s)\n",
3459 dss_get_generic_clk_source_name(dispc_clk_src),
3460 dss_feat_get_clk_source_name(dispc_clk_src));
3461
3462 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3463
3464 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3465 seq_printf(s, "- DISPC-CORE-CLK -\n");
3466 l = dispc_read_reg(DISPC_DIVISOR);
3467 lcd = FLD_GET(l, 23, 16);
3468
3469 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3470 (dispc_fclk_rate()/lcd), lcd);
3471 }
3472
3473 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3474
3475 if (dss_has_feature(FEAT_MGR_LCD2))
3476 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3477 if (dss_has_feature(FEAT_MGR_LCD3))
3478 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3479
3480 dispc_runtime_put();
3481}
3482
3483static void dispc_dump_regs(struct seq_file *s)
3484{
3485 int i, j;
3486 const char *mgr_names[] = {
3487 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3488 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3489 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3490 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3491 };
3492 const char *ovl_names[] = {
3493 [OMAP_DSS_GFX] = "GFX",
3494 [OMAP_DSS_VIDEO1] = "VID1",
3495 [OMAP_DSS_VIDEO2] = "VID2",
3496 [OMAP_DSS_VIDEO3] = "VID3",
3497 [OMAP_DSS_WB] = "WB",
3498 };
3499 const char **p_names;
3500
3501#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3502
3503 if (dispc_runtime_get())
3504 return;
3505
3506 /* DISPC common registers */
3507 DUMPREG(DISPC_REVISION);
3508 DUMPREG(DISPC_SYSCONFIG);
3509 DUMPREG(DISPC_SYSSTATUS);
3510 DUMPREG(DISPC_IRQSTATUS);
3511 DUMPREG(DISPC_IRQENABLE);
3512 DUMPREG(DISPC_CONTROL);
3513 DUMPREG(DISPC_CONFIG);
3514 DUMPREG(DISPC_CAPABLE);
3515 DUMPREG(DISPC_LINE_STATUS);
3516 DUMPREG(DISPC_LINE_NUMBER);
3517 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3518 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3519 DUMPREG(DISPC_GLOBAL_ALPHA);
3520 if (dss_has_feature(FEAT_MGR_LCD2)) {
3521 DUMPREG(DISPC_CONTROL2);
3522 DUMPREG(DISPC_CONFIG2);
3523 }
3524 if (dss_has_feature(FEAT_MGR_LCD3)) {
3525 DUMPREG(DISPC_CONTROL3);
3526 DUMPREG(DISPC_CONFIG3);
3527 }
3528 if (dss_has_feature(FEAT_MFLAG))
3529 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3530
3531#undef DUMPREG
3532
3533#define DISPC_REG(i, name) name(i)
3534#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3535 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3536 dispc_read_reg(DISPC_REG(i, r)))
3537
3538 p_names = mgr_names;
3539
3540 /* DISPC channel specific registers */
3541 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3542 DUMPREG(i, DISPC_DEFAULT_COLOR);
3543 DUMPREG(i, DISPC_TRANS_COLOR);
3544 DUMPREG(i, DISPC_SIZE_MGR);
3545
3546 if (i == OMAP_DSS_CHANNEL_DIGIT)
3547 continue;
3548
3549 DUMPREG(i, DISPC_TIMING_H);
3550 DUMPREG(i, DISPC_TIMING_V);
3551 DUMPREG(i, DISPC_POL_FREQ);
3552 DUMPREG(i, DISPC_DIVISORo);
3553
3554 DUMPREG(i, DISPC_DATA_CYCLE1);
3555 DUMPREG(i, DISPC_DATA_CYCLE2);
3556 DUMPREG(i, DISPC_DATA_CYCLE3);
3557
3558 if (dss_has_feature(FEAT_CPR)) {
3559 DUMPREG(i, DISPC_CPR_COEF_R);
3560 DUMPREG(i, DISPC_CPR_COEF_G);
3561 DUMPREG(i, DISPC_CPR_COEF_B);
3562 }
3563 }
3564
3565 p_names = ovl_names;
3566
3567 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3568 DUMPREG(i, DISPC_OVL_BA0);
3569 DUMPREG(i, DISPC_OVL_BA1);
3570 DUMPREG(i, DISPC_OVL_POSITION);
3571 DUMPREG(i, DISPC_OVL_SIZE);
3572 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3573 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3574 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3575 DUMPREG(i, DISPC_OVL_ROW_INC);
3576 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3577
3578 if (dss_has_feature(FEAT_PRELOAD))
3579 DUMPREG(i, DISPC_OVL_PRELOAD);
3580 if (dss_has_feature(FEAT_MFLAG))
3581 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3582
3583 if (i == OMAP_DSS_GFX) {
3584 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3585 DUMPREG(i, DISPC_OVL_TABLE_BA);
3586 continue;
3587 }
3588
3589 DUMPREG(i, DISPC_OVL_FIR);
3590 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3591 DUMPREG(i, DISPC_OVL_ACCU0);
3592 DUMPREG(i, DISPC_OVL_ACCU1);
3593 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3594 DUMPREG(i, DISPC_OVL_BA0_UV);
3595 DUMPREG(i, DISPC_OVL_BA1_UV);
3596 DUMPREG(i, DISPC_OVL_FIR2);
3597 DUMPREG(i, DISPC_OVL_ACCU2_0);
3598 DUMPREG(i, DISPC_OVL_ACCU2_1);
3599 }
3600 if (dss_has_feature(FEAT_ATTR2))
3601 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3602 }
3603
3604 if (dispc.feat->has_writeback) {
3605 i = OMAP_DSS_WB;
3606 DUMPREG(i, DISPC_OVL_BA0);
3607 DUMPREG(i, DISPC_OVL_BA1);
3608 DUMPREG(i, DISPC_OVL_SIZE);
3609 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3610 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3611 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3612 DUMPREG(i, DISPC_OVL_ROW_INC);
3613 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3614
3615 if (dss_has_feature(FEAT_MFLAG))
3616 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3617
3618 DUMPREG(i, DISPC_OVL_FIR);
3619 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3620 DUMPREG(i, DISPC_OVL_ACCU0);
3621 DUMPREG(i, DISPC_OVL_ACCU1);
3622 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3623 DUMPREG(i, DISPC_OVL_BA0_UV);
3624 DUMPREG(i, DISPC_OVL_BA1_UV);
3625 DUMPREG(i, DISPC_OVL_FIR2);
3626 DUMPREG(i, DISPC_OVL_ACCU2_0);
3627 DUMPREG(i, DISPC_OVL_ACCU2_1);
3628 }
3629 if (dss_has_feature(FEAT_ATTR2))
3630 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3631 }
3632
3633#undef DISPC_REG
3634#undef DUMPREG
3635
3636#define DISPC_REG(plane, name, i) name(plane, i)
3637#define DUMPREG(plane, name, i) \
3638 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3639 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3640 dispc_read_reg(DISPC_REG(plane, name, i)))
3641
3642 /* Video pipeline coefficient registers */
3643
3644 /* start from OMAP_DSS_VIDEO1 */
3645 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3646 for (j = 0; j < 8; j++)
3647 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3648
3649 for (j = 0; j < 8; j++)
3650 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3651
3652 for (j = 0; j < 5; j++)
3653 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3654
3655 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3656 for (j = 0; j < 8; j++)
3657 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3658 }
3659
3660 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3661 for (j = 0; j < 8; j++)
3662 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3663
3664 for (j = 0; j < 8; j++)
3665 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3666
3667 for (j = 0; j < 8; j++)
3668 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3669 }
3670 }
3671
3672 dispc_runtime_put();
3673
3674#undef DISPC_REG
3675#undef DUMPREG
3676}
3677
3678/* calculate clock rates using dividers in cinfo */
3679int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3680 struct dispc_clock_info *cinfo)
3681{
3682 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3683 return -EINVAL;
3684 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3685 return -EINVAL;
3686
3687 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3688 cinfo->pck = cinfo->lck / cinfo->pck_div;
3689
3690 return 0;
3691}
3692
3693bool dispc_div_calc(unsigned long dispc,
3694 unsigned long pck_min, unsigned long pck_max,
3695 dispc_div_calc_func func, void *data)
3696{
3697 int lckd, lckd_start, lckd_stop;
3698 int pckd, pckd_start, pckd_stop;
3699 unsigned long pck, lck;
3700 unsigned long lck_max;
3701 unsigned long pckd_hw_min, pckd_hw_max;
3702 unsigned min_fck_per_pck;
3703 unsigned long fck;
3704
3705#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3706 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3707#else
3708 min_fck_per_pck = 0;
3709#endif
3710
3711 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3712 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3713
3714 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3715
3716 pck_min = pck_min ? pck_min : 1;
3717 pck_max = pck_max ? pck_max : ULONG_MAX;
3718
3719 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3720 lckd_stop = min(dispc / pck_min, 255ul);
3721
3722 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3723 lck = dispc / lckd;
3724
3725 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3726 pckd_stop = min(lck / pck_min, pckd_hw_max);
3727
3728 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3729 pck = lck / pckd;
3730
3731 /*
3732 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3733 * clock, which means we're configuring DISPC fclk here
3734 * also. Thus we need to use the calculated lck. For
3735 * OMAP4+ the DISPC fclk is a separate clock.
3736 */
3737 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3738 fck = dispc_core_clk_rate();
3739 else
3740 fck = lck;
3741
3742 if (fck < pck * min_fck_per_pck)
3743 continue;
3744
3745 if (func(lckd, pckd, lck, pck, data))
3746 return true;
3747 }
3748 }
3749
3750 return false;
3751}
3752
3753void dispc_mgr_set_clock_div(enum omap_channel channel,
3754 const struct dispc_clock_info *cinfo)
3755{
3756 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3757 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3758
3759 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3760}
3761
3762int dispc_mgr_get_clock_div(enum omap_channel channel,
3763 struct dispc_clock_info *cinfo)
3764{
3765 unsigned long fck;
3766
3767 fck = dispc_fclk_rate();
3768
3769 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3770 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3771
3772 cinfo->lck = fck / cinfo->lck_div;
3773 cinfo->pck = cinfo->lck / cinfo->pck_div;
3774
3775 return 0;
3776}
3777
3778u32 dispc_read_irqstatus(void)
3779{
3780 return dispc_read_reg(DISPC_IRQSTATUS);
3781}
3782EXPORT_SYMBOL(dispc_read_irqstatus);
3783
3784void dispc_clear_irqstatus(u32 mask)
3785{
3786 dispc_write_reg(DISPC_IRQSTATUS, mask);
3787}
3788EXPORT_SYMBOL(dispc_clear_irqstatus);
3789
3790u32 dispc_read_irqenable(void)
3791{
3792 return dispc_read_reg(DISPC_IRQENABLE);
3793}
3794EXPORT_SYMBOL(dispc_read_irqenable);
3795
3796void dispc_write_irqenable(u32 mask)
3797{
3798 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3799
3800 /* clear the irqstatus for newly enabled irqs */
3801 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3802
3803 dispc_write_reg(DISPC_IRQENABLE, mask);
3804}
3805EXPORT_SYMBOL(dispc_write_irqenable);
3806
3807void dispc_enable_sidle(void)
3808{
3809 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3810}
3811
3812void dispc_disable_sidle(void)
3813{
3814 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3815}
3816
3817static void _omap_dispc_initial_config(void)
3818{
3819 u32 l;
3820
3821 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3822 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3823 l = dispc_read_reg(DISPC_DIVISOR);
3824 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3825 l = FLD_MOD(l, 1, 0, 0);
3826 l = FLD_MOD(l, 1, 23, 16);
3827 dispc_write_reg(DISPC_DIVISOR, l);
3828
3829 dispc.core_clk_rate = dispc_fclk_rate();
3830 }
3831
3832 /* FUNCGATED */
3833 if (dss_has_feature(FEAT_FUNCGATED))
3834 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3835
3836 dispc_setup_color_conv_coef();
3837
3838 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3839
3840 dispc_init_fifos();
3841
3842 dispc_configure_burst_sizes();
3843
3844 dispc_ovl_enable_zorder_planes();
3845
3846 if (dispc.feat->mstandby_workaround)
3847 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3848
3849 if (dss_has_feature(FEAT_MFLAG))
3850 dispc_init_mflag();
3851}
3852
3853static const struct dispc_features omap24xx_dispc_feats = {
3854 .sw_start = 5,
3855 .fp_start = 15,
3856 .bp_start = 27,
3857 .sw_max = 64,
3858 .vp_max = 255,
3859 .hp_max = 256,
3860 .mgr_width_start = 10,
3861 .mgr_height_start = 26,
3862 .mgr_width_max = 2048,
3863 .mgr_height_max = 2048,
3864 .max_lcd_pclk = 66500000,
3865 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3866 .calc_core_clk = calc_core_clk_24xx,
3867 .num_fifos = 3,
3868 .no_framedone_tv = true,
3869 .set_max_preload = false,
3870 .last_pixel_inc_missing = true,
3871};
3872
3873static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3874 .sw_start = 5,
3875 .fp_start = 15,
3876 .bp_start = 27,
3877 .sw_max = 64,
3878 .vp_max = 255,
3879 .hp_max = 256,
3880 .mgr_width_start = 10,
3881 .mgr_height_start = 26,
3882 .mgr_width_max = 2048,
3883 .mgr_height_max = 2048,
3884 .max_lcd_pclk = 173000000,
3885 .max_tv_pclk = 59000000,
3886 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3887 .calc_core_clk = calc_core_clk_34xx,
3888 .num_fifos = 3,
3889 .no_framedone_tv = true,
3890 .set_max_preload = false,
3891 .last_pixel_inc_missing = true,
3892};
3893
3894static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3895 .sw_start = 7,
3896 .fp_start = 19,
3897 .bp_start = 31,
3898 .sw_max = 256,
3899 .vp_max = 4095,
3900 .hp_max = 4096,
3901 .mgr_width_start = 10,
3902 .mgr_height_start = 26,
3903 .mgr_width_max = 2048,
3904 .mgr_height_max = 2048,
3905 .max_lcd_pclk = 173000000,
3906 .max_tv_pclk = 59000000,
3907 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3908 .calc_core_clk = calc_core_clk_34xx,
3909 .num_fifos = 3,
3910 .no_framedone_tv = true,
3911 .set_max_preload = false,
3912 .last_pixel_inc_missing = true,
3913};
3914
3915static const struct dispc_features omap44xx_dispc_feats = {
3916 .sw_start = 7,
3917 .fp_start = 19,
3918 .bp_start = 31,
3919 .sw_max = 256,
3920 .vp_max = 4095,
3921 .hp_max = 4096,
3922 .mgr_width_start = 10,
3923 .mgr_height_start = 26,
3924 .mgr_width_max = 2048,
3925 .mgr_height_max = 2048,
3926 .max_lcd_pclk = 170000000,
3927 .max_tv_pclk = 185625000,
3928 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3929 .calc_core_clk = calc_core_clk_44xx,
3930 .num_fifos = 5,
3931 .gfx_fifo_workaround = true,
3932 .set_max_preload = true,
3933 .supports_sync_align = true,
3934 .has_writeback = true,
3935 .supports_double_pixel = true,
3936 .reverse_ilace_field_order = true,
3937};
3938
3939static const struct dispc_features omap54xx_dispc_feats = {
3940 .sw_start = 7,
3941 .fp_start = 19,
3942 .bp_start = 31,
3943 .sw_max = 256,
3944 .vp_max = 4095,
3945 .hp_max = 4096,
3946 .mgr_width_start = 11,
3947 .mgr_height_start = 27,
3948 .mgr_width_max = 4096,
3949 .mgr_height_max = 4096,
3950 .max_lcd_pclk = 170000000,
3951 .max_tv_pclk = 186000000,
3952 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3953 .calc_core_clk = calc_core_clk_44xx,
3954 .num_fifos = 5,
3955 .gfx_fifo_workaround = true,
3956 .mstandby_workaround = true,
3957 .set_max_preload = true,
3958 .supports_sync_align = true,
3959 .has_writeback = true,
3960 .supports_double_pixel = true,
3961 .reverse_ilace_field_order = true,
3962};
3963
3964static int dispc_init_features(struct platform_device *pdev)
3965{
3966 const struct dispc_features *src;
3967 struct dispc_features *dst;
3968
3969 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3970 if (!dst) {
3971 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3972 return -ENOMEM;
3973 }
3974
3975 switch (omapdss_get_version()) {
3976 case OMAPDSS_VER_OMAP24xx:
3977 src = &omap24xx_dispc_feats;
3978 break;
3979
3980 case OMAPDSS_VER_OMAP34xx_ES1:
3981 src = &omap34xx_rev1_0_dispc_feats;
3982 break;
3983
3984 case OMAPDSS_VER_OMAP34xx_ES3:
3985 case OMAPDSS_VER_OMAP3630:
3986 case OMAPDSS_VER_AM35xx:
3987 case OMAPDSS_VER_AM43xx:
3988 src = &omap34xx_rev3_0_dispc_feats;
3989 break;
3990
3991 case OMAPDSS_VER_OMAP4430_ES1:
3992 case OMAPDSS_VER_OMAP4430_ES2:
3993 case OMAPDSS_VER_OMAP4:
3994 src = &omap44xx_dispc_feats;
3995 break;
3996
3997 case OMAPDSS_VER_OMAP5:
3998 case OMAPDSS_VER_DRA7xx:
3999 src = &omap54xx_dispc_feats;
4000 break;
4001
4002 default:
4003 return -ENODEV;
4004 }
4005
4006 memcpy(dst, src, sizeof(*dst));
4007 dispc.feat = dst;
4008
4009 return 0;
4010}
4011
4012static irqreturn_t dispc_irq_handler(int irq, void *arg)
4013{
4014 if (!dispc.is_enabled)
4015 return IRQ_NONE;
4016
4017 return dispc.user_handler(irq, dispc.user_data);
4018}
4019
4020int dispc_request_irq(irq_handler_t handler, void *dev_id)
4021{
4022 int r;
4023
4024 if (dispc.user_handler != NULL)
4025 return -EBUSY;
4026
4027 dispc.user_handler = handler;
4028 dispc.user_data = dev_id;
4029
4030 /* ensure the dispc_irq_handler sees the values above */
4031 smp_wmb();
4032
4033 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4034 IRQF_SHARED, "OMAP DISPC", &dispc);
4035 if (r) {
4036 dispc.user_handler = NULL;
4037 dispc.user_data = NULL;
4038 }
4039
4040 return r;
4041}
4042EXPORT_SYMBOL(dispc_request_irq);
4043
4044void dispc_free_irq(void *dev_id)
4045{
4046 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4047
4048 dispc.user_handler = NULL;
4049 dispc.user_data = NULL;
4050}
4051EXPORT_SYMBOL(dispc_free_irq);
4052
4053/* DISPC HW IP initialisation */
4054static int dispc_bind(struct device *dev, struct device *master, void *data)
4055{
4056 struct platform_device *pdev = to_platform_device(dev);
4057 u32 rev;
4058 int r = 0;
4059 struct resource *dispc_mem;
4060 struct device_node *np = pdev->dev.of_node;
4061
4062 dispc.pdev = pdev;
4063
4064 spin_lock_init(&dispc.control_lock);
4065
4066 r = dispc_init_features(dispc.pdev);
4067 if (r)
4068 return r;
4069
4070 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4071 if (!dispc_mem) {
4072 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4073 return -EINVAL;
4074 }
4075
4076 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4077 resource_size(dispc_mem));
4078 if (!dispc.base) {
4079 DSSERR("can't ioremap DISPC\n");
4080 return -ENOMEM;
4081 }
4082
4083 dispc.irq = platform_get_irq(dispc.pdev, 0);
4084 if (dispc.irq < 0) {
4085 DSSERR("platform_get_irq failed\n");
4086 return -ENODEV;
4087 }
4088
4089 if (np && of_property_read_bool(np, "syscon-pol")) {
4090 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4091 if (IS_ERR(dispc.syscon_pol)) {
4092 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4093 return PTR_ERR(dispc.syscon_pol);
4094 }
4095
4096 if (of_property_read_u32_index(np, "syscon-pol", 1,
4097 &dispc.syscon_pol_offset)) {
4098 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4099 return -EINVAL;
4100 }
4101 }
4102
4103 pm_runtime_enable(&pdev->dev);
4104
4105 r = dispc_runtime_get();
4106 if (r)
4107 goto err_runtime_get;
4108
4109 _omap_dispc_initial_config();
4110
4111 rev = dispc_read_reg(DISPC_REVISION);
4112 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4113 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4114
4115 dispc_runtime_put();
4116
4117 dss_debugfs_create_file("dispc", dispc_dump_regs);
4118
4119 return 0;
4120
4121err_runtime_get:
4122 pm_runtime_disable(&pdev->dev);
4123 return r;
4124}
4125
4126static void dispc_unbind(struct device *dev, struct device *master,
4127 void *data)
4128{
4129 pm_runtime_disable(dev);
4130}
4131
4132static const struct component_ops dispc_component_ops = {
4133 .bind = dispc_bind,
4134 .unbind = dispc_unbind,
4135};
4136
4137static int dispc_probe(struct platform_device *pdev)
4138{
4139 return component_add(&pdev->dev, &dispc_component_ops);
4140}
4141
4142static int dispc_remove(struct platform_device *pdev)
4143{
4144 component_del(&pdev->dev, &dispc_component_ops);
4145 return 0;
4146}
4147
4148static int dispc_runtime_suspend(struct device *dev)
4149{
4150 dispc.is_enabled = false;
4151 /* ensure the dispc_irq_handler sees the is_enabled value */
4152 smp_wmb();
4153 /* wait for current handler to finish before turning the DISPC off */
4154 synchronize_irq(dispc.irq);
4155
4156 dispc_save_context();
4157
4158 return 0;
4159}
4160
4161static int dispc_runtime_resume(struct device *dev)
4162{
4163 /*
4164 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4165 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4166 * _omap_dispc_initial_config(). We can thus use it to detect if
4167 * we have lost register context.
4168 */
4169 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4170 _omap_dispc_initial_config();
4171
4172 dispc_restore_context();
4173 }
4174
4175 dispc.is_enabled = true;
4176 /* ensure the dispc_irq_handler sees the is_enabled value */
4177 smp_wmb();
4178
4179 return 0;
4180}
4181
4182static const struct dev_pm_ops dispc_pm_ops = {
4183 .runtime_suspend = dispc_runtime_suspend,
4184 .runtime_resume = dispc_runtime_resume,
4185};
4186
4187static const struct of_device_id dispc_of_match[] = {
4188 { .compatible = "ti,omap2-dispc", },
4189 { .compatible = "ti,omap3-dispc", },
4190 { .compatible = "ti,omap4-dispc", },
4191 { .compatible = "ti,omap5-dispc", },
4192 { .compatible = "ti,dra7-dispc", },
4193 {},
4194};
4195
4196static struct platform_driver omap_dispchw_driver = {
4197 .probe = dispc_probe,
4198 .remove = dispc_remove,
4199 .driver = {
4200 .name = "omapdss_dispc",
4201 .pm = &dispc_pm_ops,
4202 .of_match_table = dispc_of_match,
4203 .suppress_bind_attrs = true,
4204 },
4205};
4206
4207int __init dispc_init_platform_driver(void)
4208{
4209 return platform_driver_register(&omap_dispchw_driver);
4210}
4211
4212void dispc_uninit_platform_driver(void)
4213{
4214 platform_driver_unregister(&omap_dispchw_driver);
4215}
1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/export.h>
29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
35#include <linux/hardirq.h>
36#include <linux/platform_device.h>
37#include <linux/pm_runtime.h>
38#include <linux/sizes.h>
39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
42#include <linux/component.h>
43
44#include "omapdss.h"
45#include "dss.h"
46#include "dss_features.h"
47#include "dispc.h"
48
49/* DISPC */
50#define DISPC_SZ_REGS SZ_4K
51
52enum omap_burst_size {
53 BURST_SIZE_X2 = 0,
54 BURST_SIZE_X4 = 1,
55 BURST_SIZE_X8 = 2,
56};
57
58#define REG_GET(idx, start, end) \
59 FLD_GET(dispc_read_reg(idx), start, end)
60
61#define REG_FLD_MOD(idx, val, start, end) \
62 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
63
64struct dispc_features {
65 u8 sw_start;
66 u8 fp_start;
67 u8 bp_start;
68 u16 sw_max;
69 u16 vp_max;
70 u16 hp_max;
71 u8 mgr_width_start;
72 u8 mgr_height_start;
73 u16 mgr_width_max;
74 u16 mgr_height_max;
75 unsigned long max_lcd_pclk;
76 unsigned long max_tv_pclk;
77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
78 const struct videomode *vm,
79 u16 width, u16 height, u16 out_width, u16 out_height,
80 enum omap_color_mode color_mode, bool *five_taps,
81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
82 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
83 unsigned long (*calc_core_clk) (unsigned long pclk,
84 u16 width, u16 height, u16 out_width, u16 out_height,
85 bool mem_to_mem);
86 u8 num_fifos;
87
88 /* swap GFX & WB fifos */
89 bool gfx_fifo_workaround:1;
90
91 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
92 bool no_framedone_tv:1;
93
94 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
95 bool mstandby_workaround:1;
96
97 bool set_max_preload:1;
98
99 /* PIXEL_INC is not added to the last pixel of a line */
100 bool last_pixel_inc_missing:1;
101
102 /* POL_FREQ has ALIGN bit */
103 bool supports_sync_align:1;
104
105 bool has_writeback:1;
106
107 bool supports_double_pixel:1;
108
109 /*
110 * Field order for VENC is different than HDMI. We should handle this in
111 * some intelligent manner, but as the SoCs have either HDMI or VENC,
112 * never both, we can just use this flag for now.
113 */
114 bool reverse_ilace_field_order:1;
115
116 bool has_gamma_table:1;
117
118 bool has_gamma_i734_bug:1;
119};
120
121#define DISPC_MAX_NR_FIFOS 5
122#define DISPC_MAX_CHANNEL_GAMMA 4
123
124static struct {
125 struct platform_device *pdev;
126 void __iomem *base;
127
128 int irq;
129 irq_handler_t user_handler;
130 void *user_data;
131
132 unsigned long core_clk_rate;
133 unsigned long tv_pclk_rate;
134
135 u32 fifo_size[DISPC_MAX_NR_FIFOS];
136 /* maps which plane is using a fifo. fifo-id -> plane-id */
137 int fifo_assignment[DISPC_MAX_NR_FIFOS];
138
139 bool ctx_valid;
140 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
141
142 u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA];
143
144 const struct dispc_features *feat;
145
146 bool is_enabled;
147
148 struct regmap *syscon_pol;
149 u32 syscon_pol_offset;
150
151 /* DISPC_CONTROL & DISPC_CONFIG lock*/
152 spinlock_t control_lock;
153} dispc;
154
155enum omap_color_component {
156 /* used for all color formats for OMAP3 and earlier
157 * and for RGB and Y color component on OMAP4
158 */
159 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
160 /* used for UV component for
161 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
162 * color formats on OMAP4
163 */
164 DISPC_COLOR_COMPONENT_UV = 1 << 1,
165};
166
167enum mgr_reg_fields {
168 DISPC_MGR_FLD_ENABLE,
169 DISPC_MGR_FLD_STNTFT,
170 DISPC_MGR_FLD_GO,
171 DISPC_MGR_FLD_TFTDATALINES,
172 DISPC_MGR_FLD_STALLMODE,
173 DISPC_MGR_FLD_TCKENABLE,
174 DISPC_MGR_FLD_TCKSELECTION,
175 DISPC_MGR_FLD_CPR,
176 DISPC_MGR_FLD_FIFOHANDCHECK,
177 /* used to maintain a count of the above fields */
178 DISPC_MGR_FLD_NUM,
179};
180
181struct dispc_reg_field {
182 u16 reg;
183 u8 high;
184 u8 low;
185};
186
187struct dispc_gamma_desc {
188 u32 len;
189 u32 bits;
190 u16 reg;
191 bool has_index;
192};
193
194static const struct {
195 const char *name;
196 u32 vsync_irq;
197 u32 framedone_irq;
198 u32 sync_lost_irq;
199 struct dispc_gamma_desc gamma;
200 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
201} mgr_desc[] = {
202 [OMAP_DSS_CHANNEL_LCD] = {
203 .name = "LCD",
204 .vsync_irq = DISPC_IRQ_VSYNC,
205 .framedone_irq = DISPC_IRQ_FRAMEDONE,
206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
207 .gamma = {
208 .len = 256,
209 .bits = 8,
210 .reg = DISPC_GAMMA_TABLE0,
211 .has_index = true,
212 },
213 .reg_desc = {
214 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
215 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
216 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
217 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
218 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
219 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
220 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
221 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
222 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
223 },
224 },
225 [OMAP_DSS_CHANNEL_DIGIT] = {
226 .name = "DIGIT",
227 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
228 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
229 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
230 .gamma = {
231 .len = 1024,
232 .bits = 10,
233 .reg = DISPC_GAMMA_TABLE2,
234 .has_index = false,
235 },
236 .reg_desc = {
237 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
238 [DISPC_MGR_FLD_STNTFT] = { },
239 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
240 [DISPC_MGR_FLD_TFTDATALINES] = { },
241 [DISPC_MGR_FLD_STALLMODE] = { },
242 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
243 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
244 [DISPC_MGR_FLD_CPR] = { },
245 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
246 },
247 },
248 [OMAP_DSS_CHANNEL_LCD2] = {
249 .name = "LCD2",
250 .vsync_irq = DISPC_IRQ_VSYNC2,
251 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
252 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
253 .gamma = {
254 .len = 256,
255 .bits = 8,
256 .reg = DISPC_GAMMA_TABLE1,
257 .has_index = true,
258 },
259 .reg_desc = {
260 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
261 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
262 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
263 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
264 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
265 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
266 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
267 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
268 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
269 },
270 },
271 [OMAP_DSS_CHANNEL_LCD3] = {
272 .name = "LCD3",
273 .vsync_irq = DISPC_IRQ_VSYNC3,
274 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
275 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
276 .gamma = {
277 .len = 256,
278 .bits = 8,
279 .reg = DISPC_GAMMA_TABLE3,
280 .has_index = true,
281 },
282 .reg_desc = {
283 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
284 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
285 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
286 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
287 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
288 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
289 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
290 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
291 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
292 },
293 },
294};
295
296struct color_conv_coef {
297 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
298 int full_range;
299};
300
301static unsigned long dispc_fclk_rate(void);
302static unsigned long dispc_core_clk_rate(void);
303static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
304static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
305
306static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
307static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
308
309static inline void dispc_write_reg(const u16 idx, u32 val)
310{
311 __raw_writel(val, dispc.base + idx);
312}
313
314static inline u32 dispc_read_reg(const u16 idx)
315{
316 return __raw_readl(dispc.base + idx);
317}
318
319static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
320{
321 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
322 return REG_GET(rfld.reg, rfld.high, rfld.low);
323}
324
325static void mgr_fld_write(enum omap_channel channel,
326 enum mgr_reg_fields regfld, int val) {
327 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
328 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
329 unsigned long flags;
330
331 if (need_lock)
332 spin_lock_irqsave(&dispc.control_lock, flags);
333
334 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
335
336 if (need_lock)
337 spin_unlock_irqrestore(&dispc.control_lock, flags);
338}
339
340#define SR(reg) \
341 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
342#define RR(reg) \
343 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
344
345static void dispc_save_context(void)
346{
347 int i, j;
348
349 DSSDBG("dispc_save_context\n");
350
351 SR(IRQENABLE);
352 SR(CONTROL);
353 SR(CONFIG);
354 SR(LINE_NUMBER);
355 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
356 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
357 SR(GLOBAL_ALPHA);
358 if (dss_has_feature(FEAT_MGR_LCD2)) {
359 SR(CONTROL2);
360 SR(CONFIG2);
361 }
362 if (dss_has_feature(FEAT_MGR_LCD3)) {
363 SR(CONTROL3);
364 SR(CONFIG3);
365 }
366
367 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
368 SR(DEFAULT_COLOR(i));
369 SR(TRANS_COLOR(i));
370 SR(SIZE_MGR(i));
371 if (i == OMAP_DSS_CHANNEL_DIGIT)
372 continue;
373 SR(TIMING_H(i));
374 SR(TIMING_V(i));
375 SR(POL_FREQ(i));
376 SR(DIVISORo(i));
377
378 SR(DATA_CYCLE1(i));
379 SR(DATA_CYCLE2(i));
380 SR(DATA_CYCLE3(i));
381
382 if (dss_has_feature(FEAT_CPR)) {
383 SR(CPR_COEF_R(i));
384 SR(CPR_COEF_G(i));
385 SR(CPR_COEF_B(i));
386 }
387 }
388
389 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
390 SR(OVL_BA0(i));
391 SR(OVL_BA1(i));
392 SR(OVL_POSITION(i));
393 SR(OVL_SIZE(i));
394 SR(OVL_ATTRIBUTES(i));
395 SR(OVL_FIFO_THRESHOLD(i));
396 SR(OVL_ROW_INC(i));
397 SR(OVL_PIXEL_INC(i));
398 if (dss_has_feature(FEAT_PRELOAD))
399 SR(OVL_PRELOAD(i));
400 if (i == OMAP_DSS_GFX) {
401 SR(OVL_WINDOW_SKIP(i));
402 SR(OVL_TABLE_BA(i));
403 continue;
404 }
405 SR(OVL_FIR(i));
406 SR(OVL_PICTURE_SIZE(i));
407 SR(OVL_ACCU0(i));
408 SR(OVL_ACCU1(i));
409
410 for (j = 0; j < 8; j++)
411 SR(OVL_FIR_COEF_H(i, j));
412
413 for (j = 0; j < 8; j++)
414 SR(OVL_FIR_COEF_HV(i, j));
415
416 for (j = 0; j < 5; j++)
417 SR(OVL_CONV_COEF(i, j));
418
419 if (dss_has_feature(FEAT_FIR_COEF_V)) {
420 for (j = 0; j < 8; j++)
421 SR(OVL_FIR_COEF_V(i, j));
422 }
423
424 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
425 SR(OVL_BA0_UV(i));
426 SR(OVL_BA1_UV(i));
427 SR(OVL_FIR2(i));
428 SR(OVL_ACCU2_0(i));
429 SR(OVL_ACCU2_1(i));
430
431 for (j = 0; j < 8; j++)
432 SR(OVL_FIR_COEF_H2(i, j));
433
434 for (j = 0; j < 8; j++)
435 SR(OVL_FIR_COEF_HV2(i, j));
436
437 for (j = 0; j < 8; j++)
438 SR(OVL_FIR_COEF_V2(i, j));
439 }
440 if (dss_has_feature(FEAT_ATTR2))
441 SR(OVL_ATTRIBUTES2(i));
442 }
443
444 if (dss_has_feature(FEAT_CORE_CLK_DIV))
445 SR(DIVISOR);
446
447 dispc.ctx_valid = true;
448
449 DSSDBG("context saved\n");
450}
451
452static void dispc_restore_context(void)
453{
454 int i, j;
455
456 DSSDBG("dispc_restore_context\n");
457
458 if (!dispc.ctx_valid)
459 return;
460
461 /*RR(IRQENABLE);*/
462 /*RR(CONTROL);*/
463 RR(CONFIG);
464 RR(LINE_NUMBER);
465 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
466 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
467 RR(GLOBAL_ALPHA);
468 if (dss_has_feature(FEAT_MGR_LCD2))
469 RR(CONFIG2);
470 if (dss_has_feature(FEAT_MGR_LCD3))
471 RR(CONFIG3);
472
473 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
474 RR(DEFAULT_COLOR(i));
475 RR(TRANS_COLOR(i));
476 RR(SIZE_MGR(i));
477 if (i == OMAP_DSS_CHANNEL_DIGIT)
478 continue;
479 RR(TIMING_H(i));
480 RR(TIMING_V(i));
481 RR(POL_FREQ(i));
482 RR(DIVISORo(i));
483
484 RR(DATA_CYCLE1(i));
485 RR(DATA_CYCLE2(i));
486 RR(DATA_CYCLE3(i));
487
488 if (dss_has_feature(FEAT_CPR)) {
489 RR(CPR_COEF_R(i));
490 RR(CPR_COEF_G(i));
491 RR(CPR_COEF_B(i));
492 }
493 }
494
495 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
496 RR(OVL_BA0(i));
497 RR(OVL_BA1(i));
498 RR(OVL_POSITION(i));
499 RR(OVL_SIZE(i));
500 RR(OVL_ATTRIBUTES(i));
501 RR(OVL_FIFO_THRESHOLD(i));
502 RR(OVL_ROW_INC(i));
503 RR(OVL_PIXEL_INC(i));
504 if (dss_has_feature(FEAT_PRELOAD))
505 RR(OVL_PRELOAD(i));
506 if (i == OMAP_DSS_GFX) {
507 RR(OVL_WINDOW_SKIP(i));
508 RR(OVL_TABLE_BA(i));
509 continue;
510 }
511 RR(OVL_FIR(i));
512 RR(OVL_PICTURE_SIZE(i));
513 RR(OVL_ACCU0(i));
514 RR(OVL_ACCU1(i));
515
516 for (j = 0; j < 8; j++)
517 RR(OVL_FIR_COEF_H(i, j));
518
519 for (j = 0; j < 8; j++)
520 RR(OVL_FIR_COEF_HV(i, j));
521
522 for (j = 0; j < 5; j++)
523 RR(OVL_CONV_COEF(i, j));
524
525 if (dss_has_feature(FEAT_FIR_COEF_V)) {
526 for (j = 0; j < 8; j++)
527 RR(OVL_FIR_COEF_V(i, j));
528 }
529
530 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
531 RR(OVL_BA0_UV(i));
532 RR(OVL_BA1_UV(i));
533 RR(OVL_FIR2(i));
534 RR(OVL_ACCU2_0(i));
535 RR(OVL_ACCU2_1(i));
536
537 for (j = 0; j < 8; j++)
538 RR(OVL_FIR_COEF_H2(i, j));
539
540 for (j = 0; j < 8; j++)
541 RR(OVL_FIR_COEF_HV2(i, j));
542
543 for (j = 0; j < 8; j++)
544 RR(OVL_FIR_COEF_V2(i, j));
545 }
546 if (dss_has_feature(FEAT_ATTR2))
547 RR(OVL_ATTRIBUTES2(i));
548 }
549
550 if (dss_has_feature(FEAT_CORE_CLK_DIV))
551 RR(DIVISOR);
552
553 /* enable last, because LCD & DIGIT enable are here */
554 RR(CONTROL);
555 if (dss_has_feature(FEAT_MGR_LCD2))
556 RR(CONTROL2);
557 if (dss_has_feature(FEAT_MGR_LCD3))
558 RR(CONTROL3);
559 /* clear spurious SYNC_LOST_DIGIT interrupts */
560 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
561
562 /*
563 * enable last so IRQs won't trigger before
564 * the context is fully restored
565 */
566 RR(IRQENABLE);
567
568 DSSDBG("context restored\n");
569}
570
571#undef SR
572#undef RR
573
574int dispc_runtime_get(void)
575{
576 int r;
577
578 DSSDBG("dispc_runtime_get\n");
579
580 r = pm_runtime_get_sync(&dispc.pdev->dev);
581 WARN_ON(r < 0);
582 return r < 0 ? r : 0;
583}
584EXPORT_SYMBOL(dispc_runtime_get);
585
586void dispc_runtime_put(void)
587{
588 int r;
589
590 DSSDBG("dispc_runtime_put\n");
591
592 r = pm_runtime_put_sync(&dispc.pdev->dev);
593 WARN_ON(r < 0 && r != -ENOSYS);
594}
595EXPORT_SYMBOL(dispc_runtime_put);
596
597u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
598{
599 return mgr_desc[channel].vsync_irq;
600}
601EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
602
603u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
604{
605 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
606 return 0;
607
608 return mgr_desc[channel].framedone_irq;
609}
610EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
611
612u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
613{
614 return mgr_desc[channel].sync_lost_irq;
615}
616EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
617
618u32 dispc_wb_get_framedone_irq(void)
619{
620 return DISPC_IRQ_FRAMEDONEWB;
621}
622
623bool dispc_mgr_go_busy(enum omap_channel channel)
624{
625 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
626}
627EXPORT_SYMBOL(dispc_mgr_go_busy);
628
629void dispc_mgr_go(enum omap_channel channel)
630{
631 WARN_ON(!dispc_mgr_is_enabled(channel));
632 WARN_ON(dispc_mgr_go_busy(channel));
633
634 DSSDBG("GO %s\n", mgr_desc[channel].name);
635
636 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
637}
638EXPORT_SYMBOL(dispc_mgr_go);
639
640bool dispc_wb_go_busy(void)
641{
642 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
643}
644
645void dispc_wb_go(void)
646{
647 enum omap_plane plane = OMAP_DSS_WB;
648 bool enable, go;
649
650 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
651
652 if (!enable)
653 return;
654
655 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
656 if (go) {
657 DSSERR("GO bit not down for WB\n");
658 return;
659 }
660
661 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
662}
663
664static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
665{
666 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
667}
668
669static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
670{
671 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
672}
673
674static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
675{
676 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
677}
678
679static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
680{
681 BUG_ON(plane == OMAP_DSS_GFX);
682
683 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
684}
685
686static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
687 u32 value)
688{
689 BUG_ON(plane == OMAP_DSS_GFX);
690
691 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
692}
693
694static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
695{
696 BUG_ON(plane == OMAP_DSS_GFX);
697
698 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
699}
700
701static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
702 int fir_vinc, int five_taps,
703 enum omap_color_component color_comp)
704{
705 const struct dispc_coef *h_coef, *v_coef;
706 int i;
707
708 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
709 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
710
711 for (i = 0; i < 8; i++) {
712 u32 h, hv;
713
714 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
715 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
716 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
717 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
718 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
719 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
720 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
721 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
722
723 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
724 dispc_ovl_write_firh_reg(plane, i, h);
725 dispc_ovl_write_firhv_reg(plane, i, hv);
726 } else {
727 dispc_ovl_write_firh2_reg(plane, i, h);
728 dispc_ovl_write_firhv2_reg(plane, i, hv);
729 }
730
731 }
732
733 if (five_taps) {
734 for (i = 0; i < 8; i++) {
735 u32 v;
736 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
737 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
738 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
739 dispc_ovl_write_firv_reg(plane, i, v);
740 else
741 dispc_ovl_write_firv2_reg(plane, i, v);
742 }
743 }
744}
745
746
747static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
748 const struct color_conv_coef *ct)
749{
750#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
751
752 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
753 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
754 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
755 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
756 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
757
758 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
759
760#undef CVAL
761}
762
763static void dispc_setup_color_conv_coef(void)
764{
765 int i;
766 int num_ovl = dss_feat_get_num_ovls();
767 const struct color_conv_coef ctbl_bt601_5_ovl = {
768 /* YUV -> RGB */
769 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
770 };
771 const struct color_conv_coef ctbl_bt601_5_wb = {
772 /* RGB -> YUV */
773 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
774 };
775
776 for (i = 1; i < num_ovl; i++)
777 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
778
779 if (dispc.feat->has_writeback)
780 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
781}
782
783static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
784{
785 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
786}
787
788static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
789{
790 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
791}
792
793static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
794{
795 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
796}
797
798static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
799{
800 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
801}
802
803static void dispc_ovl_set_pos(enum omap_plane plane,
804 enum omap_overlay_caps caps, int x, int y)
805{
806 u32 val;
807
808 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
809 return;
810
811 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
812
813 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
814}
815
816static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
817 int height)
818{
819 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
820
821 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
822 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
823 else
824 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
825}
826
827static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
828 int height)
829{
830 u32 val;
831
832 BUG_ON(plane == OMAP_DSS_GFX);
833
834 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
835
836 if (plane == OMAP_DSS_WB)
837 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
838 else
839 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
840}
841
842static void dispc_ovl_set_zorder(enum omap_plane plane,
843 enum omap_overlay_caps caps, u8 zorder)
844{
845 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
846 return;
847
848 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
849}
850
851static void dispc_ovl_enable_zorder_planes(void)
852{
853 int i;
854
855 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
856 return;
857
858 for (i = 0; i < dss_feat_get_num_ovls(); i++)
859 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
860}
861
862static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
863 enum omap_overlay_caps caps, bool enable)
864{
865 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
866 return;
867
868 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
869}
870
871static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
872 enum omap_overlay_caps caps, u8 global_alpha)
873{
874 static const unsigned shifts[] = { 0, 8, 16, 24, };
875 int shift;
876
877 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
878 return;
879
880 shift = shifts[plane];
881 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
882}
883
884static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
885{
886 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
887}
888
889static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
890{
891 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
892}
893
894static void dispc_ovl_set_color_mode(enum omap_plane plane,
895 enum omap_color_mode color_mode)
896{
897 u32 m = 0;
898 if (plane != OMAP_DSS_GFX) {
899 switch (color_mode) {
900 case OMAP_DSS_COLOR_NV12:
901 m = 0x0; break;
902 case OMAP_DSS_COLOR_RGBX16:
903 m = 0x1; break;
904 case OMAP_DSS_COLOR_RGBA16:
905 m = 0x2; break;
906 case OMAP_DSS_COLOR_RGB12U:
907 m = 0x4; break;
908 case OMAP_DSS_COLOR_ARGB16:
909 m = 0x5; break;
910 case OMAP_DSS_COLOR_RGB16:
911 m = 0x6; break;
912 case OMAP_DSS_COLOR_ARGB16_1555:
913 m = 0x7; break;
914 case OMAP_DSS_COLOR_RGB24U:
915 m = 0x8; break;
916 case OMAP_DSS_COLOR_RGB24P:
917 m = 0x9; break;
918 case OMAP_DSS_COLOR_YUV2:
919 m = 0xa; break;
920 case OMAP_DSS_COLOR_UYVY:
921 m = 0xb; break;
922 case OMAP_DSS_COLOR_ARGB32:
923 m = 0xc; break;
924 case OMAP_DSS_COLOR_RGBA32:
925 m = 0xd; break;
926 case OMAP_DSS_COLOR_RGBX32:
927 m = 0xe; break;
928 case OMAP_DSS_COLOR_XRGB16_1555:
929 m = 0xf; break;
930 default:
931 BUG(); return;
932 }
933 } else {
934 switch (color_mode) {
935 case OMAP_DSS_COLOR_CLUT1:
936 m = 0x0; break;
937 case OMAP_DSS_COLOR_CLUT2:
938 m = 0x1; break;
939 case OMAP_DSS_COLOR_CLUT4:
940 m = 0x2; break;
941 case OMAP_DSS_COLOR_CLUT8:
942 m = 0x3; break;
943 case OMAP_DSS_COLOR_RGB12U:
944 m = 0x4; break;
945 case OMAP_DSS_COLOR_ARGB16:
946 m = 0x5; break;
947 case OMAP_DSS_COLOR_RGB16:
948 m = 0x6; break;
949 case OMAP_DSS_COLOR_ARGB16_1555:
950 m = 0x7; break;
951 case OMAP_DSS_COLOR_RGB24U:
952 m = 0x8; break;
953 case OMAP_DSS_COLOR_RGB24P:
954 m = 0x9; break;
955 case OMAP_DSS_COLOR_RGBX16:
956 m = 0xa; break;
957 case OMAP_DSS_COLOR_RGBA16:
958 m = 0xb; break;
959 case OMAP_DSS_COLOR_ARGB32:
960 m = 0xc; break;
961 case OMAP_DSS_COLOR_RGBA32:
962 m = 0xd; break;
963 case OMAP_DSS_COLOR_RGBX32:
964 m = 0xe; break;
965 case OMAP_DSS_COLOR_XRGB16_1555:
966 m = 0xf; break;
967 default:
968 BUG(); return;
969 }
970 }
971
972 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
973}
974
975static void dispc_ovl_configure_burst_type(enum omap_plane plane,
976 enum omap_dss_rotation_type rotation_type)
977{
978 if (dss_has_feature(FEAT_BURST_2D) == 0)
979 return;
980
981 if (rotation_type == OMAP_DSS_ROT_TILER)
982 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
983 else
984 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
985}
986
987void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
988{
989 int shift;
990 u32 val;
991 int chan = 0, chan2 = 0;
992
993 switch (plane) {
994 case OMAP_DSS_GFX:
995 shift = 8;
996 break;
997 case OMAP_DSS_VIDEO1:
998 case OMAP_DSS_VIDEO2:
999 case OMAP_DSS_VIDEO3:
1000 shift = 16;
1001 break;
1002 default:
1003 BUG();
1004 return;
1005 }
1006
1007 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1008 if (dss_has_feature(FEAT_MGR_LCD2)) {
1009 switch (channel) {
1010 case OMAP_DSS_CHANNEL_LCD:
1011 chan = 0;
1012 chan2 = 0;
1013 break;
1014 case OMAP_DSS_CHANNEL_DIGIT:
1015 chan = 1;
1016 chan2 = 0;
1017 break;
1018 case OMAP_DSS_CHANNEL_LCD2:
1019 chan = 0;
1020 chan2 = 1;
1021 break;
1022 case OMAP_DSS_CHANNEL_LCD3:
1023 if (dss_has_feature(FEAT_MGR_LCD3)) {
1024 chan = 0;
1025 chan2 = 2;
1026 } else {
1027 BUG();
1028 return;
1029 }
1030 break;
1031 case OMAP_DSS_CHANNEL_WB:
1032 chan = 0;
1033 chan2 = 3;
1034 break;
1035 default:
1036 BUG();
1037 return;
1038 }
1039
1040 val = FLD_MOD(val, chan, shift, shift);
1041 val = FLD_MOD(val, chan2, 31, 30);
1042 } else {
1043 val = FLD_MOD(val, channel, shift, shift);
1044 }
1045 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1046}
1047EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1048
1049static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1050{
1051 int shift;
1052 u32 val;
1053
1054 switch (plane) {
1055 case OMAP_DSS_GFX:
1056 shift = 8;
1057 break;
1058 case OMAP_DSS_VIDEO1:
1059 case OMAP_DSS_VIDEO2:
1060 case OMAP_DSS_VIDEO3:
1061 shift = 16;
1062 break;
1063 default:
1064 BUG();
1065 return 0;
1066 }
1067
1068 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1069
1070 if (FLD_GET(val, shift, shift) == 1)
1071 return OMAP_DSS_CHANNEL_DIGIT;
1072
1073 if (!dss_has_feature(FEAT_MGR_LCD2))
1074 return OMAP_DSS_CHANNEL_LCD;
1075
1076 switch (FLD_GET(val, 31, 30)) {
1077 case 0:
1078 default:
1079 return OMAP_DSS_CHANNEL_LCD;
1080 case 1:
1081 return OMAP_DSS_CHANNEL_LCD2;
1082 case 2:
1083 return OMAP_DSS_CHANNEL_LCD3;
1084 case 3:
1085 return OMAP_DSS_CHANNEL_WB;
1086 }
1087}
1088
1089void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1090{
1091 enum omap_plane plane = OMAP_DSS_WB;
1092
1093 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1094}
1095
1096static void dispc_ovl_set_burst_size(enum omap_plane plane,
1097 enum omap_burst_size burst_size)
1098{
1099 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1100 int shift;
1101
1102 shift = shifts[plane];
1103 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1104}
1105
1106static void dispc_configure_burst_sizes(void)
1107{
1108 int i;
1109 const int burst_size = BURST_SIZE_X8;
1110
1111 /* Configure burst size always to maximum size */
1112 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1113 dispc_ovl_set_burst_size(i, burst_size);
1114 if (dispc.feat->has_writeback)
1115 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1116}
1117
1118static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1119{
1120 unsigned unit = dss_feat_get_burst_size_unit();
1121 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1122 return unit * 8;
1123}
1124
1125static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1126{
1127 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1128 return;
1129
1130 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1131}
1132
1133static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1134 const struct omap_dss_cpr_coefs *coefs)
1135{
1136 u32 coef_r, coef_g, coef_b;
1137
1138 if (!dss_mgr_is_lcd(channel))
1139 return;
1140
1141 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1142 FLD_VAL(coefs->rb, 9, 0);
1143 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1144 FLD_VAL(coefs->gb, 9, 0);
1145 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1146 FLD_VAL(coefs->bb, 9, 0);
1147
1148 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1149 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1150 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1151}
1152
1153static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1154{
1155 u32 val;
1156
1157 BUG_ON(plane == OMAP_DSS_GFX);
1158
1159 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1160 val = FLD_MOD(val, enable, 9, 9);
1161 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1162}
1163
1164static void dispc_ovl_enable_replication(enum omap_plane plane,
1165 enum omap_overlay_caps caps, bool enable)
1166{
1167 static const unsigned shifts[] = { 5, 10, 10, 10 };
1168 int shift;
1169
1170 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1171 return;
1172
1173 shift = shifts[plane];
1174 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1175}
1176
1177static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1178 u16 height)
1179{
1180 u32 val;
1181
1182 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1183 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1184
1185 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1186}
1187
1188static void dispc_init_fifos(void)
1189{
1190 u32 size;
1191 int fifo;
1192 u8 start, end;
1193 u32 unit;
1194 int i;
1195
1196 unit = dss_feat_get_buffer_size_unit();
1197
1198 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1199
1200 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1201 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1202 size *= unit;
1203 dispc.fifo_size[fifo] = size;
1204
1205 /*
1206 * By default fifos are mapped directly to overlays, fifo 0 to
1207 * ovl 0, fifo 1 to ovl 1, etc.
1208 */
1209 dispc.fifo_assignment[fifo] = fifo;
1210 }
1211
1212 /*
1213 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1214 * causes problems with certain use cases, like using the tiler in 2D
1215 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1216 * giving GFX plane a larger fifo. WB but should work fine with a
1217 * smaller fifo.
1218 */
1219 if (dispc.feat->gfx_fifo_workaround) {
1220 u32 v;
1221
1222 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1223
1224 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1225 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1226 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1227 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1228
1229 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1230
1231 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1232 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1233 }
1234
1235 /*
1236 * Setup default fifo thresholds.
1237 */
1238 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1239 u32 low, high;
1240 const bool use_fifomerge = false;
1241 const bool manual_update = false;
1242
1243 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1244 use_fifomerge, manual_update);
1245
1246 dispc_ovl_set_fifo_threshold(i, low, high);
1247 }
1248
1249 if (dispc.feat->has_writeback) {
1250 u32 low, high;
1251 const bool use_fifomerge = false;
1252 const bool manual_update = false;
1253
1254 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1255 use_fifomerge, manual_update);
1256
1257 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1258 }
1259}
1260
1261static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1262{
1263 int fifo;
1264 u32 size = 0;
1265
1266 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1267 if (dispc.fifo_assignment[fifo] == plane)
1268 size += dispc.fifo_size[fifo];
1269 }
1270
1271 return size;
1272}
1273
1274void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1275{
1276 u8 hi_start, hi_end, lo_start, lo_end;
1277 u32 unit;
1278
1279 unit = dss_feat_get_buffer_size_unit();
1280
1281 WARN_ON(low % unit != 0);
1282 WARN_ON(high % unit != 0);
1283
1284 low /= unit;
1285 high /= unit;
1286
1287 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1288 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1289
1290 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1291 plane,
1292 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1293 lo_start, lo_end) * unit,
1294 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1295 hi_start, hi_end) * unit,
1296 low * unit, high * unit);
1297
1298 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1299 FLD_VAL(high, hi_start, hi_end) |
1300 FLD_VAL(low, lo_start, lo_end));
1301
1302 /*
1303 * configure the preload to the pipeline's high threhold, if HT it's too
1304 * large for the preload field, set the threshold to the maximum value
1305 * that can be held by the preload register
1306 */
1307 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1308 plane != OMAP_DSS_WB)
1309 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1310}
1311
1312void dispc_enable_fifomerge(bool enable)
1313{
1314 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1315 WARN_ON(enable);
1316 return;
1317 }
1318
1319 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1320 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1321}
1322
1323void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1324 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1325 bool manual_update)
1326{
1327 /*
1328 * All sizes are in bytes. Both the buffer and burst are made of
1329 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1330 */
1331
1332 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1333 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1334 int i;
1335
1336 burst_size = dispc_ovl_get_burst_size(plane);
1337 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1338
1339 if (use_fifomerge) {
1340 total_fifo_size = 0;
1341 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1342 total_fifo_size += dispc_ovl_get_fifo_size(i);
1343 } else {
1344 total_fifo_size = ovl_fifo_size;
1345 }
1346
1347 /*
1348 * We use the same low threshold for both fifomerge and non-fifomerge
1349 * cases, but for fifomerge we calculate the high threshold using the
1350 * combined fifo size
1351 */
1352
1353 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1354 *fifo_low = ovl_fifo_size - burst_size * 2;
1355 *fifo_high = total_fifo_size - burst_size;
1356 } else if (plane == OMAP_DSS_WB) {
1357 /*
1358 * Most optimal configuration for writeback is to push out data
1359 * to the interconnect the moment writeback pushes enough pixels
1360 * in the FIFO to form a burst
1361 */
1362 *fifo_low = 0;
1363 *fifo_high = burst_size;
1364 } else {
1365 *fifo_low = ovl_fifo_size - burst_size;
1366 *fifo_high = total_fifo_size - buf_unit;
1367 }
1368}
1369
1370static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1371{
1372 int bit;
1373
1374 if (plane == OMAP_DSS_GFX)
1375 bit = 14;
1376 else
1377 bit = 23;
1378
1379 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1380}
1381
1382static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1383 int low, int high)
1384{
1385 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1386 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1387}
1388
1389static void dispc_init_mflag(void)
1390{
1391 int i;
1392
1393 /*
1394 * HACK: NV12 color format and MFLAG seem to have problems working
1395 * together: using two displays, and having an NV12 overlay on one of
1396 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1397 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1398 * remove the errors, but there doesn't seem to be a clear logic on
1399 * which values work and which not.
1400 *
1401 * As a work-around, set force MFLAG to always on.
1402 */
1403 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1404 (1 << 0) | /* MFLAG_CTRL = force always on */
1405 (0 << 2)); /* MFLAG_START = disable */
1406
1407 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1408 u32 size = dispc_ovl_get_fifo_size(i);
1409 u32 unit = dss_feat_get_buffer_size_unit();
1410 u32 low, high;
1411
1412 dispc_ovl_set_mflag(i, true);
1413
1414 /*
1415 * Simulation team suggests below thesholds:
1416 * HT = fifosize * 5 / 8;
1417 * LT = fifosize * 4 / 8;
1418 */
1419
1420 low = size * 4 / 8 / unit;
1421 high = size * 5 / 8 / unit;
1422
1423 dispc_ovl_set_mflag_threshold(i, low, high);
1424 }
1425
1426 if (dispc.feat->has_writeback) {
1427 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1428 u32 unit = dss_feat_get_buffer_size_unit();
1429 u32 low, high;
1430
1431 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1432
1433 /*
1434 * Simulation team suggests below thesholds:
1435 * HT = fifosize * 5 / 8;
1436 * LT = fifosize * 4 / 8;
1437 */
1438
1439 low = size * 4 / 8 / unit;
1440 high = size * 5 / 8 / unit;
1441
1442 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1443 }
1444}
1445
1446static void dispc_ovl_set_fir(enum omap_plane plane,
1447 int hinc, int vinc,
1448 enum omap_color_component color_comp)
1449{
1450 u32 val;
1451
1452 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1453 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1454
1455 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1456 &hinc_start, &hinc_end);
1457 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1458 &vinc_start, &vinc_end);
1459 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1460 FLD_VAL(hinc, hinc_start, hinc_end);
1461
1462 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1463 } else {
1464 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1465 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1466 }
1467}
1468
1469static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1470{
1471 u32 val;
1472 u8 hor_start, hor_end, vert_start, vert_end;
1473
1474 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1475 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1476
1477 val = FLD_VAL(vaccu, vert_start, vert_end) |
1478 FLD_VAL(haccu, hor_start, hor_end);
1479
1480 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1481}
1482
1483static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1484{
1485 u32 val;
1486 u8 hor_start, hor_end, vert_start, vert_end;
1487
1488 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1489 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1490
1491 val = FLD_VAL(vaccu, vert_start, vert_end) |
1492 FLD_VAL(haccu, hor_start, hor_end);
1493
1494 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1495}
1496
1497static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1498 int vaccu)
1499{
1500 u32 val;
1501
1502 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1503 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1504}
1505
1506static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1507 int vaccu)
1508{
1509 u32 val;
1510
1511 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1512 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1513}
1514
1515static void dispc_ovl_set_scale_param(enum omap_plane plane,
1516 u16 orig_width, u16 orig_height,
1517 u16 out_width, u16 out_height,
1518 bool five_taps, u8 rotation,
1519 enum omap_color_component color_comp)
1520{
1521 int fir_hinc, fir_vinc;
1522
1523 fir_hinc = 1024 * orig_width / out_width;
1524 fir_vinc = 1024 * orig_height / out_height;
1525
1526 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1527 color_comp);
1528 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1529}
1530
1531static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1532 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1533 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1534{
1535 int h_accu2_0, h_accu2_1;
1536 int v_accu2_0, v_accu2_1;
1537 int chroma_hinc, chroma_vinc;
1538 int idx;
1539
1540 struct accu {
1541 s8 h0_m, h0_n;
1542 s8 h1_m, h1_n;
1543 s8 v0_m, v0_n;
1544 s8 v1_m, v1_n;
1545 };
1546
1547 const struct accu *accu_table;
1548 const struct accu *accu_val;
1549
1550 static const struct accu accu_nv12[4] = {
1551 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1552 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1553 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1554 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1555 };
1556
1557 static const struct accu accu_nv12_ilace[4] = {
1558 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1559 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1560 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1561 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1562 };
1563
1564 static const struct accu accu_yuv[4] = {
1565 { 0, 1, 0, 1, 0, 1, 0, 1 },
1566 { 0, 1, 0, 1, 0, 1, 0, 1 },
1567 { -1, 1, 0, 1, 0, 1, 0, 1 },
1568 { 0, 1, 0, 1, -1, 1, 0, 1 },
1569 };
1570
1571 switch (rotation) {
1572 case OMAP_DSS_ROT_0:
1573 idx = 0;
1574 break;
1575 case OMAP_DSS_ROT_90:
1576 idx = 1;
1577 break;
1578 case OMAP_DSS_ROT_180:
1579 idx = 2;
1580 break;
1581 case OMAP_DSS_ROT_270:
1582 idx = 3;
1583 break;
1584 default:
1585 BUG();
1586 return;
1587 }
1588
1589 switch (color_mode) {
1590 case OMAP_DSS_COLOR_NV12:
1591 if (ilace)
1592 accu_table = accu_nv12_ilace;
1593 else
1594 accu_table = accu_nv12;
1595 break;
1596 case OMAP_DSS_COLOR_YUV2:
1597 case OMAP_DSS_COLOR_UYVY:
1598 accu_table = accu_yuv;
1599 break;
1600 default:
1601 BUG();
1602 return;
1603 }
1604
1605 accu_val = &accu_table[idx];
1606
1607 chroma_hinc = 1024 * orig_width / out_width;
1608 chroma_vinc = 1024 * orig_height / out_height;
1609
1610 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1611 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1612 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1613 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1614
1615 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1616 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1617}
1618
1619static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1620 u16 orig_width, u16 orig_height,
1621 u16 out_width, u16 out_height,
1622 bool ilace, bool five_taps,
1623 bool fieldmode, enum omap_color_mode color_mode,
1624 u8 rotation)
1625{
1626 int accu0 = 0;
1627 int accu1 = 0;
1628 u32 l;
1629
1630 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1631 out_width, out_height, five_taps,
1632 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1633 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1634
1635 /* RESIZEENABLE and VERTICALTAPS */
1636 l &= ~((0x3 << 5) | (0x1 << 21));
1637 l |= (orig_width != out_width) ? (1 << 5) : 0;
1638 l |= (orig_height != out_height) ? (1 << 6) : 0;
1639 l |= five_taps ? (1 << 21) : 0;
1640
1641 /* VRESIZECONF and HRESIZECONF */
1642 if (dss_has_feature(FEAT_RESIZECONF)) {
1643 l &= ~(0x3 << 7);
1644 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1645 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1646 }
1647
1648 /* LINEBUFFERSPLIT */
1649 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1650 l &= ~(0x1 << 22);
1651 l |= five_taps ? (1 << 22) : 0;
1652 }
1653
1654 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1655
1656 /*
1657 * field 0 = even field = bottom field
1658 * field 1 = odd field = top field
1659 */
1660 if (ilace && !fieldmode) {
1661 accu1 = 0;
1662 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1663 if (accu0 >= 1024/2) {
1664 accu1 = 1024/2;
1665 accu0 -= accu1;
1666 }
1667 }
1668
1669 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1670 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1671}
1672
1673static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1674 u16 orig_width, u16 orig_height,
1675 u16 out_width, u16 out_height,
1676 bool ilace, bool five_taps,
1677 bool fieldmode, enum omap_color_mode color_mode,
1678 u8 rotation)
1679{
1680 int scale_x = out_width != orig_width;
1681 int scale_y = out_height != orig_height;
1682 bool chroma_upscale = plane != OMAP_DSS_WB;
1683
1684 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1685 return;
1686 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1687 color_mode != OMAP_DSS_COLOR_UYVY &&
1688 color_mode != OMAP_DSS_COLOR_NV12)) {
1689 /* reset chroma resampling for RGB formats */
1690 if (plane != OMAP_DSS_WB)
1691 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1692 return;
1693 }
1694
1695 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1696 out_height, ilace, color_mode, rotation);
1697
1698 switch (color_mode) {
1699 case OMAP_DSS_COLOR_NV12:
1700 if (chroma_upscale) {
1701 /* UV is subsampled by 2 horizontally and vertically */
1702 orig_height >>= 1;
1703 orig_width >>= 1;
1704 } else {
1705 /* UV is downsampled by 2 horizontally and vertically */
1706 orig_height <<= 1;
1707 orig_width <<= 1;
1708 }
1709
1710 break;
1711 case OMAP_DSS_COLOR_YUV2:
1712 case OMAP_DSS_COLOR_UYVY:
1713 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1714 if (rotation == OMAP_DSS_ROT_0 ||
1715 rotation == OMAP_DSS_ROT_180) {
1716 if (chroma_upscale)
1717 /* UV is subsampled by 2 horizontally */
1718 orig_width >>= 1;
1719 else
1720 /* UV is downsampled by 2 horizontally */
1721 orig_width <<= 1;
1722 }
1723
1724 /* must use FIR for YUV422 if rotated */
1725 if (rotation != OMAP_DSS_ROT_0)
1726 scale_x = scale_y = true;
1727
1728 break;
1729 default:
1730 BUG();
1731 return;
1732 }
1733
1734 if (out_width != orig_width)
1735 scale_x = true;
1736 if (out_height != orig_height)
1737 scale_y = true;
1738
1739 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1740 out_width, out_height, five_taps,
1741 rotation, DISPC_COLOR_COMPONENT_UV);
1742
1743 if (plane != OMAP_DSS_WB)
1744 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1745 (scale_x || scale_y) ? 1 : 0, 8, 8);
1746
1747 /* set H scaling */
1748 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1749 /* set V scaling */
1750 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1751}
1752
1753static void dispc_ovl_set_scaling(enum omap_plane plane,
1754 u16 orig_width, u16 orig_height,
1755 u16 out_width, u16 out_height,
1756 bool ilace, bool five_taps,
1757 bool fieldmode, enum omap_color_mode color_mode,
1758 u8 rotation)
1759{
1760 BUG_ON(plane == OMAP_DSS_GFX);
1761
1762 dispc_ovl_set_scaling_common(plane,
1763 orig_width, orig_height,
1764 out_width, out_height,
1765 ilace, five_taps,
1766 fieldmode, color_mode,
1767 rotation);
1768
1769 dispc_ovl_set_scaling_uv(plane,
1770 orig_width, orig_height,
1771 out_width, out_height,
1772 ilace, five_taps,
1773 fieldmode, color_mode,
1774 rotation);
1775}
1776
1777static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1778 enum omap_dss_rotation_type rotation_type,
1779 bool mirroring, enum omap_color_mode color_mode)
1780{
1781 bool row_repeat = false;
1782 int vidrot = 0;
1783
1784 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1785 color_mode == OMAP_DSS_COLOR_UYVY) {
1786
1787 if (mirroring) {
1788 switch (rotation) {
1789 case OMAP_DSS_ROT_0:
1790 vidrot = 2;
1791 break;
1792 case OMAP_DSS_ROT_90:
1793 vidrot = 1;
1794 break;
1795 case OMAP_DSS_ROT_180:
1796 vidrot = 0;
1797 break;
1798 case OMAP_DSS_ROT_270:
1799 vidrot = 3;
1800 break;
1801 }
1802 } else {
1803 switch (rotation) {
1804 case OMAP_DSS_ROT_0:
1805 vidrot = 0;
1806 break;
1807 case OMAP_DSS_ROT_90:
1808 vidrot = 1;
1809 break;
1810 case OMAP_DSS_ROT_180:
1811 vidrot = 2;
1812 break;
1813 case OMAP_DSS_ROT_270:
1814 vidrot = 3;
1815 break;
1816 }
1817 }
1818
1819 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1820 row_repeat = true;
1821 else
1822 row_repeat = false;
1823 }
1824
1825 /*
1826 * OMAP4/5 Errata i631:
1827 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1828 * rows beyond the framebuffer, which may cause OCP error.
1829 */
1830 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1831 rotation_type != OMAP_DSS_ROT_TILER)
1832 vidrot = 1;
1833
1834 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1835 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1836 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1837 row_repeat ? 1 : 0, 18, 18);
1838
1839 if (color_mode == OMAP_DSS_COLOR_NV12) {
1840 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1841 (rotation == OMAP_DSS_ROT_0 ||
1842 rotation == OMAP_DSS_ROT_180);
1843 /* DOUBLESTRIDE */
1844 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1845 }
1846
1847}
1848
1849static int color_mode_to_bpp(enum omap_color_mode color_mode)
1850{
1851 switch (color_mode) {
1852 case OMAP_DSS_COLOR_CLUT1:
1853 return 1;
1854 case OMAP_DSS_COLOR_CLUT2:
1855 return 2;
1856 case OMAP_DSS_COLOR_CLUT4:
1857 return 4;
1858 case OMAP_DSS_COLOR_CLUT8:
1859 case OMAP_DSS_COLOR_NV12:
1860 return 8;
1861 case OMAP_DSS_COLOR_RGB12U:
1862 case OMAP_DSS_COLOR_RGB16:
1863 case OMAP_DSS_COLOR_ARGB16:
1864 case OMAP_DSS_COLOR_YUV2:
1865 case OMAP_DSS_COLOR_UYVY:
1866 case OMAP_DSS_COLOR_RGBA16:
1867 case OMAP_DSS_COLOR_RGBX16:
1868 case OMAP_DSS_COLOR_ARGB16_1555:
1869 case OMAP_DSS_COLOR_XRGB16_1555:
1870 return 16;
1871 case OMAP_DSS_COLOR_RGB24P:
1872 return 24;
1873 case OMAP_DSS_COLOR_RGB24U:
1874 case OMAP_DSS_COLOR_ARGB32:
1875 case OMAP_DSS_COLOR_RGBA32:
1876 case OMAP_DSS_COLOR_RGBX32:
1877 return 32;
1878 default:
1879 BUG();
1880 return 0;
1881 }
1882}
1883
1884static s32 pixinc(int pixels, u8 ps)
1885{
1886 if (pixels == 1)
1887 return 1;
1888 else if (pixels > 1)
1889 return 1 + (pixels - 1) * ps;
1890 else if (pixels < 0)
1891 return 1 - (-pixels + 1) * ps;
1892 else
1893 BUG();
1894 return 0;
1895}
1896
1897static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1898 u16 screen_width,
1899 u16 width, u16 height,
1900 enum omap_color_mode color_mode, bool fieldmode,
1901 unsigned int field_offset,
1902 unsigned *offset0, unsigned *offset1,
1903 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1904{
1905 u8 ps;
1906
1907 /* FIXME CLUT formats */
1908 switch (color_mode) {
1909 case OMAP_DSS_COLOR_CLUT1:
1910 case OMAP_DSS_COLOR_CLUT2:
1911 case OMAP_DSS_COLOR_CLUT4:
1912 case OMAP_DSS_COLOR_CLUT8:
1913 BUG();
1914 return;
1915 case OMAP_DSS_COLOR_YUV2:
1916 case OMAP_DSS_COLOR_UYVY:
1917 ps = 4;
1918 break;
1919 default:
1920 ps = color_mode_to_bpp(color_mode) / 8;
1921 break;
1922 }
1923
1924 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1925 width, height);
1926
1927 /*
1928 * field 0 = even field = bottom field
1929 * field 1 = odd field = top field
1930 */
1931 switch (rotation + mirror * 4) {
1932 case OMAP_DSS_ROT_0:
1933 case OMAP_DSS_ROT_180:
1934 /*
1935 * If the pixel format is YUV or UYVY divide the width
1936 * of the image by 2 for 0 and 180 degree rotation.
1937 */
1938 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1939 color_mode == OMAP_DSS_COLOR_UYVY)
1940 width = width >> 1;
1941 case OMAP_DSS_ROT_90:
1942 case OMAP_DSS_ROT_270:
1943 *offset1 = 0;
1944 if (field_offset)
1945 *offset0 = field_offset * screen_width * ps;
1946 else
1947 *offset0 = 0;
1948
1949 *row_inc = pixinc(1 +
1950 (y_predecim * screen_width - x_predecim * width) +
1951 (fieldmode ? screen_width : 0), ps);
1952 *pix_inc = pixinc(x_predecim, ps);
1953 break;
1954
1955 case OMAP_DSS_ROT_0 + 4:
1956 case OMAP_DSS_ROT_180 + 4:
1957 /* If the pixel format is YUV or UYVY divide the width
1958 * of the image by 2 for 0 degree and 180 degree
1959 */
1960 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1961 color_mode == OMAP_DSS_COLOR_UYVY)
1962 width = width >> 1;
1963 case OMAP_DSS_ROT_90 + 4:
1964 case OMAP_DSS_ROT_270 + 4:
1965 *offset1 = 0;
1966 if (field_offset)
1967 *offset0 = field_offset * screen_width * ps;
1968 else
1969 *offset0 = 0;
1970 *row_inc = pixinc(1 -
1971 (y_predecim * screen_width + x_predecim * width) -
1972 (fieldmode ? screen_width : 0), ps);
1973 *pix_inc = pixinc(x_predecim, ps);
1974 break;
1975
1976 default:
1977 BUG();
1978 return;
1979 }
1980}
1981
1982static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1983 u16 screen_width,
1984 u16 width, u16 height,
1985 enum omap_color_mode color_mode, bool fieldmode,
1986 unsigned int field_offset,
1987 unsigned *offset0, unsigned *offset1,
1988 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1989{
1990 u8 ps;
1991 u16 fbw, fbh;
1992
1993 /* FIXME CLUT formats */
1994 switch (color_mode) {
1995 case OMAP_DSS_COLOR_CLUT1:
1996 case OMAP_DSS_COLOR_CLUT2:
1997 case OMAP_DSS_COLOR_CLUT4:
1998 case OMAP_DSS_COLOR_CLUT8:
1999 BUG();
2000 return;
2001 default:
2002 ps = color_mode_to_bpp(color_mode) / 8;
2003 break;
2004 }
2005
2006 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
2007 width, height);
2008
2009 /* width & height are overlay sizes, convert to fb sizes */
2010
2011 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
2012 fbw = width;
2013 fbh = height;
2014 } else {
2015 fbw = height;
2016 fbh = width;
2017 }
2018
2019 /*
2020 * field 0 = even field = bottom field
2021 * field 1 = odd field = top field
2022 */
2023 switch (rotation + mirror * 4) {
2024 case OMAP_DSS_ROT_0:
2025 *offset1 = 0;
2026 if (field_offset)
2027 *offset0 = *offset1 + field_offset * screen_width * ps;
2028 else
2029 *offset0 = *offset1;
2030 *row_inc = pixinc(1 +
2031 (y_predecim * screen_width - fbw * x_predecim) +
2032 (fieldmode ? screen_width : 0), ps);
2033 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2034 color_mode == OMAP_DSS_COLOR_UYVY)
2035 *pix_inc = pixinc(x_predecim, 2 * ps);
2036 else
2037 *pix_inc = pixinc(x_predecim, ps);
2038 break;
2039 case OMAP_DSS_ROT_90:
2040 *offset1 = screen_width * (fbh - 1) * ps;
2041 if (field_offset)
2042 *offset0 = *offset1 + field_offset * ps;
2043 else
2044 *offset0 = *offset1;
2045 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2046 y_predecim + (fieldmode ? 1 : 0), ps);
2047 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2048 break;
2049 case OMAP_DSS_ROT_180:
2050 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2051 if (field_offset)
2052 *offset0 = *offset1 - field_offset * screen_width * ps;
2053 else
2054 *offset0 = *offset1;
2055 *row_inc = pixinc(-1 -
2056 (y_predecim * screen_width - fbw * x_predecim) -
2057 (fieldmode ? screen_width : 0), ps);
2058 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2059 color_mode == OMAP_DSS_COLOR_UYVY)
2060 *pix_inc = pixinc(-x_predecim, 2 * ps);
2061 else
2062 *pix_inc = pixinc(-x_predecim, ps);
2063 break;
2064 case OMAP_DSS_ROT_270:
2065 *offset1 = (fbw - 1) * ps;
2066 if (field_offset)
2067 *offset0 = *offset1 - field_offset * ps;
2068 else
2069 *offset0 = *offset1;
2070 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2071 y_predecim - (fieldmode ? 1 : 0), ps);
2072 *pix_inc = pixinc(x_predecim * screen_width, ps);
2073 break;
2074
2075 /* mirroring */
2076 case OMAP_DSS_ROT_0 + 4:
2077 *offset1 = (fbw - 1) * ps;
2078 if (field_offset)
2079 *offset0 = *offset1 + field_offset * screen_width * ps;
2080 else
2081 *offset0 = *offset1;
2082 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2083 (fieldmode ? screen_width : 0),
2084 ps);
2085 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2086 color_mode == OMAP_DSS_COLOR_UYVY)
2087 *pix_inc = pixinc(-x_predecim, 2 * ps);
2088 else
2089 *pix_inc = pixinc(-x_predecim, ps);
2090 break;
2091
2092 case OMAP_DSS_ROT_90 + 4:
2093 *offset1 = 0;
2094 if (field_offset)
2095 *offset0 = *offset1 + field_offset * ps;
2096 else
2097 *offset0 = *offset1;
2098 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2099 y_predecim + (fieldmode ? 1 : 0),
2100 ps);
2101 *pix_inc = pixinc(x_predecim * screen_width, ps);
2102 break;
2103
2104 case OMAP_DSS_ROT_180 + 4:
2105 *offset1 = screen_width * (fbh - 1) * ps;
2106 if (field_offset)
2107 *offset0 = *offset1 - field_offset * screen_width * ps;
2108 else
2109 *offset0 = *offset1;
2110 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2111 (fieldmode ? screen_width : 0),
2112 ps);
2113 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2114 color_mode == OMAP_DSS_COLOR_UYVY)
2115 *pix_inc = pixinc(x_predecim, 2 * ps);
2116 else
2117 *pix_inc = pixinc(x_predecim, ps);
2118 break;
2119
2120 case OMAP_DSS_ROT_270 + 4:
2121 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2122 if (field_offset)
2123 *offset0 = *offset1 - field_offset * ps;
2124 else
2125 *offset0 = *offset1;
2126 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2127 y_predecim - (fieldmode ? 1 : 0),
2128 ps);
2129 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2130 break;
2131
2132 default:
2133 BUG();
2134 return;
2135 }
2136}
2137
2138static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2139 enum omap_color_mode color_mode, bool fieldmode,
2140 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2141 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2142{
2143 u8 ps;
2144
2145 switch (color_mode) {
2146 case OMAP_DSS_COLOR_CLUT1:
2147 case OMAP_DSS_COLOR_CLUT2:
2148 case OMAP_DSS_COLOR_CLUT4:
2149 case OMAP_DSS_COLOR_CLUT8:
2150 BUG();
2151 return;
2152 default:
2153 ps = color_mode_to_bpp(color_mode) / 8;
2154 break;
2155 }
2156
2157 DSSDBG("scrw %d, width %d\n", screen_width, width);
2158
2159 /*
2160 * field 0 = even field = bottom field
2161 * field 1 = odd field = top field
2162 */
2163 *offset1 = 0;
2164 if (field_offset)
2165 *offset0 = *offset1 + field_offset * screen_width * ps;
2166 else
2167 *offset0 = *offset1;
2168 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2169 (fieldmode ? screen_width : 0), ps);
2170 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2171 color_mode == OMAP_DSS_COLOR_UYVY)
2172 *pix_inc = pixinc(x_predecim, 2 * ps);
2173 else
2174 *pix_inc = pixinc(x_predecim, ps);
2175}
2176
2177/*
2178 * This function is used to avoid synclosts in OMAP3, because of some
2179 * undocumented horizontal position and timing related limitations.
2180 */
2181static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2182 const struct videomode *vm, u16 pos_x,
2183 u16 width, u16 height, u16 out_width, u16 out_height,
2184 bool five_taps)
2185{
2186 const int ds = DIV_ROUND_UP(height, out_height);
2187 unsigned long nonactive;
2188 static const u8 limits[3] = { 8, 10, 20 };
2189 u64 val, blank;
2190 int i;
2191
2192 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len +
2193 vm->hback_porch - out_width;
2194
2195 i = 0;
2196 if (out_height < height)
2197 i++;
2198 if (out_width < width)
2199 i++;
2200 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) *
2201 lclk, pclk);
2202 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2203 if (blank <= limits[i])
2204 return -EINVAL;
2205
2206 /* FIXME add checks for 3-tap filter once the limitations are known */
2207 if (!five_taps)
2208 return 0;
2209
2210 /*
2211 * Pixel data should be prepared before visible display point starts.
2212 * So, atleast DS-2 lines must have already been fetched by DISPC
2213 * during nonactive - pos_x period.
2214 */
2215 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2216 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2217 val, max(0, ds - 2) * width);
2218 if (val < max(0, ds - 2) * width)
2219 return -EINVAL;
2220
2221 /*
2222 * All lines need to be refilled during the nonactive period of which
2223 * only one line can be loaded during the active period. So, atleast
2224 * DS - 1 lines should be loaded during nonactive period.
2225 */
2226 val = div_u64((u64)nonactive * lclk, pclk);
2227 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2228 val, max(0, ds - 1) * width);
2229 if (val < max(0, ds - 1) * width)
2230 return -EINVAL;
2231
2232 return 0;
2233}
2234
2235static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2236 const struct videomode *vm, u16 width,
2237 u16 height, u16 out_width, u16 out_height,
2238 enum omap_color_mode color_mode)
2239{
2240 u32 core_clk = 0;
2241 u64 tmp;
2242
2243 if (height <= out_height && width <= out_width)
2244 return (unsigned long) pclk;
2245
2246 if (height > out_height) {
2247 unsigned int ppl = vm->hactive;
2248
2249 tmp = (u64)pclk * height * out_width;
2250 do_div(tmp, 2 * out_height * ppl);
2251 core_clk = tmp;
2252
2253 if (height > 2 * out_height) {
2254 if (ppl == out_width)
2255 return 0;
2256
2257 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2258 do_div(tmp, 2 * out_height * (ppl - out_width));
2259 core_clk = max_t(u32, core_clk, tmp);
2260 }
2261 }
2262
2263 if (width > out_width) {
2264 tmp = (u64)pclk * width;
2265 do_div(tmp, out_width);
2266 core_clk = max_t(u32, core_clk, tmp);
2267
2268 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2269 core_clk <<= 1;
2270 }
2271
2272 return core_clk;
2273}
2274
2275static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2276 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2277{
2278 if (height > out_height && width > out_width)
2279 return pclk * 4;
2280 else
2281 return pclk * 2;
2282}
2283
2284static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2285 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2286{
2287 unsigned int hf, vf;
2288
2289 /*
2290 * FIXME how to determine the 'A' factor
2291 * for the no downscaling case ?
2292 */
2293
2294 if (width > 3 * out_width)
2295 hf = 4;
2296 else if (width > 2 * out_width)
2297 hf = 3;
2298 else if (width > out_width)
2299 hf = 2;
2300 else
2301 hf = 1;
2302 if (height > out_height)
2303 vf = 2;
2304 else
2305 vf = 1;
2306
2307 return pclk * vf * hf;
2308}
2309
2310static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2311 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2312{
2313 /*
2314 * If the overlay/writeback is in mem to mem mode, there are no
2315 * downscaling limitations with respect to pixel clock, return 1 as
2316 * required core clock to represent that we have sufficient enough
2317 * core clock to do maximum downscaling
2318 */
2319 if (mem_to_mem)
2320 return 1;
2321
2322 if (width > out_width)
2323 return DIV_ROUND_UP(pclk, out_width) * width;
2324 else
2325 return pclk;
2326}
2327
2328static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2329 const struct videomode *vm,
2330 u16 width, u16 height, u16 out_width, u16 out_height,
2331 enum omap_color_mode color_mode, bool *five_taps,
2332 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2333 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2334{
2335 int error;
2336 u16 in_width, in_height;
2337 int min_factor = min(*decim_x, *decim_y);
2338 const int maxsinglelinewidth =
2339 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2340
2341 *five_taps = false;
2342
2343 do {
2344 in_height = height / *decim_y;
2345 in_width = width / *decim_x;
2346 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2347 in_height, out_width, out_height, mem_to_mem);
2348 error = (in_width > maxsinglelinewidth || !*core_clk ||
2349 *core_clk > dispc_core_clk_rate());
2350 if (error) {
2351 if (*decim_x == *decim_y) {
2352 *decim_x = min_factor;
2353 ++*decim_y;
2354 } else {
2355 swap(*decim_x, *decim_y);
2356 if (*decim_x < *decim_y)
2357 ++*decim_x;
2358 }
2359 }
2360 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2361
2362 if (error) {
2363 DSSERR("failed to find scaling settings\n");
2364 return -EINVAL;
2365 }
2366
2367 if (in_width > maxsinglelinewidth) {
2368 DSSERR("Cannot scale max input width exceeded");
2369 return -EINVAL;
2370 }
2371 return 0;
2372}
2373
2374static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2375 const struct videomode *vm,
2376 u16 width, u16 height, u16 out_width, u16 out_height,
2377 enum omap_color_mode color_mode, bool *five_taps,
2378 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2379 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2380{
2381 int error;
2382 u16 in_width, in_height;
2383 const int maxsinglelinewidth =
2384 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2385
2386 do {
2387 in_height = height / *decim_y;
2388 in_width = width / *decim_x;
2389 *five_taps = in_height > out_height;
2390
2391 if (in_width > maxsinglelinewidth)
2392 if (in_height > out_height &&
2393 in_height < out_height * 2)
2394 *five_taps = false;
2395again:
2396 if (*five_taps)
2397 *core_clk = calc_core_clk_five_taps(pclk, vm,
2398 in_width, in_height, out_width,
2399 out_height, color_mode);
2400 else
2401 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2402 in_height, out_width, out_height,
2403 mem_to_mem);
2404
2405 error = check_horiz_timing_omap3(pclk, lclk, vm,
2406 pos_x, in_width, in_height, out_width,
2407 out_height, *five_taps);
2408 if (error && *five_taps) {
2409 *five_taps = false;
2410 goto again;
2411 }
2412
2413 error = (error || in_width > maxsinglelinewidth * 2 ||
2414 (in_width > maxsinglelinewidth && *five_taps) ||
2415 !*core_clk || *core_clk > dispc_core_clk_rate());
2416
2417 if (!error) {
2418 /* verify that we're inside the limits of scaler */
2419 if (in_width / 4 > out_width)
2420 error = 1;
2421
2422 if (*five_taps) {
2423 if (in_height / 4 > out_height)
2424 error = 1;
2425 } else {
2426 if (in_height / 2 > out_height)
2427 error = 1;
2428 }
2429 }
2430
2431 if (error)
2432 ++*decim_y;
2433 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2434
2435 if (error) {
2436 DSSERR("failed to find scaling settings\n");
2437 return -EINVAL;
2438 }
2439
2440 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width,
2441 in_height, out_width, out_height, *five_taps)) {
2442 DSSERR("horizontal timing too tight\n");
2443 return -EINVAL;
2444 }
2445
2446 if (in_width > (maxsinglelinewidth * 2)) {
2447 DSSERR("Cannot setup scaling");
2448 DSSERR("width exceeds maximum width possible");
2449 return -EINVAL;
2450 }
2451
2452 if (in_width > maxsinglelinewidth && *five_taps) {
2453 DSSERR("cannot setup scaling with five taps");
2454 return -EINVAL;
2455 }
2456 return 0;
2457}
2458
2459static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2460 const struct videomode *vm,
2461 u16 width, u16 height, u16 out_width, u16 out_height,
2462 enum omap_color_mode color_mode, bool *five_taps,
2463 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2464 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2465{
2466 u16 in_width, in_width_max;
2467 int decim_x_min = *decim_x;
2468 u16 in_height = height / *decim_y;
2469 const int maxsinglelinewidth =
2470 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2471 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2472
2473 if (mem_to_mem) {
2474 in_width_max = out_width * maxdownscale;
2475 } else {
2476 in_width_max = dispc_core_clk_rate() /
2477 DIV_ROUND_UP(pclk, out_width);
2478 }
2479
2480 *decim_x = DIV_ROUND_UP(width, in_width_max);
2481
2482 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2483 if (*decim_x > *x_predecim)
2484 return -EINVAL;
2485
2486 do {
2487 in_width = width / *decim_x;
2488 } while (*decim_x <= *x_predecim &&
2489 in_width > maxsinglelinewidth && ++*decim_x);
2490
2491 if (in_width > maxsinglelinewidth) {
2492 DSSERR("Cannot scale width exceeds max line width");
2493 return -EINVAL;
2494 }
2495
2496 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2497 out_width, out_height, mem_to_mem);
2498 return 0;
2499}
2500
2501#define DIV_FRAC(dividend, divisor) \
2502 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2503
2504static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2505 enum omap_overlay_caps caps,
2506 const struct videomode *vm,
2507 u16 width, u16 height, u16 out_width, u16 out_height,
2508 enum omap_color_mode color_mode, bool *five_taps,
2509 int *x_predecim, int *y_predecim, u16 pos_x,
2510 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2511{
2512 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2513 const int max_decim_limit = 16;
2514 unsigned long core_clk = 0;
2515 int decim_x, decim_y, ret;
2516
2517 if (width == out_width && height == out_height)
2518 return 0;
2519
2520 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) {
2521 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2522 return -EINVAL;
2523 }
2524
2525 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2526 return -EINVAL;
2527
2528 if (mem_to_mem) {
2529 *x_predecim = *y_predecim = 1;
2530 } else {
2531 *x_predecim = max_decim_limit;
2532 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2533 dss_has_feature(FEAT_BURST_2D)) ?
2534 2 : max_decim_limit;
2535 }
2536
2537 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2538 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2539 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2540 color_mode == OMAP_DSS_COLOR_CLUT8) {
2541 *x_predecim = 1;
2542 *y_predecim = 1;
2543 *five_taps = false;
2544 return 0;
2545 }
2546
2547 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2548 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2549
2550 if (decim_x > *x_predecim || out_width > width * 8)
2551 return -EINVAL;
2552
2553 if (decim_y > *y_predecim || out_height > height * 8)
2554 return -EINVAL;
2555
2556 ret = dispc.feat->calc_scaling(pclk, lclk, vm, width, height,
2557 out_width, out_height, color_mode, five_taps,
2558 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2559 mem_to_mem);
2560 if (ret)
2561 return ret;
2562
2563 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2564 width, height,
2565 out_width, out_height,
2566 out_width / width, DIV_FRAC(out_width, width),
2567 out_height / height, DIV_FRAC(out_height, height),
2568
2569 decim_x, decim_y,
2570 width / decim_x, height / decim_y,
2571 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2572 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2573
2574 *five_taps ? 5 : 3,
2575 core_clk, dispc_core_clk_rate());
2576
2577 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2578 DSSERR("failed to set up scaling, "
2579 "required core clk rate = %lu Hz, "
2580 "current core clk rate = %lu Hz\n",
2581 core_clk, dispc_core_clk_rate());
2582 return -EINVAL;
2583 }
2584
2585 *x_predecim = decim_x;
2586 *y_predecim = decim_y;
2587 return 0;
2588}
2589
2590static int dispc_ovl_setup_common(enum omap_plane plane,
2591 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2592 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2593 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2594 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2595 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2596 bool replication, const struct videomode *vm,
2597 bool mem_to_mem)
2598{
2599 bool five_taps = true;
2600 bool fieldmode = false;
2601 int r, cconv = 0;
2602 unsigned offset0, offset1;
2603 s32 row_inc;
2604 s32 pix_inc;
2605 u16 frame_width, frame_height;
2606 unsigned int field_offset = 0;
2607 u16 in_height = height;
2608 u16 in_width = width;
2609 int x_predecim = 1, y_predecim = 1;
2610 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED);
2611 unsigned long pclk = dispc_plane_pclk_rate(plane);
2612 unsigned long lclk = dispc_plane_lclk_rate(plane);
2613
2614 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2615 return -EINVAL;
2616
2617 switch (color_mode) {
2618 case OMAP_DSS_COLOR_YUV2:
2619 case OMAP_DSS_COLOR_UYVY:
2620 case OMAP_DSS_COLOR_NV12:
2621 if (in_width & 1) {
2622 DSSERR("input width %d is not even for YUV format\n",
2623 in_width);
2624 return -EINVAL;
2625 }
2626 break;
2627
2628 default:
2629 break;
2630 }
2631
2632 out_width = out_width == 0 ? width : out_width;
2633 out_height = out_height == 0 ? height : out_height;
2634
2635 if (ilace && height == out_height)
2636 fieldmode = true;
2637
2638 if (ilace) {
2639 if (fieldmode)
2640 in_height /= 2;
2641 pos_y /= 2;
2642 out_height /= 2;
2643
2644 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2645 "out_height %d\n", in_height, pos_y,
2646 out_height);
2647 }
2648
2649 if (!dss_feat_color_mode_supported(plane, color_mode))
2650 return -EINVAL;
2651
2652 r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width,
2653 in_height, out_width, out_height, color_mode,
2654 &five_taps, &x_predecim, &y_predecim, pos_x,
2655 rotation_type, mem_to_mem);
2656 if (r)
2657 return r;
2658
2659 in_width = in_width / x_predecim;
2660 in_height = in_height / y_predecim;
2661
2662 if (x_predecim > 1 || y_predecim > 1)
2663 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2664 x_predecim, y_predecim, in_width, in_height);
2665
2666 switch (color_mode) {
2667 case OMAP_DSS_COLOR_YUV2:
2668 case OMAP_DSS_COLOR_UYVY:
2669 case OMAP_DSS_COLOR_NV12:
2670 if (in_width & 1) {
2671 DSSDBG("predecimated input width is not even for YUV format\n");
2672 DSSDBG("adjusting input width %d -> %d\n",
2673 in_width, in_width & ~1);
2674
2675 in_width &= ~1;
2676 }
2677 break;
2678
2679 default:
2680 break;
2681 }
2682
2683 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2684 color_mode == OMAP_DSS_COLOR_UYVY ||
2685 color_mode == OMAP_DSS_COLOR_NV12)
2686 cconv = 1;
2687
2688 if (ilace && !fieldmode) {
2689 /*
2690 * when downscaling the bottom field may have to start several
2691 * source lines below the top field. Unfortunately ACCUI
2692 * registers will only hold the fractional part of the offset
2693 * so the integer part must be added to the base address of the
2694 * bottom field.
2695 */
2696 if (!in_height || in_height == out_height)
2697 field_offset = 0;
2698 else
2699 field_offset = in_height / out_height / 2;
2700 }
2701
2702 /* Fields are independent but interleaved in memory. */
2703 if (fieldmode)
2704 field_offset = 1;
2705
2706 offset0 = 0;
2707 offset1 = 0;
2708 row_inc = 0;
2709 pix_inc = 0;
2710
2711 if (plane == OMAP_DSS_WB) {
2712 frame_width = out_width;
2713 frame_height = out_height;
2714 } else {
2715 frame_width = in_width;
2716 frame_height = height;
2717 }
2718
2719 if (rotation_type == OMAP_DSS_ROT_TILER)
2720 calc_tiler_rotation_offset(screen_width, frame_width,
2721 color_mode, fieldmode, field_offset,
2722 &offset0, &offset1, &row_inc, &pix_inc,
2723 x_predecim, y_predecim);
2724 else if (rotation_type == OMAP_DSS_ROT_DMA)
2725 calc_dma_rotation_offset(rotation, mirror, screen_width,
2726 frame_width, frame_height,
2727 color_mode, fieldmode, field_offset,
2728 &offset0, &offset1, &row_inc, &pix_inc,
2729 x_predecim, y_predecim);
2730 else
2731 calc_vrfb_rotation_offset(rotation, mirror,
2732 screen_width, frame_width, frame_height,
2733 color_mode, fieldmode, field_offset,
2734 &offset0, &offset1, &row_inc, &pix_inc,
2735 x_predecim, y_predecim);
2736
2737 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2738 offset0, offset1, row_inc, pix_inc);
2739
2740 dispc_ovl_set_color_mode(plane, color_mode);
2741
2742 dispc_ovl_configure_burst_type(plane, rotation_type);
2743
2744 if (dispc.feat->reverse_ilace_field_order)
2745 swap(offset0, offset1);
2746
2747 dispc_ovl_set_ba0(plane, paddr + offset0);
2748 dispc_ovl_set_ba1(plane, paddr + offset1);
2749
2750 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2751 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2752 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2753 }
2754
2755 if (dispc.feat->last_pixel_inc_missing)
2756 row_inc += pix_inc - 1;
2757
2758 dispc_ovl_set_row_inc(plane, row_inc);
2759 dispc_ovl_set_pix_inc(plane, pix_inc);
2760
2761 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2762 in_height, out_width, out_height);
2763
2764 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2765
2766 dispc_ovl_set_input_size(plane, in_width, in_height);
2767
2768 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2769 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2770 out_height, ilace, five_taps, fieldmode,
2771 color_mode, rotation);
2772 dispc_ovl_set_output_size(plane, out_width, out_height);
2773 dispc_ovl_set_vid_color_conv(plane, cconv);
2774 }
2775
2776 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2777 color_mode);
2778
2779 dispc_ovl_set_zorder(plane, caps, zorder);
2780 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2781 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2782
2783 dispc_ovl_enable_replication(plane, caps, replication);
2784
2785 return 0;
2786}
2787
2788int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2789 bool replication, const struct videomode *vm,
2790 bool mem_to_mem)
2791{
2792 int r;
2793 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2794 enum omap_channel channel;
2795
2796 channel = dispc_ovl_get_channel_out(plane);
2797
2798 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2799 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2800 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2801 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2802 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2803
2804 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2805 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2806 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2807 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2808 oi->rotation_type, replication, vm, mem_to_mem);
2809
2810 return r;
2811}
2812EXPORT_SYMBOL(dispc_ovl_setup);
2813
2814int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2815 bool mem_to_mem, const struct videomode *vm)
2816{
2817 int r;
2818 u32 l;
2819 enum omap_plane plane = OMAP_DSS_WB;
2820 const int pos_x = 0, pos_y = 0;
2821 const u8 zorder = 0, global_alpha = 0;
2822 const bool replication = false;
2823 bool truncation;
2824 int in_width = vm->hactive;
2825 int in_height = vm->vactive;
2826 enum omap_overlay_caps caps =
2827 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2828
2829 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2830 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2831 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2832 wi->mirror);
2833
2834 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2835 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2836 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2837 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2838 replication, vm, mem_to_mem);
2839
2840 switch (wi->color_mode) {
2841 case OMAP_DSS_COLOR_RGB16:
2842 case OMAP_DSS_COLOR_RGB24P:
2843 case OMAP_DSS_COLOR_ARGB16:
2844 case OMAP_DSS_COLOR_RGBA16:
2845 case OMAP_DSS_COLOR_RGB12U:
2846 case OMAP_DSS_COLOR_ARGB16_1555:
2847 case OMAP_DSS_COLOR_XRGB16_1555:
2848 case OMAP_DSS_COLOR_RGBX16:
2849 truncation = true;
2850 break;
2851 default:
2852 truncation = false;
2853 break;
2854 }
2855
2856 /* setup extra DISPC_WB_ATTRIBUTES */
2857 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2858 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2859 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2860 if (mem_to_mem)
2861 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
2862 else
2863 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
2864 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2865
2866 if (mem_to_mem) {
2867 /* WBDELAYCOUNT */
2868 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2869 } else {
2870 int wbdelay;
2871
2872 wbdelay = min(vm->vfront_porch +
2873 vm->vsync_len + vm->vback_porch, (u32)255);
2874
2875 /* WBDELAYCOUNT */
2876 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2877 }
2878
2879 return r;
2880}
2881
2882int dispc_ovl_enable(enum omap_plane plane, bool enable)
2883{
2884 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2885
2886 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2887
2888 return 0;
2889}
2890EXPORT_SYMBOL(dispc_ovl_enable);
2891
2892bool dispc_ovl_enabled(enum omap_plane plane)
2893{
2894 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2895}
2896EXPORT_SYMBOL(dispc_ovl_enabled);
2897
2898enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)
2899{
2900 return dss_feat_get_supported_outputs(channel);
2901}
2902EXPORT_SYMBOL(dispc_mgr_get_supported_outputs);
2903
2904void dispc_mgr_enable(enum omap_channel channel, bool enable)
2905{
2906 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2907 /* flush posted write */
2908 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2909}
2910EXPORT_SYMBOL(dispc_mgr_enable);
2911
2912bool dispc_mgr_is_enabled(enum omap_channel channel)
2913{
2914 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2915}
2916EXPORT_SYMBOL(dispc_mgr_is_enabled);
2917
2918void dispc_wb_enable(bool enable)
2919{
2920 dispc_ovl_enable(OMAP_DSS_WB, enable);
2921}
2922
2923bool dispc_wb_is_enabled(void)
2924{
2925 return dispc_ovl_enabled(OMAP_DSS_WB);
2926}
2927
2928static void dispc_lcd_enable_signal_polarity(bool act_high)
2929{
2930 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2931 return;
2932
2933 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2934}
2935
2936void dispc_lcd_enable_signal(bool enable)
2937{
2938 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2939 return;
2940
2941 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2942}
2943
2944void dispc_pck_free_enable(bool enable)
2945{
2946 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2947 return;
2948
2949 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2950}
2951
2952static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2953{
2954 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2955}
2956
2957
2958static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2959{
2960 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2961}
2962
2963static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2964{
2965 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2966}
2967
2968
2969static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2970{
2971 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2972}
2973
2974static void dispc_mgr_set_trans_key(enum omap_channel ch,
2975 enum omap_dss_trans_key_type type,
2976 u32 trans_key)
2977{
2978 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2979
2980 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2981}
2982
2983static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2984{
2985 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2986}
2987
2988static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2989 bool enable)
2990{
2991 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2992 return;
2993
2994 if (ch == OMAP_DSS_CHANNEL_LCD)
2995 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2996 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2997 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2998}
2999
3000void dispc_mgr_setup(enum omap_channel channel,
3001 const struct omap_overlay_manager_info *info)
3002{
3003 dispc_mgr_set_default_color(channel, info->default_color);
3004 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
3005 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
3006 dispc_mgr_enable_alpha_fixed_zorder(channel,
3007 info->partial_alpha_enabled);
3008 if (dss_has_feature(FEAT_CPR)) {
3009 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3010 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3011 }
3012}
3013EXPORT_SYMBOL(dispc_mgr_setup);
3014
3015static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
3016{
3017 int code;
3018
3019 switch (data_lines) {
3020 case 12:
3021 code = 0;
3022 break;
3023 case 16:
3024 code = 1;
3025 break;
3026 case 18:
3027 code = 2;
3028 break;
3029 case 24:
3030 code = 3;
3031 break;
3032 default:
3033 BUG();
3034 return;
3035 }
3036
3037 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3038}
3039
3040static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3041{
3042 u32 l;
3043 int gpout0, gpout1;
3044
3045 switch (mode) {
3046 case DSS_IO_PAD_MODE_RESET:
3047 gpout0 = 0;
3048 gpout1 = 0;
3049 break;
3050 case DSS_IO_PAD_MODE_RFBI:
3051 gpout0 = 1;
3052 gpout1 = 0;
3053 break;
3054 case DSS_IO_PAD_MODE_BYPASS:
3055 gpout0 = 1;
3056 gpout1 = 1;
3057 break;
3058 default:
3059 BUG();
3060 return;
3061 }
3062
3063 l = dispc_read_reg(DISPC_CONTROL);
3064 l = FLD_MOD(l, gpout0, 15, 15);
3065 l = FLD_MOD(l, gpout1, 16, 16);
3066 dispc_write_reg(DISPC_CONTROL, l);
3067}
3068
3069static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3070{
3071 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3072}
3073
3074void dispc_mgr_set_lcd_config(enum omap_channel channel,
3075 const struct dss_lcd_mgr_config *config)
3076{
3077 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3078
3079 dispc_mgr_enable_stallmode(channel, config->stallmode);
3080 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3081
3082 dispc_mgr_set_clock_div(channel, &config->clock_info);
3083
3084 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3085
3086 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3087
3088 dispc_mgr_set_lcd_type_tft(channel);
3089}
3090EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3091
3092static bool _dispc_mgr_size_ok(u16 width, u16 height)
3093{
3094 return width <= dispc.feat->mgr_width_max &&
3095 height <= dispc.feat->mgr_height_max;
3096}
3097
3098static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp,
3099 int vsw, int vfp, int vbp)
3100{
3101 if (hsync_len < 1 || hsync_len > dispc.feat->sw_max ||
3102 hfp < 1 || hfp > dispc.feat->hp_max ||
3103 hbp < 1 || hbp > dispc.feat->hp_max ||
3104 vsw < 1 || vsw > dispc.feat->sw_max ||
3105 vfp < 0 || vfp > dispc.feat->vp_max ||
3106 vbp < 0 || vbp > dispc.feat->vp_max)
3107 return false;
3108 return true;
3109}
3110
3111static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3112 unsigned long pclk)
3113{
3114 if (dss_mgr_is_lcd(channel))
3115 return pclk <= dispc.feat->max_lcd_pclk;
3116 else
3117 return pclk <= dispc.feat->max_tv_pclk;
3118}
3119
3120bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm)
3121{
3122 if (!_dispc_mgr_size_ok(vm->hactive, vm->vactive))
3123 return false;
3124
3125 if (!_dispc_mgr_pclk_ok(channel, vm->pixelclock))
3126 return false;
3127
3128 if (dss_mgr_is_lcd(channel)) {
3129 /* TODO: OMAP4+ supports interlace for LCD outputs */
3130 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
3131 return false;
3132
3133 if (!_dispc_lcd_timings_ok(vm->hsync_len,
3134 vm->hfront_porch, vm->hback_porch,
3135 vm->vsync_len, vm->vfront_porch,
3136 vm->vback_porch))
3137 return false;
3138 }
3139
3140 return true;
3141}
3142
3143static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
3144 const struct videomode *vm)
3145{
3146 u32 timing_h, timing_v, l;
3147 bool onoff, rf, ipc, vs, hs, de;
3148
3149 timing_h = FLD_VAL(vm->hsync_len - 1, dispc.feat->sw_start, 0) |
3150 FLD_VAL(vm->hfront_porch - 1, dispc.feat->fp_start, 8) |
3151 FLD_VAL(vm->hback_porch - 1, dispc.feat->bp_start, 20);
3152 timing_v = FLD_VAL(vm->vsync_len - 1, dispc.feat->sw_start, 0) |
3153 FLD_VAL(vm->vfront_porch, dispc.feat->fp_start, 8) |
3154 FLD_VAL(vm->vback_porch, dispc.feat->bp_start, 20);
3155
3156 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3157 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3158
3159 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
3160 vs = false;
3161 else
3162 vs = true;
3163
3164 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
3165 hs = false;
3166 else
3167 hs = true;
3168
3169 if (vm->flags & DISPLAY_FLAGS_DE_HIGH)
3170 de = false;
3171 else
3172 de = true;
3173
3174 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
3175 ipc = false;
3176 else
3177 ipc = true;
3178
3179 /* always use the 'rf' setting */
3180 onoff = true;
3181
3182 if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE)
3183 rf = true;
3184 else
3185 rf = false;
3186
3187 l = FLD_VAL(onoff, 17, 17) |
3188 FLD_VAL(rf, 16, 16) |
3189 FLD_VAL(de, 15, 15) |
3190 FLD_VAL(ipc, 14, 14) |
3191 FLD_VAL(hs, 13, 13) |
3192 FLD_VAL(vs, 12, 12);
3193
3194 /* always set ALIGN bit when available */
3195 if (dispc.feat->supports_sync_align)
3196 l |= (1 << 18);
3197
3198 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3199
3200 if (dispc.syscon_pol) {
3201 const int shifts[] = {
3202 [OMAP_DSS_CHANNEL_LCD] = 0,
3203 [OMAP_DSS_CHANNEL_LCD2] = 1,
3204 [OMAP_DSS_CHANNEL_LCD3] = 2,
3205 };
3206
3207 u32 mask, val;
3208
3209 mask = (1 << 0) | (1 << 3) | (1 << 6);
3210 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3211
3212 mask <<= 16 + shifts[channel];
3213 val <<= 16 + shifts[channel];
3214
3215 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3216 mask, val);
3217 }
3218}
3219
3220/* change name to mode? */
3221void dispc_mgr_set_timings(enum omap_channel channel,
3222 const struct videomode *vm)
3223{
3224 unsigned xtot, ytot;
3225 unsigned long ht, vt;
3226 struct videomode t = *vm;
3227
3228 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
3229
3230 if (!dispc_mgr_timings_ok(channel, &t)) {
3231 BUG();
3232 return;
3233 }
3234
3235 if (dss_mgr_is_lcd(channel)) {
3236 _dispc_mgr_set_lcd_timings(channel, &t);
3237
3238 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
3239 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;
3240
3241 ht = vm->pixelclock / xtot;
3242 vt = vm->pixelclock / xtot / ytot;
3243
3244 DSSDBG("pck %lu\n", vm->pixelclock);
3245 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3246 t.hsync_len, t.hfront_porch, t.hback_porch,
3247 t.vsync_len, t.vfront_porch, t.vback_porch);
3248 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3249 !!(t.flags & DISPLAY_FLAGS_VSYNC_HIGH),
3250 !!(t.flags & DISPLAY_FLAGS_HSYNC_HIGH),
3251 !!(t.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE),
3252 !!(t.flags & DISPLAY_FLAGS_DE_HIGH),
3253 !!(t.flags & DISPLAY_FLAGS_SYNC_POSEDGE));
3254
3255 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3256 } else {
3257 if (t.flags & DISPLAY_FLAGS_INTERLACED)
3258 t.vactive /= 2;
3259
3260 if (dispc.feat->supports_double_pixel)
3261 REG_FLD_MOD(DISPC_CONTROL,
3262 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK),
3263 19, 17);
3264 }
3265
3266 dispc_mgr_set_size(channel, t.hactive, t.vactive);
3267}
3268EXPORT_SYMBOL(dispc_mgr_set_timings);
3269
3270static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3271 u16 pck_div)
3272{
3273 BUG_ON(lck_div < 1);
3274 BUG_ON(pck_div < 1);
3275
3276 dispc_write_reg(DISPC_DIVISORo(channel),
3277 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3278
3279 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3280 channel == OMAP_DSS_CHANNEL_LCD)
3281 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3282}
3283
3284static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3285 int *pck_div)
3286{
3287 u32 l;
3288 l = dispc_read_reg(DISPC_DIVISORo(channel));
3289 *lck_div = FLD_GET(l, 23, 16);
3290 *pck_div = FLD_GET(l, 7, 0);
3291}
3292
3293static unsigned long dispc_fclk_rate(void)
3294{
3295 unsigned long r;
3296 enum dss_clk_source src;
3297
3298 src = dss_get_dispc_clk_source();
3299
3300 if (src == DSS_CLK_SRC_FCK) {
3301 r = dss_get_dispc_clk_rate();
3302 } else {
3303 struct dss_pll *pll;
3304 unsigned clkout_idx;
3305
3306 pll = dss_pll_find_by_src(src);
3307 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3308
3309 r = pll->cinfo.clkout[clkout_idx];
3310 }
3311
3312 return r;
3313}
3314
3315static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3316{
3317 int lcd;
3318 unsigned long r;
3319 enum dss_clk_source src;
3320
3321 /* for TV, LCLK rate is the FCLK rate */
3322 if (!dss_mgr_is_lcd(channel))
3323 return dispc_fclk_rate();
3324
3325 src = dss_get_lcd_clk_source(channel);
3326
3327 if (src == DSS_CLK_SRC_FCK) {
3328 r = dss_get_dispc_clk_rate();
3329 } else {
3330 struct dss_pll *pll;
3331 unsigned clkout_idx;
3332
3333 pll = dss_pll_find_by_src(src);
3334 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3335
3336 r = pll->cinfo.clkout[clkout_idx];
3337 }
3338
3339 lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3340
3341 return r / lcd;
3342}
3343
3344static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3345{
3346 unsigned long r;
3347
3348 if (dss_mgr_is_lcd(channel)) {
3349 int pcd;
3350 u32 l;
3351
3352 l = dispc_read_reg(DISPC_DIVISORo(channel));
3353
3354 pcd = FLD_GET(l, 7, 0);
3355
3356 r = dispc_mgr_lclk_rate(channel);
3357
3358 return r / pcd;
3359 } else {
3360 return dispc.tv_pclk_rate;
3361 }
3362}
3363
3364void dispc_set_tv_pclk(unsigned long pclk)
3365{
3366 dispc.tv_pclk_rate = pclk;
3367}
3368
3369static unsigned long dispc_core_clk_rate(void)
3370{
3371 return dispc.core_clk_rate;
3372}
3373
3374static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3375{
3376 enum omap_channel channel;
3377
3378 if (plane == OMAP_DSS_WB)
3379 return 0;
3380
3381 channel = dispc_ovl_get_channel_out(plane);
3382
3383 return dispc_mgr_pclk_rate(channel);
3384}
3385
3386static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3387{
3388 enum omap_channel channel;
3389
3390 if (plane == OMAP_DSS_WB)
3391 return 0;
3392
3393 channel = dispc_ovl_get_channel_out(plane);
3394
3395 return dispc_mgr_lclk_rate(channel);
3396}
3397
3398static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3399{
3400 int lcd, pcd;
3401 enum dss_clk_source lcd_clk_src;
3402
3403 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3404
3405 lcd_clk_src = dss_get_lcd_clk_source(channel);
3406
3407 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
3408 dss_get_clk_source_name(lcd_clk_src));
3409
3410 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3411
3412 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3413 dispc_mgr_lclk_rate(channel), lcd);
3414 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3415 dispc_mgr_pclk_rate(channel), pcd);
3416}
3417
3418void dispc_dump_clocks(struct seq_file *s)
3419{
3420 int lcd;
3421 u32 l;
3422 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3423
3424 if (dispc_runtime_get())
3425 return;
3426
3427 seq_printf(s, "- DISPC -\n");
3428
3429 seq_printf(s, "dispc fclk source = %s\n",
3430 dss_get_clk_source_name(dispc_clk_src));
3431
3432 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3433
3434 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3435 seq_printf(s, "- DISPC-CORE-CLK -\n");
3436 l = dispc_read_reg(DISPC_DIVISOR);
3437 lcd = FLD_GET(l, 23, 16);
3438
3439 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3440 (dispc_fclk_rate()/lcd), lcd);
3441 }
3442
3443 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3444
3445 if (dss_has_feature(FEAT_MGR_LCD2))
3446 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3447 if (dss_has_feature(FEAT_MGR_LCD3))
3448 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3449
3450 dispc_runtime_put();
3451}
3452
3453static void dispc_dump_regs(struct seq_file *s)
3454{
3455 int i, j;
3456 const char *mgr_names[] = {
3457 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3458 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3459 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3460 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3461 };
3462 const char *ovl_names[] = {
3463 [OMAP_DSS_GFX] = "GFX",
3464 [OMAP_DSS_VIDEO1] = "VID1",
3465 [OMAP_DSS_VIDEO2] = "VID2",
3466 [OMAP_DSS_VIDEO3] = "VID3",
3467 [OMAP_DSS_WB] = "WB",
3468 };
3469 const char **p_names;
3470
3471#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3472
3473 if (dispc_runtime_get())
3474 return;
3475
3476 /* DISPC common registers */
3477 DUMPREG(DISPC_REVISION);
3478 DUMPREG(DISPC_SYSCONFIG);
3479 DUMPREG(DISPC_SYSSTATUS);
3480 DUMPREG(DISPC_IRQSTATUS);
3481 DUMPREG(DISPC_IRQENABLE);
3482 DUMPREG(DISPC_CONTROL);
3483 DUMPREG(DISPC_CONFIG);
3484 DUMPREG(DISPC_CAPABLE);
3485 DUMPREG(DISPC_LINE_STATUS);
3486 DUMPREG(DISPC_LINE_NUMBER);
3487 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3488 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3489 DUMPREG(DISPC_GLOBAL_ALPHA);
3490 if (dss_has_feature(FEAT_MGR_LCD2)) {
3491 DUMPREG(DISPC_CONTROL2);
3492 DUMPREG(DISPC_CONFIG2);
3493 }
3494 if (dss_has_feature(FEAT_MGR_LCD3)) {
3495 DUMPREG(DISPC_CONTROL3);
3496 DUMPREG(DISPC_CONFIG3);
3497 }
3498 if (dss_has_feature(FEAT_MFLAG))
3499 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3500
3501#undef DUMPREG
3502
3503#define DISPC_REG(i, name) name(i)
3504#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3505 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3506 dispc_read_reg(DISPC_REG(i, r)))
3507
3508 p_names = mgr_names;
3509
3510 /* DISPC channel specific registers */
3511 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3512 DUMPREG(i, DISPC_DEFAULT_COLOR);
3513 DUMPREG(i, DISPC_TRANS_COLOR);
3514 DUMPREG(i, DISPC_SIZE_MGR);
3515
3516 if (i == OMAP_DSS_CHANNEL_DIGIT)
3517 continue;
3518
3519 DUMPREG(i, DISPC_TIMING_H);
3520 DUMPREG(i, DISPC_TIMING_V);
3521 DUMPREG(i, DISPC_POL_FREQ);
3522 DUMPREG(i, DISPC_DIVISORo);
3523
3524 DUMPREG(i, DISPC_DATA_CYCLE1);
3525 DUMPREG(i, DISPC_DATA_CYCLE2);
3526 DUMPREG(i, DISPC_DATA_CYCLE3);
3527
3528 if (dss_has_feature(FEAT_CPR)) {
3529 DUMPREG(i, DISPC_CPR_COEF_R);
3530 DUMPREG(i, DISPC_CPR_COEF_G);
3531 DUMPREG(i, DISPC_CPR_COEF_B);
3532 }
3533 }
3534
3535 p_names = ovl_names;
3536
3537 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3538 DUMPREG(i, DISPC_OVL_BA0);
3539 DUMPREG(i, DISPC_OVL_BA1);
3540 DUMPREG(i, DISPC_OVL_POSITION);
3541 DUMPREG(i, DISPC_OVL_SIZE);
3542 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3543 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3544 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3545 DUMPREG(i, DISPC_OVL_ROW_INC);
3546 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3547
3548 if (dss_has_feature(FEAT_PRELOAD))
3549 DUMPREG(i, DISPC_OVL_PRELOAD);
3550 if (dss_has_feature(FEAT_MFLAG))
3551 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3552
3553 if (i == OMAP_DSS_GFX) {
3554 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3555 DUMPREG(i, DISPC_OVL_TABLE_BA);
3556 continue;
3557 }
3558
3559 DUMPREG(i, DISPC_OVL_FIR);
3560 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3561 DUMPREG(i, DISPC_OVL_ACCU0);
3562 DUMPREG(i, DISPC_OVL_ACCU1);
3563 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3564 DUMPREG(i, DISPC_OVL_BA0_UV);
3565 DUMPREG(i, DISPC_OVL_BA1_UV);
3566 DUMPREG(i, DISPC_OVL_FIR2);
3567 DUMPREG(i, DISPC_OVL_ACCU2_0);
3568 DUMPREG(i, DISPC_OVL_ACCU2_1);
3569 }
3570 if (dss_has_feature(FEAT_ATTR2))
3571 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3572 }
3573
3574 if (dispc.feat->has_writeback) {
3575 i = OMAP_DSS_WB;
3576 DUMPREG(i, DISPC_OVL_BA0);
3577 DUMPREG(i, DISPC_OVL_BA1);
3578 DUMPREG(i, DISPC_OVL_SIZE);
3579 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3580 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3581 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3582 DUMPREG(i, DISPC_OVL_ROW_INC);
3583 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3584
3585 if (dss_has_feature(FEAT_MFLAG))
3586 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3587
3588 DUMPREG(i, DISPC_OVL_FIR);
3589 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3590 DUMPREG(i, DISPC_OVL_ACCU0);
3591 DUMPREG(i, DISPC_OVL_ACCU1);
3592 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3593 DUMPREG(i, DISPC_OVL_BA0_UV);
3594 DUMPREG(i, DISPC_OVL_BA1_UV);
3595 DUMPREG(i, DISPC_OVL_FIR2);
3596 DUMPREG(i, DISPC_OVL_ACCU2_0);
3597 DUMPREG(i, DISPC_OVL_ACCU2_1);
3598 }
3599 if (dss_has_feature(FEAT_ATTR2))
3600 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3601 }
3602
3603#undef DISPC_REG
3604#undef DUMPREG
3605
3606#define DISPC_REG(plane, name, i) name(plane, i)
3607#define DUMPREG(plane, name, i) \
3608 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3609 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3610 dispc_read_reg(DISPC_REG(plane, name, i)))
3611
3612 /* Video pipeline coefficient registers */
3613
3614 /* start from OMAP_DSS_VIDEO1 */
3615 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3616 for (j = 0; j < 8; j++)
3617 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3618
3619 for (j = 0; j < 8; j++)
3620 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3621
3622 for (j = 0; j < 5; j++)
3623 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3624
3625 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3626 for (j = 0; j < 8; j++)
3627 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3628 }
3629
3630 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3631 for (j = 0; j < 8; j++)
3632 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3633
3634 for (j = 0; j < 8; j++)
3635 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3636
3637 for (j = 0; j < 8; j++)
3638 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3639 }
3640 }
3641
3642 dispc_runtime_put();
3643
3644#undef DISPC_REG
3645#undef DUMPREG
3646}
3647
3648/* calculate clock rates using dividers in cinfo */
3649int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3650 struct dispc_clock_info *cinfo)
3651{
3652 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3653 return -EINVAL;
3654 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3655 return -EINVAL;
3656
3657 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3658 cinfo->pck = cinfo->lck / cinfo->pck_div;
3659
3660 return 0;
3661}
3662
3663bool dispc_div_calc(unsigned long dispc,
3664 unsigned long pck_min, unsigned long pck_max,
3665 dispc_div_calc_func func, void *data)
3666{
3667 int lckd, lckd_start, lckd_stop;
3668 int pckd, pckd_start, pckd_stop;
3669 unsigned long pck, lck;
3670 unsigned long lck_max;
3671 unsigned long pckd_hw_min, pckd_hw_max;
3672 unsigned min_fck_per_pck;
3673 unsigned long fck;
3674
3675#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3676 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3677#else
3678 min_fck_per_pck = 0;
3679#endif
3680
3681 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3682 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3683
3684 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3685
3686 pck_min = pck_min ? pck_min : 1;
3687 pck_max = pck_max ? pck_max : ULONG_MAX;
3688
3689 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3690 lckd_stop = min(dispc / pck_min, 255ul);
3691
3692 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3693 lck = dispc / lckd;
3694
3695 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3696 pckd_stop = min(lck / pck_min, pckd_hw_max);
3697
3698 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3699 pck = lck / pckd;
3700
3701 /*
3702 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3703 * clock, which means we're configuring DISPC fclk here
3704 * also. Thus we need to use the calculated lck. For
3705 * OMAP4+ the DISPC fclk is a separate clock.
3706 */
3707 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3708 fck = dispc_core_clk_rate();
3709 else
3710 fck = lck;
3711
3712 if (fck < pck * min_fck_per_pck)
3713 continue;
3714
3715 if (func(lckd, pckd, lck, pck, data))
3716 return true;
3717 }
3718 }
3719
3720 return false;
3721}
3722
3723void dispc_mgr_set_clock_div(enum omap_channel channel,
3724 const struct dispc_clock_info *cinfo)
3725{
3726 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3727 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3728
3729 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3730}
3731
3732int dispc_mgr_get_clock_div(enum omap_channel channel,
3733 struct dispc_clock_info *cinfo)
3734{
3735 unsigned long fck;
3736
3737 fck = dispc_fclk_rate();
3738
3739 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3740 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3741
3742 cinfo->lck = fck / cinfo->lck_div;
3743 cinfo->pck = cinfo->lck / cinfo->pck_div;
3744
3745 return 0;
3746}
3747
3748u32 dispc_read_irqstatus(void)
3749{
3750 return dispc_read_reg(DISPC_IRQSTATUS);
3751}
3752EXPORT_SYMBOL(dispc_read_irqstatus);
3753
3754void dispc_clear_irqstatus(u32 mask)
3755{
3756 dispc_write_reg(DISPC_IRQSTATUS, mask);
3757}
3758EXPORT_SYMBOL(dispc_clear_irqstatus);
3759
3760u32 dispc_read_irqenable(void)
3761{
3762 return dispc_read_reg(DISPC_IRQENABLE);
3763}
3764EXPORT_SYMBOL(dispc_read_irqenable);
3765
3766void dispc_write_irqenable(u32 mask)
3767{
3768 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3769
3770 /* clear the irqstatus for newly enabled irqs */
3771 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3772
3773 dispc_write_reg(DISPC_IRQENABLE, mask);
3774}
3775EXPORT_SYMBOL(dispc_write_irqenable);
3776
3777void dispc_enable_sidle(void)
3778{
3779 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3780}
3781
3782void dispc_disable_sidle(void)
3783{
3784 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3785}
3786
3787u32 dispc_mgr_gamma_size(enum omap_channel channel)
3788{
3789 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3790
3791 if (!dispc.feat->has_gamma_table)
3792 return 0;
3793
3794 return gdesc->len;
3795}
3796EXPORT_SYMBOL(dispc_mgr_gamma_size);
3797
3798static void dispc_mgr_write_gamma_table(enum omap_channel channel)
3799{
3800 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3801 u32 *table = dispc.gamma_table[channel];
3802 unsigned int i;
3803
3804 DSSDBG("%s: channel %d\n", __func__, channel);
3805
3806 for (i = 0; i < gdesc->len; ++i) {
3807 u32 v = table[i];
3808
3809 if (gdesc->has_index)
3810 v |= i << 24;
3811 else if (i == 0)
3812 v |= 1 << 31;
3813
3814 dispc_write_reg(gdesc->reg, v);
3815 }
3816}
3817
3818static void dispc_restore_gamma_tables(void)
3819{
3820 DSSDBG("%s()\n", __func__);
3821
3822 if (!dispc.feat->has_gamma_table)
3823 return;
3824
3825 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD);
3826
3827 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT);
3828
3829 if (dss_has_feature(FEAT_MGR_LCD2))
3830 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2);
3831
3832 if (dss_has_feature(FEAT_MGR_LCD3))
3833 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3);
3834}
3835
3836static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = {
3837 { .red = 0, .green = 0, .blue = 0, },
3838 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
3839};
3840
3841void dispc_mgr_set_gamma(enum omap_channel channel,
3842 const struct drm_color_lut *lut,
3843 unsigned int length)
3844{
3845 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3846 u32 *table = dispc.gamma_table[channel];
3847 uint i;
3848
3849 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3850 channel, length, gdesc->len);
3851
3852 if (!dispc.feat->has_gamma_table)
3853 return;
3854
3855 if (lut == NULL || length < 2) {
3856 lut = dispc_mgr_gamma_default_lut;
3857 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut);
3858 }
3859
3860 for (i = 0; i < length - 1; ++i) {
3861 uint first = i * (gdesc->len - 1) / (length - 1);
3862 uint last = (i + 1) * (gdesc->len - 1) / (length - 1);
3863 uint w = last - first;
3864 u16 r, g, b;
3865 uint j;
3866
3867 if (w == 0)
3868 continue;
3869
3870 for (j = 0; j <= w; j++) {
3871 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w;
3872 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w;
3873 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w;
3874
3875 r >>= 16 - gdesc->bits;
3876 g >>= 16 - gdesc->bits;
3877 b >>= 16 - gdesc->bits;
3878
3879 table[first + j] = (r << (gdesc->bits * 2)) |
3880 (g << gdesc->bits) | b;
3881 }
3882 }
3883
3884 if (dispc.is_enabled)
3885 dispc_mgr_write_gamma_table(channel);
3886}
3887EXPORT_SYMBOL(dispc_mgr_set_gamma);
3888
3889static int dispc_init_gamma_tables(void)
3890{
3891 int channel;
3892
3893 if (!dispc.feat->has_gamma_table)
3894 return 0;
3895
3896 for (channel = 0; channel < ARRAY_SIZE(dispc.gamma_table); channel++) {
3897 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3898 u32 *gt;
3899
3900 if (channel == OMAP_DSS_CHANNEL_LCD2 &&
3901 !dss_has_feature(FEAT_MGR_LCD2))
3902 continue;
3903
3904 if (channel == OMAP_DSS_CHANNEL_LCD3 &&
3905 !dss_has_feature(FEAT_MGR_LCD3))
3906 continue;
3907
3908 gt = devm_kmalloc_array(&dispc.pdev->dev, gdesc->len,
3909 sizeof(u32), GFP_KERNEL);
3910 if (!gt)
3911 return -ENOMEM;
3912
3913 dispc.gamma_table[channel] = gt;
3914
3915 dispc_mgr_set_gamma(channel, NULL, 0);
3916 }
3917 return 0;
3918}
3919
3920static void _omap_dispc_initial_config(void)
3921{
3922 u32 l;
3923
3924 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3925 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3926 l = dispc_read_reg(DISPC_DIVISOR);
3927 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3928 l = FLD_MOD(l, 1, 0, 0);
3929 l = FLD_MOD(l, 1, 23, 16);
3930 dispc_write_reg(DISPC_DIVISOR, l);
3931
3932 dispc.core_clk_rate = dispc_fclk_rate();
3933 }
3934
3935 /* Use gamma table mode, instead of palette mode */
3936 if (dispc.feat->has_gamma_table)
3937 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
3938
3939 /* For older DSS versions (FEAT_FUNCGATED) this enables
3940 * func-clock auto-gating. For newer versions
3941 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables.
3942 */
3943 if (dss_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table)
3944 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3945
3946 dispc_setup_color_conv_coef();
3947
3948 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3949
3950 dispc_init_fifos();
3951
3952 dispc_configure_burst_sizes();
3953
3954 dispc_ovl_enable_zorder_planes();
3955
3956 if (dispc.feat->mstandby_workaround)
3957 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3958
3959 if (dss_has_feature(FEAT_MFLAG))
3960 dispc_init_mflag();
3961}
3962
3963static const struct dispc_features omap24xx_dispc_feats = {
3964 .sw_start = 5,
3965 .fp_start = 15,
3966 .bp_start = 27,
3967 .sw_max = 64,
3968 .vp_max = 255,
3969 .hp_max = 256,
3970 .mgr_width_start = 10,
3971 .mgr_height_start = 26,
3972 .mgr_width_max = 2048,
3973 .mgr_height_max = 2048,
3974 .max_lcd_pclk = 66500000,
3975 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3976 .calc_core_clk = calc_core_clk_24xx,
3977 .num_fifos = 3,
3978 .no_framedone_tv = true,
3979 .set_max_preload = false,
3980 .last_pixel_inc_missing = true,
3981};
3982
3983static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3984 .sw_start = 5,
3985 .fp_start = 15,
3986 .bp_start = 27,
3987 .sw_max = 64,
3988 .vp_max = 255,
3989 .hp_max = 256,
3990 .mgr_width_start = 10,
3991 .mgr_height_start = 26,
3992 .mgr_width_max = 2048,
3993 .mgr_height_max = 2048,
3994 .max_lcd_pclk = 173000000,
3995 .max_tv_pclk = 59000000,
3996 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3997 .calc_core_clk = calc_core_clk_34xx,
3998 .num_fifos = 3,
3999 .no_framedone_tv = true,
4000 .set_max_preload = false,
4001 .last_pixel_inc_missing = true,
4002};
4003
4004static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
4005 .sw_start = 7,
4006 .fp_start = 19,
4007 .bp_start = 31,
4008 .sw_max = 256,
4009 .vp_max = 4095,
4010 .hp_max = 4096,
4011 .mgr_width_start = 10,
4012 .mgr_height_start = 26,
4013 .mgr_width_max = 2048,
4014 .mgr_height_max = 2048,
4015 .max_lcd_pclk = 173000000,
4016 .max_tv_pclk = 59000000,
4017 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4018 .calc_core_clk = calc_core_clk_34xx,
4019 .num_fifos = 3,
4020 .no_framedone_tv = true,
4021 .set_max_preload = false,
4022 .last_pixel_inc_missing = true,
4023};
4024
4025static const struct dispc_features omap44xx_dispc_feats = {
4026 .sw_start = 7,
4027 .fp_start = 19,
4028 .bp_start = 31,
4029 .sw_max = 256,
4030 .vp_max = 4095,
4031 .hp_max = 4096,
4032 .mgr_width_start = 10,
4033 .mgr_height_start = 26,
4034 .mgr_width_max = 2048,
4035 .mgr_height_max = 2048,
4036 .max_lcd_pclk = 170000000,
4037 .max_tv_pclk = 185625000,
4038 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4039 .calc_core_clk = calc_core_clk_44xx,
4040 .num_fifos = 5,
4041 .gfx_fifo_workaround = true,
4042 .set_max_preload = true,
4043 .supports_sync_align = true,
4044 .has_writeback = true,
4045 .supports_double_pixel = true,
4046 .reverse_ilace_field_order = true,
4047 .has_gamma_table = true,
4048 .has_gamma_i734_bug = true,
4049};
4050
4051static const struct dispc_features omap54xx_dispc_feats = {
4052 .sw_start = 7,
4053 .fp_start = 19,
4054 .bp_start = 31,
4055 .sw_max = 256,
4056 .vp_max = 4095,
4057 .hp_max = 4096,
4058 .mgr_width_start = 11,
4059 .mgr_height_start = 27,
4060 .mgr_width_max = 4096,
4061 .mgr_height_max = 4096,
4062 .max_lcd_pclk = 170000000,
4063 .max_tv_pclk = 186000000,
4064 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4065 .calc_core_clk = calc_core_clk_44xx,
4066 .num_fifos = 5,
4067 .gfx_fifo_workaround = true,
4068 .mstandby_workaround = true,
4069 .set_max_preload = true,
4070 .supports_sync_align = true,
4071 .has_writeback = true,
4072 .supports_double_pixel = true,
4073 .reverse_ilace_field_order = true,
4074 .has_gamma_table = true,
4075 .has_gamma_i734_bug = true,
4076};
4077
4078static int dispc_init_features(struct platform_device *pdev)
4079{
4080 const struct dispc_features *src;
4081 struct dispc_features *dst;
4082
4083 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
4084 if (!dst) {
4085 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
4086 return -ENOMEM;
4087 }
4088
4089 switch (omapdss_get_version()) {
4090 case OMAPDSS_VER_OMAP24xx:
4091 src = &omap24xx_dispc_feats;
4092 break;
4093
4094 case OMAPDSS_VER_OMAP34xx_ES1:
4095 src = &omap34xx_rev1_0_dispc_feats;
4096 break;
4097
4098 case OMAPDSS_VER_OMAP34xx_ES3:
4099 case OMAPDSS_VER_OMAP3630:
4100 case OMAPDSS_VER_AM35xx:
4101 case OMAPDSS_VER_AM43xx:
4102 src = &omap34xx_rev3_0_dispc_feats;
4103 break;
4104
4105 case OMAPDSS_VER_OMAP4430_ES1:
4106 case OMAPDSS_VER_OMAP4430_ES2:
4107 case OMAPDSS_VER_OMAP4:
4108 src = &omap44xx_dispc_feats;
4109 break;
4110
4111 case OMAPDSS_VER_OMAP5:
4112 case OMAPDSS_VER_DRA7xx:
4113 src = &omap54xx_dispc_feats;
4114 break;
4115
4116 default:
4117 return -ENODEV;
4118 }
4119
4120 memcpy(dst, src, sizeof(*dst));
4121 dispc.feat = dst;
4122
4123 return 0;
4124}
4125
4126static irqreturn_t dispc_irq_handler(int irq, void *arg)
4127{
4128 if (!dispc.is_enabled)
4129 return IRQ_NONE;
4130
4131 return dispc.user_handler(irq, dispc.user_data);
4132}
4133
4134int dispc_request_irq(irq_handler_t handler, void *dev_id)
4135{
4136 int r;
4137
4138 if (dispc.user_handler != NULL)
4139 return -EBUSY;
4140
4141 dispc.user_handler = handler;
4142 dispc.user_data = dev_id;
4143
4144 /* ensure the dispc_irq_handler sees the values above */
4145 smp_wmb();
4146
4147 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4148 IRQF_SHARED, "OMAP DISPC", &dispc);
4149 if (r) {
4150 dispc.user_handler = NULL;
4151 dispc.user_data = NULL;
4152 }
4153
4154 return r;
4155}
4156EXPORT_SYMBOL(dispc_request_irq);
4157
4158void dispc_free_irq(void *dev_id)
4159{
4160 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4161
4162 dispc.user_handler = NULL;
4163 dispc.user_data = NULL;
4164}
4165EXPORT_SYMBOL(dispc_free_irq);
4166
4167/*
4168 * Workaround for errata i734 in DSS dispc
4169 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
4170 *
4171 * For gamma tables to work on LCD1 the GFX plane has to be used at
4172 * least once after DSS HW has come out of reset. The workaround
4173 * sets up a minimal LCD setup with GFX plane and waits for one
4174 * vertical sync irq before disabling the setup and continuing with
4175 * the context restore. The physical outputs are gated during the
4176 * operation. This workaround requires that gamma table's LOADMODE
4177 * is set to 0x2 in DISPC_CONTROL1 register.
4178 *
4179 * For details see:
4180 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata
4181 * Literature Number: SWPZ037E
4182 * Or some other relevant errata document for the DSS IP version.
4183 */
4184
4185static const struct dispc_errata_i734_data {
4186 struct videomode vm;
4187 struct omap_overlay_info ovli;
4188 struct omap_overlay_manager_info mgri;
4189 struct dss_lcd_mgr_config lcd_conf;
4190} i734 = {
4191 .vm = {
4192 .hactive = 8, .vactive = 1,
4193 .pixelclock = 16000000,
4194 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
4195 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1,
4196
4197 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4198 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
4199 DISPLAY_FLAGS_PIXDATA_POSEDGE,
4200 },
4201 .ovli = {
4202 .screen_width = 1,
4203 .width = 1, .height = 1,
4204 .color_mode = OMAP_DSS_COLOR_RGB24U,
4205 .rotation = OMAP_DSS_ROT_0,
4206 .rotation_type = OMAP_DSS_ROT_DMA,
4207 .mirror = 0,
4208 .pos_x = 0, .pos_y = 0,
4209 .out_width = 0, .out_height = 0,
4210 .global_alpha = 0xff,
4211 .pre_mult_alpha = 0,
4212 .zorder = 0,
4213 },
4214 .mgri = {
4215 .default_color = 0,
4216 .trans_enabled = false,
4217 .partial_alpha_enabled = false,
4218 .cpr_enable = false,
4219 },
4220 .lcd_conf = {
4221 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS,
4222 .stallmode = false,
4223 .fifohandcheck = false,
4224 .clock_info = {
4225 .lck_div = 1,
4226 .pck_div = 2,
4227 },
4228 .video_port_width = 24,
4229 .lcden_sig_polarity = 0,
4230 },
4231};
4232
4233static struct i734_buf {
4234 size_t size;
4235 dma_addr_t paddr;
4236 void *vaddr;
4237} i734_buf;
4238
4239static int dispc_errata_i734_wa_init(void)
4240{
4241 if (!dispc.feat->has_gamma_i734_bug)
4242 return 0;
4243
4244 i734_buf.size = i734.ovli.width * i734.ovli.height *
4245 color_mode_to_bpp(i734.ovli.color_mode) / 8;
4246
4247 i734_buf.vaddr = dma_alloc_writecombine(&dispc.pdev->dev, i734_buf.size,
4248 &i734_buf.paddr, GFP_KERNEL);
4249 if (!i734_buf.vaddr) {
4250 dev_err(&dispc.pdev->dev, "%s: dma_alloc_writecombine failed",
4251 __func__);
4252 return -ENOMEM;
4253 }
4254
4255 return 0;
4256}
4257
4258static void dispc_errata_i734_wa_fini(void)
4259{
4260 if (!dispc.feat->has_gamma_i734_bug)
4261 return;
4262
4263 dma_free_writecombine(&dispc.pdev->dev, i734_buf.size, i734_buf.vaddr,
4264 i734_buf.paddr);
4265}
4266
4267static void dispc_errata_i734_wa(void)
4268{
4269 u32 framedone_irq = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_LCD);
4270 struct omap_overlay_info ovli;
4271 struct dss_lcd_mgr_config lcd_conf;
4272 u32 gatestate;
4273 unsigned int count;
4274
4275 if (!dispc.feat->has_gamma_i734_bug)
4276 return;
4277
4278 gatestate = REG_GET(DISPC_CONFIG, 8, 4);
4279
4280 ovli = i734.ovli;
4281 ovli.paddr = i734_buf.paddr;
4282 lcd_conf = i734.lcd_conf;
4283
4284 /* Gate all LCD1 outputs */
4285 REG_FLD_MOD(DISPC_CONFIG, 0x1f, 8, 4);
4286
4287 /* Setup and enable GFX plane */
4288 dispc_ovl_set_channel_out(OMAP_DSS_GFX, OMAP_DSS_CHANNEL_LCD);
4289 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, false, &i734.vm, false);
4290 dispc_ovl_enable(OMAP_DSS_GFX, true);
4291
4292 /* Set up and enable display manager for LCD1 */
4293 dispc_mgr_setup(OMAP_DSS_CHANNEL_LCD, &i734.mgri);
4294 dispc_calc_clock_rates(dss_get_dispc_clk_rate(),
4295 &lcd_conf.clock_info);
4296 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf);
4297 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.vm);
4298
4299 dispc_clear_irqstatus(framedone_irq);
4300
4301 /* Enable and shut the channel to produce just one frame */
4302 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, true);
4303 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, false);
4304
4305 /* Busy wait for framedone. We can't fiddle with irq handlers
4306 * in PM resume. Typically the loop runs less than 5 times and
4307 * waits less than a micro second.
4308 */
4309 count = 0;
4310 while (!(dispc_read_irqstatus() & framedone_irq)) {
4311 if (count++ > 10000) {
4312 dev_err(&dispc.pdev->dev, "%s: framedone timeout\n",
4313 __func__);
4314 break;
4315 }
4316 }
4317 dispc_ovl_enable(OMAP_DSS_GFX, false);
4318
4319 /* Clear all irq bits before continuing */
4320 dispc_clear_irqstatus(0xffffffff);
4321
4322 /* Restore the original state to LCD1 output gates */
4323 REG_FLD_MOD(DISPC_CONFIG, gatestate, 8, 4);
4324}
4325
4326/* DISPC HW IP initialisation */
4327static int dispc_bind(struct device *dev, struct device *master, void *data)
4328{
4329 struct platform_device *pdev = to_platform_device(dev);
4330 u32 rev;
4331 int r = 0;
4332 struct resource *dispc_mem;
4333 struct device_node *np = pdev->dev.of_node;
4334
4335 dispc.pdev = pdev;
4336
4337 spin_lock_init(&dispc.control_lock);
4338
4339 r = dispc_init_features(dispc.pdev);
4340 if (r)
4341 return r;
4342
4343 r = dispc_errata_i734_wa_init();
4344 if (r)
4345 return r;
4346
4347 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4348 if (!dispc_mem) {
4349 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4350 return -EINVAL;
4351 }
4352
4353 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4354 resource_size(dispc_mem));
4355 if (!dispc.base) {
4356 DSSERR("can't ioremap DISPC\n");
4357 return -ENOMEM;
4358 }
4359
4360 dispc.irq = platform_get_irq(dispc.pdev, 0);
4361 if (dispc.irq < 0) {
4362 DSSERR("platform_get_irq failed\n");
4363 return -ENODEV;
4364 }
4365
4366 if (np && of_property_read_bool(np, "syscon-pol")) {
4367 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4368 if (IS_ERR(dispc.syscon_pol)) {
4369 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4370 return PTR_ERR(dispc.syscon_pol);
4371 }
4372
4373 if (of_property_read_u32_index(np, "syscon-pol", 1,
4374 &dispc.syscon_pol_offset)) {
4375 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4376 return -EINVAL;
4377 }
4378 }
4379
4380 r = dispc_init_gamma_tables();
4381 if (r)
4382 return r;
4383
4384 pm_runtime_enable(&pdev->dev);
4385
4386 r = dispc_runtime_get();
4387 if (r)
4388 goto err_runtime_get;
4389
4390 _omap_dispc_initial_config();
4391
4392 rev = dispc_read_reg(DISPC_REVISION);
4393 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4394 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4395
4396 dispc_runtime_put();
4397
4398 dss_debugfs_create_file("dispc", dispc_dump_regs);
4399
4400 return 0;
4401
4402err_runtime_get:
4403 pm_runtime_disable(&pdev->dev);
4404 return r;
4405}
4406
4407static void dispc_unbind(struct device *dev, struct device *master,
4408 void *data)
4409{
4410 pm_runtime_disable(dev);
4411
4412 dispc_errata_i734_wa_fini();
4413}
4414
4415static const struct component_ops dispc_component_ops = {
4416 .bind = dispc_bind,
4417 .unbind = dispc_unbind,
4418};
4419
4420static int dispc_probe(struct platform_device *pdev)
4421{
4422 return component_add(&pdev->dev, &dispc_component_ops);
4423}
4424
4425static int dispc_remove(struct platform_device *pdev)
4426{
4427 component_del(&pdev->dev, &dispc_component_ops);
4428 return 0;
4429}
4430
4431static int dispc_runtime_suspend(struct device *dev)
4432{
4433 dispc.is_enabled = false;
4434 /* ensure the dispc_irq_handler sees the is_enabled value */
4435 smp_wmb();
4436 /* wait for current handler to finish before turning the DISPC off */
4437 synchronize_irq(dispc.irq);
4438
4439 dispc_save_context();
4440
4441 return 0;
4442}
4443
4444static int dispc_runtime_resume(struct device *dev)
4445{
4446 /*
4447 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4448 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4449 * _omap_dispc_initial_config(). We can thus use it to detect if
4450 * we have lost register context.
4451 */
4452 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4453 _omap_dispc_initial_config();
4454
4455 dispc_errata_i734_wa();
4456
4457 dispc_restore_context();
4458
4459 dispc_restore_gamma_tables();
4460 }
4461
4462 dispc.is_enabled = true;
4463 /* ensure the dispc_irq_handler sees the is_enabled value */
4464 smp_wmb();
4465
4466 return 0;
4467}
4468
4469static const struct dev_pm_ops dispc_pm_ops = {
4470 .runtime_suspend = dispc_runtime_suspend,
4471 .runtime_resume = dispc_runtime_resume,
4472};
4473
4474static const struct of_device_id dispc_of_match[] = {
4475 { .compatible = "ti,omap2-dispc", },
4476 { .compatible = "ti,omap3-dispc", },
4477 { .compatible = "ti,omap4-dispc", },
4478 { .compatible = "ti,omap5-dispc", },
4479 { .compatible = "ti,dra7-dispc", },
4480 {},
4481};
4482
4483static struct platform_driver omap_dispchw_driver = {
4484 .probe = dispc_probe,
4485 .remove = dispc_remove,
4486 .driver = {
4487 .name = "omapdss_dispc",
4488 .pm = &dispc_pm_ops,
4489 .of_match_table = dispc_of_match,
4490 .suppress_bind_attrs = true,
4491 },
4492};
4493
4494int __init dispc_init_platform_driver(void)
4495{
4496 return platform_driver_register(&omap_dispchw_driver);
4497}
4498
4499void dispc_uninit_platform_driver(void)
4500{
4501 platform_driver_unregister(&omap_dispchw_driver);
4502}