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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "i915_drv.h"
25#include "intel_drv.h"
26#include "i915_vgpu.h"
27
28#include <linux/pm_runtime.h>
29
30#define FORCEWAKE_ACK_TIMEOUT_MS 50
31
32#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
33
34static const char * const forcewake_domain_names[] = {
35 "render",
36 "blitter",
37 "media",
38};
39
40const char *
41intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
42{
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
44
45 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
46 return forcewake_domain_names[id];
47
48 WARN_ON(id);
49
50 return "unknown";
51}
52
53static inline void
54fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
55{
56 WARN_ON(!i915_mmio_reg_valid(d->reg_set));
57 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
58}
59
60static inline void
61fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
62{
63 mod_timer_pinned(&d->timer, jiffies + 1);
64}
65
66static inline void
67fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
68{
69 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
70 FORCEWAKE_KERNEL) == 0,
71 FORCEWAKE_ACK_TIMEOUT_MS))
72 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
73 intel_uncore_forcewake_domain_to_str(d->id));
74}
75
76static inline void
77fw_domain_get(const struct intel_uncore_forcewake_domain *d)
78{
79 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
80}
81
82static inline void
83fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
84{
85 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
86 FORCEWAKE_KERNEL),
87 FORCEWAKE_ACK_TIMEOUT_MS))
88 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
89 intel_uncore_forcewake_domain_to_str(d->id));
90}
91
92static inline void
93fw_domain_put(const struct intel_uncore_forcewake_domain *d)
94{
95 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
96}
97
98static inline void
99fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
100{
101 /* something from same cacheline, but not from the set register */
102 if (i915_mmio_reg_valid(d->reg_post))
103 __raw_posting_read(d->i915, d->reg_post);
104}
105
106static void
107fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
108{
109 struct intel_uncore_forcewake_domain *d;
110 enum forcewake_domain_id id;
111
112 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
113 fw_domain_wait_ack_clear(d);
114 fw_domain_get(d);
115 fw_domain_wait_ack(d);
116 }
117}
118
119static void
120fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
121{
122 struct intel_uncore_forcewake_domain *d;
123 enum forcewake_domain_id id;
124
125 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
126 fw_domain_put(d);
127 fw_domain_posting_read(d);
128 }
129}
130
131static void
132fw_domains_posting_read(struct drm_i915_private *dev_priv)
133{
134 struct intel_uncore_forcewake_domain *d;
135 enum forcewake_domain_id id;
136
137 /* No need to do for all, just do for first found */
138 for_each_fw_domain(d, dev_priv, id) {
139 fw_domain_posting_read(d);
140 break;
141 }
142}
143
144static void
145fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
146{
147 struct intel_uncore_forcewake_domain *d;
148 enum forcewake_domain_id id;
149
150 if (dev_priv->uncore.fw_domains == 0)
151 return;
152
153 for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
154 fw_domain_reset(d);
155
156 fw_domains_posting_read(dev_priv);
157}
158
159static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
160{
161 /* w/a for a sporadic read returning 0 by waiting for the GT
162 * thread to wake up.
163 */
164 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
165 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
166 DRM_ERROR("GT thread status wait timed out\n");
167}
168
169static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
170 enum forcewake_domains fw_domains)
171{
172 fw_domains_get(dev_priv, fw_domains);
173
174 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
175 __gen6_gt_wait_for_thread_c0(dev_priv);
176}
177
178static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
179{
180 u32 gtfifodbg;
181
182 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
183 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
184 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
185}
186
187static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
188 enum forcewake_domains fw_domains)
189{
190 fw_domains_put(dev_priv, fw_domains);
191 gen6_gt_check_fifodbg(dev_priv);
192}
193
194static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
195{
196 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
197
198 return count & GT_FIFO_FREE_ENTRIES_MASK;
199}
200
201static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
202{
203 int ret = 0;
204
205 /* On VLV, FIFO will be shared by both SW and HW.
206 * So, we need to read the FREE_ENTRIES everytime */
207 if (IS_VALLEYVIEW(dev_priv->dev))
208 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
209
210 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
211 int loop = 500;
212 u32 fifo = fifo_free_entries(dev_priv);
213
214 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
215 udelay(10);
216 fifo = fifo_free_entries(dev_priv);
217 }
218 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
219 ++ret;
220 dev_priv->uncore.fifo_count = fifo;
221 }
222 dev_priv->uncore.fifo_count--;
223
224 return ret;
225}
226
227static void intel_uncore_fw_release_timer(unsigned long arg)
228{
229 struct intel_uncore_forcewake_domain *domain = (void *)arg;
230 unsigned long irqflags;
231
232 assert_rpm_device_not_suspended(domain->i915);
233
234 spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
235 if (WARN_ON(domain->wake_count == 0))
236 domain->wake_count++;
237
238 if (--domain->wake_count == 0)
239 domain->i915->uncore.funcs.force_wake_put(domain->i915,
240 1 << domain->id);
241
242 spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
243}
244
245void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
246{
247 struct drm_i915_private *dev_priv = dev->dev_private;
248 unsigned long irqflags;
249 struct intel_uncore_forcewake_domain *domain;
250 int retry_count = 100;
251 enum forcewake_domain_id id;
252 enum forcewake_domains fw = 0, active_domains;
253
254 /* Hold uncore.lock across reset to prevent any register access
255 * with forcewake not set correctly. Wait until all pending
256 * timers are run before holding.
257 */
258 while (1) {
259 active_domains = 0;
260
261 for_each_fw_domain(domain, dev_priv, id) {
262 if (del_timer_sync(&domain->timer) == 0)
263 continue;
264
265 intel_uncore_fw_release_timer((unsigned long)domain);
266 }
267
268 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
269
270 for_each_fw_domain(domain, dev_priv, id) {
271 if (timer_pending(&domain->timer))
272 active_domains |= (1 << id);
273 }
274
275 if (active_domains == 0)
276 break;
277
278 if (--retry_count == 0) {
279 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
280 break;
281 }
282
283 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
284 cond_resched();
285 }
286
287 WARN_ON(active_domains);
288
289 for_each_fw_domain(domain, dev_priv, id)
290 if (domain->wake_count)
291 fw |= 1 << id;
292
293 if (fw)
294 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
295
296 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
297
298 if (restore) { /* If reset with a user forcewake, try to restore */
299 if (fw)
300 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
301
302 if (IS_GEN6(dev) || IS_GEN7(dev))
303 dev_priv->uncore.fifo_count =
304 fifo_free_entries(dev_priv);
305 }
306
307 if (!restore)
308 assert_forcewakes_inactive(dev_priv);
309
310 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
311}
312
313static void intel_uncore_ellc_detect(struct drm_device *dev)
314{
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
318 INTEL_INFO(dev)->gen >= 9) &&
319 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
320 /* The docs do not explain exactly how the calculation can be
321 * made. It is somewhat guessable, but for now, it's always
322 * 128MB.
323 * NB: We can't write IDICR yet because we do not have gt funcs
324 * set up */
325 dev_priv->ellc_size = 128;
326 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
327 }
328}
329
330static bool
331fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
332{
333 u32 dbg;
334
335 dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
336 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
337 return false;
338
339 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
340
341 return true;
342}
343
344static bool
345vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
346{
347 u32 cer;
348
349 cer = __raw_i915_read32(dev_priv, CLAIM_ER);
350 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
351 return false;
352
353 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
354
355 return true;
356}
357
358static bool
359check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
360{
361 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
362 return fpga_check_for_unclaimed_mmio(dev_priv);
363
364 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
365 return vlv_check_for_unclaimed_mmio(dev_priv);
366
367 return false;
368}
369
370static void __intel_uncore_early_sanitize(struct drm_device *dev,
371 bool restore_forcewake)
372{
373 struct drm_i915_private *dev_priv = dev->dev_private;
374
375 /* clear out unclaimed reg detection bit */
376 if (check_for_unclaimed_mmio(dev_priv))
377 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
378
379 /* clear out old GT FIFO errors */
380 if (IS_GEN6(dev) || IS_GEN7(dev))
381 __raw_i915_write32(dev_priv, GTFIFODBG,
382 __raw_i915_read32(dev_priv, GTFIFODBG));
383
384 /* WaDisableShadowRegForCpd:chv */
385 if (IS_CHERRYVIEW(dev)) {
386 __raw_i915_write32(dev_priv, GTFIFOCTL,
387 __raw_i915_read32(dev_priv, GTFIFOCTL) |
388 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
389 GT_FIFO_CTL_RC6_POLICY_STALL);
390 }
391
392 intel_uncore_forcewake_reset(dev, restore_forcewake);
393}
394
395void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
396{
397 __intel_uncore_early_sanitize(dev, restore_forcewake);
398 i915_check_and_clear_faults(dev);
399}
400
401void intel_uncore_sanitize(struct drm_device *dev)
402{
403 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
404
405 /* BIOS often leaves RC6 enabled, but disable it for hw init */
406 intel_disable_gt_powersave(dev);
407}
408
409static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
410 enum forcewake_domains fw_domains)
411{
412 struct intel_uncore_forcewake_domain *domain;
413 enum forcewake_domain_id id;
414
415 if (!dev_priv->uncore.funcs.force_wake_get)
416 return;
417
418 fw_domains &= dev_priv->uncore.fw_domains;
419
420 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
421 if (domain->wake_count++)
422 fw_domains &= ~(1 << id);
423 }
424
425 if (fw_domains)
426 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
427}
428
429/**
430 * intel_uncore_forcewake_get - grab forcewake domain references
431 * @dev_priv: i915 device instance
432 * @fw_domains: forcewake domains to get reference on
433 *
434 * This function can be used get GT's forcewake domain references.
435 * Normal register access will handle the forcewake domains automatically.
436 * However if some sequence requires the GT to not power down a particular
437 * forcewake domains this function should be called at the beginning of the
438 * sequence. And subsequently the reference should be dropped by symmetric
439 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
440 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
441 */
442void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
443 enum forcewake_domains fw_domains)
444{
445 unsigned long irqflags;
446
447 if (!dev_priv->uncore.funcs.force_wake_get)
448 return;
449
450 assert_rpm_wakelock_held(dev_priv);
451
452 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
453 __intel_uncore_forcewake_get(dev_priv, fw_domains);
454 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
455}
456
457/**
458 * intel_uncore_forcewake_get__locked - grab forcewake domain references
459 * @dev_priv: i915 device instance
460 * @fw_domains: forcewake domains to get reference on
461 *
462 * See intel_uncore_forcewake_get(). This variant places the onus
463 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
464 */
465void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
466 enum forcewake_domains fw_domains)
467{
468 assert_spin_locked(&dev_priv->uncore.lock);
469
470 if (!dev_priv->uncore.funcs.force_wake_get)
471 return;
472
473 __intel_uncore_forcewake_get(dev_priv, fw_domains);
474}
475
476static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
477 enum forcewake_domains fw_domains)
478{
479 struct intel_uncore_forcewake_domain *domain;
480 enum forcewake_domain_id id;
481
482 if (!dev_priv->uncore.funcs.force_wake_put)
483 return;
484
485 fw_domains &= dev_priv->uncore.fw_domains;
486
487 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
488 if (WARN_ON(domain->wake_count == 0))
489 continue;
490
491 if (--domain->wake_count)
492 continue;
493
494 domain->wake_count++;
495 fw_domain_arm_timer(domain);
496 }
497}
498
499/**
500 * intel_uncore_forcewake_put - release a forcewake domain reference
501 * @dev_priv: i915 device instance
502 * @fw_domains: forcewake domains to put references
503 *
504 * This function drops the device-level forcewakes for specified
505 * domains obtained by intel_uncore_forcewake_get().
506 */
507void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
508 enum forcewake_domains fw_domains)
509{
510 unsigned long irqflags;
511
512 if (!dev_priv->uncore.funcs.force_wake_put)
513 return;
514
515 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
516 __intel_uncore_forcewake_put(dev_priv, fw_domains);
517 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
518}
519
520/**
521 * intel_uncore_forcewake_put__locked - grab forcewake domain references
522 * @dev_priv: i915 device instance
523 * @fw_domains: forcewake domains to get reference on
524 *
525 * See intel_uncore_forcewake_put(). This variant places the onus
526 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
527 */
528void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
529 enum forcewake_domains fw_domains)
530{
531 assert_spin_locked(&dev_priv->uncore.lock);
532
533 if (!dev_priv->uncore.funcs.force_wake_put)
534 return;
535
536 __intel_uncore_forcewake_put(dev_priv, fw_domains);
537}
538
539void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
540{
541 struct intel_uncore_forcewake_domain *domain;
542 enum forcewake_domain_id id;
543
544 if (!dev_priv->uncore.funcs.force_wake_get)
545 return;
546
547 for_each_fw_domain(domain, dev_priv, id)
548 WARN_ON(domain->wake_count);
549}
550
551/* We give fast paths for the really cool registers */
552#define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
553
554#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
555
556#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
557 (REG_RANGE((reg), 0x2000, 0x4000) || \
558 REG_RANGE((reg), 0x5000, 0x8000) || \
559 REG_RANGE((reg), 0xB000, 0x12000) || \
560 REG_RANGE((reg), 0x2E000, 0x30000))
561
562#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
563 (REG_RANGE((reg), 0x12000, 0x14000) || \
564 REG_RANGE((reg), 0x22000, 0x24000) || \
565 REG_RANGE((reg), 0x30000, 0x40000))
566
567#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
568 (REG_RANGE((reg), 0x2000, 0x4000) || \
569 REG_RANGE((reg), 0x5200, 0x8000) || \
570 REG_RANGE((reg), 0x8300, 0x8500) || \
571 REG_RANGE((reg), 0xB000, 0xB480) || \
572 REG_RANGE((reg), 0xE000, 0xE800))
573
574#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
575 (REG_RANGE((reg), 0x8800, 0x8900) || \
576 REG_RANGE((reg), 0xD000, 0xD800) || \
577 REG_RANGE((reg), 0x12000, 0x14000) || \
578 REG_RANGE((reg), 0x1A000, 0x1C000) || \
579 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
580 REG_RANGE((reg), 0x30000, 0x38000))
581
582#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
583 (REG_RANGE((reg), 0x4000, 0x5000) || \
584 REG_RANGE((reg), 0x8000, 0x8300) || \
585 REG_RANGE((reg), 0x8500, 0x8600) || \
586 REG_RANGE((reg), 0x9000, 0xB000) || \
587 REG_RANGE((reg), 0xF000, 0x10000))
588
589#define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
590 REG_RANGE((reg), 0xB00, 0x2000)
591
592#define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
593 (REG_RANGE((reg), 0x2000, 0x2700) || \
594 REG_RANGE((reg), 0x3000, 0x4000) || \
595 REG_RANGE((reg), 0x5200, 0x8000) || \
596 REG_RANGE((reg), 0x8140, 0x8160) || \
597 REG_RANGE((reg), 0x8300, 0x8500) || \
598 REG_RANGE((reg), 0x8C00, 0x8D00) || \
599 REG_RANGE((reg), 0xB000, 0xB480) || \
600 REG_RANGE((reg), 0xE000, 0xE900) || \
601 REG_RANGE((reg), 0x24400, 0x24800))
602
603#define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
604 (REG_RANGE((reg), 0x8130, 0x8140) || \
605 REG_RANGE((reg), 0x8800, 0x8A00) || \
606 REG_RANGE((reg), 0xD000, 0xD800) || \
607 REG_RANGE((reg), 0x12000, 0x14000) || \
608 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
609 REG_RANGE((reg), 0x30000, 0x40000))
610
611#define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
612 REG_RANGE((reg), 0x9400, 0x9800)
613
614#define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
615 ((reg) < 0x40000 && \
616 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
617 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
618 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
619 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
620
621static void
622ilk_dummy_write(struct drm_i915_private *dev_priv)
623{
624 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
625 * the chip from rc6 before touching it for real. MI_MODE is masked,
626 * hence harmless to write 0 into. */
627 __raw_i915_write32(dev_priv, MI_MODE, 0);
628}
629
630static void
631__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
632 const i915_reg_t reg,
633 const bool read,
634 const bool before)
635{
636 /* XXX. We limit the auto arming traces for mmio
637 * debugs on these platforms. There are just too many
638 * revealed by these and CI/Bat suffers from the noise.
639 * Please fix and then re-enable the automatic traces.
640 */
641 if (i915.mmio_debug < 2 &&
642 (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
643 return;
644
645 if (WARN(check_for_unclaimed_mmio(dev_priv),
646 "Unclaimed register detected %s %s register 0x%x\n",
647 before ? "before" : "after",
648 read ? "reading" : "writing to",
649 i915_mmio_reg_offset(reg)))
650 i915.mmio_debug--; /* Only report the first N failures */
651}
652
653static inline void
654unclaimed_reg_debug(struct drm_i915_private *dev_priv,
655 const i915_reg_t reg,
656 const bool read,
657 const bool before)
658{
659 if (likely(!i915.mmio_debug))
660 return;
661
662 __unclaimed_reg_debug(dev_priv, reg, read, before);
663}
664
665#define GEN2_READ_HEADER(x) \
666 u##x val = 0; \
667 assert_rpm_wakelock_held(dev_priv);
668
669#define GEN2_READ_FOOTER \
670 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
671 return val
672
673#define __gen2_read(x) \
674static u##x \
675gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
676 GEN2_READ_HEADER(x); \
677 val = __raw_i915_read##x(dev_priv, reg); \
678 GEN2_READ_FOOTER; \
679}
680
681#define __gen5_read(x) \
682static u##x \
683gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
684 GEN2_READ_HEADER(x); \
685 ilk_dummy_write(dev_priv); \
686 val = __raw_i915_read##x(dev_priv, reg); \
687 GEN2_READ_FOOTER; \
688}
689
690__gen5_read(8)
691__gen5_read(16)
692__gen5_read(32)
693__gen5_read(64)
694__gen2_read(8)
695__gen2_read(16)
696__gen2_read(32)
697__gen2_read(64)
698
699#undef __gen5_read
700#undef __gen2_read
701
702#undef GEN2_READ_FOOTER
703#undef GEN2_READ_HEADER
704
705#define GEN6_READ_HEADER(x) \
706 u32 offset = i915_mmio_reg_offset(reg); \
707 unsigned long irqflags; \
708 u##x val = 0; \
709 assert_rpm_wakelock_held(dev_priv); \
710 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
711 unclaimed_reg_debug(dev_priv, reg, true, true)
712
713#define GEN6_READ_FOOTER \
714 unclaimed_reg_debug(dev_priv, reg, true, false); \
715 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
716 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
717 return val
718
719static inline void __force_wake_get(struct drm_i915_private *dev_priv,
720 enum forcewake_domains fw_domains)
721{
722 struct intel_uncore_forcewake_domain *domain;
723 enum forcewake_domain_id id;
724
725 if (WARN_ON(!fw_domains))
726 return;
727
728 /* Ideally GCC would be constant-fold and eliminate this loop */
729 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
730 if (domain->wake_count) {
731 fw_domains &= ~(1 << id);
732 continue;
733 }
734
735 domain->wake_count++;
736 fw_domain_arm_timer(domain);
737 }
738
739 if (fw_domains)
740 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
741}
742
743#define __gen6_read(x) \
744static u##x \
745gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
746 GEN6_READ_HEADER(x); \
747 if (NEEDS_FORCE_WAKE(offset)) \
748 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
749 val = __raw_i915_read##x(dev_priv, reg); \
750 GEN6_READ_FOOTER; \
751}
752
753#define __vlv_read(x) \
754static u##x \
755vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
756 enum forcewake_domains fw_engine = 0; \
757 GEN6_READ_HEADER(x); \
758 if (!NEEDS_FORCE_WAKE(offset)) \
759 fw_engine = 0; \
760 else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
761 fw_engine = FORCEWAKE_RENDER; \
762 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
763 fw_engine = FORCEWAKE_MEDIA; \
764 if (fw_engine) \
765 __force_wake_get(dev_priv, fw_engine); \
766 val = __raw_i915_read##x(dev_priv, reg); \
767 GEN6_READ_FOOTER; \
768}
769
770#define __chv_read(x) \
771static u##x \
772chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
773 enum forcewake_domains fw_engine = 0; \
774 GEN6_READ_HEADER(x); \
775 if (!NEEDS_FORCE_WAKE(offset)) \
776 fw_engine = 0; \
777 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
778 fw_engine = FORCEWAKE_RENDER; \
779 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
780 fw_engine = FORCEWAKE_MEDIA; \
781 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
782 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
783 if (fw_engine) \
784 __force_wake_get(dev_priv, fw_engine); \
785 val = __raw_i915_read##x(dev_priv, reg); \
786 GEN6_READ_FOOTER; \
787}
788
789#define SKL_NEEDS_FORCE_WAKE(reg) \
790 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
791
792#define __gen9_read(x) \
793static u##x \
794gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
795 enum forcewake_domains fw_engine; \
796 GEN6_READ_HEADER(x); \
797 if (!SKL_NEEDS_FORCE_WAKE(offset)) \
798 fw_engine = 0; \
799 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
800 fw_engine = FORCEWAKE_RENDER; \
801 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
802 fw_engine = FORCEWAKE_MEDIA; \
803 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
804 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
805 else \
806 fw_engine = FORCEWAKE_BLITTER; \
807 if (fw_engine) \
808 __force_wake_get(dev_priv, fw_engine); \
809 val = __raw_i915_read##x(dev_priv, reg); \
810 GEN6_READ_FOOTER; \
811}
812
813__gen9_read(8)
814__gen9_read(16)
815__gen9_read(32)
816__gen9_read(64)
817__chv_read(8)
818__chv_read(16)
819__chv_read(32)
820__chv_read(64)
821__vlv_read(8)
822__vlv_read(16)
823__vlv_read(32)
824__vlv_read(64)
825__gen6_read(8)
826__gen6_read(16)
827__gen6_read(32)
828__gen6_read(64)
829
830#undef __gen9_read
831#undef __chv_read
832#undef __vlv_read
833#undef __gen6_read
834#undef GEN6_READ_FOOTER
835#undef GEN6_READ_HEADER
836
837#define VGPU_READ_HEADER(x) \
838 unsigned long irqflags; \
839 u##x val = 0; \
840 assert_rpm_device_not_suspended(dev_priv); \
841 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
842
843#define VGPU_READ_FOOTER \
844 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
845 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
846 return val
847
848#define __vgpu_read(x) \
849static u##x \
850vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
851 VGPU_READ_HEADER(x); \
852 val = __raw_i915_read##x(dev_priv, reg); \
853 VGPU_READ_FOOTER; \
854}
855
856__vgpu_read(8)
857__vgpu_read(16)
858__vgpu_read(32)
859__vgpu_read(64)
860
861#undef __vgpu_read
862#undef VGPU_READ_FOOTER
863#undef VGPU_READ_HEADER
864
865#define GEN2_WRITE_HEADER \
866 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
867 assert_rpm_wakelock_held(dev_priv); \
868
869#define GEN2_WRITE_FOOTER
870
871#define __gen2_write(x) \
872static void \
873gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
874 GEN2_WRITE_HEADER; \
875 __raw_i915_write##x(dev_priv, reg, val); \
876 GEN2_WRITE_FOOTER; \
877}
878
879#define __gen5_write(x) \
880static void \
881gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
882 GEN2_WRITE_HEADER; \
883 ilk_dummy_write(dev_priv); \
884 __raw_i915_write##x(dev_priv, reg, val); \
885 GEN2_WRITE_FOOTER; \
886}
887
888__gen5_write(8)
889__gen5_write(16)
890__gen5_write(32)
891__gen5_write(64)
892__gen2_write(8)
893__gen2_write(16)
894__gen2_write(32)
895__gen2_write(64)
896
897#undef __gen5_write
898#undef __gen2_write
899
900#undef GEN2_WRITE_FOOTER
901#undef GEN2_WRITE_HEADER
902
903#define GEN6_WRITE_HEADER \
904 u32 offset = i915_mmio_reg_offset(reg); \
905 unsigned long irqflags; \
906 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
907 assert_rpm_wakelock_held(dev_priv); \
908 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
909 unclaimed_reg_debug(dev_priv, reg, false, true)
910
911#define GEN6_WRITE_FOOTER \
912 unclaimed_reg_debug(dev_priv, reg, false, false); \
913 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
914
915#define __gen6_write(x) \
916static void \
917gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
918 u32 __fifo_ret = 0; \
919 GEN6_WRITE_HEADER; \
920 if (NEEDS_FORCE_WAKE(offset)) { \
921 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
922 } \
923 __raw_i915_write##x(dev_priv, reg, val); \
924 if (unlikely(__fifo_ret)) { \
925 gen6_gt_check_fifodbg(dev_priv); \
926 } \
927 GEN6_WRITE_FOOTER; \
928}
929
930#define __hsw_write(x) \
931static void \
932hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
933 u32 __fifo_ret = 0; \
934 GEN6_WRITE_HEADER; \
935 if (NEEDS_FORCE_WAKE(offset)) { \
936 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
937 } \
938 __raw_i915_write##x(dev_priv, reg, val); \
939 if (unlikely(__fifo_ret)) { \
940 gen6_gt_check_fifodbg(dev_priv); \
941 } \
942 GEN6_WRITE_FOOTER; \
943}
944
945static const i915_reg_t gen8_shadowed_regs[] = {
946 FORCEWAKE_MT,
947 GEN6_RPNSWREQ,
948 GEN6_RC_VIDEO_FREQ,
949 RING_TAIL(RENDER_RING_BASE),
950 RING_TAIL(GEN6_BSD_RING_BASE),
951 RING_TAIL(VEBOX_RING_BASE),
952 RING_TAIL(BLT_RING_BASE),
953 /* TODO: Other registers are not yet used */
954};
955
956static bool is_gen8_shadowed(struct drm_i915_private *dev_priv,
957 i915_reg_t reg)
958{
959 int i;
960 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
961 if (i915_mmio_reg_equal(reg, gen8_shadowed_regs[i]))
962 return true;
963
964 return false;
965}
966
967#define __gen8_write(x) \
968static void \
969gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
970 GEN6_WRITE_HEADER; \
971 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \
972 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
973 __raw_i915_write##x(dev_priv, reg, val); \
974 GEN6_WRITE_FOOTER; \
975}
976
977#define __chv_write(x) \
978static void \
979chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
980 enum forcewake_domains fw_engine = 0; \
981 GEN6_WRITE_HEADER; \
982 if (!NEEDS_FORCE_WAKE(offset) || \
983 is_gen8_shadowed(dev_priv, reg)) \
984 fw_engine = 0; \
985 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
986 fw_engine = FORCEWAKE_RENDER; \
987 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
988 fw_engine = FORCEWAKE_MEDIA; \
989 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
990 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
991 if (fw_engine) \
992 __force_wake_get(dev_priv, fw_engine); \
993 __raw_i915_write##x(dev_priv, reg, val); \
994 GEN6_WRITE_FOOTER; \
995}
996
997static const i915_reg_t gen9_shadowed_regs[] = {
998 RING_TAIL(RENDER_RING_BASE),
999 RING_TAIL(GEN6_BSD_RING_BASE),
1000 RING_TAIL(VEBOX_RING_BASE),
1001 RING_TAIL(BLT_RING_BASE),
1002 FORCEWAKE_BLITTER_GEN9,
1003 FORCEWAKE_RENDER_GEN9,
1004 FORCEWAKE_MEDIA_GEN9,
1005 GEN6_RPNSWREQ,
1006 GEN6_RC_VIDEO_FREQ,
1007 /* TODO: Other registers are not yet used */
1008};
1009
1010static bool is_gen9_shadowed(struct drm_i915_private *dev_priv,
1011 i915_reg_t reg)
1012{
1013 int i;
1014 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
1015 if (i915_mmio_reg_equal(reg, gen9_shadowed_regs[i]))
1016 return true;
1017
1018 return false;
1019}
1020
1021#define __gen9_write(x) \
1022static void \
1023gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1024 bool trace) { \
1025 enum forcewake_domains fw_engine; \
1026 GEN6_WRITE_HEADER; \
1027 if (!SKL_NEEDS_FORCE_WAKE(offset) || \
1028 is_gen9_shadowed(dev_priv, reg)) \
1029 fw_engine = 0; \
1030 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
1031 fw_engine = FORCEWAKE_RENDER; \
1032 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
1033 fw_engine = FORCEWAKE_MEDIA; \
1034 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
1035 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
1036 else \
1037 fw_engine = FORCEWAKE_BLITTER; \
1038 if (fw_engine) \
1039 __force_wake_get(dev_priv, fw_engine); \
1040 __raw_i915_write##x(dev_priv, reg, val); \
1041 GEN6_WRITE_FOOTER; \
1042}
1043
1044__gen9_write(8)
1045__gen9_write(16)
1046__gen9_write(32)
1047__gen9_write(64)
1048__chv_write(8)
1049__chv_write(16)
1050__chv_write(32)
1051__chv_write(64)
1052__gen8_write(8)
1053__gen8_write(16)
1054__gen8_write(32)
1055__gen8_write(64)
1056__hsw_write(8)
1057__hsw_write(16)
1058__hsw_write(32)
1059__hsw_write(64)
1060__gen6_write(8)
1061__gen6_write(16)
1062__gen6_write(32)
1063__gen6_write(64)
1064
1065#undef __gen9_write
1066#undef __chv_write
1067#undef __gen8_write
1068#undef __hsw_write
1069#undef __gen6_write
1070#undef GEN6_WRITE_FOOTER
1071#undef GEN6_WRITE_HEADER
1072
1073#define VGPU_WRITE_HEADER \
1074 unsigned long irqflags; \
1075 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1076 assert_rpm_device_not_suspended(dev_priv); \
1077 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1078
1079#define VGPU_WRITE_FOOTER \
1080 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1081
1082#define __vgpu_write(x) \
1083static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1084 i915_reg_t reg, u##x val, bool trace) { \
1085 VGPU_WRITE_HEADER; \
1086 __raw_i915_write##x(dev_priv, reg, val); \
1087 VGPU_WRITE_FOOTER; \
1088}
1089
1090__vgpu_write(8)
1091__vgpu_write(16)
1092__vgpu_write(32)
1093__vgpu_write(64)
1094
1095#undef __vgpu_write
1096#undef VGPU_WRITE_FOOTER
1097#undef VGPU_WRITE_HEADER
1098
1099#define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1100do { \
1101 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1102 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1103 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1104 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1105} while (0)
1106
1107#define ASSIGN_READ_MMIO_VFUNCS(x) \
1108do { \
1109 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1110 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1111 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1112 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1113} while (0)
1114
1115
1116static void fw_domain_init(struct drm_i915_private *dev_priv,
1117 enum forcewake_domain_id domain_id,
1118 i915_reg_t reg_set,
1119 i915_reg_t reg_ack)
1120{
1121 struct intel_uncore_forcewake_domain *d;
1122
1123 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1124 return;
1125
1126 d = &dev_priv->uncore.fw_domain[domain_id];
1127
1128 WARN_ON(d->wake_count);
1129
1130 d->wake_count = 0;
1131 d->reg_set = reg_set;
1132 d->reg_ack = reg_ack;
1133
1134 if (IS_GEN6(dev_priv)) {
1135 d->val_reset = 0;
1136 d->val_set = FORCEWAKE_KERNEL;
1137 d->val_clear = 0;
1138 } else {
1139 /* WaRsClearFWBitsAtReset:bdw,skl */
1140 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1141 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1142 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1143 }
1144
1145 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1146 d->reg_post = FORCEWAKE_ACK_VLV;
1147 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1148 d->reg_post = ECOBUS;
1149
1150 d->i915 = dev_priv;
1151 d->id = domain_id;
1152
1153 setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1154
1155 dev_priv->uncore.fw_domains |= (1 << domain_id);
1156
1157 fw_domain_reset(d);
1158}
1159
1160static void intel_uncore_fw_domains_init(struct drm_device *dev)
1161{
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163
1164 if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1165 return;
1166
1167 if (IS_GEN9(dev)) {
1168 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1169 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1170 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1171 FORCEWAKE_RENDER_GEN9,
1172 FORCEWAKE_ACK_RENDER_GEN9);
1173 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1174 FORCEWAKE_BLITTER_GEN9,
1175 FORCEWAKE_ACK_BLITTER_GEN9);
1176 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1177 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1178 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1179 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1180 if (!IS_CHERRYVIEW(dev))
1181 dev_priv->uncore.funcs.force_wake_put =
1182 fw_domains_put_with_fifo;
1183 else
1184 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1185 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1186 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1187 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1188 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1189 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1190 dev_priv->uncore.funcs.force_wake_get =
1191 fw_domains_get_with_thread_status;
1192 if (IS_HASWELL(dev))
1193 dev_priv->uncore.funcs.force_wake_put =
1194 fw_domains_put_with_fifo;
1195 else
1196 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1197 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1198 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1199 } else if (IS_IVYBRIDGE(dev)) {
1200 u32 ecobus;
1201
1202 /* IVB configs may use multi-threaded forcewake */
1203
1204 /* A small trick here - if the bios hasn't configured
1205 * MT forcewake, and if the device is in RC6, then
1206 * force_wake_mt_get will not wake the device and the
1207 * ECOBUS read will return zero. Which will be
1208 * (correctly) interpreted by the test below as MT
1209 * forcewake being disabled.
1210 */
1211 dev_priv->uncore.funcs.force_wake_get =
1212 fw_domains_get_with_thread_status;
1213 dev_priv->uncore.funcs.force_wake_put =
1214 fw_domains_put_with_fifo;
1215
1216 /* We need to init first for ECOBUS access and then
1217 * determine later if we want to reinit, in case of MT access is
1218 * not working. In this stage we don't know which flavour this
1219 * ivb is, so it is better to reset also the gen6 fw registers
1220 * before the ecobus check.
1221 */
1222
1223 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1224 __raw_posting_read(dev_priv, ECOBUS);
1225
1226 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1227 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1228
1229 mutex_lock(&dev->struct_mutex);
1230 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1231 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1232 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1233 mutex_unlock(&dev->struct_mutex);
1234
1235 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1236 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1237 DRM_INFO("when using vblank-synced partial screen updates.\n");
1238 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1239 FORCEWAKE, FORCEWAKE_ACK);
1240 }
1241 } else if (IS_GEN6(dev)) {
1242 dev_priv->uncore.funcs.force_wake_get =
1243 fw_domains_get_with_thread_status;
1244 dev_priv->uncore.funcs.force_wake_put =
1245 fw_domains_put_with_fifo;
1246 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1247 FORCEWAKE, FORCEWAKE_ACK);
1248 }
1249
1250 /* All future platforms are expected to require complex power gating */
1251 WARN_ON(dev_priv->uncore.fw_domains == 0);
1252}
1253
1254void intel_uncore_init(struct drm_device *dev)
1255{
1256 struct drm_i915_private *dev_priv = dev->dev_private;
1257
1258 i915_check_vgpu(dev);
1259
1260 intel_uncore_ellc_detect(dev);
1261 intel_uncore_fw_domains_init(dev);
1262 __intel_uncore_early_sanitize(dev, false);
1263
1264 dev_priv->uncore.unclaimed_mmio_check = 1;
1265
1266 switch (INTEL_INFO(dev)->gen) {
1267 default:
1268 case 9:
1269 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1270 ASSIGN_READ_MMIO_VFUNCS(gen9);
1271 break;
1272 case 8:
1273 if (IS_CHERRYVIEW(dev)) {
1274 ASSIGN_WRITE_MMIO_VFUNCS(chv);
1275 ASSIGN_READ_MMIO_VFUNCS(chv);
1276
1277 } else {
1278 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1279 ASSIGN_READ_MMIO_VFUNCS(gen6);
1280 }
1281 break;
1282 case 7:
1283 case 6:
1284 if (IS_HASWELL(dev)) {
1285 ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1286 } else {
1287 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1288 }
1289
1290 if (IS_VALLEYVIEW(dev)) {
1291 ASSIGN_READ_MMIO_VFUNCS(vlv);
1292 } else {
1293 ASSIGN_READ_MMIO_VFUNCS(gen6);
1294 }
1295 break;
1296 case 5:
1297 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1298 ASSIGN_READ_MMIO_VFUNCS(gen5);
1299 break;
1300 case 4:
1301 case 3:
1302 case 2:
1303 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1304 ASSIGN_READ_MMIO_VFUNCS(gen2);
1305 break;
1306 }
1307
1308 if (intel_vgpu_active(dev)) {
1309 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1310 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1311 }
1312
1313 i915_check_and_clear_faults(dev);
1314}
1315#undef ASSIGN_WRITE_MMIO_VFUNCS
1316#undef ASSIGN_READ_MMIO_VFUNCS
1317
1318void intel_uncore_fini(struct drm_device *dev)
1319{
1320 /* Paranoia: make sure we have disabled everything before we exit. */
1321 intel_uncore_sanitize(dev);
1322 intel_uncore_forcewake_reset(dev, false);
1323}
1324
1325#define GEN_RANGE(l, h) GENMASK(h, l)
1326
1327static const struct register_whitelist {
1328 i915_reg_t offset_ldw, offset_udw;
1329 uint32_t size;
1330 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1331 uint32_t gen_bitmask;
1332} whitelist[] = {
1333 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1334 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1335 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1336};
1337
1338int i915_reg_read_ioctl(struct drm_device *dev,
1339 void *data, struct drm_file *file)
1340{
1341 struct drm_i915_private *dev_priv = dev->dev_private;
1342 struct drm_i915_reg_read *reg = data;
1343 struct register_whitelist const *entry = whitelist;
1344 unsigned size;
1345 i915_reg_t offset_ldw, offset_udw;
1346 int i, ret = 0;
1347
1348 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1349 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1350 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1351 break;
1352 }
1353
1354 if (i == ARRAY_SIZE(whitelist))
1355 return -EINVAL;
1356
1357 /* We use the low bits to encode extra flags as the register should
1358 * be naturally aligned (and those that are not so aligned merely
1359 * limit the available flags for that register).
1360 */
1361 offset_ldw = entry->offset_ldw;
1362 offset_udw = entry->offset_udw;
1363 size = entry->size;
1364 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1365
1366 intel_runtime_pm_get(dev_priv);
1367
1368 switch (size) {
1369 case 8 | 1:
1370 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1371 break;
1372 case 8:
1373 reg->val = I915_READ64(offset_ldw);
1374 break;
1375 case 4:
1376 reg->val = I915_READ(offset_ldw);
1377 break;
1378 case 2:
1379 reg->val = I915_READ16(offset_ldw);
1380 break;
1381 case 1:
1382 reg->val = I915_READ8(offset_ldw);
1383 break;
1384 default:
1385 ret = -EINVAL;
1386 goto out;
1387 }
1388
1389out:
1390 intel_runtime_pm_put(dev_priv);
1391 return ret;
1392}
1393
1394int i915_get_reset_stats_ioctl(struct drm_device *dev,
1395 void *data, struct drm_file *file)
1396{
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 struct drm_i915_reset_stats *args = data;
1399 struct i915_ctx_hang_stats *hs;
1400 struct intel_context *ctx;
1401 int ret;
1402
1403 if (args->flags || args->pad)
1404 return -EINVAL;
1405
1406 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1407 return -EPERM;
1408
1409 ret = mutex_lock_interruptible(&dev->struct_mutex);
1410 if (ret)
1411 return ret;
1412
1413 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1414 if (IS_ERR(ctx)) {
1415 mutex_unlock(&dev->struct_mutex);
1416 return PTR_ERR(ctx);
1417 }
1418 hs = &ctx->hang_stats;
1419
1420 if (capable(CAP_SYS_ADMIN))
1421 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1422 else
1423 args->reset_count = 0;
1424
1425 args->batch_active = hs->batch_active;
1426 args->batch_pending = hs->batch_pending;
1427
1428 mutex_unlock(&dev->struct_mutex);
1429
1430 return 0;
1431}
1432
1433static int i915_reset_complete(struct drm_device *dev)
1434{
1435 u8 gdrst;
1436 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1437 return (gdrst & GRDOM_RESET_STATUS) == 0;
1438}
1439
1440static int i915_do_reset(struct drm_device *dev)
1441{
1442 /* assert reset for at least 20 usec */
1443 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1444 udelay(20);
1445 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1446
1447 return wait_for(i915_reset_complete(dev), 500);
1448}
1449
1450static int g4x_reset_complete(struct drm_device *dev)
1451{
1452 u8 gdrst;
1453 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1454 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1455}
1456
1457static int g33_do_reset(struct drm_device *dev)
1458{
1459 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1460 return wait_for(g4x_reset_complete(dev), 500);
1461}
1462
1463static int g4x_do_reset(struct drm_device *dev)
1464{
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1466 int ret;
1467
1468 pci_write_config_byte(dev->pdev, I915_GDRST,
1469 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1470 ret = wait_for(g4x_reset_complete(dev), 500);
1471 if (ret)
1472 return ret;
1473
1474 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1475 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1476 POSTING_READ(VDECCLK_GATE_D);
1477
1478 pci_write_config_byte(dev->pdev, I915_GDRST,
1479 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1480 ret = wait_for(g4x_reset_complete(dev), 500);
1481 if (ret)
1482 return ret;
1483
1484 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1485 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1486 POSTING_READ(VDECCLK_GATE_D);
1487
1488 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1489
1490 return 0;
1491}
1492
1493static int ironlake_do_reset(struct drm_device *dev)
1494{
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 int ret;
1497
1498 I915_WRITE(ILK_GDSR,
1499 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1500 ret = wait_for((I915_READ(ILK_GDSR) &
1501 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1502 if (ret)
1503 return ret;
1504
1505 I915_WRITE(ILK_GDSR,
1506 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1507 ret = wait_for((I915_READ(ILK_GDSR) &
1508 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1509 if (ret)
1510 return ret;
1511
1512 I915_WRITE(ILK_GDSR, 0);
1513
1514 return 0;
1515}
1516
1517static int gen6_do_reset(struct drm_device *dev)
1518{
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520 int ret;
1521
1522 /* Reset the chip */
1523
1524 /* GEN6_GDRST is not in the gt power well, no need to check
1525 * for fifo space for the write or forcewake the chip for
1526 * the read
1527 */
1528 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1529
1530 /* Spin waiting for the device to ack the reset request */
1531 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1532
1533 intel_uncore_forcewake_reset(dev, true);
1534
1535 return ret;
1536}
1537
1538static int wait_for_register(struct drm_i915_private *dev_priv,
1539 i915_reg_t reg,
1540 const u32 mask,
1541 const u32 value,
1542 const unsigned long timeout_ms)
1543{
1544 return wait_for((I915_READ(reg) & mask) == value, timeout_ms);
1545}
1546
1547static int gen8_do_reset(struct drm_device *dev)
1548{
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 struct intel_engine_cs *engine;
1551 int i;
1552
1553 for_each_ring(engine, dev_priv, i) {
1554 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1555 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1556
1557 if (wait_for_register(dev_priv,
1558 RING_RESET_CTL(engine->mmio_base),
1559 RESET_CTL_READY_TO_RESET,
1560 RESET_CTL_READY_TO_RESET,
1561 700)) {
1562 DRM_ERROR("%s: reset request timeout\n", engine->name);
1563 goto not_ready;
1564 }
1565 }
1566
1567 return gen6_do_reset(dev);
1568
1569not_ready:
1570 for_each_ring(engine, dev_priv, i)
1571 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1572 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1573
1574 return -EIO;
1575}
1576
1577static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
1578{
1579 if (!i915.reset)
1580 return NULL;
1581
1582 if (INTEL_INFO(dev)->gen >= 8)
1583 return gen8_do_reset;
1584 else if (INTEL_INFO(dev)->gen >= 6)
1585 return gen6_do_reset;
1586 else if (IS_GEN5(dev))
1587 return ironlake_do_reset;
1588 else if (IS_G4X(dev))
1589 return g4x_do_reset;
1590 else if (IS_G33(dev))
1591 return g33_do_reset;
1592 else if (INTEL_INFO(dev)->gen >= 3)
1593 return i915_do_reset;
1594 else
1595 return NULL;
1596}
1597
1598int intel_gpu_reset(struct drm_device *dev)
1599{
1600 struct drm_i915_private *dev_priv = to_i915(dev);
1601 int (*reset)(struct drm_device *);
1602 int ret;
1603
1604 reset = intel_get_gpu_reset(dev);
1605 if (reset == NULL)
1606 return -ENODEV;
1607
1608 /* If the power well sleeps during the reset, the reset
1609 * request may be dropped and never completes (causing -EIO).
1610 */
1611 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1612 ret = reset(dev);
1613 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1614
1615 return ret;
1616}
1617
1618bool intel_has_gpu_reset(struct drm_device *dev)
1619{
1620 return intel_get_gpu_reset(dev) != NULL;
1621}
1622
1623bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1624{
1625 return check_for_unclaimed_mmio(dev_priv);
1626}
1627
1628bool
1629intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1630{
1631 if (unlikely(i915.mmio_debug ||
1632 dev_priv->uncore.unclaimed_mmio_check <= 0))
1633 return false;
1634
1635 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1636 DRM_DEBUG("Unclaimed register detected, "
1637 "enabling oneshot unclaimed register reporting. "
1638 "Please use i915.mmio_debug=N for more information.\n");
1639 i915.mmio_debug++;
1640 dev_priv->uncore.unclaimed_mmio_check--;
1641 return true;
1642 }
1643
1644 return false;
1645}
1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "i915_drv.h"
25#include "intel_drv.h"
26#include "i915_vgpu.h"
27
28#include <linux/pm_runtime.h>
29
30#define FORCEWAKE_ACK_TIMEOUT_MS 50
31
32#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
33
34static const char * const forcewake_domain_names[] = {
35 "render",
36 "blitter",
37 "media",
38};
39
40const char *
41intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
42{
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
44
45 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
46 return forcewake_domain_names[id];
47
48 WARN_ON(id);
49
50 return "unknown";
51}
52
53static inline void
54fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
55{
56 WARN_ON(!i915_mmio_reg_valid(d->reg_set));
57 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
58}
59
60static inline void
61fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
62{
63 d->wake_count++;
64 hrtimer_start_range_ns(&d->timer,
65 NSEC_PER_MSEC,
66 NSEC_PER_MSEC,
67 HRTIMER_MODE_REL);
68}
69
70static inline void
71fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
72{
73 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
74 FORCEWAKE_KERNEL) == 0,
75 FORCEWAKE_ACK_TIMEOUT_MS))
76 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
77 intel_uncore_forcewake_domain_to_str(d->id));
78}
79
80static inline void
81fw_domain_get(const struct intel_uncore_forcewake_domain *d)
82{
83 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
84}
85
86static inline void
87fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
88{
89 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
90 FORCEWAKE_KERNEL),
91 FORCEWAKE_ACK_TIMEOUT_MS))
92 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
93 intel_uncore_forcewake_domain_to_str(d->id));
94}
95
96static inline void
97fw_domain_put(const struct intel_uncore_forcewake_domain *d)
98{
99 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
100}
101
102static inline void
103fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
104{
105 /* something from same cacheline, but not from the set register */
106 if (i915_mmio_reg_valid(d->reg_post))
107 __raw_posting_read(d->i915, d->reg_post);
108}
109
110static void
111fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
112{
113 struct intel_uncore_forcewake_domain *d;
114
115 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
116 fw_domain_wait_ack_clear(d);
117 fw_domain_get(d);
118 }
119
120 for_each_fw_domain_masked(d, fw_domains, dev_priv)
121 fw_domain_wait_ack(d);
122
123 dev_priv->uncore.fw_domains_active |= fw_domains;
124}
125
126static void
127fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
128{
129 struct intel_uncore_forcewake_domain *d;
130
131 for_each_fw_domain_masked(d, fw_domains, dev_priv) {
132 fw_domain_put(d);
133 fw_domain_posting_read(d);
134 }
135
136 dev_priv->uncore.fw_domains_active &= ~fw_domains;
137}
138
139static void
140fw_domains_posting_read(struct drm_i915_private *dev_priv)
141{
142 struct intel_uncore_forcewake_domain *d;
143
144 /* No need to do for all, just do for first found */
145 for_each_fw_domain(d, dev_priv) {
146 fw_domain_posting_read(d);
147 break;
148 }
149}
150
151static void
152fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
153{
154 struct intel_uncore_forcewake_domain *d;
155
156 if (dev_priv->uncore.fw_domains == 0)
157 return;
158
159 for_each_fw_domain_masked(d, fw_domains, dev_priv)
160 fw_domain_reset(d);
161
162 fw_domains_posting_read(dev_priv);
163}
164
165static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
166{
167 /* w/a for a sporadic read returning 0 by waiting for the GT
168 * thread to wake up.
169 */
170 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
171 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
172 DRM_ERROR("GT thread status wait timed out\n");
173}
174
175static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
176 enum forcewake_domains fw_domains)
177{
178 fw_domains_get(dev_priv, fw_domains);
179
180 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
181 __gen6_gt_wait_for_thread_c0(dev_priv);
182}
183
184static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
185{
186 u32 gtfifodbg;
187
188 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
189 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
190 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
191}
192
193static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
194 enum forcewake_domains fw_domains)
195{
196 fw_domains_put(dev_priv, fw_domains);
197 gen6_gt_check_fifodbg(dev_priv);
198}
199
200static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
201{
202 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
203
204 return count & GT_FIFO_FREE_ENTRIES_MASK;
205}
206
207static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
208{
209 int ret = 0;
210
211 /* On VLV, FIFO will be shared by both SW and HW.
212 * So, we need to read the FREE_ENTRIES everytime */
213 if (IS_VALLEYVIEW(dev_priv))
214 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
215
216 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
217 int loop = 500;
218 u32 fifo = fifo_free_entries(dev_priv);
219
220 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
221 udelay(10);
222 fifo = fifo_free_entries(dev_priv);
223 }
224 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
225 ++ret;
226 dev_priv->uncore.fifo_count = fifo;
227 }
228 dev_priv->uncore.fifo_count--;
229
230 return ret;
231}
232
233static enum hrtimer_restart
234intel_uncore_fw_release_timer(struct hrtimer *timer)
235{
236 struct intel_uncore_forcewake_domain *domain =
237 container_of(timer, struct intel_uncore_forcewake_domain, timer);
238 struct drm_i915_private *dev_priv = domain->i915;
239 unsigned long irqflags;
240
241 assert_rpm_device_not_suspended(dev_priv);
242
243 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
244 if (WARN_ON(domain->wake_count == 0))
245 domain->wake_count++;
246
247 if (--domain->wake_count == 0)
248 dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
249
250 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
251
252 return HRTIMER_NORESTART;
253}
254
255void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
256 bool restore)
257{
258 unsigned long irqflags;
259 struct intel_uncore_forcewake_domain *domain;
260 int retry_count = 100;
261 enum forcewake_domains fw, active_domains;
262
263 /* Hold uncore.lock across reset to prevent any register access
264 * with forcewake not set correctly. Wait until all pending
265 * timers are run before holding.
266 */
267 while (1) {
268 active_domains = 0;
269
270 for_each_fw_domain(domain, dev_priv) {
271 if (hrtimer_cancel(&domain->timer) == 0)
272 continue;
273
274 intel_uncore_fw_release_timer(&domain->timer);
275 }
276
277 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
278
279 for_each_fw_domain(domain, dev_priv) {
280 if (hrtimer_active(&domain->timer))
281 active_domains |= domain->mask;
282 }
283
284 if (active_domains == 0)
285 break;
286
287 if (--retry_count == 0) {
288 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
289 break;
290 }
291
292 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
293 cond_resched();
294 }
295
296 WARN_ON(active_domains);
297
298 fw = dev_priv->uncore.fw_domains_active;
299 if (fw)
300 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
301
302 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
303
304 if (restore) { /* If reset with a user forcewake, try to restore */
305 if (fw)
306 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
307
308 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
309 dev_priv->uncore.fifo_count =
310 fifo_free_entries(dev_priv);
311 }
312
313 if (!restore)
314 assert_forcewakes_inactive(dev_priv);
315
316 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
317}
318
319static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
320{
321 const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
322 const unsigned int sets[4] = { 1, 1, 2, 2 };
323 const u32 cap = dev_priv->edram_cap;
324
325 return EDRAM_NUM_BANKS(cap) *
326 ways[EDRAM_WAYS_IDX(cap)] *
327 sets[EDRAM_SETS_IDX(cap)] *
328 1024 * 1024;
329}
330
331u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
332{
333 if (!HAS_EDRAM(dev_priv))
334 return 0;
335
336 /* The needed capability bits for size calculation
337 * are not there with pre gen9 so return 128MB always.
338 */
339 if (INTEL_GEN(dev_priv) < 9)
340 return 128 * 1024 * 1024;
341
342 return gen9_edram_size(dev_priv);
343}
344
345static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
346{
347 if (IS_HASWELL(dev_priv) ||
348 IS_BROADWELL(dev_priv) ||
349 INTEL_GEN(dev_priv) >= 9) {
350 dev_priv->edram_cap = __raw_i915_read32(dev_priv,
351 HSW_EDRAM_CAP);
352
353 /* NB: We can't write IDICR yet because we do not have gt funcs
354 * set up */
355 } else {
356 dev_priv->edram_cap = 0;
357 }
358
359 if (HAS_EDRAM(dev_priv))
360 DRM_INFO("Found %lluMB of eDRAM\n",
361 intel_uncore_edram_size(dev_priv) / (1024 * 1024));
362}
363
364static bool
365fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
366{
367 u32 dbg;
368
369 dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
370 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
371 return false;
372
373 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
374
375 return true;
376}
377
378static bool
379vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
380{
381 u32 cer;
382
383 cer = __raw_i915_read32(dev_priv, CLAIM_ER);
384 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
385 return false;
386
387 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
388
389 return true;
390}
391
392static bool
393check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
394{
395 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
396 return fpga_check_for_unclaimed_mmio(dev_priv);
397
398 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
399 return vlv_check_for_unclaimed_mmio(dev_priv);
400
401 return false;
402}
403
404static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
405 bool restore_forcewake)
406{
407 struct intel_device_info *info = mkwrite_device_info(dev_priv);
408
409 /* clear out unclaimed reg detection bit */
410 if (check_for_unclaimed_mmio(dev_priv))
411 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
412
413 /* clear out old GT FIFO errors */
414 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
415 __raw_i915_write32(dev_priv, GTFIFODBG,
416 __raw_i915_read32(dev_priv, GTFIFODBG));
417
418 /* WaDisableShadowRegForCpd:chv */
419 if (IS_CHERRYVIEW(dev_priv)) {
420 __raw_i915_write32(dev_priv, GTFIFOCTL,
421 __raw_i915_read32(dev_priv, GTFIFOCTL) |
422 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
423 GT_FIFO_CTL_RC6_POLICY_STALL);
424 }
425
426 /* Enable Decoupled MMIO only on BXT C stepping onwards */
427 if (!IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
428 info->has_decoupled_mmio = false;
429
430 intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
431}
432
433void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
434 bool restore_forcewake)
435{
436 __intel_uncore_early_sanitize(dev_priv, restore_forcewake);
437 i915_check_and_clear_faults(dev_priv);
438}
439
440void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
441{
442 i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
443
444 /* BIOS often leaves RC6 enabled, but disable it for hw init */
445 intel_sanitize_gt_powersave(dev_priv);
446}
447
448static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
449 enum forcewake_domains fw_domains)
450{
451 struct intel_uncore_forcewake_domain *domain;
452
453 fw_domains &= dev_priv->uncore.fw_domains;
454
455 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
456 if (domain->wake_count++)
457 fw_domains &= ~domain->mask;
458 }
459
460 if (fw_domains)
461 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
462}
463
464/**
465 * intel_uncore_forcewake_get - grab forcewake domain references
466 * @dev_priv: i915 device instance
467 * @fw_domains: forcewake domains to get reference on
468 *
469 * This function can be used get GT's forcewake domain references.
470 * Normal register access will handle the forcewake domains automatically.
471 * However if some sequence requires the GT to not power down a particular
472 * forcewake domains this function should be called at the beginning of the
473 * sequence. And subsequently the reference should be dropped by symmetric
474 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
475 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
476 */
477void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
478 enum forcewake_domains fw_domains)
479{
480 unsigned long irqflags;
481
482 if (!dev_priv->uncore.funcs.force_wake_get)
483 return;
484
485 assert_rpm_wakelock_held(dev_priv);
486
487 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
488 __intel_uncore_forcewake_get(dev_priv, fw_domains);
489 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
490}
491
492/**
493 * intel_uncore_forcewake_get__locked - grab forcewake domain references
494 * @dev_priv: i915 device instance
495 * @fw_domains: forcewake domains to get reference on
496 *
497 * See intel_uncore_forcewake_get(). This variant places the onus
498 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
499 */
500void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
501 enum forcewake_domains fw_domains)
502{
503 assert_spin_locked(&dev_priv->uncore.lock);
504
505 if (!dev_priv->uncore.funcs.force_wake_get)
506 return;
507
508 __intel_uncore_forcewake_get(dev_priv, fw_domains);
509}
510
511static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
512 enum forcewake_domains fw_domains)
513{
514 struct intel_uncore_forcewake_domain *domain;
515
516 fw_domains &= dev_priv->uncore.fw_domains;
517
518 for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
519 if (WARN_ON(domain->wake_count == 0))
520 continue;
521
522 if (--domain->wake_count)
523 continue;
524
525 fw_domain_arm_timer(domain);
526 }
527}
528
529/**
530 * intel_uncore_forcewake_put - release a forcewake domain reference
531 * @dev_priv: i915 device instance
532 * @fw_domains: forcewake domains to put references
533 *
534 * This function drops the device-level forcewakes for specified
535 * domains obtained by intel_uncore_forcewake_get().
536 */
537void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
538 enum forcewake_domains fw_domains)
539{
540 unsigned long irqflags;
541
542 if (!dev_priv->uncore.funcs.force_wake_put)
543 return;
544
545 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
546 __intel_uncore_forcewake_put(dev_priv, fw_domains);
547 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
548}
549
550/**
551 * intel_uncore_forcewake_put__locked - grab forcewake domain references
552 * @dev_priv: i915 device instance
553 * @fw_domains: forcewake domains to get reference on
554 *
555 * See intel_uncore_forcewake_put(). This variant places the onus
556 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
557 */
558void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
559 enum forcewake_domains fw_domains)
560{
561 assert_spin_locked(&dev_priv->uncore.lock);
562
563 if (!dev_priv->uncore.funcs.force_wake_put)
564 return;
565
566 __intel_uncore_forcewake_put(dev_priv, fw_domains);
567}
568
569void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
570{
571 if (!dev_priv->uncore.funcs.force_wake_get)
572 return;
573
574 WARN_ON(dev_priv->uncore.fw_domains_active);
575}
576
577/* We give fast paths for the really cool registers */
578#define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
579
580#define __gen6_reg_read_fw_domains(offset) \
581({ \
582 enum forcewake_domains __fwd; \
583 if (NEEDS_FORCE_WAKE(offset)) \
584 __fwd = FORCEWAKE_RENDER; \
585 else \
586 __fwd = 0; \
587 __fwd; \
588})
589
590static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
591{
592 if (offset < entry->start)
593 return -1;
594 else if (offset > entry->end)
595 return 1;
596 else
597 return 0;
598}
599
600/* Copied and "macroized" from lib/bsearch.c */
601#define BSEARCH(key, base, num, cmp) ({ \
602 unsigned int start__ = 0, end__ = (num); \
603 typeof(base) result__ = NULL; \
604 while (start__ < end__) { \
605 unsigned int mid__ = start__ + (end__ - start__) / 2; \
606 int ret__ = (cmp)((key), (base) + mid__); \
607 if (ret__ < 0) { \
608 end__ = mid__; \
609 } else if (ret__ > 0) { \
610 start__ = mid__ + 1; \
611 } else { \
612 result__ = (base) + mid__; \
613 break; \
614 } \
615 } \
616 result__; \
617})
618
619static enum forcewake_domains
620find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
621{
622 const struct intel_forcewake_range *entry;
623
624 entry = BSEARCH(offset,
625 dev_priv->uncore.fw_domains_table,
626 dev_priv->uncore.fw_domains_table_entries,
627 fw_range_cmp);
628
629 return entry ? entry->domains : 0;
630}
631
632static void
633intel_fw_table_check(struct drm_i915_private *dev_priv)
634{
635 const struct intel_forcewake_range *ranges;
636 unsigned int num_ranges;
637 s32 prev;
638 unsigned int i;
639
640 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
641 return;
642
643 ranges = dev_priv->uncore.fw_domains_table;
644 if (!ranges)
645 return;
646
647 num_ranges = dev_priv->uncore.fw_domains_table_entries;
648
649 for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
650 WARN_ON_ONCE(IS_GEN9(dev_priv) &&
651 (prev + 1) != (s32)ranges->start);
652 WARN_ON_ONCE(prev >= (s32)ranges->start);
653 prev = ranges->start;
654 WARN_ON_ONCE(prev >= (s32)ranges->end);
655 prev = ranges->end;
656 }
657}
658
659#define GEN_FW_RANGE(s, e, d) \
660 { .start = (s), .end = (e), .domains = (d) }
661
662#define HAS_FWTABLE(dev_priv) \
663 (IS_GEN9(dev_priv) || \
664 IS_CHERRYVIEW(dev_priv) || \
665 IS_VALLEYVIEW(dev_priv))
666
667/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
668static const struct intel_forcewake_range __vlv_fw_ranges[] = {
669 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
670 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
671 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
672 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
673 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
674 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
675 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
676};
677
678#define __fwtable_reg_read_fw_domains(offset) \
679({ \
680 enum forcewake_domains __fwd = 0; \
681 if (NEEDS_FORCE_WAKE((offset))) \
682 __fwd = find_fw_domain(dev_priv, offset); \
683 __fwd; \
684})
685
686/* *Must* be sorted by offset! See intel_shadow_table_check(). */
687static const i915_reg_t gen8_shadowed_regs[] = {
688 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
689 GEN6_RPNSWREQ, /* 0xA008 */
690 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
691 RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
692 RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
693 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
694 /* TODO: Other registers are not yet used */
695};
696
697static void intel_shadow_table_check(void)
698{
699 const i915_reg_t *reg = gen8_shadowed_regs;
700 s32 prev;
701 u32 offset;
702 unsigned int i;
703
704 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
705 return;
706
707 for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) {
708 offset = i915_mmio_reg_offset(*reg);
709 WARN_ON_ONCE(prev >= (s32)offset);
710 prev = offset;
711 }
712}
713
714static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
715{
716 u32 offset = i915_mmio_reg_offset(*reg);
717
718 if (key < offset)
719 return -1;
720 else if (key > offset)
721 return 1;
722 else
723 return 0;
724}
725
726static bool is_gen8_shadowed(u32 offset)
727{
728 const i915_reg_t *regs = gen8_shadowed_regs;
729
730 return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs),
731 mmio_reg_cmp);
732}
733
734#define __gen8_reg_write_fw_domains(offset) \
735({ \
736 enum forcewake_domains __fwd; \
737 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
738 __fwd = FORCEWAKE_RENDER; \
739 else \
740 __fwd = 0; \
741 __fwd; \
742})
743
744/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
745static const struct intel_forcewake_range __chv_fw_ranges[] = {
746 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
747 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
748 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
749 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
750 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
751 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
752 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
753 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
754 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
755 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
756 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
757 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
758 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
759 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
760 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
761 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
762};
763
764#define __fwtable_reg_write_fw_domains(offset) \
765({ \
766 enum forcewake_domains __fwd = 0; \
767 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
768 __fwd = find_fw_domain(dev_priv, offset); \
769 __fwd; \
770})
771
772/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
773static const struct intel_forcewake_range __gen9_fw_ranges[] = {
774 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
775 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
776 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
777 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
778 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
779 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
780 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
781 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
782 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
783 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
784 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
785 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
786 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
787 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
788 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
789 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
790 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
791 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
792 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
793 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
794 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
795 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
796 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
797 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
798 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
799 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
800 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
801 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
802 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
803 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
804 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
805 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
806};
807
808static void
809ilk_dummy_write(struct drm_i915_private *dev_priv)
810{
811 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
812 * the chip from rc6 before touching it for real. MI_MODE is masked,
813 * hence harmless to write 0 into. */
814 __raw_i915_write32(dev_priv, MI_MODE, 0);
815}
816
817static void
818__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
819 const i915_reg_t reg,
820 const bool read,
821 const bool before)
822{
823 if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
824 "Unclaimed %s register 0x%x\n",
825 read ? "read from" : "write to",
826 i915_mmio_reg_offset(reg)))
827 i915.mmio_debug--; /* Only report the first N failures */
828}
829
830static inline void
831unclaimed_reg_debug(struct drm_i915_private *dev_priv,
832 const i915_reg_t reg,
833 const bool read,
834 const bool before)
835{
836 if (likely(!i915.mmio_debug))
837 return;
838
839 __unclaimed_reg_debug(dev_priv, reg, read, before);
840}
841
842static const enum decoupled_power_domain fw2dpd_domain[] = {
843 GEN9_DECOUPLED_PD_RENDER,
844 GEN9_DECOUPLED_PD_BLITTER,
845 GEN9_DECOUPLED_PD_ALL,
846 GEN9_DECOUPLED_PD_MEDIA,
847 GEN9_DECOUPLED_PD_ALL,
848 GEN9_DECOUPLED_PD_ALL,
849 GEN9_DECOUPLED_PD_ALL
850};
851
852/*
853 * Decoupled MMIO access for only 1 DWORD
854 */
855static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,
856 u32 reg,
857 enum forcewake_domains fw_domain,
858 enum decoupled_ops operation)
859{
860 enum decoupled_power_domain dp_domain;
861 u32 ctrl_reg_data = 0;
862
863 dp_domain = fw2dpd_domain[fw_domain - 1];
864
865 ctrl_reg_data |= reg;
866 ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT);
867 ctrl_reg_data |= (dp_domain << GEN9_DECOUPLED_PD_SHIFT);
868 ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO;
869 __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data);
870
871 if (wait_for_atomic((__raw_i915_read32(dev_priv,
872 GEN9_DECOUPLED_REG0_DW1) &
873 GEN9_DECOUPLED_DW1_GO) == 0,
874 FORCEWAKE_ACK_TIMEOUT_MS))
875 DRM_ERROR("Decoupled MMIO wait timed out\n");
876}
877
878static inline u32
879__gen9_decoupled_mmio_read32(struct drm_i915_private *dev_priv,
880 u32 reg,
881 enum forcewake_domains fw_domain)
882{
883 __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
884 GEN9_DECOUPLED_OP_READ);
885
886 return __raw_i915_read32(dev_priv, GEN9_DECOUPLED_REG0_DW0);
887}
888
889static inline void
890__gen9_decoupled_mmio_write(struct drm_i915_private *dev_priv,
891 u32 reg, u32 data,
892 enum forcewake_domains fw_domain)
893{
894
895 __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW0, data);
896
897 __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain,
898 GEN9_DECOUPLED_OP_WRITE);
899}
900
901
902#define GEN2_READ_HEADER(x) \
903 u##x val = 0; \
904 assert_rpm_wakelock_held(dev_priv);
905
906#define GEN2_READ_FOOTER \
907 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
908 return val
909
910#define __gen2_read(x) \
911static u##x \
912gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
913 GEN2_READ_HEADER(x); \
914 val = __raw_i915_read##x(dev_priv, reg); \
915 GEN2_READ_FOOTER; \
916}
917
918#define __gen5_read(x) \
919static u##x \
920gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
921 GEN2_READ_HEADER(x); \
922 ilk_dummy_write(dev_priv); \
923 val = __raw_i915_read##x(dev_priv, reg); \
924 GEN2_READ_FOOTER; \
925}
926
927__gen5_read(8)
928__gen5_read(16)
929__gen5_read(32)
930__gen5_read(64)
931__gen2_read(8)
932__gen2_read(16)
933__gen2_read(32)
934__gen2_read(64)
935
936#undef __gen5_read
937#undef __gen2_read
938
939#undef GEN2_READ_FOOTER
940#undef GEN2_READ_HEADER
941
942#define GEN6_READ_HEADER(x) \
943 u32 offset = i915_mmio_reg_offset(reg); \
944 unsigned long irqflags; \
945 u##x val = 0; \
946 assert_rpm_wakelock_held(dev_priv); \
947 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
948 unclaimed_reg_debug(dev_priv, reg, true, true)
949
950#define GEN6_READ_FOOTER \
951 unclaimed_reg_debug(dev_priv, reg, true, false); \
952 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
953 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
954 return val
955
956static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
957 enum forcewake_domains fw_domains)
958{
959 struct intel_uncore_forcewake_domain *domain;
960
961 for_each_fw_domain_masked(domain, fw_domains, dev_priv)
962 fw_domain_arm_timer(domain);
963
964 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
965}
966
967static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
968 enum forcewake_domains fw_domains)
969{
970 if (WARN_ON(!fw_domains))
971 return;
972
973 /* Turn on all requested but inactive supported forcewake domains. */
974 fw_domains &= dev_priv->uncore.fw_domains;
975 fw_domains &= ~dev_priv->uncore.fw_domains_active;
976
977 if (fw_domains)
978 ___force_wake_auto(dev_priv, fw_domains);
979}
980
981#define __gen6_read(x) \
982static u##x \
983gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
984 enum forcewake_domains fw_engine; \
985 GEN6_READ_HEADER(x); \
986 fw_engine = __gen6_reg_read_fw_domains(offset); \
987 if (fw_engine) \
988 __force_wake_auto(dev_priv, fw_engine); \
989 val = __raw_i915_read##x(dev_priv, reg); \
990 GEN6_READ_FOOTER; \
991}
992
993#define __fwtable_read(x) \
994static u##x \
995fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
996 enum forcewake_domains fw_engine; \
997 GEN6_READ_HEADER(x); \
998 fw_engine = __fwtable_reg_read_fw_domains(offset); \
999 if (fw_engine) \
1000 __force_wake_auto(dev_priv, fw_engine); \
1001 val = __raw_i915_read##x(dev_priv, reg); \
1002 GEN6_READ_FOOTER; \
1003}
1004
1005#define __gen9_decoupled_read(x) \
1006static u##x \
1007gen9_decoupled_read##x(struct drm_i915_private *dev_priv, \
1008 i915_reg_t reg, bool trace) { \
1009 enum forcewake_domains fw_engine; \
1010 GEN6_READ_HEADER(x); \
1011 fw_engine = __fwtable_reg_read_fw_domains(offset); \
1012 if (fw_engine & ~dev_priv->uncore.fw_domains_active) { \
1013 unsigned i; \
1014 u32 *ptr_data = (u32 *) &val; \
1015 for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \
1016 *ptr_data = __gen9_decoupled_mmio_read32(dev_priv, \
1017 offset, \
1018 fw_engine); \
1019 } else { \
1020 val = __raw_i915_read##x(dev_priv, reg); \
1021 } \
1022 GEN6_READ_FOOTER; \
1023}
1024
1025__gen9_decoupled_read(32)
1026__gen9_decoupled_read(64)
1027__fwtable_read(8)
1028__fwtable_read(16)
1029__fwtable_read(32)
1030__fwtable_read(64)
1031__gen6_read(8)
1032__gen6_read(16)
1033__gen6_read(32)
1034__gen6_read(64)
1035
1036#undef __fwtable_read
1037#undef __gen6_read
1038#undef GEN6_READ_FOOTER
1039#undef GEN6_READ_HEADER
1040
1041#define VGPU_READ_HEADER(x) \
1042 unsigned long irqflags; \
1043 u##x val = 0; \
1044 assert_rpm_device_not_suspended(dev_priv); \
1045 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1046
1047#define VGPU_READ_FOOTER \
1048 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
1049 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1050 return val
1051
1052#define __vgpu_read(x) \
1053static u##x \
1054vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1055 VGPU_READ_HEADER(x); \
1056 val = __raw_i915_read##x(dev_priv, reg); \
1057 VGPU_READ_FOOTER; \
1058}
1059
1060__vgpu_read(8)
1061__vgpu_read(16)
1062__vgpu_read(32)
1063__vgpu_read(64)
1064
1065#undef __vgpu_read
1066#undef VGPU_READ_FOOTER
1067#undef VGPU_READ_HEADER
1068
1069#define GEN2_WRITE_HEADER \
1070 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1071 assert_rpm_wakelock_held(dev_priv); \
1072
1073#define GEN2_WRITE_FOOTER
1074
1075#define __gen2_write(x) \
1076static void \
1077gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1078 GEN2_WRITE_HEADER; \
1079 __raw_i915_write##x(dev_priv, reg, val); \
1080 GEN2_WRITE_FOOTER; \
1081}
1082
1083#define __gen5_write(x) \
1084static void \
1085gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1086 GEN2_WRITE_HEADER; \
1087 ilk_dummy_write(dev_priv); \
1088 __raw_i915_write##x(dev_priv, reg, val); \
1089 GEN2_WRITE_FOOTER; \
1090}
1091
1092__gen5_write(8)
1093__gen5_write(16)
1094__gen5_write(32)
1095__gen2_write(8)
1096__gen2_write(16)
1097__gen2_write(32)
1098
1099#undef __gen5_write
1100#undef __gen2_write
1101
1102#undef GEN2_WRITE_FOOTER
1103#undef GEN2_WRITE_HEADER
1104
1105#define GEN6_WRITE_HEADER \
1106 u32 offset = i915_mmio_reg_offset(reg); \
1107 unsigned long irqflags; \
1108 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1109 assert_rpm_wakelock_held(dev_priv); \
1110 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1111 unclaimed_reg_debug(dev_priv, reg, false, true)
1112
1113#define GEN6_WRITE_FOOTER \
1114 unclaimed_reg_debug(dev_priv, reg, false, false); \
1115 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1116
1117#define __gen6_write(x) \
1118static void \
1119gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1120 u32 __fifo_ret = 0; \
1121 GEN6_WRITE_HEADER; \
1122 if (NEEDS_FORCE_WAKE(offset)) { \
1123 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1124 } \
1125 __raw_i915_write##x(dev_priv, reg, val); \
1126 if (unlikely(__fifo_ret)) { \
1127 gen6_gt_check_fifodbg(dev_priv); \
1128 } \
1129 GEN6_WRITE_FOOTER; \
1130}
1131
1132#define __gen8_write(x) \
1133static void \
1134gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1135 enum forcewake_domains fw_engine; \
1136 GEN6_WRITE_HEADER; \
1137 fw_engine = __gen8_reg_write_fw_domains(offset); \
1138 if (fw_engine) \
1139 __force_wake_auto(dev_priv, fw_engine); \
1140 __raw_i915_write##x(dev_priv, reg, val); \
1141 GEN6_WRITE_FOOTER; \
1142}
1143
1144#define __fwtable_write(x) \
1145static void \
1146fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1147 enum forcewake_domains fw_engine; \
1148 GEN6_WRITE_HEADER; \
1149 fw_engine = __fwtable_reg_write_fw_domains(offset); \
1150 if (fw_engine) \
1151 __force_wake_auto(dev_priv, fw_engine); \
1152 __raw_i915_write##x(dev_priv, reg, val); \
1153 GEN6_WRITE_FOOTER; \
1154}
1155
1156#define __gen9_decoupled_write(x) \
1157static void \
1158gen9_decoupled_write##x(struct drm_i915_private *dev_priv, \
1159 i915_reg_t reg, u##x val, \
1160 bool trace) { \
1161 enum forcewake_domains fw_engine; \
1162 GEN6_WRITE_HEADER; \
1163 fw_engine = __fwtable_reg_write_fw_domains(offset); \
1164 if (fw_engine & ~dev_priv->uncore.fw_domains_active) \
1165 __gen9_decoupled_mmio_write(dev_priv, \
1166 offset, \
1167 val, \
1168 fw_engine); \
1169 else \
1170 __raw_i915_write##x(dev_priv, reg, val); \
1171 GEN6_WRITE_FOOTER; \
1172}
1173
1174__gen9_decoupled_write(32)
1175__fwtable_write(8)
1176__fwtable_write(16)
1177__fwtable_write(32)
1178__gen8_write(8)
1179__gen8_write(16)
1180__gen8_write(32)
1181__gen6_write(8)
1182__gen6_write(16)
1183__gen6_write(32)
1184
1185#undef __fwtable_write
1186#undef __gen8_write
1187#undef __gen6_write
1188#undef GEN6_WRITE_FOOTER
1189#undef GEN6_WRITE_HEADER
1190
1191#define VGPU_WRITE_HEADER \
1192 unsigned long irqflags; \
1193 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1194 assert_rpm_device_not_suspended(dev_priv); \
1195 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1196
1197#define VGPU_WRITE_FOOTER \
1198 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1199
1200#define __vgpu_write(x) \
1201static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1202 i915_reg_t reg, u##x val, bool trace) { \
1203 VGPU_WRITE_HEADER; \
1204 __raw_i915_write##x(dev_priv, reg, val); \
1205 VGPU_WRITE_FOOTER; \
1206}
1207
1208__vgpu_write(8)
1209__vgpu_write(16)
1210__vgpu_write(32)
1211
1212#undef __vgpu_write
1213#undef VGPU_WRITE_FOOTER
1214#undef VGPU_WRITE_HEADER
1215
1216#define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1217do { \
1218 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1219 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1220 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1221} while (0)
1222
1223#define ASSIGN_READ_MMIO_VFUNCS(x) \
1224do { \
1225 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1226 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1227 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1228 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1229} while (0)
1230
1231
1232static void fw_domain_init(struct drm_i915_private *dev_priv,
1233 enum forcewake_domain_id domain_id,
1234 i915_reg_t reg_set,
1235 i915_reg_t reg_ack)
1236{
1237 struct intel_uncore_forcewake_domain *d;
1238
1239 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1240 return;
1241
1242 d = &dev_priv->uncore.fw_domain[domain_id];
1243
1244 WARN_ON(d->wake_count);
1245
1246 d->wake_count = 0;
1247 d->reg_set = reg_set;
1248 d->reg_ack = reg_ack;
1249
1250 if (IS_GEN6(dev_priv)) {
1251 d->val_reset = 0;
1252 d->val_set = FORCEWAKE_KERNEL;
1253 d->val_clear = 0;
1254 } else {
1255 /* WaRsClearFWBitsAtReset:bdw,skl */
1256 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1257 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1258 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1259 }
1260
1261 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1262 d->reg_post = FORCEWAKE_ACK_VLV;
1263 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1264 d->reg_post = ECOBUS;
1265
1266 d->i915 = dev_priv;
1267 d->id = domain_id;
1268
1269 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1270 BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1271 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1272
1273 d->mask = 1 << domain_id;
1274
1275 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1276 d->timer.function = intel_uncore_fw_release_timer;
1277
1278 dev_priv->uncore.fw_domains |= (1 << domain_id);
1279
1280 fw_domain_reset(d);
1281}
1282
1283static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1284{
1285 if (INTEL_INFO(dev_priv)->gen <= 5)
1286 return;
1287
1288 if (IS_GEN9(dev_priv)) {
1289 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1290 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1291 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1292 FORCEWAKE_RENDER_GEN9,
1293 FORCEWAKE_ACK_RENDER_GEN9);
1294 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1295 FORCEWAKE_BLITTER_GEN9,
1296 FORCEWAKE_ACK_BLITTER_GEN9);
1297 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1298 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1299 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1300 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1301 if (!IS_CHERRYVIEW(dev_priv))
1302 dev_priv->uncore.funcs.force_wake_put =
1303 fw_domains_put_with_fifo;
1304 else
1305 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1306 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1307 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1308 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1309 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1310 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1311 dev_priv->uncore.funcs.force_wake_get =
1312 fw_domains_get_with_thread_status;
1313 if (IS_HASWELL(dev_priv))
1314 dev_priv->uncore.funcs.force_wake_put =
1315 fw_domains_put_with_fifo;
1316 else
1317 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1318 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1319 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1320 } else if (IS_IVYBRIDGE(dev_priv)) {
1321 u32 ecobus;
1322
1323 /* IVB configs may use multi-threaded forcewake */
1324
1325 /* A small trick here - if the bios hasn't configured
1326 * MT forcewake, and if the device is in RC6, then
1327 * force_wake_mt_get will not wake the device and the
1328 * ECOBUS read will return zero. Which will be
1329 * (correctly) interpreted by the test below as MT
1330 * forcewake being disabled.
1331 */
1332 dev_priv->uncore.funcs.force_wake_get =
1333 fw_domains_get_with_thread_status;
1334 dev_priv->uncore.funcs.force_wake_put =
1335 fw_domains_put_with_fifo;
1336
1337 /* We need to init first for ECOBUS access and then
1338 * determine later if we want to reinit, in case of MT access is
1339 * not working. In this stage we don't know which flavour this
1340 * ivb is, so it is better to reset also the gen6 fw registers
1341 * before the ecobus check.
1342 */
1343
1344 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1345 __raw_posting_read(dev_priv, ECOBUS);
1346
1347 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1348 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1349
1350 spin_lock_irq(&dev_priv->uncore.lock);
1351 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1352 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1353 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1354 spin_unlock_irq(&dev_priv->uncore.lock);
1355
1356 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1357 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1358 DRM_INFO("when using vblank-synced partial screen updates.\n");
1359 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1360 FORCEWAKE, FORCEWAKE_ACK);
1361 }
1362 } else if (IS_GEN6(dev_priv)) {
1363 dev_priv->uncore.funcs.force_wake_get =
1364 fw_domains_get_with_thread_status;
1365 dev_priv->uncore.funcs.force_wake_put =
1366 fw_domains_put_with_fifo;
1367 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1368 FORCEWAKE, FORCEWAKE_ACK);
1369 }
1370
1371 /* All future platforms are expected to require complex power gating */
1372 WARN_ON(dev_priv->uncore.fw_domains == 0);
1373}
1374
1375#define ASSIGN_FW_DOMAINS_TABLE(d) \
1376{ \
1377 dev_priv->uncore.fw_domains_table = \
1378 (struct intel_forcewake_range *)(d); \
1379 dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
1380}
1381
1382void intel_uncore_init(struct drm_i915_private *dev_priv)
1383{
1384 i915_check_vgpu(dev_priv);
1385
1386 intel_uncore_edram_detect(dev_priv);
1387 intel_uncore_fw_domains_init(dev_priv);
1388 __intel_uncore_early_sanitize(dev_priv, false);
1389
1390 dev_priv->uncore.unclaimed_mmio_check = 1;
1391
1392 switch (INTEL_INFO(dev_priv)->gen) {
1393 default:
1394 case 9:
1395 ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
1396 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1397 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1398 if (HAS_DECOUPLED_MMIO(dev_priv)) {
1399 dev_priv->uncore.funcs.mmio_readl =
1400 gen9_decoupled_read32;
1401 dev_priv->uncore.funcs.mmio_readq =
1402 gen9_decoupled_read64;
1403 dev_priv->uncore.funcs.mmio_writel =
1404 gen9_decoupled_write32;
1405 }
1406 break;
1407 case 8:
1408 if (IS_CHERRYVIEW(dev_priv)) {
1409 ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1410 ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
1411 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1412
1413 } else {
1414 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1415 ASSIGN_READ_MMIO_VFUNCS(gen6);
1416 }
1417 break;
1418 case 7:
1419 case 6:
1420 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1421
1422 if (IS_VALLEYVIEW(dev_priv)) {
1423 ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
1424 ASSIGN_READ_MMIO_VFUNCS(fwtable);
1425 } else {
1426 ASSIGN_READ_MMIO_VFUNCS(gen6);
1427 }
1428 break;
1429 case 5:
1430 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1431 ASSIGN_READ_MMIO_VFUNCS(gen5);
1432 break;
1433 case 4:
1434 case 3:
1435 case 2:
1436 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1437 ASSIGN_READ_MMIO_VFUNCS(gen2);
1438 break;
1439 }
1440
1441 intel_fw_table_check(dev_priv);
1442 if (INTEL_GEN(dev_priv) >= 8)
1443 intel_shadow_table_check();
1444
1445 if (intel_vgpu_active(dev_priv)) {
1446 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1447 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1448 }
1449
1450 i915_check_and_clear_faults(dev_priv);
1451}
1452#undef ASSIGN_WRITE_MMIO_VFUNCS
1453#undef ASSIGN_READ_MMIO_VFUNCS
1454
1455void intel_uncore_fini(struct drm_i915_private *dev_priv)
1456{
1457 /* Paranoia: make sure we have disabled everything before we exit. */
1458 intel_uncore_sanitize(dev_priv);
1459 intel_uncore_forcewake_reset(dev_priv, false);
1460}
1461
1462#define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
1463
1464static const struct register_whitelist {
1465 i915_reg_t offset_ldw, offset_udw;
1466 uint32_t size;
1467 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1468 uint32_t gen_bitmask;
1469} whitelist[] = {
1470 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1471 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1472 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1473};
1474
1475int i915_reg_read_ioctl(struct drm_device *dev,
1476 void *data, struct drm_file *file)
1477{
1478 struct drm_i915_private *dev_priv = to_i915(dev);
1479 struct drm_i915_reg_read *reg = data;
1480 struct register_whitelist const *entry = whitelist;
1481 unsigned size;
1482 i915_reg_t offset_ldw, offset_udw;
1483 int i, ret = 0;
1484
1485 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1486 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1487 (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
1488 break;
1489 }
1490
1491 if (i == ARRAY_SIZE(whitelist))
1492 return -EINVAL;
1493
1494 /* We use the low bits to encode extra flags as the register should
1495 * be naturally aligned (and those that are not so aligned merely
1496 * limit the available flags for that register).
1497 */
1498 offset_ldw = entry->offset_ldw;
1499 offset_udw = entry->offset_udw;
1500 size = entry->size;
1501 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1502
1503 intel_runtime_pm_get(dev_priv);
1504
1505 switch (size) {
1506 case 8 | 1:
1507 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1508 break;
1509 case 8:
1510 reg->val = I915_READ64(offset_ldw);
1511 break;
1512 case 4:
1513 reg->val = I915_READ(offset_ldw);
1514 break;
1515 case 2:
1516 reg->val = I915_READ16(offset_ldw);
1517 break;
1518 case 1:
1519 reg->val = I915_READ8(offset_ldw);
1520 break;
1521 default:
1522 ret = -EINVAL;
1523 goto out;
1524 }
1525
1526out:
1527 intel_runtime_pm_put(dev_priv);
1528 return ret;
1529}
1530
1531static int i915_reset_complete(struct pci_dev *pdev)
1532{
1533 u8 gdrst;
1534 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1535 return (gdrst & GRDOM_RESET_STATUS) == 0;
1536}
1537
1538static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1539{
1540 struct pci_dev *pdev = dev_priv->drm.pdev;
1541
1542 /* assert reset for at least 20 usec */
1543 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1544 udelay(20);
1545 pci_write_config_byte(pdev, I915_GDRST, 0);
1546
1547 return wait_for(i915_reset_complete(pdev), 500);
1548}
1549
1550static int g4x_reset_complete(struct pci_dev *pdev)
1551{
1552 u8 gdrst;
1553 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1554 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1555}
1556
1557static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1558{
1559 struct pci_dev *pdev = dev_priv->drm.pdev;
1560 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1561 return wait_for(g4x_reset_complete(pdev), 500);
1562}
1563
1564static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1565{
1566 struct pci_dev *pdev = dev_priv->drm.pdev;
1567 int ret;
1568
1569 pci_write_config_byte(pdev, I915_GDRST,
1570 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1571 ret = wait_for(g4x_reset_complete(pdev), 500);
1572 if (ret)
1573 return ret;
1574
1575 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1576 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1577 POSTING_READ(VDECCLK_GATE_D);
1578
1579 pci_write_config_byte(pdev, I915_GDRST,
1580 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1581 ret = wait_for(g4x_reset_complete(pdev), 500);
1582 if (ret)
1583 return ret;
1584
1585 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1586 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1587 POSTING_READ(VDECCLK_GATE_D);
1588
1589 pci_write_config_byte(pdev, I915_GDRST, 0);
1590
1591 return 0;
1592}
1593
1594static int ironlake_do_reset(struct drm_i915_private *dev_priv,
1595 unsigned engine_mask)
1596{
1597 int ret;
1598
1599 I915_WRITE(ILK_GDSR,
1600 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1601 ret = intel_wait_for_register(dev_priv,
1602 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1603 500);
1604 if (ret)
1605 return ret;
1606
1607 I915_WRITE(ILK_GDSR,
1608 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1609 ret = intel_wait_for_register(dev_priv,
1610 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
1611 500);
1612 if (ret)
1613 return ret;
1614
1615 I915_WRITE(ILK_GDSR, 0);
1616
1617 return 0;
1618}
1619
1620/* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1621static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
1622 u32 hw_domain_mask)
1623{
1624 /* GEN6_GDRST is not in the gt power well, no need to check
1625 * for fifo space for the write or forcewake the chip for
1626 * the read
1627 */
1628 __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1629
1630 /* Spin waiting for the device to ack the reset requests */
1631 return intel_wait_for_register_fw(dev_priv,
1632 GEN6_GDRST, hw_domain_mask, 0,
1633 500);
1634}
1635
1636/**
1637 * gen6_reset_engines - reset individual engines
1638 * @dev_priv: i915 device
1639 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1640 *
1641 * This function will reset the individual engines that are set in engine_mask.
1642 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1643 *
1644 * Note: It is responsibility of the caller to handle the difference between
1645 * asking full domain reset versus reset for all available individual engines.
1646 *
1647 * Returns 0 on success, nonzero on error.
1648 */
1649static int gen6_reset_engines(struct drm_i915_private *dev_priv,
1650 unsigned engine_mask)
1651{
1652 struct intel_engine_cs *engine;
1653 const u32 hw_engine_mask[I915_NUM_ENGINES] = {
1654 [RCS] = GEN6_GRDOM_RENDER,
1655 [BCS] = GEN6_GRDOM_BLT,
1656 [VCS] = GEN6_GRDOM_MEDIA,
1657 [VCS2] = GEN8_GRDOM_MEDIA2,
1658 [VECS] = GEN6_GRDOM_VECS,
1659 };
1660 u32 hw_mask;
1661 int ret;
1662
1663 if (engine_mask == ALL_ENGINES) {
1664 hw_mask = GEN6_GRDOM_FULL;
1665 } else {
1666 unsigned int tmp;
1667
1668 hw_mask = 0;
1669 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1670 hw_mask |= hw_engine_mask[engine->id];
1671 }
1672
1673 ret = gen6_hw_domain_reset(dev_priv, hw_mask);
1674
1675 intel_uncore_forcewake_reset(dev_priv, true);
1676
1677 return ret;
1678}
1679
1680/**
1681 * intel_wait_for_register_fw - wait until register matches expected state
1682 * @dev_priv: the i915 device
1683 * @reg: the register to read
1684 * @mask: mask to apply to register value
1685 * @value: expected value
1686 * @timeout_ms: timeout in millisecond
1687 *
1688 * This routine waits until the target register @reg contains the expected
1689 * @value after applying the @mask, i.e. it waits until ::
1690 *
1691 * (I915_READ_FW(reg) & mask) == value
1692 *
1693 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1694 *
1695 * Note that this routine assumes the caller holds forcewake asserted, it is
1696 * not suitable for very long waits. See intel_wait_for_register() if you
1697 * wish to wait without holding forcewake for the duration (i.e. you expect
1698 * the wait to be slow).
1699 *
1700 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1701 */
1702int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1703 i915_reg_t reg,
1704 const u32 mask,
1705 const u32 value,
1706 const unsigned long timeout_ms)
1707{
1708#define done ((I915_READ_FW(reg) & mask) == value)
1709 int ret = wait_for_us(done, 2);
1710 if (ret)
1711 ret = wait_for(done, timeout_ms);
1712 return ret;
1713#undef done
1714}
1715
1716/**
1717 * intel_wait_for_register - wait until register matches expected state
1718 * @dev_priv: the i915 device
1719 * @reg: the register to read
1720 * @mask: mask to apply to register value
1721 * @value: expected value
1722 * @timeout_ms: timeout in millisecond
1723 *
1724 * This routine waits until the target register @reg contains the expected
1725 * @value after applying the @mask, i.e. it waits until ::
1726 *
1727 * (I915_READ(reg) & mask) == value
1728 *
1729 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1730 *
1731 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1732 */
1733int intel_wait_for_register(struct drm_i915_private *dev_priv,
1734 i915_reg_t reg,
1735 const u32 mask,
1736 const u32 value,
1737 const unsigned long timeout_ms)
1738{
1739
1740 unsigned fw =
1741 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1742 int ret;
1743
1744 intel_uncore_forcewake_get(dev_priv, fw);
1745 ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
1746 intel_uncore_forcewake_put(dev_priv, fw);
1747 if (ret)
1748 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
1749 timeout_ms);
1750
1751 return ret;
1752}
1753
1754static int gen8_request_engine_reset(struct intel_engine_cs *engine)
1755{
1756 struct drm_i915_private *dev_priv = engine->i915;
1757 int ret;
1758
1759 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1760 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1761
1762 ret = intel_wait_for_register_fw(dev_priv,
1763 RING_RESET_CTL(engine->mmio_base),
1764 RESET_CTL_READY_TO_RESET,
1765 RESET_CTL_READY_TO_RESET,
1766 700);
1767 if (ret)
1768 DRM_ERROR("%s: reset request timeout\n", engine->name);
1769
1770 return ret;
1771}
1772
1773static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
1774{
1775 struct drm_i915_private *dev_priv = engine->i915;
1776
1777 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
1778 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1779}
1780
1781static int gen8_reset_engines(struct drm_i915_private *dev_priv,
1782 unsigned engine_mask)
1783{
1784 struct intel_engine_cs *engine;
1785 unsigned int tmp;
1786
1787 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1788 if (gen8_request_engine_reset(engine))
1789 goto not_ready;
1790
1791 return gen6_reset_engines(dev_priv, engine_mask);
1792
1793not_ready:
1794 for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1795 gen8_unrequest_engine_reset(engine);
1796
1797 return -EIO;
1798}
1799
1800typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
1801
1802static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
1803{
1804 if (!i915.reset)
1805 return NULL;
1806
1807 if (INTEL_INFO(dev_priv)->gen >= 8)
1808 return gen8_reset_engines;
1809 else if (INTEL_INFO(dev_priv)->gen >= 6)
1810 return gen6_reset_engines;
1811 else if (IS_GEN5(dev_priv))
1812 return ironlake_do_reset;
1813 else if (IS_G4X(dev_priv))
1814 return g4x_do_reset;
1815 else if (IS_G33(dev_priv))
1816 return g33_do_reset;
1817 else if (INTEL_INFO(dev_priv)->gen >= 3)
1818 return i915_do_reset;
1819 else
1820 return NULL;
1821}
1822
1823int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1824{
1825 reset_func reset;
1826 int ret;
1827
1828 reset = intel_get_gpu_reset(dev_priv);
1829 if (reset == NULL)
1830 return -ENODEV;
1831
1832 /* If the power well sleeps during the reset, the reset
1833 * request may be dropped and never completes (causing -EIO).
1834 */
1835 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1836 ret = reset(dev_priv, engine_mask);
1837 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1838
1839 return ret;
1840}
1841
1842bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
1843{
1844 return intel_get_gpu_reset(dev_priv) != NULL;
1845}
1846
1847int intel_guc_reset(struct drm_i915_private *dev_priv)
1848{
1849 int ret;
1850 unsigned long irqflags;
1851
1852 if (!HAS_GUC(dev_priv))
1853 return -EINVAL;
1854
1855 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1856 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1857
1858 ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
1859
1860 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1861 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1862
1863 return ret;
1864}
1865
1866bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1867{
1868 return check_for_unclaimed_mmio(dev_priv);
1869}
1870
1871bool
1872intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1873{
1874 if (unlikely(i915.mmio_debug ||
1875 dev_priv->uncore.unclaimed_mmio_check <= 0))
1876 return false;
1877
1878 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1879 DRM_DEBUG("Unclaimed register detected, "
1880 "enabling oneshot unclaimed register reporting. "
1881 "Please use i915.mmio_debug=N for more information.\n");
1882 i915.mmio_debug++;
1883 dev_priv->uncore.unclaimed_mmio_check--;
1884 return true;
1885 }
1886
1887 return false;
1888}
1889
1890static enum forcewake_domains
1891intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
1892 i915_reg_t reg)
1893{
1894 u32 offset = i915_mmio_reg_offset(reg);
1895 enum forcewake_domains fw_domains;
1896
1897 if (HAS_FWTABLE(dev_priv)) {
1898 fw_domains = __fwtable_reg_read_fw_domains(offset);
1899 } else if (INTEL_GEN(dev_priv) >= 6) {
1900 fw_domains = __gen6_reg_read_fw_domains(offset);
1901 } else {
1902 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1903 fw_domains = 0;
1904 }
1905
1906 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1907
1908 return fw_domains;
1909}
1910
1911static enum forcewake_domains
1912intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
1913 i915_reg_t reg)
1914{
1915 u32 offset = i915_mmio_reg_offset(reg);
1916 enum forcewake_domains fw_domains;
1917
1918 if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
1919 fw_domains = __fwtable_reg_write_fw_domains(offset);
1920 } else if (IS_GEN8(dev_priv)) {
1921 fw_domains = __gen8_reg_write_fw_domains(offset);
1922 } else if (IS_GEN(dev_priv, 6, 7)) {
1923 fw_domains = FORCEWAKE_RENDER;
1924 } else {
1925 WARN_ON(!IS_GEN(dev_priv, 2, 5));
1926 fw_domains = 0;
1927 }
1928
1929 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1930
1931 return fw_domains;
1932}
1933
1934/**
1935 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1936 * a register
1937 * @dev_priv: pointer to struct drm_i915_private
1938 * @reg: register in question
1939 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1940 *
1941 * Returns a set of forcewake domains required to be taken with for example
1942 * intel_uncore_forcewake_get for the specified register to be accessible in the
1943 * specified mode (read, write or read/write) with raw mmio accessors.
1944 *
1945 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1946 * callers to do FIFO management on their own or risk losing writes.
1947 */
1948enum forcewake_domains
1949intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
1950 i915_reg_t reg, unsigned int op)
1951{
1952 enum forcewake_domains fw_domains = 0;
1953
1954 WARN_ON(!op);
1955
1956 if (intel_vgpu_active(dev_priv))
1957 return 0;
1958
1959 if (op & FW_REG_READ)
1960 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
1961
1962 if (op & FW_REG_WRITE)
1963 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
1964
1965 return fw_domains;
1966}