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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24#ifndef _INTEL_GUC_H_
25#define _INTEL_GUC_H_
26
27#include "intel_guc_fwif.h"
28#include "i915_guc_reg.h"
29
30struct i915_guc_client {
31 struct drm_i915_gem_object *client_obj;
32 struct intel_context *owner;
33 struct intel_guc *guc;
34 uint32_t priority;
35 uint32_t ctx_index;
36
37 uint32_t proc_desc_offset;
38 uint32_t doorbell_offset;
39 uint32_t cookie;
40 uint16_t doorbell_id;
41 uint16_t padding; /* Maintain alignment */
42
43 uint32_t wq_offset;
44 uint32_t wq_size;
45 uint32_t wq_tail;
46 uint32_t wq_head;
47
48 /* GuC submission statistics & status */
49 uint64_t submissions[GUC_MAX_ENGINES_NUM];
50 uint32_t q_fail;
51 uint32_t b_fail;
52 int retcode;
53};
54
55enum intel_guc_fw_status {
56 GUC_FIRMWARE_FAIL = -1,
57 GUC_FIRMWARE_NONE = 0,
58 GUC_FIRMWARE_PENDING,
59 GUC_FIRMWARE_SUCCESS
60};
61
62/*
63 * This structure encapsulates all the data needed during the process
64 * of fetching, caching, and loading the firmware image into the GuC.
65 */
66struct intel_guc_fw {
67 struct drm_device * guc_dev;
68 const char * guc_fw_path;
69 size_t guc_fw_size;
70 struct drm_i915_gem_object * guc_fw_obj;
71 enum intel_guc_fw_status guc_fw_fetch_status;
72 enum intel_guc_fw_status guc_fw_load_status;
73
74 uint16_t guc_fw_major_wanted;
75 uint16_t guc_fw_minor_wanted;
76 uint16_t guc_fw_major_found;
77 uint16_t guc_fw_minor_found;
78
79 uint32_t header_size;
80 uint32_t header_offset;
81 uint32_t rsa_size;
82 uint32_t rsa_offset;
83 uint32_t ucode_size;
84 uint32_t ucode_offset;
85};
86
87struct intel_guc {
88 struct intel_guc_fw guc_fw;
89 uint32_t log_flags;
90 struct drm_i915_gem_object *log_obj;
91
92 struct drm_i915_gem_object *ads_obj;
93
94 struct drm_i915_gem_object *ctx_pool_obj;
95 struct ida ctx_ids;
96
97 struct i915_guc_client *execbuf_client;
98
99 DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS);
100 uint32_t db_cacheline; /* Cyclic counter mod pagesize */
101
102 /* Action status & statistics */
103 uint64_t action_count; /* Total commands issued */
104 uint32_t action_cmd; /* Last command word */
105 uint32_t action_status; /* Last return status */
106 uint32_t action_fail; /* Total number of failures */
107 int32_t action_err; /* Last error code */
108
109 uint64_t submissions[GUC_MAX_ENGINES_NUM];
110 uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
111};
112
113/* intel_guc_loader.c */
114extern void intel_guc_ucode_init(struct drm_device *dev);
115extern int intel_guc_ucode_load(struct drm_device *dev);
116extern void intel_guc_ucode_fini(struct drm_device *dev);
117extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
118extern int intel_guc_suspend(struct drm_device *dev);
119extern int intel_guc_resume(struct drm_device *dev);
120
121/* i915_guc_submission.c */
122int i915_guc_submission_init(struct drm_device *dev);
123int i915_guc_submission_enable(struct drm_device *dev);
124int i915_guc_submit(struct i915_guc_client *client,
125 struct drm_i915_gem_request *rq);
126void i915_guc_submission_disable(struct drm_device *dev);
127void i915_guc_submission_fini(struct drm_device *dev);
128int i915_guc_wq_check_space(struct i915_guc_client *client);
129
130#endif
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24#ifndef _INTEL_GUC_H_
25#define _INTEL_GUC_H_
26
27#include "intel_guc_fwif.h"
28#include "i915_guc_reg.h"
29#include "intel_ringbuffer.h"
30
31struct drm_i915_gem_request;
32
33/*
34 * This structure primarily describes the GEM object shared with the GuC.
35 * The GEM object is held for the entire lifetime of our interaction with
36 * the GuC, being allocated before the GuC is loaded with its firmware.
37 * Because there's no way to update the address used by the GuC after
38 * initialisation, the shared object must stay pinned into the GGTT as
39 * long as the GuC is in use. We also keep the first page (only) mapped
40 * into kernel address space, as it includes shared data that must be
41 * updated on every request submission.
42 *
43 * The single GEM object described here is actually made up of several
44 * separate areas, as far as the GuC is concerned. The first page (kept
45 * kmap'd) includes the "process decriptor" which holds sequence data for
46 * the doorbell, and one cacheline which actually *is* the doorbell; a
47 * write to this will "ring the doorbell" (i.e. send an interrupt to the
48 * GuC). The subsequent pages of the client object constitute the work
49 * queue (a circular array of work items), again described in the process
50 * descriptor. Work queue pages are mapped momentarily as required.
51 *
52 * We also keep a few statistics on failures. Ideally, these should all
53 * be zero!
54 * no_wq_space: times that the submission pre-check found no space was
55 * available in the work queue (note, the queue is shared,
56 * not per-engine). It is OK for this to be nonzero, but
57 * it should not be huge!
58 * q_fail: failed to enqueue a work item. This should never happen,
59 * because we check for space beforehand.
60 * b_fail: failed to ring the doorbell. This should never happen, unless
61 * somehow the hardware misbehaves, or maybe if the GuC firmware
62 * crashes? We probably need to reset the GPU to recover.
63 * retcode: errno from last guc_submit()
64 */
65struct i915_guc_client {
66 struct i915_vma *vma;
67 void *vaddr;
68 struct i915_gem_context *owner;
69 struct intel_guc *guc;
70
71 uint32_t engines; /* bitmap of (host) engine ids */
72 uint32_t priority;
73 uint32_t ctx_index;
74 uint32_t proc_desc_offset;
75
76 uint32_t doorbell_offset;
77 uint32_t cookie;
78 uint16_t doorbell_id;
79 uint16_t padding[3]; /* Maintain alignment */
80
81 spinlock_t wq_lock;
82 uint32_t wq_offset;
83 uint32_t wq_size;
84 uint32_t wq_tail;
85 uint32_t wq_rsvd;
86 uint32_t no_wq_space;
87 uint32_t b_fail;
88 int retcode;
89
90 /* Per-engine counts of GuC submissions */
91 uint64_t submissions[I915_NUM_ENGINES];
92};
93
94enum intel_guc_fw_status {
95 GUC_FIRMWARE_FAIL = -1,
96 GUC_FIRMWARE_NONE = 0,
97 GUC_FIRMWARE_PENDING,
98 GUC_FIRMWARE_SUCCESS
99};
100
101/*
102 * This structure encapsulates all the data needed during the process
103 * of fetching, caching, and loading the firmware image into the GuC.
104 */
105struct intel_guc_fw {
106 struct drm_device * guc_dev;
107 const char * guc_fw_path;
108 size_t guc_fw_size;
109 struct drm_i915_gem_object * guc_fw_obj;
110 enum intel_guc_fw_status guc_fw_fetch_status;
111 enum intel_guc_fw_status guc_fw_load_status;
112
113 uint16_t guc_fw_major_wanted;
114 uint16_t guc_fw_minor_wanted;
115 uint16_t guc_fw_major_found;
116 uint16_t guc_fw_minor_found;
117
118 uint32_t header_size;
119 uint32_t header_offset;
120 uint32_t rsa_size;
121 uint32_t rsa_offset;
122 uint32_t ucode_size;
123 uint32_t ucode_offset;
124};
125
126struct intel_guc_log {
127 uint32_t flags;
128 struct i915_vma *vma;
129 void *buf_addr;
130 struct workqueue_struct *flush_wq;
131 struct work_struct flush_work;
132 struct rchan *relay_chan;
133
134 /* logging related stats */
135 u32 capture_miss_count;
136 u32 flush_interrupt_count;
137 u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
138 u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
139 u32 flush_count[GUC_MAX_LOG_BUFFER];
140};
141
142struct intel_guc {
143 struct intel_guc_fw guc_fw;
144 struct intel_guc_log log;
145
146 /* GuC2Host interrupt related state */
147 bool interrupts_enabled;
148
149 struct i915_vma *ads_vma;
150 struct i915_vma *ctx_pool_vma;
151 struct ida ctx_ids;
152
153 struct i915_guc_client *execbuf_client;
154
155 DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS);
156 uint32_t db_cacheline; /* Cyclic counter mod pagesize */
157
158 /* Action status & statistics */
159 uint64_t action_count; /* Total commands issued */
160 uint32_t action_cmd; /* Last command word */
161 uint32_t action_status; /* Last return status */
162 uint32_t action_fail; /* Total number of failures */
163 int32_t action_err; /* Last error code */
164
165 uint64_t submissions[I915_NUM_ENGINES];
166 uint32_t last_seqno[I915_NUM_ENGINES];
167
168 /* To serialize the Host2GuC actions */
169 struct mutex action_lock;
170};
171
172/* intel_guc_loader.c */
173extern void intel_guc_init(struct drm_device *dev);
174extern int intel_guc_setup(struct drm_device *dev);
175extern void intel_guc_fini(struct drm_device *dev);
176extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
177extern int intel_guc_suspend(struct drm_device *dev);
178extern int intel_guc_resume(struct drm_device *dev);
179
180/* i915_guc_submission.c */
181int i915_guc_submission_init(struct drm_i915_private *dev_priv);
182int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
183int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
184void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
185void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
186void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
187void i915_guc_capture_logs(struct drm_i915_private *dev_priv);
188void i915_guc_flush_logs(struct drm_i915_private *dev_priv);
189void i915_guc_register(struct drm_i915_private *dev_priv);
190void i915_guc_unregister(struct drm_i915_private *dev_priv);
191int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
192
193#endif