1/*
  2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
  3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  4 *
  5 * This program is free software and is provided to you under the terms of the
  6 * GNU General Public License version 2 as published by the Free Software
  7 * Foundation, and any use by you of this program is subject to the terms
  8 * of such GNU licence.
  9 *
 10 * ARM Mali DP500/DP550/DP650 registers definition.
 11 */
 12
 13#ifndef __MALIDP_REGS_H__
 14#define __MALIDP_REGS_H__
 15
 16/*
 17 * abbreviations used:
 18 *    - DC - display core (general settings)
 19 *    - DE - display engine
 20 *    - SE - scaling engine
 21 */
 22
 23/* interrupt bit masks */
 24#define MALIDP_DE_IRQ_UNDERRUN			(1 << 0)
 25
 26#define MALIDP500_DE_IRQ_AXI_ERR		(1 << 4)
 27#define MALIDP500_DE_IRQ_VSYNC			(1 << 5)
 28#define MALIDP500_DE_IRQ_PROG_LINE		(1 << 6)
 29#define MALIDP500_DE_IRQ_SATURATION		(1 << 7)
 30#define MALIDP500_DE_IRQ_CONF_VALID		(1 << 8)
 31#define MALIDP500_DE_IRQ_CONF_MODE		(1 << 11)
 32#define MALIDP500_DE_IRQ_CONF_ACTIVE		(1 << 17)
 33#define MALIDP500_DE_IRQ_PM_ACTIVE		(1 << 18)
 34#define MALIDP500_DE_IRQ_TESTMODE_ACTIVE	(1 << 19)
 35#define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE	(1 << 24)
 36#define MALIDP500_DE_IRQ_AXI_BUSY		(1 << 28)
 37#define MALIDP500_DE_IRQ_GLOBAL			(1 << 31)
 38#define MALIDP500_SE_IRQ_CONF_MODE		(1 << 0)
 39#define MALIDP500_SE_IRQ_CONF_VALID		(1 << 4)
 40#define MALIDP500_SE_IRQ_INIT_BUSY		(1 << 5)
 41#define MALIDP500_SE_IRQ_AXI_ERROR		(1 << 8)
 42#define MALIDP500_SE_IRQ_OVERRUN		(1 << 9)
 43#define MALIDP500_SE_IRQ_PROG_LINE1		(1 << 12)
 44#define MALIDP500_SE_IRQ_PROG_LINE2		(1 << 13)
 45#define MALIDP500_SE_IRQ_CONF_ACTIVE		(1 << 17)
 46#define MALIDP500_SE_IRQ_PM_ACTIVE		(1 << 18)
 47#define MALIDP500_SE_IRQ_AXI_BUSY		(1 << 28)
 48#define MALIDP500_SE_IRQ_GLOBAL			(1 << 31)
 49
 50#define MALIDP550_DE_IRQ_SATURATION		(1 << 8)
 51#define MALIDP550_DE_IRQ_VSYNC			(1 << 12)
 52#define MALIDP550_DE_IRQ_PROG_LINE		(1 << 13)
 53#define MALIDP550_DE_IRQ_AXI_ERR		(1 << 16)
 54#define MALIDP550_SE_IRQ_EOW			(1 << 0)
 55#define MALIDP550_SE_IRQ_AXI_ERR		(1 << 16)
 56#define MALIDP550_DC_IRQ_CONF_VALID		(1 << 0)
 57#define MALIDP550_DC_IRQ_CONF_MODE		(1 << 4)
 58#define MALIDP550_DC_IRQ_CONF_ACTIVE		(1 << 16)
 59#define MALIDP550_DC_IRQ_DE			(1 << 20)
 60#define MALIDP550_DC_IRQ_SE			(1 << 24)
 61
 62#define MALIDP650_DE_IRQ_DRIFT			(1 << 4)
 63
 64/* bit masks that are common between products */
 65#define   MALIDP_CFG_VALID		(1 << 0)
 66#define   MALIDP_DISP_FUNC_ILACED	(1 << 8)
 67
 68/* register offsets for IRQ management */
 69#define MALIDP_REG_STATUS		0x00000
 70#define MALIDP_REG_SETIRQ		0x00004
 71#define MALIDP_REG_MASKIRQ		0x00008
 72#define MALIDP_REG_CLEARIRQ		0x0000c
 73
 74/* register offsets */
 75#define MALIDP_DE_CORE_ID		0x00018
 76#define MALIDP_DE_DISPLAY_FUNC		0x00020
 77
 78/* these offsets are relative to MALIDP5x0_TIMINGS_BASE */
 79#define MALIDP_DE_H_TIMINGS		0x0
 80#define MALIDP_DE_V_TIMINGS		0x4
 81#define MALIDP_DE_SYNC_WIDTH		0x8
 82#define MALIDP_DE_HV_ACTIVE		0xc
 83
 84/* macros to set values into registers */
 85#define MALIDP_DE_H_FRONTPORCH(x)	(((x) & 0xfff) << 0)
 86#define MALIDP_DE_H_BACKPORCH(x)	(((x) & 0x3ff) << 16)
 87#define MALIDP500_DE_V_FRONTPORCH(x)	(((x) & 0xff) << 0)
 88#define MALIDP550_DE_V_FRONTPORCH(x)	(((x) & 0xfff) << 0)
 89#define MALIDP_DE_V_BACKPORCH(x)	(((x) & 0xff) << 16)
 90#define MALIDP_DE_H_SYNCWIDTH(x)	(((x) & 0x3ff) << 0)
 91#define MALIDP_DE_V_SYNCWIDTH(x)	(((x) & 0xff) << 16)
 92#define MALIDP_DE_H_ACTIVE(x)		(((x) & 0x1fff) << 0)
 93#define MALIDP_DE_V_ACTIVE(x)		(((x) & 0x1fff) << 16)
 94
 95/* register offsets and bits specific to DP500 */
 96#define MALIDP500_DC_BASE		0x00000
 97#define MALIDP500_DC_CONTROL		0x0000c
 98#define   MALIDP500_DC_CONFIG_REQ	(1 << 17)
 99#define   MALIDP500_HSYNCPOL		(1 << 20)
100#define   MALIDP500_VSYNCPOL		(1 << 21)
101#define   MALIDP500_DC_CLEAR_MASK	0x300fff
102#define MALIDP500_DE_LINE_COUNTER	0x00010
103#define MALIDP500_DE_AXI_CONTROL	0x00014
104#define MALIDP500_DE_SECURE_CTRL	0x0001c
105#define MALIDP500_DE_CHROMA_KEY		0x00024
106#define MALIDP500_TIMINGS_BASE		0x00028
107
108#define MALIDP500_CONFIG_3D		0x00038
109#define MALIDP500_BGND_COLOR		0x0003c
110#define MALIDP500_OUTPUT_DEPTH		0x00044
111#define MALIDP500_YUV_RGB_COEF		0x00048
112#define MALIDP500_COLOR_ADJ_COEF	0x00078
113#define MALIDP500_COEF_TABLE_ADDR	0x000a8
114#define MALIDP500_COEF_TABLE_DATA	0x000ac
115#define MALIDP500_DE_LV_BASE		0x00100
116#define MALIDP500_DE_LV_PTR_BASE	0x00124
117#define MALIDP500_DE_LG1_BASE		0x00200
118#define MALIDP500_DE_LG1_PTR_BASE	0x0021c
119#define MALIDP500_DE_LG2_BASE		0x00300
120#define MALIDP500_DE_LG2_PTR_BASE	0x0031c
121#define MALIDP500_SE_BASE		0x00c00
122#define MALIDP500_SE_PTR_BASE		0x00e0c
123#define MALIDP500_DC_IRQ_BASE		0x00f00
124#define MALIDP500_CONFIG_VALID		0x00f00
125#define MALIDP500_CONFIG_ID		0x00fd4
126
127/* register offsets and bits specific to DP550/DP650 */
128#define MALIDP550_DE_CONTROL		0x00010
129#define MALIDP550_DE_LINE_COUNTER	0x00014
130#define MALIDP550_DE_AXI_CONTROL	0x00018
131#define MALIDP550_DE_QOS		0x0001c
132#define MALIDP550_TIMINGS_BASE		0x00030
133#define MALIDP550_HSYNCPOL		(1 << 12)
134#define MALIDP550_VSYNCPOL		(1 << 28)
135
136#define MALIDP550_DE_DISP_SIDEBAND	0x00040
137#define MALIDP550_DE_BGND_COLOR		0x00044
138#define MALIDP550_DE_OUTPUT_DEPTH	0x0004c
139#define MALIDP550_DE_COLOR_COEF		0x00050
140#define MALIDP550_DE_COEF_TABLE_ADDR	0x00080
141#define MALIDP550_DE_COEF_TABLE_DATA	0x00084
142#define MALIDP550_DE_LV1_BASE		0x00100
143#define MALIDP550_DE_LV1_PTR_BASE	0x00124
144#define MALIDP550_DE_LV2_BASE		0x00200
145#define MALIDP550_DE_LV2_PTR_BASE	0x00224
146#define MALIDP550_DE_LG_BASE		0x00300
147#define MALIDP550_DE_LG_PTR_BASE	0x0031c
148#define MALIDP550_DE_LS_BASE		0x00400
149#define MALIDP550_DE_LS_PTR_BASE	0x0042c
150#define MALIDP550_DE_PERF_BASE		0x00500
151#define MALIDP550_SE_BASE		0x08000
152#define MALIDP550_DC_BASE		0x0c000
153#define MALIDP550_DC_CONTROL		0x0c010
154#define   MALIDP550_DC_CONFIG_REQ	(1 << 16)
155#define MALIDP550_CONFIG_VALID		0x0c014
156#define MALIDP550_CONFIG_ID		0x0ffd4
157
158/*
159 * Starting with DP550 the register map blocks has been standardised to the
160 * following layout:
161 *
162 *   Offset            Block registers
163 *  0x00000            Display Engine
164 *  0x08000            Scaling Engine
165 *  0x0c000            Display Core
166 *  0x10000            Secure control
167 *
168 * The old DP500 IP mixes some DC with the DE registers, hence the need
169 * for a mapping structure.
170 */
171
172#endif /* __MALIDP_REGS_H__ */