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1/*
2 * linux/drivers/gpio/gpio-mb86s7x.c
3 *
4 * Copyright (C) 2015 Fujitsu Semiconductor Limited
5 * Copyright (C) 2015 Linaro Ltd.
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/io.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/module.h>
21#include <linux/err.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/of_device.h>
25#include <linux/gpio/driver.h>
26#include <linux/platform_device.h>
27#include <linux/spinlock.h>
28#include <linux/slab.h>
29
30/*
31 * Only first 8bits of a register correspond to each pin,
32 * so there are 4 registers for 32 pins.
33 */
34#define PDR(x) (0x0 + x / 8 * 4)
35#define DDR(x) (0x10 + x / 8 * 4)
36#define PFR(x) (0x20 + x / 8 * 4)
37
38#define OFFSET(x) BIT((x) % 8)
39
40struct mb86s70_gpio_chip {
41 struct gpio_chip gc;
42 void __iomem *base;
43 struct clk *clk;
44 spinlock_t lock;
45};
46
47static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)
48{
49 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
50 unsigned long flags;
51 u32 val;
52
53 spin_lock_irqsave(&gchip->lock, flags);
54
55 val = readl(gchip->base + PFR(gpio));
56 if (!(val & OFFSET(gpio))) {
57 spin_unlock_irqrestore(&gchip->lock, flags);
58 return -EINVAL;
59 }
60
61 val &= ~OFFSET(gpio);
62 writel(val, gchip->base + PFR(gpio));
63
64 spin_unlock_irqrestore(&gchip->lock, flags);
65
66 return 0;
67}
68
69static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio)
70{
71 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
72 unsigned long flags;
73 u32 val;
74
75 spin_lock_irqsave(&gchip->lock, flags);
76
77 val = readl(gchip->base + PFR(gpio));
78 val |= OFFSET(gpio);
79 writel(val, gchip->base + PFR(gpio));
80
81 spin_unlock_irqrestore(&gchip->lock, flags);
82}
83
84static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
85{
86 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
87 unsigned long flags;
88 unsigned char val;
89
90 spin_lock_irqsave(&gchip->lock, flags);
91
92 val = readl(gchip->base + DDR(gpio));
93 val &= ~OFFSET(gpio);
94 writel(val, gchip->base + DDR(gpio));
95
96 spin_unlock_irqrestore(&gchip->lock, flags);
97
98 return 0;
99}
100
101static int mb86s70_gpio_direction_output(struct gpio_chip *gc,
102 unsigned gpio, int value)
103{
104 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
105 unsigned long flags;
106 unsigned char val;
107
108 spin_lock_irqsave(&gchip->lock, flags);
109
110 val = readl(gchip->base + PDR(gpio));
111 if (value)
112 val |= OFFSET(gpio);
113 else
114 val &= ~OFFSET(gpio);
115 writel(val, gchip->base + PDR(gpio));
116
117 val = readl(gchip->base + DDR(gpio));
118 val |= OFFSET(gpio);
119 writel(val, gchip->base + DDR(gpio));
120
121 spin_unlock_irqrestore(&gchip->lock, flags);
122
123 return 0;
124}
125
126static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio)
127{
128 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
129
130 return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio));
131}
132
133static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value)
134{
135 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
136 unsigned long flags;
137 unsigned char val;
138
139 spin_lock_irqsave(&gchip->lock, flags);
140
141 val = readl(gchip->base + PDR(gpio));
142 if (value)
143 val |= OFFSET(gpio);
144 else
145 val &= ~OFFSET(gpio);
146 writel(val, gchip->base + PDR(gpio));
147
148 spin_unlock_irqrestore(&gchip->lock, flags);
149}
150
151static int mb86s70_gpio_probe(struct platform_device *pdev)
152{
153 struct mb86s70_gpio_chip *gchip;
154 struct resource *res;
155 int ret;
156
157 gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL);
158 if (gchip == NULL)
159 return -ENOMEM;
160
161 platform_set_drvdata(pdev, gchip);
162
163 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
164 gchip->base = devm_ioremap_resource(&pdev->dev, res);
165 if (IS_ERR(gchip->base))
166 return PTR_ERR(gchip->base);
167
168 gchip->clk = devm_clk_get(&pdev->dev, NULL);
169 if (IS_ERR(gchip->clk))
170 return PTR_ERR(gchip->clk);
171
172 clk_prepare_enable(gchip->clk);
173
174 spin_lock_init(&gchip->lock);
175
176 gchip->gc.direction_output = mb86s70_gpio_direction_output;
177 gchip->gc.direction_input = mb86s70_gpio_direction_input;
178 gchip->gc.request = mb86s70_gpio_request;
179 gchip->gc.free = mb86s70_gpio_free;
180 gchip->gc.get = mb86s70_gpio_get;
181 gchip->gc.set = mb86s70_gpio_set;
182 gchip->gc.label = dev_name(&pdev->dev);
183 gchip->gc.ngpio = 32;
184 gchip->gc.owner = THIS_MODULE;
185 gchip->gc.parent = &pdev->dev;
186 gchip->gc.base = -1;
187
188 platform_set_drvdata(pdev, gchip);
189
190 ret = gpiochip_add_data(&gchip->gc, gchip);
191 if (ret) {
192 dev_err(&pdev->dev, "couldn't register gpio driver\n");
193 clk_disable_unprepare(gchip->clk);
194 }
195
196 return ret;
197}
198
199static int mb86s70_gpio_remove(struct platform_device *pdev)
200{
201 struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev);
202
203 gpiochip_remove(&gchip->gc);
204 clk_disable_unprepare(gchip->clk);
205
206 return 0;
207}
208
209static const struct of_device_id mb86s70_gpio_dt_ids[] = {
210 { .compatible = "fujitsu,mb86s70-gpio" },
211 { /* sentinel */ }
212};
213MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids);
214
215static struct platform_driver mb86s70_gpio_driver = {
216 .driver = {
217 .name = "mb86s70-gpio",
218 .of_match_table = mb86s70_gpio_dt_ids,
219 },
220 .probe = mb86s70_gpio_probe,
221 .remove = mb86s70_gpio_remove,
222};
223
224static int __init mb86s70_gpio_init(void)
225{
226 return platform_driver_register(&mb86s70_gpio_driver);
227}
228module_init(mb86s70_gpio_init);
229
230MODULE_DESCRIPTION("MB86S7x GPIO Driver");
231MODULE_ALIAS("platform:mb86s70-gpio");
232MODULE_LICENSE("GPL");
1/*
2 * linux/drivers/gpio/gpio-mb86s7x.c
3 *
4 * Copyright (C) 2015 Fujitsu Semiconductor Limited
5 * Copyright (C) 2015 Linaro Ltd.
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/io.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/errno.h>
22#include <linux/ioport.h>
23#include <linux/of_device.h>
24#include <linux/gpio/driver.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27#include <linux/slab.h>
28
29/*
30 * Only first 8bits of a register correspond to each pin,
31 * so there are 4 registers for 32 pins.
32 */
33#define PDR(x) (0x0 + x / 8 * 4)
34#define DDR(x) (0x10 + x / 8 * 4)
35#define PFR(x) (0x20 + x / 8 * 4)
36
37#define OFFSET(x) BIT((x) % 8)
38
39struct mb86s70_gpio_chip {
40 struct gpio_chip gc;
41 void __iomem *base;
42 struct clk *clk;
43 spinlock_t lock;
44};
45
46static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)
47{
48 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
49 unsigned long flags;
50 u32 val;
51
52 spin_lock_irqsave(&gchip->lock, flags);
53
54 val = readl(gchip->base + PFR(gpio));
55 if (!(val & OFFSET(gpio))) {
56 spin_unlock_irqrestore(&gchip->lock, flags);
57 return -EINVAL;
58 }
59
60 val &= ~OFFSET(gpio);
61 writel(val, gchip->base + PFR(gpio));
62
63 spin_unlock_irqrestore(&gchip->lock, flags);
64
65 return 0;
66}
67
68static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio)
69{
70 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
71 unsigned long flags;
72 u32 val;
73
74 spin_lock_irqsave(&gchip->lock, flags);
75
76 val = readl(gchip->base + PFR(gpio));
77 val |= OFFSET(gpio);
78 writel(val, gchip->base + PFR(gpio));
79
80 spin_unlock_irqrestore(&gchip->lock, flags);
81}
82
83static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
84{
85 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
86 unsigned long flags;
87 unsigned char val;
88
89 spin_lock_irqsave(&gchip->lock, flags);
90
91 val = readl(gchip->base + DDR(gpio));
92 val &= ~OFFSET(gpio);
93 writel(val, gchip->base + DDR(gpio));
94
95 spin_unlock_irqrestore(&gchip->lock, flags);
96
97 return 0;
98}
99
100static int mb86s70_gpio_direction_output(struct gpio_chip *gc,
101 unsigned gpio, int value)
102{
103 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
104 unsigned long flags;
105 unsigned char val;
106
107 spin_lock_irqsave(&gchip->lock, flags);
108
109 val = readl(gchip->base + PDR(gpio));
110 if (value)
111 val |= OFFSET(gpio);
112 else
113 val &= ~OFFSET(gpio);
114 writel(val, gchip->base + PDR(gpio));
115
116 val = readl(gchip->base + DDR(gpio));
117 val |= OFFSET(gpio);
118 writel(val, gchip->base + DDR(gpio));
119
120 spin_unlock_irqrestore(&gchip->lock, flags);
121
122 return 0;
123}
124
125static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio)
126{
127 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
128
129 return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio));
130}
131
132static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value)
133{
134 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
135 unsigned long flags;
136 unsigned char val;
137
138 spin_lock_irqsave(&gchip->lock, flags);
139
140 val = readl(gchip->base + PDR(gpio));
141 if (value)
142 val |= OFFSET(gpio);
143 else
144 val &= ~OFFSET(gpio);
145 writel(val, gchip->base + PDR(gpio));
146
147 spin_unlock_irqrestore(&gchip->lock, flags);
148}
149
150static int mb86s70_gpio_probe(struct platform_device *pdev)
151{
152 struct mb86s70_gpio_chip *gchip;
153 struct resource *res;
154 int ret;
155
156 gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL);
157 if (gchip == NULL)
158 return -ENOMEM;
159
160 platform_set_drvdata(pdev, gchip);
161
162 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
163 gchip->base = devm_ioremap_resource(&pdev->dev, res);
164 if (IS_ERR(gchip->base))
165 return PTR_ERR(gchip->base);
166
167 gchip->clk = devm_clk_get(&pdev->dev, NULL);
168 if (IS_ERR(gchip->clk))
169 return PTR_ERR(gchip->clk);
170
171 clk_prepare_enable(gchip->clk);
172
173 spin_lock_init(&gchip->lock);
174
175 gchip->gc.direction_output = mb86s70_gpio_direction_output;
176 gchip->gc.direction_input = mb86s70_gpio_direction_input;
177 gchip->gc.request = mb86s70_gpio_request;
178 gchip->gc.free = mb86s70_gpio_free;
179 gchip->gc.get = mb86s70_gpio_get;
180 gchip->gc.set = mb86s70_gpio_set;
181 gchip->gc.label = dev_name(&pdev->dev);
182 gchip->gc.ngpio = 32;
183 gchip->gc.owner = THIS_MODULE;
184 gchip->gc.parent = &pdev->dev;
185 gchip->gc.base = -1;
186
187 ret = gpiochip_add_data(&gchip->gc, gchip);
188 if (ret) {
189 dev_err(&pdev->dev, "couldn't register gpio driver\n");
190 clk_disable_unprepare(gchip->clk);
191 }
192
193 return ret;
194}
195
196static int mb86s70_gpio_remove(struct platform_device *pdev)
197{
198 struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev);
199
200 gpiochip_remove(&gchip->gc);
201 clk_disable_unprepare(gchip->clk);
202
203 return 0;
204}
205
206static const struct of_device_id mb86s70_gpio_dt_ids[] = {
207 { .compatible = "fujitsu,mb86s70-gpio" },
208 { /* sentinel */ }
209};
210
211static struct platform_driver mb86s70_gpio_driver = {
212 .driver = {
213 .name = "mb86s70-gpio",
214 .of_match_table = mb86s70_gpio_dt_ids,
215 },
216 .probe = mb86s70_gpio_probe,
217 .remove = mb86s70_gpio_remove,
218};
219
220builtin_platform_driver(mb86s70_gpio_driver);