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1/*
2 * Copyright (C) 2013 Altera Corporation
3 * Based on gpio-mpc8xxx.c
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/io.h>
20#include <linux/of_gpio.h>
21#include <linux/platform_device.h>
22
23#define ALTERA_GPIO_MAX_NGPIO 32
24#define ALTERA_GPIO_DATA 0x0
25#define ALTERA_GPIO_DIR 0x4
26#define ALTERA_GPIO_IRQ_MASK 0x8
27#define ALTERA_GPIO_EDGE_CAP 0xc
28
29/**
30* struct altera_gpio_chip
31* @mmchip : memory mapped chip structure.
32* @gpio_lock : synchronization lock so that new irq/set/get requests
33 will be blocked until the current one completes.
34* @interrupt_trigger : specifies the hardware configured IRQ trigger type
35 (rising, falling, both, high)
36* @mapped_irq : kernel mapped irq number.
37*/
38struct altera_gpio_chip {
39 struct of_mm_gpio_chip mmchip;
40 spinlock_t gpio_lock;
41 int interrupt_trigger;
42 int mapped_irq;
43};
44
45static void altera_gpio_irq_unmask(struct irq_data *d)
46{
47 struct altera_gpio_chip *altera_gc;
48 struct of_mm_gpio_chip *mm_gc;
49 unsigned long flags;
50 u32 intmask;
51
52 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
53 mm_gc = &altera_gc->mmchip;
54
55 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
56 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
57 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
58 intmask |= BIT(irqd_to_hwirq(d));
59 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
60 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
61}
62
63static void altera_gpio_irq_mask(struct irq_data *d)
64{
65 struct altera_gpio_chip *altera_gc;
66 struct of_mm_gpio_chip *mm_gc;
67 unsigned long flags;
68 u32 intmask;
69
70 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
71 mm_gc = &altera_gc->mmchip;
72
73 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
74 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
75 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
76 intmask &= ~BIT(irqd_to_hwirq(d));
77 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
78 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
79}
80
81/**
82 * This controller's IRQ type is synthesized in hardware, so this function
83 * just checks if the requested set_type matches the synthesized IRQ type
84 */
85static int altera_gpio_irq_set_type(struct irq_data *d,
86 unsigned int type)
87{
88 struct altera_gpio_chip *altera_gc;
89
90 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
91
92 if (type == IRQ_TYPE_NONE)
93 return 0;
94 if (type == IRQ_TYPE_LEVEL_HIGH &&
95 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
96 return 0;
97 if (type == IRQ_TYPE_EDGE_RISING &&
98 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_RISING)
99 return 0;
100 if (type == IRQ_TYPE_EDGE_FALLING &&
101 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_FALLING)
102 return 0;
103 if (type == IRQ_TYPE_EDGE_BOTH &&
104 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_BOTH)
105 return 0;
106
107 return -EINVAL;
108}
109
110static unsigned int altera_gpio_irq_startup(struct irq_data *d)
111{
112 altera_gpio_irq_unmask(d);
113
114 return 0;
115}
116
117static struct irq_chip altera_irq_chip = {
118 .name = "altera-gpio",
119 .irq_mask = altera_gpio_irq_mask,
120 .irq_unmask = altera_gpio_irq_unmask,
121 .irq_set_type = altera_gpio_irq_set_type,
122 .irq_startup = altera_gpio_irq_startup,
123 .irq_shutdown = altera_gpio_irq_mask,
124};
125
126static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
127{
128 struct of_mm_gpio_chip *mm_gc;
129
130 mm_gc = to_of_mm_gpio_chip(gc);
131
132 return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
133}
134
135static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
136{
137 struct of_mm_gpio_chip *mm_gc;
138 struct altera_gpio_chip *chip;
139 unsigned long flags;
140 unsigned int data_reg;
141
142 mm_gc = to_of_mm_gpio_chip(gc);
143 chip = gpiochip_get_data(gc);
144
145 spin_lock_irqsave(&chip->gpio_lock, flags);
146 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
147 if (value)
148 data_reg |= BIT(offset);
149 else
150 data_reg &= ~BIT(offset);
151 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
152 spin_unlock_irqrestore(&chip->gpio_lock, flags);
153}
154
155static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
156{
157 struct of_mm_gpio_chip *mm_gc;
158 struct altera_gpio_chip *chip;
159 unsigned long flags;
160 unsigned int gpio_ddr;
161
162 mm_gc = to_of_mm_gpio_chip(gc);
163 chip = gpiochip_get_data(gc);
164
165 spin_lock_irqsave(&chip->gpio_lock, flags);
166 /* Set pin as input, assumes software controlled IP */
167 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
168 gpio_ddr &= ~BIT(offset);
169 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
170 spin_unlock_irqrestore(&chip->gpio_lock, flags);
171
172 return 0;
173}
174
175static int altera_gpio_direction_output(struct gpio_chip *gc,
176 unsigned offset, int value)
177{
178 struct of_mm_gpio_chip *mm_gc;
179 struct altera_gpio_chip *chip;
180 unsigned long flags;
181 unsigned int data_reg, gpio_ddr;
182
183 mm_gc = to_of_mm_gpio_chip(gc);
184 chip = gpiochip_get_data(gc);
185
186 spin_lock_irqsave(&chip->gpio_lock, flags);
187 /* Sets the GPIO value */
188 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
189 if (value)
190 data_reg |= BIT(offset);
191 else
192 data_reg &= ~BIT(offset);
193 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
194
195 /* Set pin as output, assumes software controlled IP */
196 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
197 gpio_ddr |= BIT(offset);
198 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
199 spin_unlock_irqrestore(&chip->gpio_lock, flags);
200
201 return 0;
202}
203
204static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
205{
206 struct altera_gpio_chip *altera_gc;
207 struct irq_chip *chip;
208 struct of_mm_gpio_chip *mm_gc;
209 struct irq_domain *irqdomain;
210 unsigned long status;
211 int i;
212
213 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
214 chip = irq_desc_get_chip(desc);
215 mm_gc = &altera_gc->mmchip;
216 irqdomain = altera_gc->mmchip.gc.irqdomain;
217
218 chained_irq_enter(chip, desc);
219
220 while ((status =
221 (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
222 readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
223 writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
224 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
225 generic_handle_irq(irq_find_mapping(irqdomain, i));
226 }
227 }
228
229 chained_irq_exit(chip, desc);
230}
231
232
233static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
234{
235 struct altera_gpio_chip *altera_gc;
236 struct irq_chip *chip;
237 struct of_mm_gpio_chip *mm_gc;
238 struct irq_domain *irqdomain;
239 unsigned long status;
240 int i;
241
242 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
243 chip = irq_desc_get_chip(desc);
244 mm_gc = &altera_gc->mmchip;
245 irqdomain = altera_gc->mmchip.gc.irqdomain;
246
247 chained_irq_enter(chip, desc);
248
249 status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
250 status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
251
252 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
253 generic_handle_irq(irq_find_mapping(irqdomain, i));
254 }
255 chained_irq_exit(chip, desc);
256}
257
258static int altera_gpio_probe(struct platform_device *pdev)
259{
260 struct device_node *node = pdev->dev.of_node;
261 int reg, ret;
262 struct altera_gpio_chip *altera_gc;
263
264 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
265 if (!altera_gc)
266 return -ENOMEM;
267
268 spin_lock_init(&altera_gc->gpio_lock);
269
270 if (of_property_read_u32(node, "altr,ngpio", ®))
271 /* By default assume maximum ngpio */
272 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
273 else
274 altera_gc->mmchip.gc.ngpio = reg;
275
276 if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
277 dev_warn(&pdev->dev,
278 "ngpio is greater than %d, defaulting to %d\n",
279 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
280 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
281 }
282
283 altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
284 altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
285 altera_gc->mmchip.gc.get = altera_gpio_get;
286 altera_gc->mmchip.gc.set = altera_gpio_set;
287 altera_gc->mmchip.gc.owner = THIS_MODULE;
288 altera_gc->mmchip.gc.parent = &pdev->dev;
289
290 ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
291 if (ret) {
292 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
293 return ret;
294 }
295
296 platform_set_drvdata(pdev, altera_gc);
297
298 altera_gc->mapped_irq = platform_get_irq(pdev, 0);
299
300 if (altera_gc->mapped_irq < 0)
301 goto skip_irq;
302
303 if (of_property_read_u32(node, "altr,interrupt-type", ®)) {
304 ret = -EINVAL;
305 dev_err(&pdev->dev,
306 "altr,interrupt-type value not set in device tree\n");
307 goto teardown;
308 }
309 altera_gc->interrupt_trigger = reg;
310
311 ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0,
312 handle_simple_irq, IRQ_TYPE_NONE);
313
314 if (ret) {
315 dev_err(&pdev->dev, "could not add irqchip\n");
316 goto teardown;
317 }
318
319 gpiochip_set_chained_irqchip(&altera_gc->mmchip.gc,
320 &altera_irq_chip,
321 altera_gc->mapped_irq,
322 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH ?
323 altera_gpio_irq_leveL_high_handler :
324 altera_gpio_irq_edge_handler);
325
326skip_irq:
327 return 0;
328teardown:
329 of_mm_gpiochip_remove(&altera_gc->mmchip);
330 pr_err("%s: registration failed with status %d\n",
331 node->full_name, ret);
332
333 return ret;
334}
335
336static int altera_gpio_remove(struct platform_device *pdev)
337{
338 struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
339
340 of_mm_gpiochip_remove(&altera_gc->mmchip);
341
342 return 0;
343}
344
345static const struct of_device_id altera_gpio_of_match[] = {
346 { .compatible = "altr,pio-1.0", },
347 {},
348};
349MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
350
351static struct platform_driver altera_gpio_driver = {
352 .driver = {
353 .name = "altera_gpio",
354 .of_match_table = of_match_ptr(altera_gpio_of_match),
355 },
356 .probe = altera_gpio_probe,
357 .remove = altera_gpio_remove,
358};
359
360static int __init altera_gpio_init(void)
361{
362 return platform_driver_register(&altera_gpio_driver);
363}
364subsys_initcall(altera_gpio_init);
365
366static void __exit altera_gpio_exit(void)
367{
368 platform_driver_unregister(&altera_gpio_driver);
369}
370module_exit(altera_gpio_exit);
371
372MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
373MODULE_DESCRIPTION("Altera GPIO driver");
374MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2013 Altera Corporation
3 * Based on gpio-mpc8xxx.c
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/of_gpio.h>
22#include <linux/platform_device.h>
23
24#define ALTERA_GPIO_MAX_NGPIO 32
25#define ALTERA_GPIO_DATA 0x0
26#define ALTERA_GPIO_DIR 0x4
27#define ALTERA_GPIO_IRQ_MASK 0x8
28#define ALTERA_GPIO_EDGE_CAP 0xc
29
30/**
31* struct altera_gpio_chip
32* @mmchip : memory mapped chip structure.
33* @gpio_lock : synchronization lock so that new irq/set/get requests
34 will be blocked until the current one completes.
35* @interrupt_trigger : specifies the hardware configured IRQ trigger type
36 (rising, falling, both, high)
37* @mapped_irq : kernel mapped irq number.
38*/
39struct altera_gpio_chip {
40 struct of_mm_gpio_chip mmchip;
41 spinlock_t gpio_lock;
42 int interrupt_trigger;
43 int mapped_irq;
44};
45
46static void altera_gpio_irq_unmask(struct irq_data *d)
47{
48 struct altera_gpio_chip *altera_gc;
49 struct of_mm_gpio_chip *mm_gc;
50 unsigned long flags;
51 u32 intmask;
52
53 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
54 mm_gc = &altera_gc->mmchip;
55
56 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
57 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
58 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
59 intmask |= BIT(irqd_to_hwirq(d));
60 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
61 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
62}
63
64static void altera_gpio_irq_mask(struct irq_data *d)
65{
66 struct altera_gpio_chip *altera_gc;
67 struct of_mm_gpio_chip *mm_gc;
68 unsigned long flags;
69 u32 intmask;
70
71 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
72 mm_gc = &altera_gc->mmchip;
73
74 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
75 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
76 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
77 intmask &= ~BIT(irqd_to_hwirq(d));
78 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
79 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
80}
81
82/**
83 * This controller's IRQ type is synthesized in hardware, so this function
84 * just checks if the requested set_type matches the synthesized IRQ type
85 */
86static int altera_gpio_irq_set_type(struct irq_data *d,
87 unsigned int type)
88{
89 struct altera_gpio_chip *altera_gc;
90
91 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
92
93 if (type == IRQ_TYPE_NONE)
94 return 0;
95 if (type == IRQ_TYPE_LEVEL_HIGH &&
96 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
97 return 0;
98 if (type == IRQ_TYPE_EDGE_RISING &&
99 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_RISING)
100 return 0;
101 if (type == IRQ_TYPE_EDGE_FALLING &&
102 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_FALLING)
103 return 0;
104 if (type == IRQ_TYPE_EDGE_BOTH &&
105 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_BOTH)
106 return 0;
107
108 return -EINVAL;
109}
110
111static unsigned int altera_gpio_irq_startup(struct irq_data *d)
112{
113 altera_gpio_irq_unmask(d);
114
115 return 0;
116}
117
118static struct irq_chip altera_irq_chip = {
119 .name = "altera-gpio",
120 .irq_mask = altera_gpio_irq_mask,
121 .irq_unmask = altera_gpio_irq_unmask,
122 .irq_set_type = altera_gpio_irq_set_type,
123 .irq_startup = altera_gpio_irq_startup,
124 .irq_shutdown = altera_gpio_irq_mask,
125};
126
127static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
128{
129 struct of_mm_gpio_chip *mm_gc;
130
131 mm_gc = to_of_mm_gpio_chip(gc);
132
133 return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
134}
135
136static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
137{
138 struct of_mm_gpio_chip *mm_gc;
139 struct altera_gpio_chip *chip;
140 unsigned long flags;
141 unsigned int data_reg;
142
143 mm_gc = to_of_mm_gpio_chip(gc);
144 chip = gpiochip_get_data(gc);
145
146 spin_lock_irqsave(&chip->gpio_lock, flags);
147 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
148 if (value)
149 data_reg |= BIT(offset);
150 else
151 data_reg &= ~BIT(offset);
152 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
153 spin_unlock_irqrestore(&chip->gpio_lock, flags);
154}
155
156static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
157{
158 struct of_mm_gpio_chip *mm_gc;
159 struct altera_gpio_chip *chip;
160 unsigned long flags;
161 unsigned int gpio_ddr;
162
163 mm_gc = to_of_mm_gpio_chip(gc);
164 chip = gpiochip_get_data(gc);
165
166 spin_lock_irqsave(&chip->gpio_lock, flags);
167 /* Set pin as input, assumes software controlled IP */
168 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
169 gpio_ddr &= ~BIT(offset);
170 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
171 spin_unlock_irqrestore(&chip->gpio_lock, flags);
172
173 return 0;
174}
175
176static int altera_gpio_direction_output(struct gpio_chip *gc,
177 unsigned offset, int value)
178{
179 struct of_mm_gpio_chip *mm_gc;
180 struct altera_gpio_chip *chip;
181 unsigned long flags;
182 unsigned int data_reg, gpio_ddr;
183
184 mm_gc = to_of_mm_gpio_chip(gc);
185 chip = gpiochip_get_data(gc);
186
187 spin_lock_irqsave(&chip->gpio_lock, flags);
188 /* Sets the GPIO value */
189 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
190 if (value)
191 data_reg |= BIT(offset);
192 else
193 data_reg &= ~BIT(offset);
194 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
195
196 /* Set pin as output, assumes software controlled IP */
197 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
198 gpio_ddr |= BIT(offset);
199 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
200 spin_unlock_irqrestore(&chip->gpio_lock, flags);
201
202 return 0;
203}
204
205static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
206{
207 struct altera_gpio_chip *altera_gc;
208 struct irq_chip *chip;
209 struct of_mm_gpio_chip *mm_gc;
210 struct irq_domain *irqdomain;
211 unsigned long status;
212 int i;
213
214 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
215 chip = irq_desc_get_chip(desc);
216 mm_gc = &altera_gc->mmchip;
217 irqdomain = altera_gc->mmchip.gc.irqdomain;
218
219 chained_irq_enter(chip, desc);
220
221 while ((status =
222 (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
223 readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
224 writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
225 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
226 generic_handle_irq(irq_find_mapping(irqdomain, i));
227 }
228 }
229
230 chained_irq_exit(chip, desc);
231}
232
233
234static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
235{
236 struct altera_gpio_chip *altera_gc;
237 struct irq_chip *chip;
238 struct of_mm_gpio_chip *mm_gc;
239 struct irq_domain *irqdomain;
240 unsigned long status;
241 int i;
242
243 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
244 chip = irq_desc_get_chip(desc);
245 mm_gc = &altera_gc->mmchip;
246 irqdomain = altera_gc->mmchip.gc.irqdomain;
247
248 chained_irq_enter(chip, desc);
249
250 status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
251 status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
252
253 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
254 generic_handle_irq(irq_find_mapping(irqdomain, i));
255 }
256 chained_irq_exit(chip, desc);
257}
258
259static int altera_gpio_probe(struct platform_device *pdev)
260{
261 struct device_node *node = pdev->dev.of_node;
262 int reg, ret;
263 struct altera_gpio_chip *altera_gc;
264
265 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
266 if (!altera_gc)
267 return -ENOMEM;
268
269 spin_lock_init(&altera_gc->gpio_lock);
270
271 if (of_property_read_u32(node, "altr,ngpio", ®))
272 /* By default assume maximum ngpio */
273 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
274 else
275 altera_gc->mmchip.gc.ngpio = reg;
276
277 if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
278 dev_warn(&pdev->dev,
279 "ngpio is greater than %d, defaulting to %d\n",
280 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
281 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
282 }
283
284 altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
285 altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
286 altera_gc->mmchip.gc.get = altera_gpio_get;
287 altera_gc->mmchip.gc.set = altera_gpio_set;
288 altera_gc->mmchip.gc.owner = THIS_MODULE;
289 altera_gc->mmchip.gc.parent = &pdev->dev;
290
291 ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
292 if (ret) {
293 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
294 return ret;
295 }
296
297 platform_set_drvdata(pdev, altera_gc);
298
299 altera_gc->mapped_irq = platform_get_irq(pdev, 0);
300
301 if (altera_gc->mapped_irq < 0)
302 goto skip_irq;
303
304 if (of_property_read_u32(node, "altr,interrupt-type", ®)) {
305 ret = -EINVAL;
306 dev_err(&pdev->dev,
307 "altr,interrupt-type value not set in device tree\n");
308 goto teardown;
309 }
310 altera_gc->interrupt_trigger = reg;
311
312 ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0,
313 handle_simple_irq, IRQ_TYPE_NONE);
314
315 if (ret) {
316 dev_err(&pdev->dev, "could not add irqchip\n");
317 goto teardown;
318 }
319
320 gpiochip_set_chained_irqchip(&altera_gc->mmchip.gc,
321 &altera_irq_chip,
322 altera_gc->mapped_irq,
323 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH ?
324 altera_gpio_irq_leveL_high_handler :
325 altera_gpio_irq_edge_handler);
326
327skip_irq:
328 return 0;
329teardown:
330 of_mm_gpiochip_remove(&altera_gc->mmchip);
331 pr_err("%s: registration failed with status %d\n",
332 node->full_name, ret);
333
334 return ret;
335}
336
337static int altera_gpio_remove(struct platform_device *pdev)
338{
339 struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
340
341 of_mm_gpiochip_remove(&altera_gc->mmchip);
342
343 return 0;
344}
345
346static const struct of_device_id altera_gpio_of_match[] = {
347 { .compatible = "altr,pio-1.0", },
348 {},
349};
350MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
351
352static struct platform_driver altera_gpio_driver = {
353 .driver = {
354 .name = "altera_gpio",
355 .of_match_table = of_match_ptr(altera_gpio_of_match),
356 },
357 .probe = altera_gpio_probe,
358 .remove = altera_gpio_remove,
359};
360
361static int __init altera_gpio_init(void)
362{
363 return platform_driver_register(&altera_gpio_driver);
364}
365subsys_initcall(altera_gpio_init);
366
367static void __exit altera_gpio_exit(void)
368{
369 platform_driver_unregister(&altera_gpio_driver);
370}
371module_exit(altera_gpio_exit);
372
373MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
374MODULE_DESCRIPTION("Altera GPIO driver");
375MODULE_LICENSE("GPL");