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1/* tsb.S: Sparc64 TSB table handling.
2 *
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
4 */
5
6
7#include <asm/tsb.h>
8#include <asm/hypervisor.h>
9#include <asm/page.h>
10#include <asm/cpudata.h>
11#include <asm/mmu.h>
12
13 .text
14 .align 32
15
16 /* Invoked from TLB miss handler, we are in the
17 * MMU global registers and they are setup like
18 * this:
19 *
20 * %g1: TSB entry pointer
21 * %g2: available temporary
22 * %g3: FAULT_CODE_{D,I}TLB
23 * %g4: available temporary
24 * %g5: available temporary
25 * %g6: TAG TARGET
26 * %g7: available temporary, will be loaded by us with
27 * the physical address base of the linux page
28 * tables for the current address space
29 */
30tsb_miss_dtlb:
31 mov TLB_TAG_ACCESS, %g4
32 ba,pt %xcc, tsb_miss_page_table_walk
33 ldxa [%g4] ASI_DMMU, %g4
34
35tsb_miss_itlb:
36 mov TLB_TAG_ACCESS, %g4
37 ba,pt %xcc, tsb_miss_page_table_walk
38 ldxa [%g4] ASI_IMMU, %g4
39
40 /* At this point we have:
41 * %g1 -- PAGE_SIZE TSB entry address
42 * %g3 -- FAULT_CODE_{D,I}TLB
43 * %g4 -- missing virtual address
44 * %g6 -- TAG TARGET (vaddr >> 22)
45 */
46tsb_miss_page_table_walk:
47 TRAP_LOAD_TRAP_BLOCK(%g7, %g5)
48
49 /* Before committing to a full page table walk,
50 * check the huge page TSB.
51 */
52#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
53
54661: ldx [%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
55 nop
56 .section .sun4v_2insn_patch, "ax"
57 .word 661b
58 mov SCRATCHPAD_UTSBREG2, %g5
59 ldxa [%g5] ASI_SCRATCHPAD, %g5
60 .previous
61
62 cmp %g5, -1
63 be,pt %xcc, 80f
64 nop
65
66 /* We need an aligned pair of registers containing 2 values
67 * which can be easily rematerialized. %g6 and %g7 foot the
68 * bill just nicely. We'll save %g6 away into %g2 for the
69 * huge page TSB TAG comparison.
70 *
71 * Perform a huge page TSB lookup.
72 */
73 mov %g6, %g2
74 and %g5, 0x7, %g6
75 mov 512, %g7
76 andn %g5, 0x7, %g5
77 sllx %g7, %g6, %g7
78 srlx %g4, REAL_HPAGE_SHIFT, %g6
79 sub %g7, 1, %g7
80 and %g6, %g7, %g6
81 sllx %g6, 4, %g6
82 add %g5, %g6, %g5
83
84 TSB_LOAD_QUAD(%g5, %g6)
85 cmp %g6, %g2
86 be,a,pt %xcc, tsb_tlb_reload
87 mov %g7, %g5
88
89 /* No match, remember the huge page TSB entry address,
90 * and restore %g6 and %g7.
91 */
92 TRAP_LOAD_TRAP_BLOCK(%g7, %g6)
93 srlx %g4, 22, %g6
9480: stx %g5, [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP]
95
96#endif
97
98 ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7
99
100 /* At this point we have:
101 * %g1 -- TSB entry address
102 * %g3 -- FAULT_CODE_{D,I}TLB
103 * %g4 -- missing virtual address
104 * %g6 -- TAG TARGET (vaddr >> 22)
105 * %g7 -- page table physical address
106 *
107 * We know that both the base PAGE_SIZE TSB and the HPAGE_SIZE
108 * TSB both lack a matching entry.
109 */
110tsb_miss_page_table_walk_sun4v_fastpath:
111 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
112
113 /* Valid PTE is now in %g5. */
114
115#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
116661: sethi %uhi(_PAGE_SZALL_4U), %g7
117 sllx %g7, 32, %g7
118 .section .sun4v_2insn_patch, "ax"
119 .word 661b
120 mov _PAGE_SZALL_4V, %g7
121 nop
122 .previous
123
124 and %g5, %g7, %g2
125
126661: sethi %uhi(_PAGE_SZHUGE_4U), %g7
127 sllx %g7, 32, %g7
128 .section .sun4v_2insn_patch, "ax"
129 .word 661b
130 mov _PAGE_SZHUGE_4V, %g7
131 nop
132 .previous
133
134 cmp %g2, %g7
135 bne,pt %xcc, 60f
136 nop
137
138 /* It is a huge page, use huge page TSB entry address we
139 * calculated above. If the huge page TSB has not been
140 * allocated, setup a trap stack and call hugetlb_setup()
141 * to do so, then return from the trap to replay the TLB
142 * miss.
143 *
144 * This is necessary to handle the case of transparent huge
145 * pages where we don't really have a non-atomic context
146 * in which to allocate the hugepage TSB hash table. When
147 * the 'mm' faults in the hugepage for the first time, we
148 * thus handle it here. This also makes sure that we can
149 * allocate the TSB hash table on the correct NUMA node.
150 */
151 TRAP_LOAD_TRAP_BLOCK(%g7, %g2)
152 ldx [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP], %g1
153 cmp %g1, -1
154 bne,pt %xcc, 60f
155 nop
156
157661: rdpr %pstate, %g5
158 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
159 .section .sun4v_2insn_patch, "ax"
160 .word 661b
161 SET_GL(1)
162 nop
163 .previous
164
165 rdpr %tl, %g7
166 cmp %g7, 1
167 bne,pn %xcc, winfix_trampoline
168 mov %g3, %g4
169 ba,pt %xcc, etrap
170 rd %pc, %g7
171 call hugetlb_setup
172 add %sp, PTREGS_OFF, %o0
173 ba,pt %xcc, rtrap
174 nop
175
17660:
177#endif
178
179 /* At this point we have:
180 * %g1 -- TSB entry address
181 * %g3 -- FAULT_CODE_{D,I}TLB
182 * %g5 -- valid PTE
183 * %g6 -- TAG TARGET (vaddr >> 22)
184 */
185tsb_reload:
186 TSB_LOCK_TAG(%g1, %g2, %g7)
187 TSB_WRITE(%g1, %g5, %g6)
188
189 /* Finally, load TLB and return from trap. */
190tsb_tlb_reload:
191 cmp %g3, FAULT_CODE_DTLB
192 bne,pn %xcc, tsb_itlb_load
193 nop
194
195tsb_dtlb_load:
196
197661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
198 retry
199 .section .sun4v_2insn_patch, "ax"
200 .word 661b
201 nop
202 nop
203 .previous
204
205 /* For sun4v the ASI_DTLB_DATA_IN store and the retry
206 * instruction get nop'd out and we get here to branch
207 * to the sun4v tlb load code. The registers are setup
208 * as follows:
209 *
210 * %g4: vaddr
211 * %g5: PTE
212 * %g6: TAG
213 *
214 * The sun4v TLB load wants the PTE in %g3 so we fix that
215 * up here.
216 */
217 ba,pt %xcc, sun4v_dtlb_load
218 mov %g5, %g3
219
220tsb_itlb_load:
221 /* Executable bit must be set. */
222661: sethi %hi(_PAGE_EXEC_4U), %g4
223 andcc %g5, %g4, %g0
224 .section .sun4v_2insn_patch, "ax"
225 .word 661b
226 andcc %g5, _PAGE_EXEC_4V, %g0
227 nop
228 .previous
229
230 be,pn %xcc, tsb_do_fault
231 nop
232
233661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
234 retry
235 .section .sun4v_2insn_patch, "ax"
236 .word 661b
237 nop
238 nop
239 .previous
240
241 /* For sun4v the ASI_ITLB_DATA_IN store and the retry
242 * instruction get nop'd out and we get here to branch
243 * to the sun4v tlb load code. The registers are setup
244 * as follows:
245 *
246 * %g4: vaddr
247 * %g5: PTE
248 * %g6: TAG
249 *
250 * The sun4v TLB load wants the PTE in %g3 so we fix that
251 * up here.
252 */
253 ba,pt %xcc, sun4v_itlb_load
254 mov %g5, %g3
255
256 /* No valid entry in the page tables, do full fault
257 * processing.
258 */
259
260 .globl tsb_do_fault
261tsb_do_fault:
262 cmp %g3, FAULT_CODE_DTLB
263
264661: rdpr %pstate, %g5
265 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
266 .section .sun4v_2insn_patch, "ax"
267 .word 661b
268 SET_GL(1)
269 ldxa [%g0] ASI_SCRATCHPAD, %g4
270 .previous
271
272 bne,pn %xcc, tsb_do_itlb_fault
273 nop
274
275tsb_do_dtlb_fault:
276 rdpr %tl, %g3
277 cmp %g3, 1
278
279661: mov TLB_TAG_ACCESS, %g4
280 ldxa [%g4] ASI_DMMU, %g5
281 .section .sun4v_2insn_patch, "ax"
282 .word 661b
283 ldx [%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
284 nop
285 .previous
286
287 be,pt %xcc, sparc64_realfault_common
288 mov FAULT_CODE_DTLB, %g4
289 ba,pt %xcc, winfix_trampoline
290 nop
291
292tsb_do_itlb_fault:
293 rdpr %tpc, %g5
294 ba,pt %xcc, sparc64_realfault_common
295 mov FAULT_CODE_ITLB, %g4
296
297 .globl sparc64_realfault_common
298sparc64_realfault_common:
299 /* fault code in %g4, fault address in %g5, etrap will
300 * preserve these two values in %l4 and %l5 respectively
301 */
302 ba,pt %xcc, etrap ! Save trap state
3031: rd %pc, %g7 ! ...
304 stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
305 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
306 call do_sparc64_fault ! Call fault handler
307 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
308 ba,pt %xcc, rtrap ! Restore cpu state
309 nop ! Delay slot (fill me)
310
311winfix_trampoline:
312 rdpr %tpc, %g3 ! Prepare winfixup TNPC
313 or %g3, 0x7c, %g3 ! Compute branch offset
314 wrpr %g3, %tnpc ! Write it into TNPC
315 done ! Trap return
316
317 /* Insert an entry into the TSB.
318 *
319 * %o0: TSB entry pointer (virt or phys address)
320 * %o1: tag
321 * %o2: pte
322 */
323 .align 32
324 .globl __tsb_insert
325__tsb_insert:
326 rdpr %pstate, %o5
327 wrpr %o5, PSTATE_IE, %pstate
328 TSB_LOCK_TAG(%o0, %g2, %g3)
329 TSB_WRITE(%o0, %o2, %o1)
330 wrpr %o5, %pstate
331 retl
332 nop
333 .size __tsb_insert, .-__tsb_insert
334
335 /* Flush the given TSB entry if it has the matching
336 * tag.
337 *
338 * %o0: TSB entry pointer (virt or phys address)
339 * %o1: tag
340 */
341 .align 32
342 .globl tsb_flush
343 .type tsb_flush,#function
344tsb_flush:
345 sethi %hi(TSB_TAG_LOCK_HIGH), %g2
3461: TSB_LOAD_TAG(%o0, %g1)
347 srlx %g1, 32, %o3
348 andcc %o3, %g2, %g0
349 bne,pn %icc, 1b
350 nop
351 cmp %g1, %o1
352 mov 1, %o3
353 bne,pt %xcc, 2f
354 sllx %o3, TSB_TAG_INVALID_BIT, %o3
355 TSB_CAS_TAG(%o0, %g1, %o3)
356 cmp %g1, %o3
357 bne,pn %xcc, 1b
358 nop
3592: retl
360 nop
361 .size tsb_flush, .-tsb_flush
362
363 /* Reload MMU related context switch state at
364 * schedule() time.
365 *
366 * %o0: page table physical address
367 * %o1: TSB base config pointer
368 * %o2: TSB huge config pointer, or NULL if none
369 * %o3: Hypervisor TSB descriptor physical address
370 *
371 * We have to run this whole thing with interrupts
372 * disabled so that the current cpu doesn't change
373 * due to preemption.
374 */
375 .align 32
376 .globl __tsb_context_switch
377 .type __tsb_context_switch,#function
378__tsb_context_switch:
379 rdpr %pstate, %g1
380 wrpr %g1, PSTATE_IE, %pstate
381
382 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
383
384 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
385
386 ldx [%o1 + TSB_CONFIG_REG_VAL], %o0
387 brz,pt %o2, 1f
388 mov -1, %g3
389
390 ldx [%o2 + TSB_CONFIG_REG_VAL], %g3
391
3921: stx %g3, [%g2 + TRAP_PER_CPU_TSB_HUGE]
393
394 sethi %hi(tlb_type), %g2
395 lduw [%g2 + %lo(tlb_type)], %g2
396 cmp %g2, 3
397 bne,pt %icc, 50f
398 nop
399
400 /* Hypervisor TSB switch. */
401 mov SCRATCHPAD_UTSBREG1, %o5
402 stxa %o0, [%o5] ASI_SCRATCHPAD
403 mov SCRATCHPAD_UTSBREG2, %o5
404 stxa %g3, [%o5] ASI_SCRATCHPAD
405
406 mov 2, %o0
407 cmp %g3, -1
408 move %xcc, 1, %o0
409
410 mov HV_FAST_MMU_TSB_CTXNON0, %o5
411 mov %o3, %o1
412 ta HV_FAST_TRAP
413
414 /* Finish up. */
415 ba,pt %xcc, 9f
416 nop
417
418 /* SUN4U TSB switch. */
41950: mov TSB_REG, %o5
420 stxa %o0, [%o5] ASI_DMMU
421 membar #Sync
422 stxa %o0, [%o5] ASI_IMMU
423 membar #Sync
424
4252: ldx [%o1 + TSB_CONFIG_MAP_VADDR], %o4
426 brz %o4, 9f
427 ldx [%o1 + TSB_CONFIG_MAP_PTE], %o5
428
429 sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
430 mov TLB_TAG_ACCESS, %g3
431 lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
432 stxa %o4, [%g3] ASI_DMMU
433 membar #Sync
434 sllx %g2, 3, %g2
435 stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
436 membar #Sync
437
438 brz,pt %o2, 9f
439 nop
440
441 ldx [%o2 + TSB_CONFIG_MAP_VADDR], %o4
442 ldx [%o2 + TSB_CONFIG_MAP_PTE], %o5
443 mov TLB_TAG_ACCESS, %g3
444 stxa %o4, [%g3] ASI_DMMU
445 membar #Sync
446 sub %g2, (1 << 3), %g2
447 stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
448 membar #Sync
449
4509:
451 wrpr %g1, %pstate
452
453 retl
454 nop
455 .size __tsb_context_switch, .-__tsb_context_switch
456
457#define TSB_PASS_BITS ((1 << TSB_TAG_LOCK_BIT) | \
458 (1 << TSB_TAG_INVALID_BIT))
459
460 .align 32
461 .globl copy_tsb
462 .type copy_tsb,#function
463copy_tsb: /* %o0=old_tsb_base, %o1=old_tsb_size
464 * %o2=new_tsb_base, %o3=new_tsb_size
465 */
466 sethi %uhi(TSB_PASS_BITS), %g7
467 srlx %o3, 4, %o3
468 add %o0, %o1, %g1 /* end of old tsb */
469 sllx %g7, 32, %g7
470 sub %o3, 1, %o3 /* %o3 == new tsb hash mask */
471
472661: prefetcha [%o0] ASI_N, #one_read
473 .section .tsb_phys_patch, "ax"
474 .word 661b
475 prefetcha [%o0] ASI_PHYS_USE_EC, #one_read
476 .previous
477
47890: andcc %o0, (64 - 1), %g0
479 bne 1f
480 add %o0, 64, %o5
481
482661: prefetcha [%o5] ASI_N, #one_read
483 .section .tsb_phys_patch, "ax"
484 .word 661b
485 prefetcha [%o5] ASI_PHYS_USE_EC, #one_read
486 .previous
487
4881: TSB_LOAD_QUAD(%o0, %g2) /* %g2/%g3 == TSB entry */
489 andcc %g2, %g7, %g0 /* LOCK or INVALID set? */
490 bne,pn %xcc, 80f /* Skip it */
491 sllx %g2, 22, %o4 /* TAG --> VADDR */
492
493 /* This can definitely be computed faster... */
494 srlx %o0, 4, %o5 /* Build index */
495 and %o5, 511, %o5 /* Mask index */
496 sllx %o5, PAGE_SHIFT, %o5 /* Put into vaddr position */
497 or %o4, %o5, %o4 /* Full VADDR. */
498 srlx %o4, PAGE_SHIFT, %o4 /* Shift down to create index */
499 and %o4, %o3, %o4 /* Mask with new_tsb_nents-1 */
500 sllx %o4, 4, %o4 /* Shift back up into tsb ent offset */
501 TSB_STORE(%o2 + %o4, %g2) /* Store TAG */
502 add %o4, 0x8, %o4 /* Advance to TTE */
503 TSB_STORE(%o2 + %o4, %g3) /* Store TTE */
504
50580: add %o0, 16, %o0
506 cmp %o0, %g1
507 bne,pt %xcc, 90b
508 nop
509
510 retl
511 nop
512 .size copy_tsb, .-copy_tsb
513
514 /* Set the invalid bit in all TSB entries. */
515 .align 32
516 .globl tsb_init
517 .type tsb_init,#function
518tsb_init: /* %o0 = TSB vaddr, %o1 = size in bytes */
519 prefetch [%o0 + 0x000], #n_writes
520 mov 1, %g1
521 prefetch [%o0 + 0x040], #n_writes
522 sllx %g1, TSB_TAG_INVALID_BIT, %g1
523 prefetch [%o0 + 0x080], #n_writes
5241: prefetch [%o0 + 0x0c0], #n_writes
525 stx %g1, [%o0 + 0x00]
526 stx %g1, [%o0 + 0x10]
527 stx %g1, [%o0 + 0x20]
528 stx %g1, [%o0 + 0x30]
529 prefetch [%o0 + 0x100], #n_writes
530 stx %g1, [%o0 + 0x40]
531 stx %g1, [%o0 + 0x50]
532 stx %g1, [%o0 + 0x60]
533 stx %g1, [%o0 + 0x70]
534 prefetch [%o0 + 0x140], #n_writes
535 stx %g1, [%o0 + 0x80]
536 stx %g1, [%o0 + 0x90]
537 stx %g1, [%o0 + 0xa0]
538 stx %g1, [%o0 + 0xb0]
539 prefetch [%o0 + 0x180], #n_writes
540 stx %g1, [%o0 + 0xc0]
541 stx %g1, [%o0 + 0xd0]
542 stx %g1, [%o0 + 0xe0]
543 stx %g1, [%o0 + 0xf0]
544 subcc %o1, 0x100, %o1
545 bne,pt %xcc, 1b
546 add %o0, 0x100, %o0
547 retl
548 nop
549 nop
550 nop
551 .size tsb_init, .-tsb_init
552
553 .globl NGtsb_init
554 .type NGtsb_init,#function
555NGtsb_init:
556 rd %asi, %g2
557 mov 1, %g1
558 wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
559 sllx %g1, TSB_TAG_INVALID_BIT, %g1
5601: stxa %g1, [%o0 + 0x00] %asi
561 stxa %g1, [%o0 + 0x10] %asi
562 stxa %g1, [%o0 + 0x20] %asi
563 stxa %g1, [%o0 + 0x30] %asi
564 stxa %g1, [%o0 + 0x40] %asi
565 stxa %g1, [%o0 + 0x50] %asi
566 stxa %g1, [%o0 + 0x60] %asi
567 stxa %g1, [%o0 + 0x70] %asi
568 stxa %g1, [%o0 + 0x80] %asi
569 stxa %g1, [%o0 + 0x90] %asi
570 stxa %g1, [%o0 + 0xa0] %asi
571 stxa %g1, [%o0 + 0xb0] %asi
572 stxa %g1, [%o0 + 0xc0] %asi
573 stxa %g1, [%o0 + 0xd0] %asi
574 stxa %g1, [%o0 + 0xe0] %asi
575 stxa %g1, [%o0 + 0xf0] %asi
576 subcc %o1, 0x100, %o1
577 bne,pt %xcc, 1b
578 add %o0, 0x100, %o0
579 membar #Sync
580 retl
581 wr %g2, 0x0, %asi
582 .size NGtsb_init, .-NGtsb_init
1/* tsb.S: Sparc64 TSB table handling.
2 *
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
4 */
5
6
7#include <asm/tsb.h>
8#include <asm/hypervisor.h>
9#include <asm/page.h>
10#include <asm/cpudata.h>
11#include <asm/mmu.h>
12
13 .text
14 .align 32
15
16 /* Invoked from TLB miss handler, we are in the
17 * MMU global registers and they are setup like
18 * this:
19 *
20 * %g1: TSB entry pointer
21 * %g2: available temporary
22 * %g3: FAULT_CODE_{D,I}TLB
23 * %g4: available temporary
24 * %g5: available temporary
25 * %g6: TAG TARGET
26 * %g7: available temporary, will be loaded by us with
27 * the physical address base of the linux page
28 * tables for the current address space
29 */
30tsb_miss_dtlb:
31 mov TLB_TAG_ACCESS, %g4
32 ldxa [%g4] ASI_DMMU, %g4
33 srlx %g4, PAGE_SHIFT, %g4
34 ba,pt %xcc, tsb_miss_page_table_walk
35 sllx %g4, PAGE_SHIFT, %g4
36
37tsb_miss_itlb:
38 mov TLB_TAG_ACCESS, %g4
39 ldxa [%g4] ASI_IMMU, %g4
40 srlx %g4, PAGE_SHIFT, %g4
41 ba,pt %xcc, tsb_miss_page_table_walk
42 sllx %g4, PAGE_SHIFT, %g4
43
44 /* At this point we have:
45 * %g1 -- PAGE_SIZE TSB entry address
46 * %g3 -- FAULT_CODE_{D,I}TLB
47 * %g4 -- missing virtual address
48 * %g6 -- TAG TARGET (vaddr >> 22)
49 */
50tsb_miss_page_table_walk:
51 TRAP_LOAD_TRAP_BLOCK(%g7, %g5)
52
53 /* Before committing to a full page table walk,
54 * check the huge page TSB.
55 */
56#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
57
58661: ldx [%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
59 nop
60 .section .sun4v_2insn_patch, "ax"
61 .word 661b
62 mov SCRATCHPAD_UTSBREG2, %g5
63 ldxa [%g5] ASI_SCRATCHPAD, %g5
64 .previous
65
66 cmp %g5, -1
67 be,pt %xcc, 80f
68 nop
69
70 /* We need an aligned pair of registers containing 2 values
71 * which can be easily rematerialized. %g6 and %g7 foot the
72 * bill just nicely. We'll save %g6 away into %g2 for the
73 * huge page TSB TAG comparison.
74 *
75 * Perform a huge page TSB lookup.
76 */
77 mov %g6, %g2
78 and %g5, 0x7, %g6
79 mov 512, %g7
80 andn %g5, 0x7, %g5
81 sllx %g7, %g6, %g7
82 srlx %g4, REAL_HPAGE_SHIFT, %g6
83 sub %g7, 1, %g7
84 and %g6, %g7, %g6
85 sllx %g6, 4, %g6
86 add %g5, %g6, %g5
87
88 TSB_LOAD_QUAD(%g5, %g6)
89 cmp %g6, %g2
90 be,a,pt %xcc, tsb_tlb_reload
91 mov %g7, %g5
92
93 /* No match, remember the huge page TSB entry address,
94 * and restore %g6 and %g7.
95 */
96 TRAP_LOAD_TRAP_BLOCK(%g7, %g6)
97 srlx %g4, 22, %g6
9880: stx %g5, [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP]
99
100#endif
101
102 ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7
103
104 /* At this point we have:
105 * %g1 -- TSB entry address
106 * %g3 -- FAULT_CODE_{D,I}TLB
107 * %g4 -- missing virtual address
108 * %g6 -- TAG TARGET (vaddr >> 22)
109 * %g7 -- page table physical address
110 *
111 * We know that both the base PAGE_SIZE TSB and the HPAGE_SIZE
112 * TSB both lack a matching entry.
113 */
114tsb_miss_page_table_walk_sun4v_fastpath:
115 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
116
117 /* Valid PTE is now in %g5. */
118
119#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
120661: sethi %uhi(_PAGE_SZALL_4U), %g7
121 sllx %g7, 32, %g7
122 .section .sun4v_2insn_patch, "ax"
123 .word 661b
124 mov _PAGE_SZALL_4V, %g7
125 nop
126 .previous
127
128 and %g5, %g7, %g2
129
130661: sethi %uhi(_PAGE_SZHUGE_4U), %g7
131 sllx %g7, 32, %g7
132 .section .sun4v_2insn_patch, "ax"
133 .word 661b
134 mov _PAGE_SZHUGE_4V, %g7
135 nop
136 .previous
137
138 cmp %g2, %g7
139 bne,pt %xcc, 60f
140 nop
141
142 /* It is a huge page, use huge page TSB entry address we
143 * calculated above. If the huge page TSB has not been
144 * allocated, setup a trap stack and call hugetlb_setup()
145 * to do so, then return from the trap to replay the TLB
146 * miss.
147 *
148 * This is necessary to handle the case of transparent huge
149 * pages where we don't really have a non-atomic context
150 * in which to allocate the hugepage TSB hash table. When
151 * the 'mm' faults in the hugepage for the first time, we
152 * thus handle it here. This also makes sure that we can
153 * allocate the TSB hash table on the correct NUMA node.
154 */
155 TRAP_LOAD_TRAP_BLOCK(%g7, %g2)
156 ldx [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP], %g1
157 cmp %g1, -1
158 bne,pt %xcc, 60f
159 nop
160
161661: rdpr %pstate, %g5
162 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
163 .section .sun4v_2insn_patch, "ax"
164 .word 661b
165 SET_GL(1)
166 nop
167 .previous
168
169 rdpr %tl, %g7
170 cmp %g7, 1
171 bne,pn %xcc, winfix_trampoline
172 mov %g3, %g4
173 ba,pt %xcc, etrap
174 rd %pc, %g7
175 call hugetlb_setup
176 add %sp, PTREGS_OFF, %o0
177 ba,pt %xcc, rtrap
178 nop
179
18060:
181#endif
182
183 /* At this point we have:
184 * %g1 -- TSB entry address
185 * %g3 -- FAULT_CODE_{D,I}TLB
186 * %g5 -- valid PTE
187 * %g6 -- TAG TARGET (vaddr >> 22)
188 */
189tsb_reload:
190 TSB_LOCK_TAG(%g1, %g2, %g7)
191 TSB_WRITE(%g1, %g5, %g6)
192
193 /* Finally, load TLB and return from trap. */
194tsb_tlb_reload:
195 cmp %g3, FAULT_CODE_DTLB
196 bne,pn %xcc, tsb_itlb_load
197 nop
198
199tsb_dtlb_load:
200
201661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
202 retry
203 .section .sun4v_2insn_patch, "ax"
204 .word 661b
205 nop
206 nop
207 .previous
208
209 /* For sun4v the ASI_DTLB_DATA_IN store and the retry
210 * instruction get nop'd out and we get here to branch
211 * to the sun4v tlb load code. The registers are setup
212 * as follows:
213 *
214 * %g4: vaddr
215 * %g5: PTE
216 * %g6: TAG
217 *
218 * The sun4v TLB load wants the PTE in %g3 so we fix that
219 * up here.
220 */
221 ba,pt %xcc, sun4v_dtlb_load
222 mov %g5, %g3
223
224tsb_itlb_load:
225 /* Executable bit must be set. */
226661: sethi %hi(_PAGE_EXEC_4U), %g4
227 andcc %g5, %g4, %g0
228 .section .sun4v_2insn_patch, "ax"
229 .word 661b
230 andcc %g5, _PAGE_EXEC_4V, %g0
231 nop
232 .previous
233
234 be,pn %xcc, tsb_do_fault
235 nop
236
237661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
238 retry
239 .section .sun4v_2insn_patch, "ax"
240 .word 661b
241 nop
242 nop
243 .previous
244
245 /* For sun4v the ASI_ITLB_DATA_IN store and the retry
246 * instruction get nop'd out and we get here to branch
247 * to the sun4v tlb load code. The registers are setup
248 * as follows:
249 *
250 * %g4: vaddr
251 * %g5: PTE
252 * %g6: TAG
253 *
254 * The sun4v TLB load wants the PTE in %g3 so we fix that
255 * up here.
256 */
257 ba,pt %xcc, sun4v_itlb_load
258 mov %g5, %g3
259
260 /* No valid entry in the page tables, do full fault
261 * processing.
262 */
263
264 .globl tsb_do_fault
265tsb_do_fault:
266 cmp %g3, FAULT_CODE_DTLB
267
268661: rdpr %pstate, %g5
269 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
270 .section .sun4v_2insn_patch, "ax"
271 .word 661b
272 SET_GL(1)
273 ldxa [%g0] ASI_SCRATCHPAD, %g4
274 .previous
275
276 bne,pn %xcc, tsb_do_itlb_fault
277 nop
278
279tsb_do_dtlb_fault:
280 rdpr %tl, %g3
281 cmp %g3, 1
282
283661: mov TLB_TAG_ACCESS, %g4
284 ldxa [%g4] ASI_DMMU, %g5
285 .section .sun4v_2insn_patch, "ax"
286 .word 661b
287 ldx [%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
288 nop
289 .previous
290
291 /* Clear context ID bits. */
292 srlx %g5, PAGE_SHIFT, %g5
293 sllx %g5, PAGE_SHIFT, %g5
294
295 be,pt %xcc, sparc64_realfault_common
296 mov FAULT_CODE_DTLB, %g4
297 ba,pt %xcc, winfix_trampoline
298 nop
299
300tsb_do_itlb_fault:
301 rdpr %tpc, %g5
302 ba,pt %xcc, sparc64_realfault_common
303 mov FAULT_CODE_ITLB, %g4
304
305 .globl sparc64_realfault_common
306sparc64_realfault_common:
307 /* fault code in %g4, fault address in %g5, etrap will
308 * preserve these two values in %l4 and %l5 respectively
309 */
310 ba,pt %xcc, etrap ! Save trap state
3111: rd %pc, %g7 ! ...
312 stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
313 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
314 call do_sparc64_fault ! Call fault handler
315 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
316 ba,pt %xcc, rtrap ! Restore cpu state
317 nop ! Delay slot (fill me)
318
319winfix_trampoline:
320 rdpr %tpc, %g3 ! Prepare winfixup TNPC
321 or %g3, 0x7c, %g3 ! Compute branch offset
322 wrpr %g3, %tnpc ! Write it into TNPC
323 done ! Trap return
324
325 /* Insert an entry into the TSB.
326 *
327 * %o0: TSB entry pointer (virt or phys address)
328 * %o1: tag
329 * %o2: pte
330 */
331 .align 32
332 .globl __tsb_insert
333__tsb_insert:
334 rdpr %pstate, %o5
335 wrpr %o5, PSTATE_IE, %pstate
336 TSB_LOCK_TAG(%o0, %g2, %g3)
337 TSB_WRITE(%o0, %o2, %o1)
338 wrpr %o5, %pstate
339 retl
340 nop
341 .size __tsb_insert, .-__tsb_insert
342
343 /* Flush the given TSB entry if it has the matching
344 * tag.
345 *
346 * %o0: TSB entry pointer (virt or phys address)
347 * %o1: tag
348 */
349 .align 32
350 .globl tsb_flush
351 .type tsb_flush,#function
352tsb_flush:
353 sethi %hi(TSB_TAG_LOCK_HIGH), %g2
3541: TSB_LOAD_TAG(%o0, %g1)
355 srlx %g1, 32, %o3
356 andcc %o3, %g2, %g0
357 bne,pn %icc, 1b
358 nop
359 cmp %g1, %o1
360 mov 1, %o3
361 bne,pt %xcc, 2f
362 sllx %o3, TSB_TAG_INVALID_BIT, %o3
363 TSB_CAS_TAG(%o0, %g1, %o3)
364 cmp %g1, %o3
365 bne,pn %xcc, 1b
366 nop
3672: retl
368 nop
369 .size tsb_flush, .-tsb_flush
370
371 /* Reload MMU related context switch state at
372 * schedule() time.
373 *
374 * %o0: page table physical address
375 * %o1: TSB base config pointer
376 * %o2: TSB huge config pointer, or NULL if none
377 * %o3: Hypervisor TSB descriptor physical address
378 *
379 * We have to run this whole thing with interrupts
380 * disabled so that the current cpu doesn't change
381 * due to preemption.
382 */
383 .align 32
384 .globl __tsb_context_switch
385 .type __tsb_context_switch,#function
386__tsb_context_switch:
387 rdpr %pstate, %g1
388 wrpr %g1, PSTATE_IE, %pstate
389
390 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
391
392 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
393
394 ldx [%o1 + TSB_CONFIG_REG_VAL], %o0
395 brz,pt %o2, 1f
396 mov -1, %g3
397
398 ldx [%o2 + TSB_CONFIG_REG_VAL], %g3
399
4001: stx %g3, [%g2 + TRAP_PER_CPU_TSB_HUGE]
401
402 sethi %hi(tlb_type), %g2
403 lduw [%g2 + %lo(tlb_type)], %g2
404 cmp %g2, 3
405 bne,pt %icc, 50f
406 nop
407
408 /* Hypervisor TSB switch. */
409 mov SCRATCHPAD_UTSBREG1, %o5
410 stxa %o0, [%o5] ASI_SCRATCHPAD
411 mov SCRATCHPAD_UTSBREG2, %o5
412 stxa %g3, [%o5] ASI_SCRATCHPAD
413
414 mov 2, %o0
415 cmp %g3, -1
416 move %xcc, 1, %o0
417
418 mov HV_FAST_MMU_TSB_CTXNON0, %o5
419 mov %o3, %o1
420 ta HV_FAST_TRAP
421
422 /* Finish up. */
423 ba,pt %xcc, 9f
424 nop
425
426 /* SUN4U TSB switch. */
42750: mov TSB_REG, %o5
428 stxa %o0, [%o5] ASI_DMMU
429 membar #Sync
430 stxa %o0, [%o5] ASI_IMMU
431 membar #Sync
432
4332: ldx [%o1 + TSB_CONFIG_MAP_VADDR], %o4
434 brz %o4, 9f
435 ldx [%o1 + TSB_CONFIG_MAP_PTE], %o5
436
437 sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
438 mov TLB_TAG_ACCESS, %g3
439 lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
440 stxa %o4, [%g3] ASI_DMMU
441 membar #Sync
442 sllx %g2, 3, %g2
443 stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
444 membar #Sync
445
446 brz,pt %o2, 9f
447 nop
448
449 ldx [%o2 + TSB_CONFIG_MAP_VADDR], %o4
450 ldx [%o2 + TSB_CONFIG_MAP_PTE], %o5
451 mov TLB_TAG_ACCESS, %g3
452 stxa %o4, [%g3] ASI_DMMU
453 membar #Sync
454 sub %g2, (1 << 3), %g2
455 stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
456 membar #Sync
457
4589:
459 wrpr %g1, %pstate
460
461 retl
462 nop
463 .size __tsb_context_switch, .-__tsb_context_switch
464
465#define TSB_PASS_BITS ((1 << TSB_TAG_LOCK_BIT) | \
466 (1 << TSB_TAG_INVALID_BIT))
467
468 .align 32
469 .globl copy_tsb
470 .type copy_tsb,#function
471copy_tsb: /* %o0=old_tsb_base, %o1=old_tsb_size
472 * %o2=new_tsb_base, %o3=new_tsb_size
473 */
474 sethi %uhi(TSB_PASS_BITS), %g7
475 srlx %o3, 4, %o3
476 add %o0, %o1, %g1 /* end of old tsb */
477 sllx %g7, 32, %g7
478 sub %o3, 1, %o3 /* %o3 == new tsb hash mask */
479
480661: prefetcha [%o0] ASI_N, #one_read
481 .section .tsb_phys_patch, "ax"
482 .word 661b
483 prefetcha [%o0] ASI_PHYS_USE_EC, #one_read
484 .previous
485
48690: andcc %o0, (64 - 1), %g0
487 bne 1f
488 add %o0, 64, %o5
489
490661: prefetcha [%o5] ASI_N, #one_read
491 .section .tsb_phys_patch, "ax"
492 .word 661b
493 prefetcha [%o5] ASI_PHYS_USE_EC, #one_read
494 .previous
495
4961: TSB_LOAD_QUAD(%o0, %g2) /* %g2/%g3 == TSB entry */
497 andcc %g2, %g7, %g0 /* LOCK or INVALID set? */
498 bne,pn %xcc, 80f /* Skip it */
499 sllx %g2, 22, %o4 /* TAG --> VADDR */
500
501 /* This can definitely be computed faster... */
502 srlx %o0, 4, %o5 /* Build index */
503 and %o5, 511, %o5 /* Mask index */
504 sllx %o5, PAGE_SHIFT, %o5 /* Put into vaddr position */
505 or %o4, %o5, %o4 /* Full VADDR. */
506 srlx %o4, PAGE_SHIFT, %o4 /* Shift down to create index */
507 and %o4, %o3, %o4 /* Mask with new_tsb_nents-1 */
508 sllx %o4, 4, %o4 /* Shift back up into tsb ent offset */
509 TSB_STORE(%o2 + %o4, %g2) /* Store TAG */
510 add %o4, 0x8, %o4 /* Advance to TTE */
511 TSB_STORE(%o2 + %o4, %g3) /* Store TTE */
512
51380: add %o0, 16, %o0
514 cmp %o0, %g1
515 bne,pt %xcc, 90b
516 nop
517
518 retl
519 nop
520 .size copy_tsb, .-copy_tsb
521
522 /* Set the invalid bit in all TSB entries. */
523 .align 32
524 .globl tsb_init
525 .type tsb_init,#function
526tsb_init: /* %o0 = TSB vaddr, %o1 = size in bytes */
527 prefetch [%o0 + 0x000], #n_writes
528 mov 1, %g1
529 prefetch [%o0 + 0x040], #n_writes
530 sllx %g1, TSB_TAG_INVALID_BIT, %g1
531 prefetch [%o0 + 0x080], #n_writes
5321: prefetch [%o0 + 0x0c0], #n_writes
533 stx %g1, [%o0 + 0x00]
534 stx %g1, [%o0 + 0x10]
535 stx %g1, [%o0 + 0x20]
536 stx %g1, [%o0 + 0x30]
537 prefetch [%o0 + 0x100], #n_writes
538 stx %g1, [%o0 + 0x40]
539 stx %g1, [%o0 + 0x50]
540 stx %g1, [%o0 + 0x60]
541 stx %g1, [%o0 + 0x70]
542 prefetch [%o0 + 0x140], #n_writes
543 stx %g1, [%o0 + 0x80]
544 stx %g1, [%o0 + 0x90]
545 stx %g1, [%o0 + 0xa0]
546 stx %g1, [%o0 + 0xb0]
547 prefetch [%o0 + 0x180], #n_writes
548 stx %g1, [%o0 + 0xc0]
549 stx %g1, [%o0 + 0xd0]
550 stx %g1, [%o0 + 0xe0]
551 stx %g1, [%o0 + 0xf0]
552 subcc %o1, 0x100, %o1
553 bne,pt %xcc, 1b
554 add %o0, 0x100, %o0
555 retl
556 nop
557 nop
558 nop
559 .size tsb_init, .-tsb_init
560
561 .globl NGtsb_init
562 .type NGtsb_init,#function
563NGtsb_init:
564 rd %asi, %g2
565 mov 1, %g1
566 wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
567 sllx %g1, TSB_TAG_INVALID_BIT, %g1
5681: stxa %g1, [%o0 + 0x00] %asi
569 stxa %g1, [%o0 + 0x10] %asi
570 stxa %g1, [%o0 + 0x20] %asi
571 stxa %g1, [%o0 + 0x30] %asi
572 stxa %g1, [%o0 + 0x40] %asi
573 stxa %g1, [%o0 + 0x50] %asi
574 stxa %g1, [%o0 + 0x60] %asi
575 stxa %g1, [%o0 + 0x70] %asi
576 stxa %g1, [%o0 + 0x80] %asi
577 stxa %g1, [%o0 + 0x90] %asi
578 stxa %g1, [%o0 + 0xa0] %asi
579 stxa %g1, [%o0 + 0xb0] %asi
580 stxa %g1, [%o0 + 0xc0] %asi
581 stxa %g1, [%o0 + 0xd0] %asi
582 stxa %g1, [%o0 + 0xe0] %asi
583 stxa %g1, [%o0 + 0xf0] %asi
584 subcc %o1, 0x100, %o1
585 bne,pt %xcc, 1b
586 add %o0, 0x100, %o0
587 membar #Sync
588 retl
589 wr %g2, 0x0, %asi
590 .size NGtsb_init, .-NGtsb_init