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1/*
2 * Count register synchronisation.
3 *
4 * All CPUs will have their count registers synchronised to the CPU0 next time
5 * value. This can cause a small timewarp for CPU0. All other CPU's should
6 * not have done anything significant (but they may have had interrupts
7 * enabled briefly - prom_smp_finish() should not be responsible for enabling
8 * interrupts...)
9 */
10
11#include <linux/kernel.h>
12#include <linux/irqflags.h>
13#include <linux/cpumask.h>
14
15#include <asm/r4k-timer.h>
16#include <linux/atomic.h>
17#include <asm/barrier.h>
18#include <asm/mipsregs.h>
19
20static unsigned int initcount = 0;
21static atomic_t count_count_start = ATOMIC_INIT(0);
22static atomic_t count_count_stop = ATOMIC_INIT(0);
23
24#define COUNTON 100
25#define NR_LOOPS 3
26
27void synchronise_count_master(int cpu)
28{
29 int i;
30 unsigned long flags;
31
32 printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);
33
34 local_irq_save(flags);
35
36 /*
37 * We loop a few times to get a primed instruction cache,
38 * then the last pass is more or less synchronised and
39 * the master and slaves each set their cycle counters to a known
40 * value all at once. This reduces the chance of having random offsets
41 * between the processors, and guarantees that the maximum
42 * delay between the cycle counters is never bigger than
43 * the latency of information-passing (cachelines) between
44 * two CPUs.
45 */
46
47 for (i = 0; i < NR_LOOPS; i++) {
48 /* slaves loop on '!= 2' */
49 while (atomic_read(&count_count_start) != 1)
50 mb();
51 atomic_set(&count_count_stop, 0);
52 smp_wmb();
53
54 /* Let the slave writes its count register */
55 atomic_inc(&count_count_start);
56
57 /* Count will be initialised to current timer */
58 if (i == 1)
59 initcount = read_c0_count();
60
61 /*
62 * Everyone initialises count in the last loop:
63 */
64 if (i == NR_LOOPS-1)
65 write_c0_count(initcount);
66
67 /*
68 * Wait for slave to leave the synchronization point:
69 */
70 while (atomic_read(&count_count_stop) != 1)
71 mb();
72 atomic_set(&count_count_start, 0);
73 smp_wmb();
74 atomic_inc(&count_count_stop);
75 }
76 /* Arrange for an interrupt in a short while */
77 write_c0_compare(read_c0_count() + COUNTON);
78
79 local_irq_restore(flags);
80
81 /*
82 * i386 code reported the skew here, but the
83 * count registers were almost certainly out of sync
84 * so no point in alarming people
85 */
86 printk("done.\n");
87}
88
89void synchronise_count_slave(int cpu)
90{
91 int i;
92
93 /*
94 * Not every cpu is online at the time this gets called,
95 * so we first wait for the master to say everyone is ready
96 */
97
98 for (i = 0; i < NR_LOOPS; i++) {
99 atomic_inc(&count_count_start);
100 while (atomic_read(&count_count_start) != 2)
101 mb();
102
103 /*
104 * Everyone initialises count in the last loop:
105 */
106 if (i == NR_LOOPS-1)
107 write_c0_count(initcount);
108
109 atomic_inc(&count_count_stop);
110 while (atomic_read(&count_count_stop) != 2)
111 mb();
112 }
113 /* Arrange for an interrupt in a short while */
114 write_c0_compare(read_c0_count() + COUNTON);
115}
116#undef NR_LOOPS
1/*
2 * Count register synchronisation.
3 *
4 * All CPUs will have their count registers synchronised to the CPU0 next time
5 * value. This can cause a small timewarp for CPU0. All other CPU's should
6 * not have done anything significant (but they may have had interrupts
7 * enabled briefly - prom_smp_finish() should not be responsible for enabling
8 * interrupts...)
9 */
10
11#include <linux/kernel.h>
12#include <linux/irqflags.h>
13#include <linux/cpumask.h>
14
15#include <asm/r4k-timer.h>
16#include <linux/atomic.h>
17#include <asm/barrier.h>
18#include <asm/mipsregs.h>
19
20static unsigned int initcount = 0;
21static atomic_t count_count_start = ATOMIC_INIT(0);
22static atomic_t count_count_stop = ATOMIC_INIT(0);
23
24#define COUNTON 100
25#define NR_LOOPS 3
26
27void synchronise_count_master(int cpu)
28{
29 int i;
30 unsigned long flags;
31
32 printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);
33
34 local_irq_save(flags);
35
36 /*
37 * We loop a few times to get a primed instruction cache,
38 * then the last pass is more or less synchronised and
39 * the master and slaves each set their cycle counters to a known
40 * value all at once. This reduces the chance of having random offsets
41 * between the processors, and guarantees that the maximum
42 * delay between the cycle counters is never bigger than
43 * the latency of information-passing (cachelines) between
44 * two CPUs.
45 */
46
47 for (i = 0; i < NR_LOOPS; i++) {
48 /* slaves loop on '!= 2' */
49 while (atomic_read(&count_count_start) != 1)
50 mb();
51 atomic_set(&count_count_stop, 0);
52 smp_wmb();
53
54 /* Let the slave writes its count register */
55 atomic_inc(&count_count_start);
56
57 /* Count will be initialised to current timer */
58 if (i == 1)
59 initcount = read_c0_count();
60
61 /*
62 * Everyone initialises count in the last loop:
63 */
64 if (i == NR_LOOPS-1)
65 write_c0_count(initcount);
66
67 /*
68 * Wait for slave to leave the synchronization point:
69 */
70 while (atomic_read(&count_count_stop) != 1)
71 mb();
72 atomic_set(&count_count_start, 0);
73 smp_wmb();
74 atomic_inc(&count_count_stop);
75 }
76 /* Arrange for an interrupt in a short while */
77 write_c0_compare(read_c0_count() + COUNTON);
78
79 local_irq_restore(flags);
80
81 /*
82 * i386 code reported the skew here, but the
83 * count registers were almost certainly out of sync
84 * so no point in alarming people
85 */
86 printk("done.\n");
87}
88
89void synchronise_count_slave(int cpu)
90{
91 int i;
92
93 /*
94 * Not every cpu is online at the time this gets called,
95 * so we first wait for the master to say everyone is ready
96 */
97
98 for (i = 0; i < NR_LOOPS; i++) {
99 atomic_inc(&count_count_start);
100 while (atomic_read(&count_count_start) != 2)
101 mb();
102
103 /*
104 * Everyone initialises count in the last loop:
105 */
106 if (i == NR_LOOPS-1)
107 write_c0_count(initcount);
108
109 atomic_inc(&count_count_stop);
110 while (atomic_read(&count_count_stop) != 2)
111 mb();
112 }
113 /* Arrange for an interrupt in a short while */
114 write_c0_compare(read_c0_count() + COUNTON);
115}
116#undef NR_LOOPS