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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_PROCESSOR_H
12#define _ASM_PROCESSOR_H
13
14#include <linux/cpumask.h>
15#include <linux/threads.h>
16
17#include <asm/cachectl.h>
18#include <asm/cpu.h>
19#include <asm/cpu-info.h>
20#include <asm/mipsregs.h>
21#include <asm/prefetch.h>
22
23/*
24 * Return current * instruction pointer ("program counter").
25 */
26#define current_text_addr() ({ __label__ _l; _l: &&_l;})
27
28/*
29 * System setup and hardware flags..
30 */
31
32extern unsigned int vced_count, vcei_count;
33
34/*
35 * MIPS does have an arch_pick_mmap_layout()
36 */
37#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
38
39#ifdef CONFIG_32BIT
40#ifdef CONFIG_KVM_GUEST
41/* User space process size is limited to 1GB in KVM Guest Mode */
42#define TASK_SIZE 0x3fff8000UL
43#else
44/*
45 * User space process size: 2GB. This is hardcoded into a few places,
46 * so don't change it unless you know what you are doing.
47 */
48#define TASK_SIZE 0x80000000UL
49#endif
50
51#define STACK_TOP_MAX TASK_SIZE
52
53#define TASK_IS_32BIT_ADDR 1
54
55#endif
56
57#ifdef CONFIG_64BIT
58/*
59 * User space process size: 1TB. This is hardcoded into a few places,
60 * so don't change it unless you know what you are doing. TASK_SIZE
61 * is limited to 1TB by the R4000 architecture; R10000 and better can
62 * support 16TB; the architectural reserve for future expansion is
63 * 8192EB ...
64 */
65#define TASK_SIZE32 0x7fff8000UL
66#define TASK_SIZE64 0x10000000000UL
67#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
68#define STACK_TOP_MAX TASK_SIZE64
69
70#define TASK_SIZE_OF(tsk) \
71 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
72
73#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
74
75#endif
76
77#define STACK_TOP (TASK_SIZE & PAGE_MASK)
78
79/*
80 * This decides where the kernel will search for a free chunk of vm
81 * space during mmap's.
82 */
83#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
84
85
86#define NUM_FPU_REGS 32
87
88#ifdef CONFIG_CPU_HAS_MSA
89# define FPU_REG_WIDTH 128
90#else
91# define FPU_REG_WIDTH 64
92#endif
93
94union fpureg {
95 __u32 val32[FPU_REG_WIDTH / 32];
96 __u64 val64[FPU_REG_WIDTH / 64];
97};
98
99#ifdef CONFIG_CPU_LITTLE_ENDIAN
100# define FPR_IDX(width, idx) (idx)
101#else
102# define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
103#endif
104
105#define BUILD_FPR_ACCESS(width) \
106static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \
107{ \
108 return fpr->val##width[FPR_IDX(width, idx)]; \
109} \
110 \
111static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \
112 u##width val) \
113{ \
114 fpr->val##width[FPR_IDX(width, idx)] = val; \
115}
116
117BUILD_FPR_ACCESS(32)
118BUILD_FPR_ACCESS(64)
119
120/*
121 * It would be nice to add some more fields for emulator statistics,
122 * the additional information is private to the FPU emulator for now.
123 * See arch/mips/include/asm/fpu_emulator.h.
124 */
125
126struct mips_fpu_struct {
127 union fpureg fpr[NUM_FPU_REGS];
128 unsigned int fcr31;
129 unsigned int msacsr;
130};
131
132#define NUM_DSP_REGS 6
133
134typedef __u32 dspreg_t;
135
136struct mips_dsp_state {
137 dspreg_t dspr[NUM_DSP_REGS];
138 unsigned int dspcontrol;
139};
140
141#define INIT_CPUMASK { \
142 {0,} \
143}
144
145struct mips3264_watch_reg_state {
146 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
147 64 bit kernel. We use unsigned long as it has the same
148 property. */
149 unsigned long watchlo[NUM_WATCH_REGS];
150 /* Only the mask and IRW bits from watchhi. */
151 u16 watchhi[NUM_WATCH_REGS];
152};
153
154union mips_watch_reg_state {
155 struct mips3264_watch_reg_state mips3264;
156};
157
158#if defined(CONFIG_CPU_CAVIUM_OCTEON)
159
160struct octeon_cop2_state {
161 /* DMFC2 rt, 0x0201 */
162 unsigned long cop2_crc_iv;
163 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
164 unsigned long cop2_crc_length;
165 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
166 unsigned long cop2_crc_poly;
167 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
168 unsigned long cop2_llm_dat[2];
169 /* DMFC2 rt, 0x0084 */
170 unsigned long cop2_3des_iv;
171 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
172 unsigned long cop2_3des_key[3];
173 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
174 unsigned long cop2_3des_result;
175 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
176 unsigned long cop2_aes_inp0;
177 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
178 unsigned long cop2_aes_iv[2];
179 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
180 * rt, 0x0107 */
181 unsigned long cop2_aes_key[4];
182 /* DMFC2 rt, 0x0110 */
183 unsigned long cop2_aes_keylen;
184 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
185 unsigned long cop2_aes_result[2];
186 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
187 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
188 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
189 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
190 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
191 unsigned long cop2_hsh_datw[15];
192 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
193 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
194 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
195 unsigned long cop2_hsh_ivw[8];
196 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
197 unsigned long cop2_gfm_mult[2];
198 /* DMFC2 rt, 0x025E - Pass2 */
199 unsigned long cop2_gfm_poly;
200 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
201 unsigned long cop2_gfm_result[2];
202 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
203 unsigned long cop2_sha3[2];
204};
205#define COP2_INIT \
206 .cp2 = {0,},
207
208struct octeon_cvmseg_state {
209 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
210 [cpu_dcache_line_size() / sizeof(unsigned long)];
211};
212
213#elif defined(CONFIG_CPU_XLP)
214struct nlm_cop2_state {
215 u64 rx[4];
216 u64 tx[4];
217 u32 tx_msg_status;
218 u32 rx_msg_status;
219};
220
221#define COP2_INIT \
222 .cp2 = {{0}, {0}, 0, 0},
223#else
224#define COP2_INIT
225#endif
226
227typedef struct {
228 unsigned long seg;
229} mm_segment_t;
230
231#ifdef CONFIG_CPU_HAS_MSA
232# define ARCH_MIN_TASKALIGN 16
233# define FPU_ALIGN __aligned(16)
234#else
235# define ARCH_MIN_TASKALIGN 8
236# define FPU_ALIGN
237#endif
238
239struct mips_abi;
240
241/*
242 * If you change thread_struct remember to change the #defines below too!
243 */
244struct thread_struct {
245 /* Saved main processor registers. */
246 unsigned long reg16;
247 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
248 unsigned long reg29, reg30, reg31;
249
250 /* Saved cp0 stuff. */
251 unsigned long cp0_status;
252
253 /* Saved fpu/fpu emulator stuff. */
254 struct mips_fpu_struct fpu FPU_ALIGN;
255#ifdef CONFIG_MIPS_MT_FPAFF
256 /* Emulated instruction count */
257 unsigned long emulated_fp;
258 /* Saved per-thread scheduler affinity mask */
259 cpumask_t user_cpus_allowed;
260#endif /* CONFIG_MIPS_MT_FPAFF */
261
262 /* Saved state of the DSP ASE, if available. */
263 struct mips_dsp_state dsp;
264
265 /* Saved watch register state, if available. */
266 union mips_watch_reg_state watch;
267
268 /* Other stuff associated with the thread. */
269 unsigned long cp0_badvaddr; /* Last user fault */
270 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
271 unsigned long error_code;
272 unsigned long trap_nr;
273#ifdef CONFIG_CPU_CAVIUM_OCTEON
274 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
275 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
276#endif
277#ifdef CONFIG_CPU_XLP
278 struct nlm_cop2_state cp2;
279#endif
280 struct mips_abi *abi;
281};
282
283#ifdef CONFIG_MIPS_MT_FPAFF
284#define FPAFF_INIT \
285 .emulated_fp = 0, \
286 .user_cpus_allowed = INIT_CPUMASK,
287#else
288#define FPAFF_INIT
289#endif /* CONFIG_MIPS_MT_FPAFF */
290
291#define INIT_THREAD { \
292 /* \
293 * Saved main processor registers \
294 */ \
295 .reg16 = 0, \
296 .reg17 = 0, \
297 .reg18 = 0, \
298 .reg19 = 0, \
299 .reg20 = 0, \
300 .reg21 = 0, \
301 .reg22 = 0, \
302 .reg23 = 0, \
303 .reg29 = 0, \
304 .reg30 = 0, \
305 .reg31 = 0, \
306 /* \
307 * Saved cp0 stuff \
308 */ \
309 .cp0_status = 0, \
310 /* \
311 * Saved FPU/FPU emulator stuff \
312 */ \
313 .fpu = { \
314 .fpr = {{{0,},},}, \
315 .fcr31 = 0, \
316 .msacsr = 0, \
317 }, \
318 /* \
319 * FPU affinity state (null if not FPAFF) \
320 */ \
321 FPAFF_INIT \
322 /* \
323 * Saved DSP stuff \
324 */ \
325 .dsp = { \
326 .dspr = {0, }, \
327 .dspcontrol = 0, \
328 }, \
329 /* \
330 * saved watch register stuff \
331 */ \
332 .watch = {{{0,},},}, \
333 /* \
334 * Other stuff associated with the process \
335 */ \
336 .cp0_badvaddr = 0, \
337 .cp0_baduaddr = 0, \
338 .error_code = 0, \
339 .trap_nr = 0, \
340 /* \
341 * Platform specific cop2 registers(null if no COP2) \
342 */ \
343 COP2_INIT \
344}
345
346struct task_struct;
347
348/* Free all resources held by a thread. */
349#define release_thread(thread) do { } while(0)
350
351extern unsigned long thread_saved_pc(struct task_struct *tsk);
352
353/*
354 * Do necessary setup to start up a newly executed thread.
355 */
356extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
357
358unsigned long get_wchan(struct task_struct *p);
359
360#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
361 THREAD_SIZE - 32 - sizeof(struct pt_regs))
362#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
363#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
364#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
365#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
366
367#define cpu_relax() barrier()
368#define cpu_relax_lowlatency() cpu_relax()
369
370/*
371 * Return_address is a replacement for __builtin_return_address(count)
372 * which on certain architectures cannot reasonably be implemented in GCC
373 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
374 * Note that __builtin_return_address(x>=1) is forbidden because GCC
375 * aborts compilation on some CPUs. It's simply not possible to unwind
376 * some CPU's stackframes.
377 *
378 * __builtin_return_address works only for non-leaf functions. We avoid the
379 * overhead of a function call by forcing the compiler to save the return
380 * address register on the stack.
381 */
382#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
383
384#ifdef CONFIG_CPU_HAS_PREFETCH
385
386#define ARCH_HAS_PREFETCH
387#define prefetch(x) __builtin_prefetch((x), 0, 1)
388
389#define ARCH_HAS_PREFETCHW
390#define prefetchw(x) __builtin_prefetch((x), 1, 1)
391
392#endif
393
394/*
395 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
396 * to the prctl syscall.
397 */
398extern int mips_get_process_fp_mode(struct task_struct *task);
399extern int mips_set_process_fp_mode(struct task_struct *task,
400 unsigned int value);
401
402#define GET_FP_MODE(task) mips_get_process_fp_mode(task)
403#define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value)
404
405#endif /* _ASM_PROCESSOR_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_PROCESSOR_H
12#define _ASM_PROCESSOR_H
13
14#include <linux/atomic.h>
15#include <linux/cpumask.h>
16#include <linux/threads.h>
17
18#include <asm/cachectl.h>
19#include <asm/cpu.h>
20#include <asm/cpu-info.h>
21#include <asm/dsemul.h>
22#include <asm/mipsregs.h>
23#include <asm/prefetch.h>
24
25/*
26 * Return current * instruction pointer ("program counter").
27 */
28#define current_text_addr() ({ __label__ _l; _l: &&_l;})
29
30/*
31 * System setup and hardware flags..
32 */
33
34extern unsigned int vced_count, vcei_count;
35
36/*
37 * MIPS does have an arch_pick_mmap_layout()
38 */
39#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
40
41#ifdef CONFIG_32BIT
42#ifdef CONFIG_KVM_GUEST
43/* User space process size is limited to 1GB in KVM Guest Mode */
44#define TASK_SIZE 0x3fff8000UL
45#else
46/*
47 * User space process size: 2GB. This is hardcoded into a few places,
48 * so don't change it unless you know what you are doing.
49 */
50#define TASK_SIZE 0x80000000UL
51#endif
52
53#define STACK_TOP_MAX TASK_SIZE
54
55#define TASK_IS_32BIT_ADDR 1
56
57#endif
58
59#ifdef CONFIG_64BIT
60/*
61 * User space process size: 1TB. This is hardcoded into a few places,
62 * so don't change it unless you know what you are doing. TASK_SIZE
63 * is limited to 1TB by the R4000 architecture; R10000 and better can
64 * support 16TB; the architectural reserve for future expansion is
65 * 8192EB ...
66 */
67#define TASK_SIZE32 0x7fff8000UL
68#ifdef CONFIG_MIPS_VA_BITS_48
69#define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
70#else
71#define TASK_SIZE64 0x10000000000UL
72#endif
73#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
74#define STACK_TOP_MAX TASK_SIZE64
75
76#define TASK_SIZE_OF(tsk) \
77 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
78
79#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
80
81#endif
82
83/*
84 * One page above the stack is used for branch delay slot "emulation".
85 * See dsemul.c for details.
86 */
87#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - PAGE_SIZE)
88
89/*
90 * This decides where the kernel will search for a free chunk of vm
91 * space during mmap's.
92 */
93#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
94
95
96#define NUM_FPU_REGS 32
97
98#ifdef CONFIG_CPU_HAS_MSA
99# define FPU_REG_WIDTH 128
100#else
101# define FPU_REG_WIDTH 64
102#endif
103
104union fpureg {
105 __u32 val32[FPU_REG_WIDTH / 32];
106 __u64 val64[FPU_REG_WIDTH / 64];
107};
108
109#ifdef CONFIG_CPU_LITTLE_ENDIAN
110# define FPR_IDX(width, idx) (idx)
111#else
112# define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
113#endif
114
115#define BUILD_FPR_ACCESS(width) \
116static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \
117{ \
118 return fpr->val##width[FPR_IDX(width, idx)]; \
119} \
120 \
121static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \
122 u##width val) \
123{ \
124 fpr->val##width[FPR_IDX(width, idx)] = val; \
125}
126
127BUILD_FPR_ACCESS(32)
128BUILD_FPR_ACCESS(64)
129
130/*
131 * It would be nice to add some more fields for emulator statistics,
132 * the additional information is private to the FPU emulator for now.
133 * See arch/mips/include/asm/fpu_emulator.h.
134 */
135
136struct mips_fpu_struct {
137 union fpureg fpr[NUM_FPU_REGS];
138 unsigned int fcr31;
139 unsigned int msacsr;
140};
141
142#define NUM_DSP_REGS 6
143
144typedef __u32 dspreg_t;
145
146struct mips_dsp_state {
147 dspreg_t dspr[NUM_DSP_REGS];
148 unsigned int dspcontrol;
149};
150
151#define INIT_CPUMASK { \
152 {0,} \
153}
154
155struct mips3264_watch_reg_state {
156 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
157 64 bit kernel. We use unsigned long as it has the same
158 property. */
159 unsigned long watchlo[NUM_WATCH_REGS];
160 /* Only the mask and IRW bits from watchhi. */
161 u16 watchhi[NUM_WATCH_REGS];
162};
163
164union mips_watch_reg_state {
165 struct mips3264_watch_reg_state mips3264;
166};
167
168#if defined(CONFIG_CPU_CAVIUM_OCTEON)
169
170struct octeon_cop2_state {
171 /* DMFC2 rt, 0x0201 */
172 unsigned long cop2_crc_iv;
173 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
174 unsigned long cop2_crc_length;
175 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
176 unsigned long cop2_crc_poly;
177 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
178 unsigned long cop2_llm_dat[2];
179 /* DMFC2 rt, 0x0084 */
180 unsigned long cop2_3des_iv;
181 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
182 unsigned long cop2_3des_key[3];
183 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
184 unsigned long cop2_3des_result;
185 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
186 unsigned long cop2_aes_inp0;
187 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
188 unsigned long cop2_aes_iv[2];
189 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
190 * rt, 0x0107 */
191 unsigned long cop2_aes_key[4];
192 /* DMFC2 rt, 0x0110 */
193 unsigned long cop2_aes_keylen;
194 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
195 unsigned long cop2_aes_result[2];
196 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
197 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
198 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
199 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
200 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
201 unsigned long cop2_hsh_datw[15];
202 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
203 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
204 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
205 unsigned long cop2_hsh_ivw[8];
206 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
207 unsigned long cop2_gfm_mult[2];
208 /* DMFC2 rt, 0x025E - Pass2 */
209 unsigned long cop2_gfm_poly;
210 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
211 unsigned long cop2_gfm_result[2];
212 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
213 unsigned long cop2_sha3[2];
214};
215#define COP2_INIT \
216 .cp2 = {0,},
217
218struct octeon_cvmseg_state {
219 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
220 [cpu_dcache_line_size() / sizeof(unsigned long)];
221};
222
223#elif defined(CONFIG_CPU_XLP)
224struct nlm_cop2_state {
225 u64 rx[4];
226 u64 tx[4];
227 u32 tx_msg_status;
228 u32 rx_msg_status;
229};
230
231#define COP2_INIT \
232 .cp2 = {{0}, {0}, 0, 0},
233#else
234#define COP2_INIT
235#endif
236
237typedef struct {
238 unsigned long seg;
239} mm_segment_t;
240
241#ifdef CONFIG_CPU_HAS_MSA
242# define ARCH_MIN_TASKALIGN 16
243# define FPU_ALIGN __aligned(16)
244#else
245# define ARCH_MIN_TASKALIGN 8
246# define FPU_ALIGN
247#endif
248
249struct mips_abi;
250
251/*
252 * If you change thread_struct remember to change the #defines below too!
253 */
254struct thread_struct {
255 /* Saved main processor registers. */
256 unsigned long reg16;
257 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
258 unsigned long reg29, reg30, reg31;
259
260 /* Saved cp0 stuff. */
261 unsigned long cp0_status;
262
263 /* Saved fpu/fpu emulator stuff. */
264 struct mips_fpu_struct fpu FPU_ALIGN;
265 /* Assigned branch delay slot 'emulation' frame */
266 atomic_t bd_emu_frame;
267 /* PC of the branch from a branch delay slot 'emulation' */
268 unsigned long bd_emu_branch_pc;
269 /* PC to continue from following a branch delay slot 'emulation' */
270 unsigned long bd_emu_cont_pc;
271#ifdef CONFIG_MIPS_MT_FPAFF
272 /* Emulated instruction count */
273 unsigned long emulated_fp;
274 /* Saved per-thread scheduler affinity mask */
275 cpumask_t user_cpus_allowed;
276#endif /* CONFIG_MIPS_MT_FPAFF */
277
278 /* Saved state of the DSP ASE, if available. */
279 struct mips_dsp_state dsp;
280
281 /* Saved watch register state, if available. */
282 union mips_watch_reg_state watch;
283
284 /* Other stuff associated with the thread. */
285 unsigned long cp0_badvaddr; /* Last user fault */
286 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
287 unsigned long error_code;
288 unsigned long trap_nr;
289#ifdef CONFIG_CPU_CAVIUM_OCTEON
290 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
291 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
292#endif
293#ifdef CONFIG_CPU_XLP
294 struct nlm_cop2_state cp2;
295#endif
296 struct mips_abi *abi;
297};
298
299#ifdef CONFIG_MIPS_MT_FPAFF
300#define FPAFF_INIT \
301 .emulated_fp = 0, \
302 .user_cpus_allowed = INIT_CPUMASK,
303#else
304#define FPAFF_INIT
305#endif /* CONFIG_MIPS_MT_FPAFF */
306
307#define INIT_THREAD { \
308 /* \
309 * Saved main processor registers \
310 */ \
311 .reg16 = 0, \
312 .reg17 = 0, \
313 .reg18 = 0, \
314 .reg19 = 0, \
315 .reg20 = 0, \
316 .reg21 = 0, \
317 .reg22 = 0, \
318 .reg23 = 0, \
319 .reg29 = 0, \
320 .reg30 = 0, \
321 .reg31 = 0, \
322 /* \
323 * Saved cp0 stuff \
324 */ \
325 .cp0_status = 0, \
326 /* \
327 * Saved FPU/FPU emulator stuff \
328 */ \
329 .fpu = { \
330 .fpr = {{{0,},},}, \
331 .fcr31 = 0, \
332 .msacsr = 0, \
333 }, \
334 /* \
335 * FPU affinity state (null if not FPAFF) \
336 */ \
337 FPAFF_INIT \
338 /* Delay slot emulation */ \
339 .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \
340 .bd_emu_branch_pc = 0, \
341 .bd_emu_cont_pc = 0, \
342 /* \
343 * Saved DSP stuff \
344 */ \
345 .dsp = { \
346 .dspr = {0, }, \
347 .dspcontrol = 0, \
348 }, \
349 /* \
350 * saved watch register stuff \
351 */ \
352 .watch = {{{0,},},}, \
353 /* \
354 * Other stuff associated with the process \
355 */ \
356 .cp0_badvaddr = 0, \
357 .cp0_baduaddr = 0, \
358 .error_code = 0, \
359 .trap_nr = 0, \
360 /* \
361 * Platform specific cop2 registers(null if no COP2) \
362 */ \
363 COP2_INIT \
364}
365
366struct task_struct;
367
368/* Free all resources held by a thread. */
369#define release_thread(thread) do { } while(0)
370
371extern unsigned long thread_saved_pc(struct task_struct *tsk);
372
373/*
374 * Do necessary setup to start up a newly executed thread.
375 */
376extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
377
378static inline void flush_thread(void)
379{
380}
381
382unsigned long get_wchan(struct task_struct *p);
383
384#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
385 THREAD_SIZE - 32 - sizeof(struct pt_regs))
386#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
387#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
388#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
389#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
390
391#define cpu_relax() barrier()
392
393/*
394 * Return_address is a replacement for __builtin_return_address(count)
395 * which on certain architectures cannot reasonably be implemented in GCC
396 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
397 * Note that __builtin_return_address(x>=1) is forbidden because GCC
398 * aborts compilation on some CPUs. It's simply not possible to unwind
399 * some CPU's stackframes.
400 *
401 * __builtin_return_address works only for non-leaf functions. We avoid the
402 * overhead of a function call by forcing the compiler to save the return
403 * address register on the stack.
404 */
405#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
406
407#ifdef CONFIG_CPU_HAS_PREFETCH
408
409#define ARCH_HAS_PREFETCH
410#define prefetch(x) __builtin_prefetch((x), 0, 1)
411
412#define ARCH_HAS_PREFETCHW
413#define prefetchw(x) __builtin_prefetch((x), 1, 1)
414
415#endif
416
417/*
418 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
419 * to the prctl syscall.
420 */
421extern int mips_get_process_fp_mode(struct task_struct *task);
422extern int mips_set_process_fp_mode(struct task_struct *task,
423 unsigned int value);
424
425#define GET_FP_MODE(task) mips_get_process_fp_mode(task)
426#define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value)
427
428#endif /* _ASM_PROCESSOR_H */