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1/*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "ssb_private.h"
12
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/ssb/ssb.h>
18#include <linux/ssb/ssb_regs.h>
19#include <linux/ssb/ssb_driver_gige.h>
20#include <linux/dma-mapping.h>
21#include <linux/pci.h>
22#include <linux/mmc/sdio_func.h>
23#include <linux/slab.h>
24
25#include <pcmcia/cistpl.h>
26#include <pcmcia/ds.h>
27
28
29MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
30MODULE_LICENSE("GPL");
31
32
33/* Temporary list of yet-to-be-attached buses */
34static LIST_HEAD(attach_queue);
35/* List if running buses */
36static LIST_HEAD(buses);
37/* Software ID counter */
38static unsigned int next_busnumber;
39/* buses_mutes locks the two buslists and the next_busnumber.
40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
41static DEFINE_MUTEX(buses_mutex);
42
43/* There are differences in the codeflow, if the bus is
44 * initialized from early boot, as various needed services
45 * are not available early. This is a mechanism to delay
46 * these initializations to after early boot has finished.
47 * It's also used to avoid mutex locking, as that's not
48 * available and needed early. */
49static bool ssb_is_early_boot = 1;
50
51static void ssb_buses_lock(void);
52static void ssb_buses_unlock(void);
53
54
55#ifdef CONFIG_SSB_PCIHOST
56struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
57{
58 struct ssb_bus *bus;
59
60 ssb_buses_lock();
61 list_for_each_entry(bus, &buses, list) {
62 if (bus->bustype == SSB_BUSTYPE_PCI &&
63 bus->host_pci == pdev)
64 goto found;
65 }
66 bus = NULL;
67found:
68 ssb_buses_unlock();
69
70 return bus;
71}
72#endif /* CONFIG_SSB_PCIHOST */
73
74#ifdef CONFIG_SSB_PCMCIAHOST
75struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
76{
77 struct ssb_bus *bus;
78
79 ssb_buses_lock();
80 list_for_each_entry(bus, &buses, list) {
81 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
82 bus->host_pcmcia == pdev)
83 goto found;
84 }
85 bus = NULL;
86found:
87 ssb_buses_unlock();
88
89 return bus;
90}
91#endif /* CONFIG_SSB_PCMCIAHOST */
92
93int ssb_for_each_bus_call(unsigned long data,
94 int (*func)(struct ssb_bus *bus, unsigned long data))
95{
96 struct ssb_bus *bus;
97 int res;
98
99 ssb_buses_lock();
100 list_for_each_entry(bus, &buses, list) {
101 res = func(bus, data);
102 if (res >= 0) {
103 ssb_buses_unlock();
104 return res;
105 }
106 }
107 ssb_buses_unlock();
108
109 return -ENODEV;
110}
111
112static struct ssb_device *ssb_device_get(struct ssb_device *dev)
113{
114 if (dev)
115 get_device(dev->dev);
116 return dev;
117}
118
119static void ssb_device_put(struct ssb_device *dev)
120{
121 if (dev)
122 put_device(dev->dev);
123}
124
125static int ssb_device_resume(struct device *dev)
126{
127 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
128 struct ssb_driver *ssb_drv;
129 int err = 0;
130
131 if (dev->driver) {
132 ssb_drv = drv_to_ssb_drv(dev->driver);
133 if (ssb_drv && ssb_drv->resume)
134 err = ssb_drv->resume(ssb_dev);
135 if (err)
136 goto out;
137 }
138out:
139 return err;
140}
141
142static int ssb_device_suspend(struct device *dev, pm_message_t state)
143{
144 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
145 struct ssb_driver *ssb_drv;
146 int err = 0;
147
148 if (dev->driver) {
149 ssb_drv = drv_to_ssb_drv(dev->driver);
150 if (ssb_drv && ssb_drv->suspend)
151 err = ssb_drv->suspend(ssb_dev, state);
152 if (err)
153 goto out;
154 }
155out:
156 return err;
157}
158
159int ssb_bus_resume(struct ssb_bus *bus)
160{
161 int err;
162
163 /* Reset HW state information in memory, so that HW is
164 * completely reinitialized. */
165 bus->mapped_device = NULL;
166#ifdef CONFIG_SSB_DRIVER_PCICORE
167 bus->pcicore.setup_done = 0;
168#endif
169
170 err = ssb_bus_powerup(bus, 0);
171 if (err)
172 return err;
173 err = ssb_pcmcia_hardware_setup(bus);
174 if (err) {
175 ssb_bus_may_powerdown(bus);
176 return err;
177 }
178 ssb_chipco_resume(&bus->chipco);
179 ssb_bus_may_powerdown(bus);
180
181 return 0;
182}
183EXPORT_SYMBOL(ssb_bus_resume);
184
185int ssb_bus_suspend(struct ssb_bus *bus)
186{
187 ssb_chipco_suspend(&bus->chipco);
188 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
189
190 return 0;
191}
192EXPORT_SYMBOL(ssb_bus_suspend);
193
194#ifdef CONFIG_SSB_SPROM
195/** ssb_devices_freeze - Freeze all devices on the bus.
196 *
197 * After freezing no device driver will be handling a device
198 * on this bus anymore. ssb_devices_thaw() must be called after
199 * a successful freeze to reactivate the devices.
200 *
201 * @bus: The bus.
202 * @ctx: Context structure. Pass this to ssb_devices_thaw().
203 */
204int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
205{
206 struct ssb_device *sdev;
207 struct ssb_driver *sdrv;
208 unsigned int i;
209
210 memset(ctx, 0, sizeof(*ctx));
211 ctx->bus = bus;
212 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
213
214 for (i = 0; i < bus->nr_devices; i++) {
215 sdev = ssb_device_get(&bus->devices[i]);
216
217 if (!sdev->dev || !sdev->dev->driver ||
218 !device_is_registered(sdev->dev)) {
219 ssb_device_put(sdev);
220 continue;
221 }
222 sdrv = drv_to_ssb_drv(sdev->dev->driver);
223 if (SSB_WARN_ON(!sdrv->remove))
224 continue;
225 sdrv->remove(sdev);
226 ctx->device_frozen[i] = 1;
227 }
228
229 return 0;
230}
231
232/** ssb_devices_thaw - Unfreeze all devices on the bus.
233 *
234 * This will re-attach the device drivers and re-init the devices.
235 *
236 * @ctx: The context structure from ssb_devices_freeze()
237 */
238int ssb_devices_thaw(struct ssb_freeze_context *ctx)
239{
240 struct ssb_bus *bus = ctx->bus;
241 struct ssb_device *sdev;
242 struct ssb_driver *sdrv;
243 unsigned int i;
244 int err, result = 0;
245
246 for (i = 0; i < bus->nr_devices; i++) {
247 if (!ctx->device_frozen[i])
248 continue;
249 sdev = &bus->devices[i];
250
251 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
252 continue;
253 sdrv = drv_to_ssb_drv(sdev->dev->driver);
254 if (SSB_WARN_ON(!sdrv || !sdrv->probe))
255 continue;
256
257 err = sdrv->probe(sdev, &sdev->id);
258 if (err) {
259 ssb_err("Failed to thaw device %s\n",
260 dev_name(sdev->dev));
261 result = err;
262 }
263 ssb_device_put(sdev);
264 }
265
266 return result;
267}
268#endif /* CONFIG_SSB_SPROM */
269
270static void ssb_device_shutdown(struct device *dev)
271{
272 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
273 struct ssb_driver *ssb_drv;
274
275 if (!dev->driver)
276 return;
277 ssb_drv = drv_to_ssb_drv(dev->driver);
278 if (ssb_drv && ssb_drv->shutdown)
279 ssb_drv->shutdown(ssb_dev);
280}
281
282static int ssb_device_remove(struct device *dev)
283{
284 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
285 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
286
287 if (ssb_drv && ssb_drv->remove)
288 ssb_drv->remove(ssb_dev);
289 ssb_device_put(ssb_dev);
290
291 return 0;
292}
293
294static int ssb_device_probe(struct device *dev)
295{
296 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
297 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
298 int err = 0;
299
300 ssb_device_get(ssb_dev);
301 if (ssb_drv && ssb_drv->probe)
302 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
303 if (err)
304 ssb_device_put(ssb_dev);
305
306 return err;
307}
308
309static int ssb_match_devid(const struct ssb_device_id *tabid,
310 const struct ssb_device_id *devid)
311{
312 if ((tabid->vendor != devid->vendor) &&
313 tabid->vendor != SSB_ANY_VENDOR)
314 return 0;
315 if ((tabid->coreid != devid->coreid) &&
316 tabid->coreid != SSB_ANY_ID)
317 return 0;
318 if ((tabid->revision != devid->revision) &&
319 tabid->revision != SSB_ANY_REV)
320 return 0;
321 return 1;
322}
323
324static int ssb_bus_match(struct device *dev, struct device_driver *drv)
325{
326 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
327 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
328 const struct ssb_device_id *id;
329
330 for (id = ssb_drv->id_table;
331 id->vendor || id->coreid || id->revision;
332 id++) {
333 if (ssb_match_devid(id, &ssb_dev->id))
334 return 1; /* found */
335 }
336
337 return 0;
338}
339
340static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
341{
342 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
343
344 if (!dev)
345 return -ENODEV;
346
347 return add_uevent_var(env,
348 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
349 ssb_dev->id.vendor, ssb_dev->id.coreid,
350 ssb_dev->id.revision);
351}
352
353#define ssb_config_attr(attrib, field, format_string) \
354static ssize_t \
355attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
356{ \
357 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
358} \
359static DEVICE_ATTR_RO(attrib);
360
361ssb_config_attr(core_num, core_index, "%u\n")
362ssb_config_attr(coreid, id.coreid, "0x%04x\n")
363ssb_config_attr(vendor, id.vendor, "0x%04x\n")
364ssb_config_attr(revision, id.revision, "%u\n")
365ssb_config_attr(irq, irq, "%u\n")
366static ssize_t
367name_show(struct device *dev, struct device_attribute *attr, char *buf)
368{
369 return sprintf(buf, "%s\n",
370 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
371}
372static DEVICE_ATTR_RO(name);
373
374static struct attribute *ssb_device_attrs[] = {
375 &dev_attr_name.attr,
376 &dev_attr_core_num.attr,
377 &dev_attr_coreid.attr,
378 &dev_attr_vendor.attr,
379 &dev_attr_revision.attr,
380 &dev_attr_irq.attr,
381 NULL,
382};
383ATTRIBUTE_GROUPS(ssb_device);
384
385static struct bus_type ssb_bustype = {
386 .name = "ssb",
387 .match = ssb_bus_match,
388 .probe = ssb_device_probe,
389 .remove = ssb_device_remove,
390 .shutdown = ssb_device_shutdown,
391 .suspend = ssb_device_suspend,
392 .resume = ssb_device_resume,
393 .uevent = ssb_device_uevent,
394 .dev_groups = ssb_device_groups,
395};
396
397static void ssb_buses_lock(void)
398{
399 /* See the comment at the ssb_is_early_boot definition */
400 if (!ssb_is_early_boot)
401 mutex_lock(&buses_mutex);
402}
403
404static void ssb_buses_unlock(void)
405{
406 /* See the comment at the ssb_is_early_boot definition */
407 if (!ssb_is_early_boot)
408 mutex_unlock(&buses_mutex);
409}
410
411static void ssb_devices_unregister(struct ssb_bus *bus)
412{
413 struct ssb_device *sdev;
414 int i;
415
416 for (i = bus->nr_devices - 1; i >= 0; i--) {
417 sdev = &(bus->devices[i]);
418 if (sdev->dev)
419 device_unregister(sdev->dev);
420 }
421
422#ifdef CONFIG_SSB_EMBEDDED
423 if (bus->bustype == SSB_BUSTYPE_SSB)
424 platform_device_unregister(bus->watchdog);
425#endif
426}
427
428void ssb_bus_unregister(struct ssb_bus *bus)
429{
430 int err;
431
432 err = ssb_gpio_unregister(bus);
433 if (err == -EBUSY)
434 ssb_dbg("Some GPIOs are still in use\n");
435 else if (err)
436 ssb_dbg("Can not unregister GPIO driver: %i\n", err);
437
438 ssb_buses_lock();
439 ssb_devices_unregister(bus);
440 list_del(&bus->list);
441 ssb_buses_unlock();
442
443 ssb_pcmcia_exit(bus);
444 ssb_pci_exit(bus);
445 ssb_iounmap(bus);
446}
447EXPORT_SYMBOL(ssb_bus_unregister);
448
449static void ssb_release_dev(struct device *dev)
450{
451 struct __ssb_dev_wrapper *devwrap;
452
453 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
454 kfree(devwrap);
455}
456
457static int ssb_devices_register(struct ssb_bus *bus)
458{
459 struct ssb_device *sdev;
460 struct device *dev;
461 struct __ssb_dev_wrapper *devwrap;
462 int i, err = 0;
463 int dev_idx = 0;
464
465 for (i = 0; i < bus->nr_devices; i++) {
466 sdev = &(bus->devices[i]);
467
468 /* We don't register SSB-system devices to the kernel,
469 * as the drivers for them are built into SSB. */
470 switch (sdev->id.coreid) {
471 case SSB_DEV_CHIPCOMMON:
472 case SSB_DEV_PCI:
473 case SSB_DEV_PCIE:
474 case SSB_DEV_PCMCIA:
475 case SSB_DEV_MIPS:
476 case SSB_DEV_MIPS_3302:
477 case SSB_DEV_EXTIF:
478 continue;
479 }
480
481 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
482 if (!devwrap) {
483 ssb_err("Could not allocate device\n");
484 err = -ENOMEM;
485 goto error;
486 }
487 dev = &devwrap->dev;
488 devwrap->sdev = sdev;
489
490 dev->release = ssb_release_dev;
491 dev->bus = &ssb_bustype;
492 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
493
494 switch (bus->bustype) {
495 case SSB_BUSTYPE_PCI:
496#ifdef CONFIG_SSB_PCIHOST
497 sdev->irq = bus->host_pci->irq;
498 dev->parent = &bus->host_pci->dev;
499 sdev->dma_dev = dev->parent;
500#endif
501 break;
502 case SSB_BUSTYPE_PCMCIA:
503#ifdef CONFIG_SSB_PCMCIAHOST
504 sdev->irq = bus->host_pcmcia->irq;
505 dev->parent = &bus->host_pcmcia->dev;
506#endif
507 break;
508 case SSB_BUSTYPE_SDIO:
509#ifdef CONFIG_SSB_SDIOHOST
510 dev->parent = &bus->host_sdio->dev;
511#endif
512 break;
513 case SSB_BUSTYPE_SSB:
514 dev->dma_mask = &dev->coherent_dma_mask;
515 sdev->dma_dev = dev;
516 break;
517 }
518
519 sdev->dev = dev;
520 err = device_register(dev);
521 if (err) {
522 ssb_err("Could not register %s\n", dev_name(dev));
523 /* Set dev to NULL to not unregister
524 * dev on error unwinding. */
525 sdev->dev = NULL;
526 kfree(devwrap);
527 goto error;
528 }
529 dev_idx++;
530 }
531
532#ifdef CONFIG_SSB_DRIVER_MIPS
533 if (bus->mipscore.pflash.present) {
534 err = platform_device_register(&ssb_pflash_dev);
535 if (err)
536 pr_err("Error registering parallel flash\n");
537 }
538#endif
539
540#ifdef CONFIG_SSB_SFLASH
541 if (bus->mipscore.sflash.present) {
542 err = platform_device_register(&ssb_sflash_dev);
543 if (err)
544 pr_err("Error registering serial flash\n");
545 }
546#endif
547
548 return 0;
549error:
550 /* Unwind the already registered devices. */
551 ssb_devices_unregister(bus);
552 return err;
553}
554
555/* Needs ssb_buses_lock() */
556static int ssb_attach_queued_buses(void)
557{
558 struct ssb_bus *bus, *n;
559 int err = 0;
560 int drop_them_all = 0;
561
562 list_for_each_entry_safe(bus, n, &attach_queue, list) {
563 if (drop_them_all) {
564 list_del(&bus->list);
565 continue;
566 }
567 /* Can't init the PCIcore in ssb_bus_register(), as that
568 * is too early in boot for embedded systems
569 * (no udelay() available). So do it here in attach stage.
570 */
571 err = ssb_bus_powerup(bus, 0);
572 if (err)
573 goto error;
574 ssb_pcicore_init(&bus->pcicore);
575 if (bus->bustype == SSB_BUSTYPE_SSB)
576 ssb_watchdog_register(bus);
577
578 err = ssb_gpio_init(bus);
579 if (err == -ENOTSUPP)
580 ssb_dbg("GPIO driver not activated\n");
581 else if (err)
582 ssb_dbg("Error registering GPIO driver: %i\n", err);
583
584 ssb_bus_may_powerdown(bus);
585
586 err = ssb_devices_register(bus);
587error:
588 if (err) {
589 drop_them_all = 1;
590 list_del(&bus->list);
591 continue;
592 }
593 list_move_tail(&bus->list, &buses);
594 }
595
596 return err;
597}
598
599static int ssb_fetch_invariants(struct ssb_bus *bus,
600 ssb_invariants_func_t get_invariants)
601{
602 struct ssb_init_invariants iv;
603 int err;
604
605 memset(&iv, 0, sizeof(iv));
606 err = get_invariants(bus, &iv);
607 if (err)
608 goto out;
609 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
610 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
611 bus->has_cardbus_slot = iv.has_cardbus_slot;
612out:
613 return err;
614}
615
616static int __maybe_unused
617ssb_bus_register(struct ssb_bus *bus,
618 ssb_invariants_func_t get_invariants,
619 unsigned long baseaddr)
620{
621 int err;
622
623 spin_lock_init(&bus->bar_lock);
624 INIT_LIST_HEAD(&bus->list);
625#ifdef CONFIG_SSB_EMBEDDED
626 spin_lock_init(&bus->gpio_lock);
627#endif
628
629 /* Powerup the bus */
630 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
631 if (err)
632 goto out;
633
634 /* Init SDIO-host device (if any), before the scan */
635 err = ssb_sdio_init(bus);
636 if (err)
637 goto err_disable_xtal;
638
639 ssb_buses_lock();
640 bus->busnumber = next_busnumber;
641 /* Scan for devices (cores) */
642 err = ssb_bus_scan(bus, baseaddr);
643 if (err)
644 goto err_sdio_exit;
645
646 /* Init PCI-host device (if any) */
647 err = ssb_pci_init(bus);
648 if (err)
649 goto err_unmap;
650 /* Init PCMCIA-host device (if any) */
651 err = ssb_pcmcia_init(bus);
652 if (err)
653 goto err_pci_exit;
654
655 /* Initialize basic system devices (if available) */
656 err = ssb_bus_powerup(bus, 0);
657 if (err)
658 goto err_pcmcia_exit;
659 ssb_chipcommon_init(&bus->chipco);
660 ssb_extif_init(&bus->extif);
661 ssb_mipscore_init(&bus->mipscore);
662 err = ssb_fetch_invariants(bus, get_invariants);
663 if (err) {
664 ssb_bus_may_powerdown(bus);
665 goto err_pcmcia_exit;
666 }
667 ssb_bus_may_powerdown(bus);
668
669 /* Queue it for attach.
670 * See the comment at the ssb_is_early_boot definition. */
671 list_add_tail(&bus->list, &attach_queue);
672 if (!ssb_is_early_boot) {
673 /* This is not early boot, so we must attach the bus now */
674 err = ssb_attach_queued_buses();
675 if (err)
676 goto err_dequeue;
677 }
678 next_busnumber++;
679 ssb_buses_unlock();
680
681out:
682 return err;
683
684err_dequeue:
685 list_del(&bus->list);
686err_pcmcia_exit:
687 ssb_pcmcia_exit(bus);
688err_pci_exit:
689 ssb_pci_exit(bus);
690err_unmap:
691 ssb_iounmap(bus);
692err_sdio_exit:
693 ssb_sdio_exit(bus);
694err_disable_xtal:
695 ssb_buses_unlock();
696 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
697 return err;
698}
699
700#ifdef CONFIG_SSB_PCIHOST
701int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci)
702{
703 int err;
704
705 bus->bustype = SSB_BUSTYPE_PCI;
706 bus->host_pci = host_pci;
707 bus->ops = &ssb_pci_ops;
708
709 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
710 if (!err) {
711 ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
712 dev_name(&host_pci->dev));
713 } else {
714 ssb_err("Failed to register PCI version of SSB with error %d\n",
715 err);
716 }
717
718 return err;
719}
720#endif /* CONFIG_SSB_PCIHOST */
721
722#ifdef CONFIG_SSB_PCMCIAHOST
723int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
724 struct pcmcia_device *pcmcia_dev,
725 unsigned long baseaddr)
726{
727 int err;
728
729 bus->bustype = SSB_BUSTYPE_PCMCIA;
730 bus->host_pcmcia = pcmcia_dev;
731 bus->ops = &ssb_pcmcia_ops;
732
733 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
734 if (!err) {
735 ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
736 pcmcia_dev->devname);
737 }
738
739 return err;
740}
741#endif /* CONFIG_SSB_PCMCIAHOST */
742
743#ifdef CONFIG_SSB_SDIOHOST
744int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
745 unsigned int quirks)
746{
747 int err;
748
749 bus->bustype = SSB_BUSTYPE_SDIO;
750 bus->host_sdio = func;
751 bus->ops = &ssb_sdio_ops;
752 bus->quirks = quirks;
753
754 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
755 if (!err) {
756 ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
757 sdio_func_id(func));
758 }
759
760 return err;
761}
762EXPORT_SYMBOL(ssb_bus_sdiobus_register);
763#endif /* CONFIG_SSB_PCMCIAHOST */
764
765#ifdef CONFIG_SSB_HOST_SOC
766int ssb_bus_host_soc_register(struct ssb_bus *bus, unsigned long baseaddr)
767{
768 int err;
769
770 bus->bustype = SSB_BUSTYPE_SSB;
771 bus->ops = &ssb_host_soc_ops;
772
773 err = ssb_bus_register(bus, ssb_host_soc_get_invariants, baseaddr);
774 if (!err) {
775 ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
776 baseaddr);
777 }
778
779 return err;
780}
781#endif
782
783int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
784{
785 drv->drv.name = drv->name;
786 drv->drv.bus = &ssb_bustype;
787 drv->drv.owner = owner;
788
789 return driver_register(&drv->drv);
790}
791EXPORT_SYMBOL(__ssb_driver_register);
792
793void ssb_driver_unregister(struct ssb_driver *drv)
794{
795 driver_unregister(&drv->drv);
796}
797EXPORT_SYMBOL(ssb_driver_unregister);
798
799void ssb_set_devtypedata(struct ssb_device *dev, void *data)
800{
801 struct ssb_bus *bus = dev->bus;
802 struct ssb_device *ent;
803 int i;
804
805 for (i = 0; i < bus->nr_devices; i++) {
806 ent = &(bus->devices[i]);
807 if (ent->id.vendor != dev->id.vendor)
808 continue;
809 if (ent->id.coreid != dev->id.coreid)
810 continue;
811
812 ent->devtypedata = data;
813 }
814}
815EXPORT_SYMBOL(ssb_set_devtypedata);
816
817static u32 clkfactor_f6_resolve(u32 v)
818{
819 /* map the magic values */
820 switch (v) {
821 case SSB_CHIPCO_CLK_F6_2:
822 return 2;
823 case SSB_CHIPCO_CLK_F6_3:
824 return 3;
825 case SSB_CHIPCO_CLK_F6_4:
826 return 4;
827 case SSB_CHIPCO_CLK_F6_5:
828 return 5;
829 case SSB_CHIPCO_CLK_F6_6:
830 return 6;
831 case SSB_CHIPCO_CLK_F6_7:
832 return 7;
833 }
834 return 0;
835}
836
837/* Calculate the speed the backplane would run at a given set of clockcontrol values */
838u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
839{
840 u32 n1, n2, clock, m1, m2, m3, mc;
841
842 n1 = (n & SSB_CHIPCO_CLK_N1);
843 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
844
845 switch (plltype) {
846 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
847 if (m & SSB_CHIPCO_CLK_T6_MMASK)
848 return SSB_CHIPCO_CLK_T6_M1;
849 return SSB_CHIPCO_CLK_T6_M0;
850 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
851 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
852 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
853 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
854 n1 = clkfactor_f6_resolve(n1);
855 n2 += SSB_CHIPCO_CLK_F5_BIAS;
856 break;
857 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
858 n1 += SSB_CHIPCO_CLK_T2_BIAS;
859 n2 += SSB_CHIPCO_CLK_T2_BIAS;
860 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
861 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
862 break;
863 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
864 return 100000000;
865 default:
866 SSB_WARN_ON(1);
867 }
868
869 switch (plltype) {
870 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
871 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
872 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
873 break;
874 default:
875 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
876 }
877 if (!clock)
878 return 0;
879
880 m1 = (m & SSB_CHIPCO_CLK_M1);
881 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
882 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
883 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
884
885 switch (plltype) {
886 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
887 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
888 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
889 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
890 m1 = clkfactor_f6_resolve(m1);
891 if ((plltype == SSB_PLLTYPE_1) ||
892 (plltype == SSB_PLLTYPE_3))
893 m2 += SSB_CHIPCO_CLK_F5_BIAS;
894 else
895 m2 = clkfactor_f6_resolve(m2);
896 m3 = clkfactor_f6_resolve(m3);
897
898 switch (mc) {
899 case SSB_CHIPCO_CLK_MC_BYPASS:
900 return clock;
901 case SSB_CHIPCO_CLK_MC_M1:
902 return (clock / m1);
903 case SSB_CHIPCO_CLK_MC_M1M2:
904 return (clock / (m1 * m2));
905 case SSB_CHIPCO_CLK_MC_M1M2M3:
906 return (clock / (m1 * m2 * m3));
907 case SSB_CHIPCO_CLK_MC_M1M3:
908 return (clock / (m1 * m3));
909 }
910 return 0;
911 case SSB_PLLTYPE_2:
912 m1 += SSB_CHIPCO_CLK_T2_BIAS;
913 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
914 m3 += SSB_CHIPCO_CLK_T2_BIAS;
915 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
916 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
917 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
918
919 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
920 clock /= m1;
921 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
922 clock /= m2;
923 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
924 clock /= m3;
925 return clock;
926 default:
927 SSB_WARN_ON(1);
928 }
929 return 0;
930}
931
932/* Get the current speed the backplane is running at */
933u32 ssb_clockspeed(struct ssb_bus *bus)
934{
935 u32 rate;
936 u32 plltype;
937 u32 clkctl_n, clkctl_m;
938
939 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
940 return ssb_pmu_get_controlclock(&bus->chipco);
941
942 if (ssb_extif_available(&bus->extif))
943 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
944 &clkctl_n, &clkctl_m);
945 else if (bus->chipco.dev)
946 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
947 &clkctl_n, &clkctl_m);
948 else
949 return 0;
950
951 if (bus->chip_id == 0x5365) {
952 rate = 100000000;
953 } else {
954 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
955 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
956 rate /= 2;
957 }
958
959 return rate;
960}
961EXPORT_SYMBOL(ssb_clockspeed);
962
963static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
964{
965 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
966
967 /* The REJECT bit seems to be different for Backplane rev 2.3 */
968 switch (rev) {
969 case SSB_IDLOW_SSBREV_22:
970 case SSB_IDLOW_SSBREV_24:
971 case SSB_IDLOW_SSBREV_26:
972 return SSB_TMSLOW_REJECT;
973 case SSB_IDLOW_SSBREV_23:
974 return SSB_TMSLOW_REJECT_23;
975 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
976 case SSB_IDLOW_SSBREV_27: /* same here */
977 return SSB_TMSLOW_REJECT; /* this is a guess */
978 case SSB_IDLOW_SSBREV:
979 break;
980 default:
981 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
982 }
983 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
984}
985
986int ssb_device_is_enabled(struct ssb_device *dev)
987{
988 u32 val;
989 u32 reject;
990
991 reject = ssb_tmslow_reject_bitmask(dev);
992 val = ssb_read32(dev, SSB_TMSLOW);
993 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
994
995 return (val == SSB_TMSLOW_CLOCK);
996}
997EXPORT_SYMBOL(ssb_device_is_enabled);
998
999static void ssb_flush_tmslow(struct ssb_device *dev)
1000{
1001 /* Make _really_ sure the device has finished the TMSLOW
1002 * register write transaction, as we risk running into
1003 * a machine check exception otherwise.
1004 * Do this by reading the register back to commit the
1005 * PCI write and delay an additional usec for the device
1006 * to react to the change. */
1007 ssb_read32(dev, SSB_TMSLOW);
1008 udelay(1);
1009}
1010
1011void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1012{
1013 u32 val;
1014
1015 ssb_device_disable(dev, core_specific_flags);
1016 ssb_write32(dev, SSB_TMSLOW,
1017 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1018 SSB_TMSLOW_FGC | core_specific_flags);
1019 ssb_flush_tmslow(dev);
1020
1021 /* Clear SERR if set. This is a hw bug workaround. */
1022 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1023 ssb_write32(dev, SSB_TMSHIGH, 0);
1024
1025 val = ssb_read32(dev, SSB_IMSTATE);
1026 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1027 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1028 ssb_write32(dev, SSB_IMSTATE, val);
1029 }
1030
1031 ssb_write32(dev, SSB_TMSLOW,
1032 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1033 core_specific_flags);
1034 ssb_flush_tmslow(dev);
1035
1036 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1037 core_specific_flags);
1038 ssb_flush_tmslow(dev);
1039}
1040EXPORT_SYMBOL(ssb_device_enable);
1041
1042/* Wait for bitmask in a register to get set or cleared.
1043 * timeout is in units of ten-microseconds */
1044static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1045 int timeout, int set)
1046{
1047 int i;
1048 u32 val;
1049
1050 for (i = 0; i < timeout; i++) {
1051 val = ssb_read32(dev, reg);
1052 if (set) {
1053 if ((val & bitmask) == bitmask)
1054 return 0;
1055 } else {
1056 if (!(val & bitmask))
1057 return 0;
1058 }
1059 udelay(10);
1060 }
1061 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1062 "register %04X to %s.\n",
1063 bitmask, reg, (set ? "set" : "clear"));
1064
1065 return -ETIMEDOUT;
1066}
1067
1068void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1069{
1070 u32 reject, val;
1071
1072 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1073 return;
1074
1075 reject = ssb_tmslow_reject_bitmask(dev);
1076
1077 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1078 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1079 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1080 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1081
1082 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1083 val = ssb_read32(dev, SSB_IMSTATE);
1084 val |= SSB_IMSTATE_REJECT;
1085 ssb_write32(dev, SSB_IMSTATE, val);
1086 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1087 0);
1088 }
1089
1090 ssb_write32(dev, SSB_TMSLOW,
1091 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1092 reject | SSB_TMSLOW_RESET |
1093 core_specific_flags);
1094 ssb_flush_tmslow(dev);
1095
1096 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1097 val = ssb_read32(dev, SSB_IMSTATE);
1098 val &= ~SSB_IMSTATE_REJECT;
1099 ssb_write32(dev, SSB_IMSTATE, val);
1100 }
1101 }
1102
1103 ssb_write32(dev, SSB_TMSLOW,
1104 reject | SSB_TMSLOW_RESET |
1105 core_specific_flags);
1106 ssb_flush_tmslow(dev);
1107}
1108EXPORT_SYMBOL(ssb_device_disable);
1109
1110/* Some chipsets need routing known for PCIe and 64-bit DMA */
1111static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1112{
1113 u16 chip_id = dev->bus->chip_id;
1114
1115 if (dev->id.coreid == SSB_DEV_80211) {
1116 return (chip_id == 0x4322 || chip_id == 43221 ||
1117 chip_id == 43231 || chip_id == 43222);
1118 }
1119
1120 return 0;
1121}
1122
1123u32 ssb_dma_translation(struct ssb_device *dev)
1124{
1125 switch (dev->bus->bustype) {
1126 case SSB_BUSTYPE_SSB:
1127 return 0;
1128 case SSB_BUSTYPE_PCI:
1129 if (pci_is_pcie(dev->bus->host_pci) &&
1130 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1131 return SSB_PCIE_DMA_H32;
1132 } else {
1133 if (ssb_dma_translation_special_bit(dev))
1134 return SSB_PCIE_DMA_H32;
1135 else
1136 return SSB_PCI_DMA;
1137 }
1138 default:
1139 __ssb_dma_not_implemented(dev);
1140 }
1141 return 0;
1142}
1143EXPORT_SYMBOL(ssb_dma_translation);
1144
1145int ssb_bus_may_powerdown(struct ssb_bus *bus)
1146{
1147 struct ssb_chipcommon *cc;
1148 int err = 0;
1149
1150 /* On buses where more than one core may be working
1151 * at a time, we must not powerdown stuff if there are
1152 * still cores that may want to run. */
1153 if (bus->bustype == SSB_BUSTYPE_SSB)
1154 goto out;
1155
1156 cc = &bus->chipco;
1157
1158 if (!cc->dev)
1159 goto out;
1160 if (cc->dev->id.revision < 5)
1161 goto out;
1162
1163 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1164 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1165 if (err)
1166 goto error;
1167out:
1168#ifdef CONFIG_SSB_DEBUG
1169 bus->powered_up = 0;
1170#endif
1171 return err;
1172error:
1173 ssb_err("Bus powerdown failed\n");
1174 goto out;
1175}
1176EXPORT_SYMBOL(ssb_bus_may_powerdown);
1177
1178int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1179{
1180 int err;
1181 enum ssb_clkmode mode;
1182
1183 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1184 if (err)
1185 goto error;
1186
1187#ifdef CONFIG_SSB_DEBUG
1188 bus->powered_up = 1;
1189#endif
1190
1191 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1192 ssb_chipco_set_clockmode(&bus->chipco, mode);
1193
1194 return 0;
1195error:
1196 ssb_err("Bus powerup failed\n");
1197 return err;
1198}
1199EXPORT_SYMBOL(ssb_bus_powerup);
1200
1201static void ssb_broadcast_value(struct ssb_device *dev,
1202 u32 address, u32 data)
1203{
1204#ifdef CONFIG_SSB_DRIVER_PCICORE
1205 /* This is used for both, PCI and ChipCommon core, so be careful. */
1206 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1207 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1208#endif
1209
1210 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1211 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1212 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1213 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1214}
1215
1216void ssb_commit_settings(struct ssb_bus *bus)
1217{
1218 struct ssb_device *dev;
1219
1220#ifdef CONFIG_SSB_DRIVER_PCICORE
1221 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1222#else
1223 dev = bus->chipco.dev;
1224#endif
1225 if (WARN_ON(!dev))
1226 return;
1227 /* This forces an update of the cached registers. */
1228 ssb_broadcast_value(dev, 0xFD8, 0);
1229}
1230EXPORT_SYMBOL(ssb_commit_settings);
1231
1232u32 ssb_admatch_base(u32 adm)
1233{
1234 u32 base = 0;
1235
1236 switch (adm & SSB_ADM_TYPE) {
1237 case SSB_ADM_TYPE0:
1238 base = (adm & SSB_ADM_BASE0);
1239 break;
1240 case SSB_ADM_TYPE1:
1241 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1242 base = (adm & SSB_ADM_BASE1);
1243 break;
1244 case SSB_ADM_TYPE2:
1245 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1246 base = (adm & SSB_ADM_BASE2);
1247 break;
1248 default:
1249 SSB_WARN_ON(1);
1250 }
1251
1252 return base;
1253}
1254EXPORT_SYMBOL(ssb_admatch_base);
1255
1256u32 ssb_admatch_size(u32 adm)
1257{
1258 u32 size = 0;
1259
1260 switch (adm & SSB_ADM_TYPE) {
1261 case SSB_ADM_TYPE0:
1262 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1263 break;
1264 case SSB_ADM_TYPE1:
1265 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1266 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1267 break;
1268 case SSB_ADM_TYPE2:
1269 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1270 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1271 break;
1272 default:
1273 SSB_WARN_ON(1);
1274 }
1275 size = (1 << (size + 1));
1276
1277 return size;
1278}
1279EXPORT_SYMBOL(ssb_admatch_size);
1280
1281static int __init ssb_modinit(void)
1282{
1283 int err;
1284
1285 /* See the comment at the ssb_is_early_boot definition */
1286 ssb_is_early_boot = 0;
1287 err = bus_register(&ssb_bustype);
1288 if (err)
1289 return err;
1290
1291 /* Maybe we already registered some buses at early boot.
1292 * Check for this and attach them
1293 */
1294 ssb_buses_lock();
1295 err = ssb_attach_queued_buses();
1296 ssb_buses_unlock();
1297 if (err) {
1298 bus_unregister(&ssb_bustype);
1299 goto out;
1300 }
1301
1302 err = b43_pci_ssb_bridge_init();
1303 if (err) {
1304 ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1305 /* don't fail SSB init because of this */
1306 err = 0;
1307 }
1308 err = ssb_host_pcmcia_init();
1309 if (err) {
1310 ssb_err("PCMCIA host initialization failed\n");
1311 /* don't fail SSB init because of this */
1312 err = 0;
1313 }
1314 err = ssb_gige_init();
1315 if (err) {
1316 ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1317 /* don't fail SSB init because of this */
1318 err = 0;
1319 }
1320out:
1321 return err;
1322}
1323/* ssb must be initialized after PCI but before the ssb drivers.
1324 * That means we must use some initcall between subsys_initcall
1325 * and device_initcall. */
1326fs_initcall(ssb_modinit);
1327
1328static void __exit ssb_modexit(void)
1329{
1330 ssb_gige_exit();
1331 ssb_host_pcmcia_exit();
1332 b43_pci_ssb_bridge_exit();
1333 bus_unregister(&ssb_bustype);
1334}
1335module_exit(ssb_modexit)
1/*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "ssb_private.h"
12
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/ssb/ssb.h>
17#include <linux/ssb/ssb_regs.h>
18#include <linux/ssb/ssb_driver_gige.h>
19#include <linux/dma-mapping.h>
20#include <linux/pci.h>
21#include <linux/mmc/sdio_func.h>
22#include <linux/slab.h>
23
24#include <pcmcia/cistpl.h>
25#include <pcmcia/ds.h>
26
27
28MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
29MODULE_LICENSE("GPL");
30
31
32/* Temporary list of yet-to-be-attached buses */
33static LIST_HEAD(attach_queue);
34/* List if running buses */
35static LIST_HEAD(buses);
36/* Software ID counter */
37static unsigned int next_busnumber;
38/* buses_mutes locks the two buslists and the next_busnumber.
39 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
40static DEFINE_MUTEX(buses_mutex);
41
42/* There are differences in the codeflow, if the bus is
43 * initialized from early boot, as various needed services
44 * are not available early. This is a mechanism to delay
45 * these initializations to after early boot has finished.
46 * It's also used to avoid mutex locking, as that's not
47 * available and needed early. */
48static bool ssb_is_early_boot = 1;
49
50static void ssb_buses_lock(void);
51static void ssb_buses_unlock(void);
52
53
54#ifdef CONFIG_SSB_PCIHOST
55struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
56{
57 struct ssb_bus *bus;
58
59 ssb_buses_lock();
60 list_for_each_entry(bus, &buses, list) {
61 if (bus->bustype == SSB_BUSTYPE_PCI &&
62 bus->host_pci == pdev)
63 goto found;
64 }
65 bus = NULL;
66found:
67 ssb_buses_unlock();
68
69 return bus;
70}
71#endif /* CONFIG_SSB_PCIHOST */
72
73#ifdef CONFIG_SSB_PCMCIAHOST
74struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
75{
76 struct ssb_bus *bus;
77
78 ssb_buses_lock();
79 list_for_each_entry(bus, &buses, list) {
80 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
81 bus->host_pcmcia == pdev)
82 goto found;
83 }
84 bus = NULL;
85found:
86 ssb_buses_unlock();
87
88 return bus;
89}
90#endif /* CONFIG_SSB_PCMCIAHOST */
91
92#ifdef CONFIG_SSB_SDIOHOST
93struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
94{
95 struct ssb_bus *bus;
96
97 ssb_buses_lock();
98 list_for_each_entry(bus, &buses, list) {
99 if (bus->bustype == SSB_BUSTYPE_SDIO &&
100 bus->host_sdio == func)
101 goto found;
102 }
103 bus = NULL;
104found:
105 ssb_buses_unlock();
106
107 return bus;
108}
109#endif /* CONFIG_SSB_SDIOHOST */
110
111int ssb_for_each_bus_call(unsigned long data,
112 int (*func)(struct ssb_bus *bus, unsigned long data))
113{
114 struct ssb_bus *bus;
115 int res;
116
117 ssb_buses_lock();
118 list_for_each_entry(bus, &buses, list) {
119 res = func(bus, data);
120 if (res >= 0) {
121 ssb_buses_unlock();
122 return res;
123 }
124 }
125 ssb_buses_unlock();
126
127 return -ENODEV;
128}
129
130static struct ssb_device *ssb_device_get(struct ssb_device *dev)
131{
132 if (dev)
133 get_device(dev->dev);
134 return dev;
135}
136
137static void ssb_device_put(struct ssb_device *dev)
138{
139 if (dev)
140 put_device(dev->dev);
141}
142
143static int ssb_device_resume(struct device *dev)
144{
145 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
146 struct ssb_driver *ssb_drv;
147 int err = 0;
148
149 if (dev->driver) {
150 ssb_drv = drv_to_ssb_drv(dev->driver);
151 if (ssb_drv && ssb_drv->resume)
152 err = ssb_drv->resume(ssb_dev);
153 if (err)
154 goto out;
155 }
156out:
157 return err;
158}
159
160static int ssb_device_suspend(struct device *dev, pm_message_t state)
161{
162 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
163 struct ssb_driver *ssb_drv;
164 int err = 0;
165
166 if (dev->driver) {
167 ssb_drv = drv_to_ssb_drv(dev->driver);
168 if (ssb_drv && ssb_drv->suspend)
169 err = ssb_drv->suspend(ssb_dev, state);
170 if (err)
171 goto out;
172 }
173out:
174 return err;
175}
176
177int ssb_bus_resume(struct ssb_bus *bus)
178{
179 int err;
180
181 /* Reset HW state information in memory, so that HW is
182 * completely reinitialized. */
183 bus->mapped_device = NULL;
184#ifdef CONFIG_SSB_DRIVER_PCICORE
185 bus->pcicore.setup_done = 0;
186#endif
187
188 err = ssb_bus_powerup(bus, 0);
189 if (err)
190 return err;
191 err = ssb_pcmcia_hardware_setup(bus);
192 if (err) {
193 ssb_bus_may_powerdown(bus);
194 return err;
195 }
196 ssb_chipco_resume(&bus->chipco);
197 ssb_bus_may_powerdown(bus);
198
199 return 0;
200}
201EXPORT_SYMBOL(ssb_bus_resume);
202
203int ssb_bus_suspend(struct ssb_bus *bus)
204{
205 ssb_chipco_suspend(&bus->chipco);
206 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
207
208 return 0;
209}
210EXPORT_SYMBOL(ssb_bus_suspend);
211
212#ifdef CONFIG_SSB_SPROM
213/** ssb_devices_freeze - Freeze all devices on the bus.
214 *
215 * After freezing no device driver will be handling a device
216 * on this bus anymore. ssb_devices_thaw() must be called after
217 * a successful freeze to reactivate the devices.
218 *
219 * @bus: The bus.
220 * @ctx: Context structure. Pass this to ssb_devices_thaw().
221 */
222int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
223{
224 struct ssb_device *sdev;
225 struct ssb_driver *sdrv;
226 unsigned int i;
227
228 memset(ctx, 0, sizeof(*ctx));
229 ctx->bus = bus;
230 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
231
232 for (i = 0; i < bus->nr_devices; i++) {
233 sdev = ssb_device_get(&bus->devices[i]);
234
235 if (!sdev->dev || !sdev->dev->driver ||
236 !device_is_registered(sdev->dev)) {
237 ssb_device_put(sdev);
238 continue;
239 }
240 sdrv = drv_to_ssb_drv(sdev->dev->driver);
241 if (SSB_WARN_ON(!sdrv->remove))
242 continue;
243 sdrv->remove(sdev);
244 ctx->device_frozen[i] = 1;
245 }
246
247 return 0;
248}
249
250/** ssb_devices_thaw - Unfreeze all devices on the bus.
251 *
252 * This will re-attach the device drivers and re-init the devices.
253 *
254 * @ctx: The context structure from ssb_devices_freeze()
255 */
256int ssb_devices_thaw(struct ssb_freeze_context *ctx)
257{
258 struct ssb_bus *bus = ctx->bus;
259 struct ssb_device *sdev;
260 struct ssb_driver *sdrv;
261 unsigned int i;
262 int err, result = 0;
263
264 for (i = 0; i < bus->nr_devices; i++) {
265 if (!ctx->device_frozen[i])
266 continue;
267 sdev = &bus->devices[i];
268
269 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
270 continue;
271 sdrv = drv_to_ssb_drv(sdev->dev->driver);
272 if (SSB_WARN_ON(!sdrv || !sdrv->probe))
273 continue;
274
275 err = sdrv->probe(sdev, &sdev->id);
276 if (err) {
277 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
278 dev_name(sdev->dev));
279 result = err;
280 }
281 ssb_device_put(sdev);
282 }
283
284 return result;
285}
286#endif /* CONFIG_SSB_SPROM */
287
288static void ssb_device_shutdown(struct device *dev)
289{
290 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
291 struct ssb_driver *ssb_drv;
292
293 if (!dev->driver)
294 return;
295 ssb_drv = drv_to_ssb_drv(dev->driver);
296 if (ssb_drv && ssb_drv->shutdown)
297 ssb_drv->shutdown(ssb_dev);
298}
299
300static int ssb_device_remove(struct device *dev)
301{
302 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
303 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
304
305 if (ssb_drv && ssb_drv->remove)
306 ssb_drv->remove(ssb_dev);
307 ssb_device_put(ssb_dev);
308
309 return 0;
310}
311
312static int ssb_device_probe(struct device *dev)
313{
314 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
315 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
316 int err = 0;
317
318 ssb_device_get(ssb_dev);
319 if (ssb_drv && ssb_drv->probe)
320 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
321 if (err)
322 ssb_device_put(ssb_dev);
323
324 return err;
325}
326
327static int ssb_match_devid(const struct ssb_device_id *tabid,
328 const struct ssb_device_id *devid)
329{
330 if ((tabid->vendor != devid->vendor) &&
331 tabid->vendor != SSB_ANY_VENDOR)
332 return 0;
333 if ((tabid->coreid != devid->coreid) &&
334 tabid->coreid != SSB_ANY_ID)
335 return 0;
336 if ((tabid->revision != devid->revision) &&
337 tabid->revision != SSB_ANY_REV)
338 return 0;
339 return 1;
340}
341
342static int ssb_bus_match(struct device *dev, struct device_driver *drv)
343{
344 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
345 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
346 const struct ssb_device_id *id;
347
348 for (id = ssb_drv->id_table;
349 id->vendor || id->coreid || id->revision;
350 id++) {
351 if (ssb_match_devid(id, &ssb_dev->id))
352 return 1; /* found */
353 }
354
355 return 0;
356}
357
358static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
359{
360 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
361
362 if (!dev)
363 return -ENODEV;
364
365 return add_uevent_var(env,
366 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
367 ssb_dev->id.vendor, ssb_dev->id.coreid,
368 ssb_dev->id.revision);
369}
370
371#define ssb_config_attr(attrib, field, format_string) \
372static ssize_t \
373attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
374{ \
375 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
376}
377
378ssb_config_attr(core_num, core_index, "%u\n")
379ssb_config_attr(coreid, id.coreid, "0x%04x\n")
380ssb_config_attr(vendor, id.vendor, "0x%04x\n")
381ssb_config_attr(revision, id.revision, "%u\n")
382ssb_config_attr(irq, irq, "%u\n")
383static ssize_t
384name_show(struct device *dev, struct device_attribute *attr, char *buf)
385{
386 return sprintf(buf, "%s\n",
387 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
388}
389
390static struct device_attribute ssb_device_attrs[] = {
391 __ATTR_RO(name),
392 __ATTR_RO(core_num),
393 __ATTR_RO(coreid),
394 __ATTR_RO(vendor),
395 __ATTR_RO(revision),
396 __ATTR_RO(irq),
397 __ATTR_NULL,
398};
399
400static struct bus_type ssb_bustype = {
401 .name = "ssb",
402 .match = ssb_bus_match,
403 .probe = ssb_device_probe,
404 .remove = ssb_device_remove,
405 .shutdown = ssb_device_shutdown,
406 .suspend = ssb_device_suspend,
407 .resume = ssb_device_resume,
408 .uevent = ssb_device_uevent,
409 .dev_attrs = ssb_device_attrs,
410};
411
412static void ssb_buses_lock(void)
413{
414 /* See the comment at the ssb_is_early_boot definition */
415 if (!ssb_is_early_boot)
416 mutex_lock(&buses_mutex);
417}
418
419static void ssb_buses_unlock(void)
420{
421 /* See the comment at the ssb_is_early_boot definition */
422 if (!ssb_is_early_boot)
423 mutex_unlock(&buses_mutex);
424}
425
426static void ssb_devices_unregister(struct ssb_bus *bus)
427{
428 struct ssb_device *sdev;
429 int i;
430
431 for (i = bus->nr_devices - 1; i >= 0; i--) {
432 sdev = &(bus->devices[i]);
433 if (sdev->dev)
434 device_unregister(sdev->dev);
435 }
436}
437
438void ssb_bus_unregister(struct ssb_bus *bus)
439{
440 ssb_buses_lock();
441 ssb_devices_unregister(bus);
442 list_del(&bus->list);
443 ssb_buses_unlock();
444
445 ssb_pcmcia_exit(bus);
446 ssb_pci_exit(bus);
447 ssb_iounmap(bus);
448}
449EXPORT_SYMBOL(ssb_bus_unregister);
450
451static void ssb_release_dev(struct device *dev)
452{
453 struct __ssb_dev_wrapper *devwrap;
454
455 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
456 kfree(devwrap);
457}
458
459static int ssb_devices_register(struct ssb_bus *bus)
460{
461 struct ssb_device *sdev;
462 struct device *dev;
463 struct __ssb_dev_wrapper *devwrap;
464 int i, err = 0;
465 int dev_idx = 0;
466
467 for (i = 0; i < bus->nr_devices; i++) {
468 sdev = &(bus->devices[i]);
469
470 /* We don't register SSB-system devices to the kernel,
471 * as the drivers for them are built into SSB. */
472 switch (sdev->id.coreid) {
473 case SSB_DEV_CHIPCOMMON:
474 case SSB_DEV_PCI:
475 case SSB_DEV_PCIE:
476 case SSB_DEV_PCMCIA:
477 case SSB_DEV_MIPS:
478 case SSB_DEV_MIPS_3302:
479 case SSB_DEV_EXTIF:
480 continue;
481 }
482
483 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
484 if (!devwrap) {
485 ssb_printk(KERN_ERR PFX
486 "Could not allocate device\n");
487 err = -ENOMEM;
488 goto error;
489 }
490 dev = &devwrap->dev;
491 devwrap->sdev = sdev;
492
493 dev->release = ssb_release_dev;
494 dev->bus = &ssb_bustype;
495 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
496
497 switch (bus->bustype) {
498 case SSB_BUSTYPE_PCI:
499#ifdef CONFIG_SSB_PCIHOST
500 sdev->irq = bus->host_pci->irq;
501 dev->parent = &bus->host_pci->dev;
502 sdev->dma_dev = dev->parent;
503#endif
504 break;
505 case SSB_BUSTYPE_PCMCIA:
506#ifdef CONFIG_SSB_PCMCIAHOST
507 sdev->irq = bus->host_pcmcia->irq;
508 dev->parent = &bus->host_pcmcia->dev;
509#endif
510 break;
511 case SSB_BUSTYPE_SDIO:
512#ifdef CONFIG_SSB_SDIOHOST
513 dev->parent = &bus->host_sdio->dev;
514#endif
515 break;
516 case SSB_BUSTYPE_SSB:
517 dev->dma_mask = &dev->coherent_dma_mask;
518 sdev->dma_dev = dev;
519 break;
520 }
521
522 sdev->dev = dev;
523 err = device_register(dev);
524 if (err) {
525 ssb_printk(KERN_ERR PFX
526 "Could not register %s\n",
527 dev_name(dev));
528 /* Set dev to NULL to not unregister
529 * dev on error unwinding. */
530 sdev->dev = NULL;
531 kfree(devwrap);
532 goto error;
533 }
534 dev_idx++;
535 }
536
537 return 0;
538error:
539 /* Unwind the already registered devices. */
540 ssb_devices_unregister(bus);
541 return err;
542}
543
544/* Needs ssb_buses_lock() */
545static int __devinit ssb_attach_queued_buses(void)
546{
547 struct ssb_bus *bus, *n;
548 int err = 0;
549 int drop_them_all = 0;
550
551 list_for_each_entry_safe(bus, n, &attach_queue, list) {
552 if (drop_them_all) {
553 list_del(&bus->list);
554 continue;
555 }
556 /* Can't init the PCIcore in ssb_bus_register(), as that
557 * is too early in boot for embedded systems
558 * (no udelay() available). So do it here in attach stage.
559 */
560 err = ssb_bus_powerup(bus, 0);
561 if (err)
562 goto error;
563 ssb_pcicore_init(&bus->pcicore);
564 ssb_bus_may_powerdown(bus);
565
566 err = ssb_devices_register(bus);
567error:
568 if (err) {
569 drop_them_all = 1;
570 list_del(&bus->list);
571 continue;
572 }
573 list_move_tail(&bus->list, &buses);
574 }
575
576 return err;
577}
578
579static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
580{
581 struct ssb_bus *bus = dev->bus;
582
583 offset += dev->core_index * SSB_CORE_SIZE;
584 return readb(bus->mmio + offset);
585}
586
587static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
588{
589 struct ssb_bus *bus = dev->bus;
590
591 offset += dev->core_index * SSB_CORE_SIZE;
592 return readw(bus->mmio + offset);
593}
594
595static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
596{
597 struct ssb_bus *bus = dev->bus;
598
599 offset += dev->core_index * SSB_CORE_SIZE;
600 return readl(bus->mmio + offset);
601}
602
603#ifdef CONFIG_SSB_BLOCKIO
604static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
605 size_t count, u16 offset, u8 reg_width)
606{
607 struct ssb_bus *bus = dev->bus;
608 void __iomem *addr;
609
610 offset += dev->core_index * SSB_CORE_SIZE;
611 addr = bus->mmio + offset;
612
613 switch (reg_width) {
614 case sizeof(u8): {
615 u8 *buf = buffer;
616
617 while (count) {
618 *buf = __raw_readb(addr);
619 buf++;
620 count--;
621 }
622 break;
623 }
624 case sizeof(u16): {
625 __le16 *buf = buffer;
626
627 SSB_WARN_ON(count & 1);
628 while (count) {
629 *buf = (__force __le16)__raw_readw(addr);
630 buf++;
631 count -= 2;
632 }
633 break;
634 }
635 case sizeof(u32): {
636 __le32 *buf = buffer;
637
638 SSB_WARN_ON(count & 3);
639 while (count) {
640 *buf = (__force __le32)__raw_readl(addr);
641 buf++;
642 count -= 4;
643 }
644 break;
645 }
646 default:
647 SSB_WARN_ON(1);
648 }
649}
650#endif /* CONFIG_SSB_BLOCKIO */
651
652static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
653{
654 struct ssb_bus *bus = dev->bus;
655
656 offset += dev->core_index * SSB_CORE_SIZE;
657 writeb(value, bus->mmio + offset);
658}
659
660static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
661{
662 struct ssb_bus *bus = dev->bus;
663
664 offset += dev->core_index * SSB_CORE_SIZE;
665 writew(value, bus->mmio + offset);
666}
667
668static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
669{
670 struct ssb_bus *bus = dev->bus;
671
672 offset += dev->core_index * SSB_CORE_SIZE;
673 writel(value, bus->mmio + offset);
674}
675
676#ifdef CONFIG_SSB_BLOCKIO
677static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
678 size_t count, u16 offset, u8 reg_width)
679{
680 struct ssb_bus *bus = dev->bus;
681 void __iomem *addr;
682
683 offset += dev->core_index * SSB_CORE_SIZE;
684 addr = bus->mmio + offset;
685
686 switch (reg_width) {
687 case sizeof(u8): {
688 const u8 *buf = buffer;
689
690 while (count) {
691 __raw_writeb(*buf, addr);
692 buf++;
693 count--;
694 }
695 break;
696 }
697 case sizeof(u16): {
698 const __le16 *buf = buffer;
699
700 SSB_WARN_ON(count & 1);
701 while (count) {
702 __raw_writew((__force u16)(*buf), addr);
703 buf++;
704 count -= 2;
705 }
706 break;
707 }
708 case sizeof(u32): {
709 const __le32 *buf = buffer;
710
711 SSB_WARN_ON(count & 3);
712 while (count) {
713 __raw_writel((__force u32)(*buf), addr);
714 buf++;
715 count -= 4;
716 }
717 break;
718 }
719 default:
720 SSB_WARN_ON(1);
721 }
722}
723#endif /* CONFIG_SSB_BLOCKIO */
724
725/* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
726static const struct ssb_bus_ops ssb_ssb_ops = {
727 .read8 = ssb_ssb_read8,
728 .read16 = ssb_ssb_read16,
729 .read32 = ssb_ssb_read32,
730 .write8 = ssb_ssb_write8,
731 .write16 = ssb_ssb_write16,
732 .write32 = ssb_ssb_write32,
733#ifdef CONFIG_SSB_BLOCKIO
734 .block_read = ssb_ssb_block_read,
735 .block_write = ssb_ssb_block_write,
736#endif
737};
738
739static int ssb_fetch_invariants(struct ssb_bus *bus,
740 ssb_invariants_func_t get_invariants)
741{
742 struct ssb_init_invariants iv;
743 int err;
744
745 memset(&iv, 0, sizeof(iv));
746 err = get_invariants(bus, &iv);
747 if (err)
748 goto out;
749 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
750 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
751 bus->has_cardbus_slot = iv.has_cardbus_slot;
752out:
753 return err;
754}
755
756static int __devinit ssb_bus_register(struct ssb_bus *bus,
757 ssb_invariants_func_t get_invariants,
758 unsigned long baseaddr)
759{
760 int err;
761
762 spin_lock_init(&bus->bar_lock);
763 INIT_LIST_HEAD(&bus->list);
764#ifdef CONFIG_SSB_EMBEDDED
765 spin_lock_init(&bus->gpio_lock);
766#endif
767
768 /* Powerup the bus */
769 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
770 if (err)
771 goto out;
772
773 /* Init SDIO-host device (if any), before the scan */
774 err = ssb_sdio_init(bus);
775 if (err)
776 goto err_disable_xtal;
777
778 ssb_buses_lock();
779 bus->busnumber = next_busnumber;
780 /* Scan for devices (cores) */
781 err = ssb_bus_scan(bus, baseaddr);
782 if (err)
783 goto err_sdio_exit;
784
785 /* Init PCI-host device (if any) */
786 err = ssb_pci_init(bus);
787 if (err)
788 goto err_unmap;
789 /* Init PCMCIA-host device (if any) */
790 err = ssb_pcmcia_init(bus);
791 if (err)
792 goto err_pci_exit;
793
794 /* Initialize basic system devices (if available) */
795 err = ssb_bus_powerup(bus, 0);
796 if (err)
797 goto err_pcmcia_exit;
798 ssb_chipcommon_init(&bus->chipco);
799 ssb_mipscore_init(&bus->mipscore);
800 err = ssb_fetch_invariants(bus, get_invariants);
801 if (err) {
802 ssb_bus_may_powerdown(bus);
803 goto err_pcmcia_exit;
804 }
805 ssb_bus_may_powerdown(bus);
806
807 /* Queue it for attach.
808 * See the comment at the ssb_is_early_boot definition. */
809 list_add_tail(&bus->list, &attach_queue);
810 if (!ssb_is_early_boot) {
811 /* This is not early boot, so we must attach the bus now */
812 err = ssb_attach_queued_buses();
813 if (err)
814 goto err_dequeue;
815 }
816 next_busnumber++;
817 ssb_buses_unlock();
818
819out:
820 return err;
821
822err_dequeue:
823 list_del(&bus->list);
824err_pcmcia_exit:
825 ssb_pcmcia_exit(bus);
826err_pci_exit:
827 ssb_pci_exit(bus);
828err_unmap:
829 ssb_iounmap(bus);
830err_sdio_exit:
831 ssb_sdio_exit(bus);
832err_disable_xtal:
833 ssb_buses_unlock();
834 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
835 return err;
836}
837
838#ifdef CONFIG_SSB_PCIHOST
839int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
840 struct pci_dev *host_pci)
841{
842 int err;
843
844 bus->bustype = SSB_BUSTYPE_PCI;
845 bus->host_pci = host_pci;
846 bus->ops = &ssb_pci_ops;
847
848 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
849 if (!err) {
850 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
851 "PCI device %s\n", dev_name(&host_pci->dev));
852 } else {
853 ssb_printk(KERN_ERR PFX "Failed to register PCI version"
854 " of SSB with error %d\n", err);
855 }
856
857 return err;
858}
859EXPORT_SYMBOL(ssb_bus_pcibus_register);
860#endif /* CONFIG_SSB_PCIHOST */
861
862#ifdef CONFIG_SSB_PCMCIAHOST
863int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
864 struct pcmcia_device *pcmcia_dev,
865 unsigned long baseaddr)
866{
867 int err;
868
869 bus->bustype = SSB_BUSTYPE_PCMCIA;
870 bus->host_pcmcia = pcmcia_dev;
871 bus->ops = &ssb_pcmcia_ops;
872
873 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
874 if (!err) {
875 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
876 "PCMCIA device %s\n", pcmcia_dev->devname);
877 }
878
879 return err;
880}
881EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
882#endif /* CONFIG_SSB_PCMCIAHOST */
883
884#ifdef CONFIG_SSB_SDIOHOST
885int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
886 struct sdio_func *func,
887 unsigned int quirks)
888{
889 int err;
890
891 bus->bustype = SSB_BUSTYPE_SDIO;
892 bus->host_sdio = func;
893 bus->ops = &ssb_sdio_ops;
894 bus->quirks = quirks;
895
896 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
897 if (!err) {
898 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
899 "SDIO device %s\n", sdio_func_id(func));
900 }
901
902 return err;
903}
904EXPORT_SYMBOL(ssb_bus_sdiobus_register);
905#endif /* CONFIG_SSB_PCMCIAHOST */
906
907int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
908 unsigned long baseaddr,
909 ssb_invariants_func_t get_invariants)
910{
911 int err;
912
913 bus->bustype = SSB_BUSTYPE_SSB;
914 bus->ops = &ssb_ssb_ops;
915
916 err = ssb_bus_register(bus, get_invariants, baseaddr);
917 if (!err) {
918 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
919 "address 0x%08lX\n", baseaddr);
920 }
921
922 return err;
923}
924
925int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
926{
927 drv->drv.name = drv->name;
928 drv->drv.bus = &ssb_bustype;
929 drv->drv.owner = owner;
930
931 return driver_register(&drv->drv);
932}
933EXPORT_SYMBOL(__ssb_driver_register);
934
935void ssb_driver_unregister(struct ssb_driver *drv)
936{
937 driver_unregister(&drv->drv);
938}
939EXPORT_SYMBOL(ssb_driver_unregister);
940
941void ssb_set_devtypedata(struct ssb_device *dev, void *data)
942{
943 struct ssb_bus *bus = dev->bus;
944 struct ssb_device *ent;
945 int i;
946
947 for (i = 0; i < bus->nr_devices; i++) {
948 ent = &(bus->devices[i]);
949 if (ent->id.vendor != dev->id.vendor)
950 continue;
951 if (ent->id.coreid != dev->id.coreid)
952 continue;
953
954 ent->devtypedata = data;
955 }
956}
957EXPORT_SYMBOL(ssb_set_devtypedata);
958
959static u32 clkfactor_f6_resolve(u32 v)
960{
961 /* map the magic values */
962 switch (v) {
963 case SSB_CHIPCO_CLK_F6_2:
964 return 2;
965 case SSB_CHIPCO_CLK_F6_3:
966 return 3;
967 case SSB_CHIPCO_CLK_F6_4:
968 return 4;
969 case SSB_CHIPCO_CLK_F6_5:
970 return 5;
971 case SSB_CHIPCO_CLK_F6_6:
972 return 6;
973 case SSB_CHIPCO_CLK_F6_7:
974 return 7;
975 }
976 return 0;
977}
978
979/* Calculate the speed the backplane would run at a given set of clockcontrol values */
980u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
981{
982 u32 n1, n2, clock, m1, m2, m3, mc;
983
984 n1 = (n & SSB_CHIPCO_CLK_N1);
985 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
986
987 switch (plltype) {
988 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
989 if (m & SSB_CHIPCO_CLK_T6_MMASK)
990 return SSB_CHIPCO_CLK_T6_M1;
991 return SSB_CHIPCO_CLK_T6_M0;
992 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
993 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
994 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
995 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
996 n1 = clkfactor_f6_resolve(n1);
997 n2 += SSB_CHIPCO_CLK_F5_BIAS;
998 break;
999 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
1000 n1 += SSB_CHIPCO_CLK_T2_BIAS;
1001 n2 += SSB_CHIPCO_CLK_T2_BIAS;
1002 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
1003 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
1004 break;
1005 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
1006 return 100000000;
1007 default:
1008 SSB_WARN_ON(1);
1009 }
1010
1011 switch (plltype) {
1012 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1013 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1014 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
1015 break;
1016 default:
1017 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
1018 }
1019 if (!clock)
1020 return 0;
1021
1022 m1 = (m & SSB_CHIPCO_CLK_M1);
1023 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
1024 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
1025 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
1026
1027 switch (plltype) {
1028 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1029 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1030 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1031 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1032 m1 = clkfactor_f6_resolve(m1);
1033 if ((plltype == SSB_PLLTYPE_1) ||
1034 (plltype == SSB_PLLTYPE_3))
1035 m2 += SSB_CHIPCO_CLK_F5_BIAS;
1036 else
1037 m2 = clkfactor_f6_resolve(m2);
1038 m3 = clkfactor_f6_resolve(m3);
1039
1040 switch (mc) {
1041 case SSB_CHIPCO_CLK_MC_BYPASS:
1042 return clock;
1043 case SSB_CHIPCO_CLK_MC_M1:
1044 return (clock / m1);
1045 case SSB_CHIPCO_CLK_MC_M1M2:
1046 return (clock / (m1 * m2));
1047 case SSB_CHIPCO_CLK_MC_M1M2M3:
1048 return (clock / (m1 * m2 * m3));
1049 case SSB_CHIPCO_CLK_MC_M1M3:
1050 return (clock / (m1 * m3));
1051 }
1052 return 0;
1053 case SSB_PLLTYPE_2:
1054 m1 += SSB_CHIPCO_CLK_T2_BIAS;
1055 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
1056 m3 += SSB_CHIPCO_CLK_T2_BIAS;
1057 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
1058 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
1059 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
1060
1061 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
1062 clock /= m1;
1063 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
1064 clock /= m2;
1065 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
1066 clock /= m3;
1067 return clock;
1068 default:
1069 SSB_WARN_ON(1);
1070 }
1071 return 0;
1072}
1073
1074/* Get the current speed the backplane is running at */
1075u32 ssb_clockspeed(struct ssb_bus *bus)
1076{
1077 u32 rate;
1078 u32 plltype;
1079 u32 clkctl_n, clkctl_m;
1080
1081 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1082 return ssb_pmu_get_controlclock(&bus->chipco);
1083
1084 if (ssb_extif_available(&bus->extif))
1085 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1086 &clkctl_n, &clkctl_m);
1087 else if (bus->chipco.dev)
1088 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
1089 &clkctl_n, &clkctl_m);
1090 else
1091 return 0;
1092
1093 if (bus->chip_id == 0x5365) {
1094 rate = 100000000;
1095 } else {
1096 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
1097 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
1098 rate /= 2;
1099 }
1100
1101 return rate;
1102}
1103EXPORT_SYMBOL(ssb_clockspeed);
1104
1105static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
1106{
1107 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1108
1109 /* The REJECT bit seems to be different for Backplane rev 2.3 */
1110 switch (rev) {
1111 case SSB_IDLOW_SSBREV_22:
1112 case SSB_IDLOW_SSBREV_24:
1113 case SSB_IDLOW_SSBREV_26:
1114 return SSB_TMSLOW_REJECT;
1115 case SSB_IDLOW_SSBREV_23:
1116 return SSB_TMSLOW_REJECT_23;
1117 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1118 case SSB_IDLOW_SSBREV_27: /* same here */
1119 return SSB_TMSLOW_REJECT; /* this is a guess */
1120 default:
1121 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1122 WARN_ON(1);
1123 }
1124 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1125}
1126
1127int ssb_device_is_enabled(struct ssb_device *dev)
1128{
1129 u32 val;
1130 u32 reject;
1131
1132 reject = ssb_tmslow_reject_bitmask(dev);
1133 val = ssb_read32(dev, SSB_TMSLOW);
1134 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
1135
1136 return (val == SSB_TMSLOW_CLOCK);
1137}
1138EXPORT_SYMBOL(ssb_device_is_enabled);
1139
1140static void ssb_flush_tmslow(struct ssb_device *dev)
1141{
1142 /* Make _really_ sure the device has finished the TMSLOW
1143 * register write transaction, as we risk running into
1144 * a machine check exception otherwise.
1145 * Do this by reading the register back to commit the
1146 * PCI write and delay an additional usec for the device
1147 * to react to the change. */
1148 ssb_read32(dev, SSB_TMSLOW);
1149 udelay(1);
1150}
1151
1152void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1153{
1154 u32 val;
1155
1156 ssb_device_disable(dev, core_specific_flags);
1157 ssb_write32(dev, SSB_TMSLOW,
1158 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1159 SSB_TMSLOW_FGC | core_specific_flags);
1160 ssb_flush_tmslow(dev);
1161
1162 /* Clear SERR if set. This is a hw bug workaround. */
1163 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1164 ssb_write32(dev, SSB_TMSHIGH, 0);
1165
1166 val = ssb_read32(dev, SSB_IMSTATE);
1167 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1168 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1169 ssb_write32(dev, SSB_IMSTATE, val);
1170 }
1171
1172 ssb_write32(dev, SSB_TMSLOW,
1173 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1174 core_specific_flags);
1175 ssb_flush_tmslow(dev);
1176
1177 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1178 core_specific_flags);
1179 ssb_flush_tmslow(dev);
1180}
1181EXPORT_SYMBOL(ssb_device_enable);
1182
1183/* Wait for bitmask in a register to get set or cleared.
1184 * timeout is in units of ten-microseconds */
1185static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1186 int timeout, int set)
1187{
1188 int i;
1189 u32 val;
1190
1191 for (i = 0; i < timeout; i++) {
1192 val = ssb_read32(dev, reg);
1193 if (set) {
1194 if ((val & bitmask) == bitmask)
1195 return 0;
1196 } else {
1197 if (!(val & bitmask))
1198 return 0;
1199 }
1200 udelay(10);
1201 }
1202 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1203 "register %04X to %s.\n",
1204 bitmask, reg, (set ? "set" : "clear"));
1205
1206 return -ETIMEDOUT;
1207}
1208
1209void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1210{
1211 u32 reject, val;
1212
1213 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1214 return;
1215
1216 reject = ssb_tmslow_reject_bitmask(dev);
1217
1218 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1219 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1220 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1221 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1222
1223 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1224 val = ssb_read32(dev, SSB_IMSTATE);
1225 val |= SSB_IMSTATE_REJECT;
1226 ssb_write32(dev, SSB_IMSTATE, val);
1227 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1228 0);
1229 }
1230
1231 ssb_write32(dev, SSB_TMSLOW,
1232 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1233 reject | SSB_TMSLOW_RESET |
1234 core_specific_flags);
1235 ssb_flush_tmslow(dev);
1236
1237 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1238 val = ssb_read32(dev, SSB_IMSTATE);
1239 val &= ~SSB_IMSTATE_REJECT;
1240 ssb_write32(dev, SSB_IMSTATE, val);
1241 }
1242 }
1243
1244 ssb_write32(dev, SSB_TMSLOW,
1245 reject | SSB_TMSLOW_RESET |
1246 core_specific_flags);
1247 ssb_flush_tmslow(dev);
1248}
1249EXPORT_SYMBOL(ssb_device_disable);
1250
1251/* Some chipsets need routing known for PCIe and 64-bit DMA */
1252static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1253{
1254 u16 chip_id = dev->bus->chip_id;
1255
1256 if (dev->id.coreid == SSB_DEV_80211) {
1257 return (chip_id == 0x4322 || chip_id == 43221 ||
1258 chip_id == 43231 || chip_id == 43222);
1259 }
1260
1261 return 0;
1262}
1263
1264u32 ssb_dma_translation(struct ssb_device *dev)
1265{
1266 switch (dev->bus->bustype) {
1267 case SSB_BUSTYPE_SSB:
1268 return 0;
1269 case SSB_BUSTYPE_PCI:
1270 if (pci_is_pcie(dev->bus->host_pci) &&
1271 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1272 return SSB_PCIE_DMA_H32;
1273 } else {
1274 if (ssb_dma_translation_special_bit(dev))
1275 return SSB_PCIE_DMA_H32;
1276 else
1277 return SSB_PCI_DMA;
1278 }
1279 default:
1280 __ssb_dma_not_implemented(dev);
1281 }
1282 return 0;
1283}
1284EXPORT_SYMBOL(ssb_dma_translation);
1285
1286int ssb_bus_may_powerdown(struct ssb_bus *bus)
1287{
1288 struct ssb_chipcommon *cc;
1289 int err = 0;
1290
1291 /* On buses where more than one core may be working
1292 * at a time, we must not powerdown stuff if there are
1293 * still cores that may want to run. */
1294 if (bus->bustype == SSB_BUSTYPE_SSB)
1295 goto out;
1296
1297 cc = &bus->chipco;
1298
1299 if (!cc->dev)
1300 goto out;
1301 if (cc->dev->id.revision < 5)
1302 goto out;
1303
1304 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1305 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1306 if (err)
1307 goto error;
1308out:
1309#ifdef CONFIG_SSB_DEBUG
1310 bus->powered_up = 0;
1311#endif
1312 return err;
1313error:
1314 ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1315 goto out;
1316}
1317EXPORT_SYMBOL(ssb_bus_may_powerdown);
1318
1319int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1320{
1321 int err;
1322 enum ssb_clkmode mode;
1323
1324 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1325 if (err)
1326 goto error;
1327
1328#ifdef CONFIG_SSB_DEBUG
1329 bus->powered_up = 1;
1330#endif
1331
1332 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1333 ssb_chipco_set_clockmode(&bus->chipco, mode);
1334
1335 return 0;
1336error:
1337 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1338 return err;
1339}
1340EXPORT_SYMBOL(ssb_bus_powerup);
1341
1342static void ssb_broadcast_value(struct ssb_device *dev,
1343 u32 address, u32 data)
1344{
1345#ifdef CONFIG_SSB_DRIVER_PCICORE
1346 /* This is used for both, PCI and ChipCommon core, so be careful. */
1347 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1348 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1349#endif
1350
1351 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1352 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1353 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1354 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1355}
1356
1357void ssb_commit_settings(struct ssb_bus *bus)
1358{
1359 struct ssb_device *dev;
1360
1361#ifdef CONFIG_SSB_DRIVER_PCICORE
1362 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1363#else
1364 dev = bus->chipco.dev;
1365#endif
1366 if (WARN_ON(!dev))
1367 return;
1368 /* This forces an update of the cached registers. */
1369 ssb_broadcast_value(dev, 0xFD8, 0);
1370}
1371EXPORT_SYMBOL(ssb_commit_settings);
1372
1373u32 ssb_admatch_base(u32 adm)
1374{
1375 u32 base = 0;
1376
1377 switch (adm & SSB_ADM_TYPE) {
1378 case SSB_ADM_TYPE0:
1379 base = (adm & SSB_ADM_BASE0);
1380 break;
1381 case SSB_ADM_TYPE1:
1382 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1383 base = (adm & SSB_ADM_BASE1);
1384 break;
1385 case SSB_ADM_TYPE2:
1386 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1387 base = (adm & SSB_ADM_BASE2);
1388 break;
1389 default:
1390 SSB_WARN_ON(1);
1391 }
1392
1393 return base;
1394}
1395EXPORT_SYMBOL(ssb_admatch_base);
1396
1397u32 ssb_admatch_size(u32 adm)
1398{
1399 u32 size = 0;
1400
1401 switch (adm & SSB_ADM_TYPE) {
1402 case SSB_ADM_TYPE0:
1403 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1404 break;
1405 case SSB_ADM_TYPE1:
1406 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1407 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1408 break;
1409 case SSB_ADM_TYPE2:
1410 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1411 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1412 break;
1413 default:
1414 SSB_WARN_ON(1);
1415 }
1416 size = (1 << (size + 1));
1417
1418 return size;
1419}
1420EXPORT_SYMBOL(ssb_admatch_size);
1421
1422static int __init ssb_modinit(void)
1423{
1424 int err;
1425
1426 /* See the comment at the ssb_is_early_boot definition */
1427 ssb_is_early_boot = 0;
1428 err = bus_register(&ssb_bustype);
1429 if (err)
1430 return err;
1431
1432 /* Maybe we already registered some buses at early boot.
1433 * Check for this and attach them
1434 */
1435 ssb_buses_lock();
1436 err = ssb_attach_queued_buses();
1437 ssb_buses_unlock();
1438 if (err) {
1439 bus_unregister(&ssb_bustype);
1440 goto out;
1441 }
1442
1443 err = b43_pci_ssb_bridge_init();
1444 if (err) {
1445 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1446 "initialization failed\n");
1447 /* don't fail SSB init because of this */
1448 err = 0;
1449 }
1450 err = ssb_gige_init();
1451 if (err) {
1452 ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1453 "driver initialization failed\n");
1454 /* don't fail SSB init because of this */
1455 err = 0;
1456 }
1457out:
1458 return err;
1459}
1460/* ssb must be initialized after PCI but before the ssb drivers.
1461 * That means we must use some initcall between subsys_initcall
1462 * and device_initcall. */
1463fs_initcall(ssb_modinit);
1464
1465static void __exit ssb_modexit(void)
1466{
1467 ssb_gige_exit();
1468 b43_pci_ssb_bridge_exit();
1469 bus_unregister(&ssb_bustype);
1470}
1471module_exit(ssb_modexit)