1/*
   2**
   3**  PCI Lower Bus Adapter (LBA) manager
   4**
   5**	(c) Copyright 1999,2000 Grant Grundler
   6**	(c) Copyright 1999,2000 Hewlett-Packard Company
   7**
   8**	This program is free software; you can redistribute it and/or modify
   9**	it under the terms of the GNU General Public License as published by
  10**      the Free Software Foundation; either version 2 of the License, or
  11**      (at your option) any later version.
  12**
  13**
  14** This module primarily provides access to PCI bus (config/IOport
  15** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
  16** with 4 digit model numbers - eg C3000 (and A400...sigh).
  17**
  18** LBA driver isn't as simple as the Dino driver because:
  19**   (a) this chip has substantial bug fixes between revisions
  20**       (Only one Dino bug has a software workaround :^(  )
  21**   (b) has more options which we don't (yet) support (DMA hints, OLARD)
  22**   (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
  23**   (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
  24**       (dino only deals with "Legacy" PDC)
  25**
  26** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
  27** (I/O SAPIC is integratd in the LBA chip).
  28**
  29** FIXME: Add support to SBA and LBA drivers for DMA hint sets
  30** FIXME: Add support for PCI card hot-plug (OLARD).
  31*/
  32
  33#include <linux/delay.h>
  34#include <linux/types.h>
  35#include <linux/kernel.h>
  36#include <linux/spinlock.h>
  37#include <linux/init.h>		/* for __init */
  38#include <linux/pci.h>
  39#include <linux/ioport.h>
  40#include <linux/slab.h>
  41
  42#include <asm/byteorder.h>
  43#include <asm/pdc.h>
  44#include <asm/pdcpat.h>
  45#include <asm/page.h>
  46
  47#include <asm/ropes.h>
  48#include <asm/hardware.h>	/* for register_parisc_driver() stuff */
  49#include <asm/parisc-device.h>
  50#include <asm/io.h>		/* read/write stuff */
  51
  52#undef DEBUG_LBA	/* general stuff */
  53#undef DEBUG_LBA_PORT	/* debug I/O Port access */
  54#undef DEBUG_LBA_CFG	/* debug Config Space Access (ie PCI Bus walk) */
  55#undef DEBUG_LBA_PAT	/* debug PCI Resource Mgt code - PDC PAT only */
  56
  57#undef FBB_SUPPORT	/* Fast Back-Back xfers - NOT READY YET */
  58
  59
  60#ifdef DEBUG_LBA
  61#define DBG(x...)	printk(x)
  62#else
  63#define DBG(x...)
  64#endif
  65
  66#ifdef DEBUG_LBA_PORT
  67#define DBG_PORT(x...)	printk(x)
  68#else
  69#define DBG_PORT(x...)
  70#endif
  71
  72#ifdef DEBUG_LBA_CFG
  73#define DBG_CFG(x...)	printk(x)
  74#else
  75#define DBG_CFG(x...)
  76#endif
  77
  78#ifdef DEBUG_LBA_PAT
  79#define DBG_PAT(x...)	printk(x)
  80#else
  81#define DBG_PAT(x...)
  82#endif
  83
  84
  85/*
  86** Config accessor functions only pass in the 8-bit bus number and not
  87** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
  88** number based on what firmware wrote into the scratch register.
  89**
  90** The "secondary" bus number is set to this before calling
  91** pci_register_ops(). If any PPB's are present, the scan will
  92** discover them and update the "secondary" and "subordinate"
  93** fields in the pci_bus structure.
  94**
  95** Changes in the configuration *may* result in a different
  96** bus number for each LBA depending on what firmware does.
  97*/
  98
  99#define MODULE_NAME "LBA"
 100
 101/* non-postable I/O port space, densely packed */
 102#define LBA_PORT_BASE	(PCI_F_EXTEND | 0xfee00000UL)
 103static void __iomem *astro_iop_base __read_mostly;
 104
 105static u32 lba_t32;
 106
 107/* lba flags */
 108#define LBA_FLAG_SKIP_PROBE	0x10
 109
 110#define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
 111
 112
 113/* Looks nice and keeps the compiler happy */
 114#define LBA_DEV(d) ((struct lba_device *) (d))
 115
 116
 117/*
 118** Only allow 8 subsidiary busses per LBA
 119** Problem is the PCI bus numbering is globally shared.
 120*/
 121#define LBA_MAX_NUM_BUSES 8
 122
 123/************************************
 124 * LBA register read and write support
 125 *
 126 * BE WARNED: register writes are posted.
 127 *  (ie follow writes which must reach HW with a read)
 128 */
 129#define READ_U8(addr)  __raw_readb(addr)
 130#define READ_U16(addr) __raw_readw(addr)
 131#define READ_U32(addr) __raw_readl(addr)
 132#define WRITE_U8(value, addr)  __raw_writeb(value, addr)
 133#define WRITE_U16(value, addr) __raw_writew(value, addr)
 134#define WRITE_U32(value, addr) __raw_writel(value, addr)
 135
 136#define READ_REG8(addr)  readb(addr)
 137#define READ_REG16(addr) readw(addr)
 138#define READ_REG32(addr) readl(addr)
 139#define READ_REG64(addr) readq(addr)
 140#define WRITE_REG8(value, addr)  writeb(value, addr)
 141#define WRITE_REG16(value, addr) writew(value, addr)
 142#define WRITE_REG32(value, addr) writel(value, addr)
 143
 144
 145#define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
 146#define LBA_CFG_BUS(tok)  ((u8) ((tok)>>16))
 147#define LBA_CFG_DEV(tok)  ((u8) ((tok)>>11) & 0x1f)
 148#define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
 149
 150
 151/*
 152** Extract LBA (Rope) number from HPA
 153** REVISIT: 16 ropes for Stretch/Ike?
 154*/
 155#define ROPES_PER_IOC	8
 156#define LBA_NUM(x)    ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
 157
 158
 159static void
 160lba_dump_res(struct resource *r, int d)
 161{
 162	int i;
 163
 164	if (NULL == r)
 165		return;
 166
 167	printk(KERN_DEBUG "(%p)", r->parent);
 168	for (i = d; i ; --i) printk(" ");
 169	printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r,
 170		(long)r->start, (long)r->end, r->flags);
 171	lba_dump_res(r->child, d+2);
 172	lba_dump_res(r->sibling, d);
 173}
 174
 175
 176/*
 177** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
 178** workaround for cfg cycles:
 179**	-- preserve  LBA state
 180**	-- prevent any DMA from occurring
 181**	-- turn on smart mode
 182**	-- probe with config writes before doing config reads
 183**	-- check ERROR_STATUS
 184**	-- clear ERROR_STATUS
 185**	-- restore LBA state
 186**
 187** The workaround is only used for device discovery.
 188*/
 189
 190static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
 191{
 192	u8 first_bus = d->hba.hba_bus->busn_res.start;
 193	u8 last_sub_bus = d->hba.hba_bus->busn_res.end;
 194
 195	if ((bus < first_bus) ||
 196	    (bus > last_sub_bus) ||
 197	    ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) {
 198		return 0;
 199	}
 200
 201	return 1;
 202}
 203
 204
 205
 206#define LBA_CFG_SETUP(d, tok) {				\
 207    /* Save contents of error config register.  */			\
 208    error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);		\
 209\
 210    /* Save contents of status control register.  */			\
 211    status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);		\
 212\
 213    /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA		\
 214    ** arbitration for full bus walks.					\
 215    */									\
 216	/* Save contents of arb mask register. */			\
 217	arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK);		\
 218\
 219	/*								\
 220	 * Turn off all device arbitration bits (i.e. everything	\
 221	 * except arbitration enable bit).				\
 222	 */								\
 223	WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK);		\
 224\
 225    /*									\
 226     * Set the smart mode bit so that master aborts don't cause		\
 227     * LBA to go into PCI fatal mode (required).			\
 228     */									\
 229    WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG);	\
 230}
 231
 232
 233#define LBA_CFG_PROBE(d, tok) {				\
 234    /*									\
 235     * Setup Vendor ID write and read back the address register		\
 236     * to make sure that LBA is the bus master.				\
 237     */									\
 238    WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
 239    /*									\
 240     * Read address register to ensure that LBA is the bus master,	\
 241     * which implies that DMA traffic has stopped when DMA arb is off.	\
 242     */									\
 243    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
 244    /*									\
 245     * Generate a cfg write cycle (will have no affect on		\
 246     * Vendor ID register since read-only).				\
 247     */									\
 248    WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA);		\
 249    /*									\
 250     * Make sure write has completed before proceeding further,		\
 251     * i.e. before setting clear enable.				\
 252     */									\
 253    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
 254}
 255
 256
 257/*
 258 * HPREVISIT:
 259 *   -- Can't tell if config cycle got the error.
 260 *
 261 *		OV bit is broken until rev 4.0, so can't use OV bit and
 262 *		LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
 263 *
 264 *		As of rev 4.0, no longer need the error check.
 265 *
 266 *   -- Even if we could tell, we still want to return -1
 267 *	for **ANY** error (not just master abort).
 268 *
 269 *   -- Only clear non-fatal errors (we don't want to bring
 270 *	LBA out of pci-fatal mode).
 271 *
 272 *		Actually, there is still a race in which
 273 *		we could be clearing a fatal error.  We will
 274 *		live with this during our initial bus walk
 275 *		until rev 4.0 (no driver activity during
 276 *		initial bus walk).  The initial bus walk
 277 *		has race conditions concerning the use of
 278 *		smart mode as well.
 279 */
 280
 281#define LBA_MASTER_ABORT_ERROR 0xc
 282#define LBA_FATAL_ERROR 0x10
 283
 284#define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) {		\
 285    u32 error_status = 0;						\
 286    /*									\
 287     * Set clear enable (CE) bit. Unset by HW when new			\
 288     * errors are logged -- LBA HW ERS section 14.3.3).		\
 289     */									\
 290    WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
 291    error_status = READ_REG32(base + LBA_ERROR_STATUS);		\
 292    if ((error_status & 0x1f) != 0) {					\
 293	/*								\
 294	 * Fail the config read request.				\
 295	 */								\
 296	error = 1;							\
 297	if ((error_status & LBA_FATAL_ERROR) == 0) {			\
 298	    /*								\
 299	     * Clear error status (if fatal bit not set) by setting	\
 300	     * clear error log bit (CL).				\
 301	     */								\
 302	    WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
 303	}								\
 304    }									\
 305}
 306
 307#define LBA_CFG_TR4_ADDR_SETUP(d, addr)					\
 308	WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
 309
 310#define LBA_CFG_ADDR_SETUP(d, addr) {					\
 311    WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
 312    /*									\
 313     * Read address register to ensure that LBA is the bus master,	\
 314     * which implies that DMA traffic has stopped when DMA arb is off.	\
 315     */									\
 316    lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
 317}
 318
 319
 320#define LBA_CFG_RESTORE(d, base) {					\
 321    /*									\
 322     * Restore status control register (turn off clear enable).		\
 323     */									\
 324    WRITE_REG32(status_control, base + LBA_STAT_CTL);			\
 325    /*									\
 326     * Restore error config register (turn off smart mode).		\
 327     */									\
 328    WRITE_REG32(error_config, base + LBA_ERROR_CONFIG);			\
 329	/*								\
 330	 * Restore arb mask register (reenables DMA arbitration).	\
 331	 */								\
 332	WRITE_REG32(arb_mask, base + LBA_ARB_MASK);			\
 333}
 334
 335
 336
 337static unsigned int
 338lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
 339{
 340	u32 data = ~0U;
 341	int error = 0;
 342	u32 arb_mask = 0;	/* used by LBA_CFG_SETUP/RESTORE */
 343	u32 error_config = 0;	/* used by LBA_CFG_SETUP/RESTORE */
 344	u32 status_control = 0;	/* used by LBA_CFG_SETUP/RESTORE */
 345
 346	LBA_CFG_SETUP(d, tok);
 347	LBA_CFG_PROBE(d, tok);
 348	LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
 349	if (!error) {
 350		void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 351
 352		LBA_CFG_ADDR_SETUP(d, tok | reg);
 353		switch (size) {
 354		case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
 355		case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
 356		case 4: data = READ_REG32(data_reg); break;
 357		}
 358	}
 359	LBA_CFG_RESTORE(d, d->hba.base_addr);
 360	return(data);
 361}
 362
 363
 364static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
 365{
 366	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
 367	u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 368	u32 tok = LBA_CFG_TOK(local_bus, devfn);
 369	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 370
 371	if ((pos > 255) || (devfn > 255))
 372		return -EINVAL;
 373
 374/* FIXME: B2K/C3600 workaround is always use old method... */
 375	/* if (!LBA_SKIP_PROBE(d)) */ {
 376		/* original - Generate config cycle on broken elroy
 377		  with risk we will miss PCI bus errors. */
 378		*data = lba_rd_cfg(d, tok, pos, size);
 379		DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data);
 380		return 0;
 381	}
 382
 383	if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {
 384		DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos);
 385		/* either don't want to look or know device isn't present. */
 386		*data = ~0U;
 387		return(0);
 388	}
 389
 390	/* Basic Algorithm
 391	** Should only get here on fully working LBA rev.
 392	** This is how simple the code should have been.
 393	*/
 394	LBA_CFG_ADDR_SETUP(d, tok | pos);
 395	switch(size) {
 396	case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
 397	case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
 398	case 4: *data = READ_REG32(data_reg); break;
 399	}
 400	DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data);
 401	return 0;
 402}
 403
 404
 405static void
 406lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
 407{
 408	int error = 0;
 409	u32 arb_mask = 0;
 410	u32 error_config = 0;
 411	u32 status_control = 0;
 412	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 413
 414	LBA_CFG_SETUP(d, tok);
 415	LBA_CFG_ADDR_SETUP(d, tok | reg);
 416	switch (size) {
 417	case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break;
 418	case 2: WRITE_REG16(data, data_reg + (reg & 2)); break;
 419	case 4: WRITE_REG32(data, data_reg);             break;
 420	}
 421	LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
 422	LBA_CFG_RESTORE(d, d->hba.base_addr);
 423}
 424
 425
 426/*
 427 * LBA 4.0 config write code implements non-postable semantics
 428 * by doing a read of CONFIG ADDR after the write.
 429 */
 430
 431static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
 432{
 433	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
 434	u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 435	u32 tok = LBA_CFG_TOK(local_bus,devfn);
 436
 437	if ((pos > 255) || (devfn > 255))
 438		return -EINVAL;
 439
 440	if (!LBA_SKIP_PROBE(d)) {
 441		/* Original Workaround */
 442		lba_wr_cfg(d, tok, pos, (u32) data, size);
 443		DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __func__, tok, pos,data);
 444		return 0;
 445	}
 446
 447	if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) {
 448		DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data);
 449		return 1; /* New Workaround */
 450	}
 451
 452	DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __func__, tok, pos, data);
 453
 454	/* Basic Algorithm */
 455	LBA_CFG_ADDR_SETUP(d, tok | pos);
 456	switch(size) {
 457	case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
 458		   break;
 459	case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
 460		   break;
 461	case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
 462		   break;
 463	}
 464	/* flush posted write */
 465	lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
 466	return 0;
 467}
 468
 469
 470static struct pci_ops elroy_cfg_ops = {
 471	.read =		elroy_cfg_read,
 472	.write =	elroy_cfg_write,
 473};
 474
 475/*
 476 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
 477 * TR4.0 as no additional bugs were found in this areea between Elroy and
 478 * Mercury
 479 */
 480
 481static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
 482{
 483	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
 484	u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 485	u32 tok = LBA_CFG_TOK(local_bus, devfn);
 486	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 487
 488	if ((pos > 255) || (devfn > 255))
 489		return -EINVAL;
 490
 491	LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
 492	switch(size) {
 493	case 1:
 494		*data = READ_REG8(data_reg + (pos & 3));
 495		break;
 496	case 2:
 497		*data = READ_REG16(data_reg + (pos & 2));
 498		break;
 499	case 4:
 500		*data = READ_REG32(data_reg);             break;
 501		break;
 502	}
 503
 504	DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
 505	return 0;
 506}
 507
 508/*
 509 * LBA 4.0 config write code implements non-postable semantics
 510 * by doing a read of CONFIG ADDR after the write.
 511 */
 512
 513static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
 514{
 515	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
 516	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
 517	u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
 518	u32 tok = LBA_CFG_TOK(local_bus,devfn);
 519
 520	if ((pos > 255) || (devfn > 255))
 521		return -EINVAL;
 522
 523	DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__, tok, pos, data);
 524
 525	LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
 526	switch(size) {
 527	case 1:
 528		WRITE_REG8 (data, data_reg + (pos & 3));
 529		break;
 530	case 2:
 531		WRITE_REG16(data, data_reg + (pos & 2));
 532		break;
 533	case 4:
 534		WRITE_REG32(data, data_reg);
 535		break;
 536	}
 537
 538	/* flush posted write */
 539	lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
 540	return 0;
 541}
 542
 543static struct pci_ops mercury_cfg_ops = {
 544	.read =		mercury_cfg_read,
 545	.write =	mercury_cfg_write,
 546};
 547
 548
 549static void
 550lba_bios_init(void)
 551{
 552	DBG(MODULE_NAME ": lba_bios_init\n");
 553}
 554
 555
 556#ifdef CONFIG_64BIT
 557
 558/*
 559 * truncate_pat_collision:  Deal with overlaps or outright collisions
 560 *			between PAT PDC reported ranges.
 561 *
 562 *   Broken PA8800 firmware will report lmmio range that
 563 *   overlaps with CPU HPA. Just truncate the lmmio range.
 564 *
 565 *   BEWARE: conflicts with this lmmio range may be an
 566 *   elmmio range which is pointing down another rope.
 567 *
 568 *  FIXME: only deals with one collision per range...theoretically we
 569 *  could have several. Supporting more than one collision will get messy.
 570 */
 571static unsigned long
 572truncate_pat_collision(struct resource *root, struct resource *new)
 573{
 574	unsigned long start = new->start;
 575	unsigned long end = new->end;
 576	struct resource *tmp = root->child;
 577
 578	if (end <= start || start < root->start || !tmp)
 579		return 0;
 580
 581	/* find first overlap */
 582	while (tmp && tmp->end < start)
 583		tmp = tmp->sibling;
 584
 585	/* no entries overlap */
 586	if (!tmp)  return 0;
 587
 588	/* found one that starts behind the new one
 589	** Don't need to do anything.
 590	*/
 591	if (tmp->start >= end) return 0;
 592
 593	if (tmp->start <= start) {
 594		/* "front" of new one overlaps */
 595		new->start = tmp->end + 1;
 596
 597		if (tmp->end >= end) {
 598			/* AACCKK! totally overlaps! drop this range. */
 599			return 1;
 600		}
 601	} 
 602
 603	if (tmp->end < end ) {
 604		/* "end" of new one overlaps */
 605		new->end = tmp->start - 1;
 606	}
 607
 608	printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] "
 609					"to [%lx,%lx]\n",
 610			start, end,
 611			(long)new->start, (long)new->end );
 612
 613	return 0;	/* truncation successful */
 614}
 615
 616/*
 617 * extend_lmmio_len: extend lmmio range to maximum length
 618 *
 619 * This is needed at least on C8000 systems to get the ATI FireGL card
 620 * working. On other systems we will currently not extend the lmmio space.
 621 */
 622static unsigned long
 623extend_lmmio_len(unsigned long start, unsigned long end, unsigned long lba_len)
 624{
 625	struct resource *tmp;
 626
 627	/* exit if not a C8000 */
 628	if (boot_cpu_data.cpu_type < mako)
 629		return end;
 630
 631	pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n",
 632		end - start, lba_len);
 633
 634	lba_len = min(lba_len+1, 256UL*1024*1024); /* limit to 256 MB */
 635
 636	pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end);
 637
 638
 639	end += lba_len;
 640	if (end < start) /* fix overflow */
 641		end = -1ULL;
 642
 643	pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end);
 644
 645	/* first overlap */
 646	for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
 647		pr_debug("LBA: testing %pR\n", tmp);
 648		if (tmp->start == start)
 649			continue; /* ignore ourself */
 650		if (tmp->end < start)
 651			continue;
 652		if (tmp->start > end)
 653			continue;
 654		if (end >= tmp->start)
 655			end = tmp->start - 1;
 656	}
 657
 658	pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end);
 659
 660	/* return new end */
 661	return end;
 662}
 663
 664#else
 665#define truncate_pat_collision(r,n)  (0)
 666#endif
 667
 668/*
 669** The algorithm is generic code.
 670** But it needs to access local data structures to get the IRQ base.
 671** Could make this a "pci_fixup_irq(bus, region)" but not sure
 672** it's worth it.
 673**
 674** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
 675** Resources aren't allocated until recursive buswalk below HBA is completed.
 676*/
 677static void
 678lba_fixup_bus(struct pci_bus *bus)
 679{
 680	struct pci_dev *dev;
 681#ifdef FBB_SUPPORT
 682	u16 status;
 683#endif
 684	struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
 685
 686	DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
 687		bus, (int)bus->busn_res.start, bus->bridge->platform_data);
 688
 689	/*
 690	** Properly Setup MMIO resources for this bus.
 691	** pci_alloc_primary_bus() mangles this.
 692	*/
 693	if (bus->parent) {
 694		int i;
 695		/* PCI-PCI Bridge */
 696		pci_read_bridge_bases(bus);
 697		for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++)
 698			pci_claim_bridge_resource(bus->self, i);
 
 699	} else {
 700		/* Host-PCI Bridge */
 701		int err;
 702
 703		DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
 704			ldev->hba.io_space.name,
 705			ldev->hba.io_space.start, ldev->hba.io_space.end,
 706			ldev->hba.io_space.flags);
 707		DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
 708			ldev->hba.lmmio_space.name,
 709			ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
 710			ldev->hba.lmmio_space.flags);
 711
 712		err = request_resource(&ioport_resource, &(ldev->hba.io_space));
 713		if (err < 0) {
 714			lba_dump_res(&ioport_resource, 2);
 715			BUG();
 716		}
 717
 718		if (ldev->hba.elmmio_space.flags) {
 719			err = request_resource(&iomem_resource,
 720					&(ldev->hba.elmmio_space));
 721			if (err < 0) {
 722
 723				printk("FAILED: lba_fixup_bus() request for "
 724						"elmmio_space [%lx/%lx]\n",
 725						(long)ldev->hba.elmmio_space.start,
 726						(long)ldev->hba.elmmio_space.end);
 727
 728				/* lba_dump_res(&iomem_resource, 2); */
 729				/* BUG(); */
 730			}
 731		}
 732
 733		if (ldev->hba.lmmio_space.flags) {
 734			err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
 735			if (err < 0) {
 736				printk(KERN_ERR "FAILED: lba_fixup_bus() request for "
 737					"lmmio_space [%lx/%lx]\n",
 738					(long)ldev->hba.lmmio_space.start,
 739					(long)ldev->hba.lmmio_space.end);
 740			}
 741		}
 742
 743#ifdef CONFIG_64BIT
 744		/* GMMIO is  distributed range. Every LBA/Rope gets part it. */
 745		if (ldev->hba.gmmio_space.flags) {
 746			err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
 747			if (err < 0) {
 748				printk("FAILED: lba_fixup_bus() request for "
 749					"gmmio_space [%lx/%lx]\n",
 750					(long)ldev->hba.gmmio_space.start,
 751					(long)ldev->hba.gmmio_space.end);
 752				lba_dump_res(&iomem_resource, 2);
 753				BUG();
 754			}
 755		}
 756#endif
 757
 758	}
 759
 760	list_for_each_entry(dev, &bus->devices, bus_list) {
 761		int i;
 
 762
 763		DBG("lba_fixup_bus() %s\n", pci_name(dev));
 764
 765		/* Virtualize Device/Bridge Resources. */
 766		for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
 767			struct resource *res = &dev->resource[i];
 768
 769			/* If resource not allocated - skip it */
 770			if (!res->start)
 771				continue;
 772
 773			/*
 774			** FIXME: this will result in whinging for devices
 775			** that share expansion ROMs (think quad tulip), but
 776			** isn't harmful.
 777			*/
 778			pci_claim_resource(dev, i);
 779		}
 780
 781#ifdef FBB_SUPPORT
 782		/*
 783		** If one device does not support FBB transfers,
 784		** No one on the bus can be allowed to use them.
 785		*/
 786		(void) pci_read_config_word(dev, PCI_STATUS, &status);
 787		bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
 788#endif
 789
 790                /*
 791		** P2PB's have no IRQs. ignore them.
 792		*/
 793		if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 794			pcibios_init_bridge(dev);
 795			continue;
 796		}
 797
 798		/* Adjust INTERRUPT_LINE for this dev */
 799		iosapic_fixup_irq(ldev->iosapic_obj, dev);
 800	}
 801
 802#ifdef FBB_SUPPORT
 803/* FIXME/REVISIT - finish figuring out to set FBB on both
 804** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
 805** Can't fixup here anyway....garr...
 806*/
 807	if (fbb_enable) {
 808		if (bus->parent) {
 809			u8 control;
 810			/* enable on PPB */
 811			(void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
 812			(void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
 813
 814		} else {
 815			/* enable on LBA */
 816		}
 817		fbb_enable = PCI_COMMAND_FAST_BACK;
 818	}
 819
 820	/* Lastly enable FBB/PERR/SERR on all devices too */
 821	list_for_each_entry(dev, &bus->devices, bus_list) {
 822		(void) pci_read_config_word(dev, PCI_COMMAND, &status);
 823		status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
 824		(void) pci_write_config_word(dev, PCI_COMMAND, status);
 825	}
 826#endif
 827}
 828
 829
 830static struct pci_bios_ops lba_bios_ops = {
 831	.init =		lba_bios_init,
 832	.fixup_bus =	lba_fixup_bus,
 833};
 834
 835
 836
 837
 838/*******************************************************
 839**
 840** LBA Sprockets "I/O Port" Space Accessor Functions
 841**
 842** This set of accessor functions is intended for use with
 843** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
 844**
 845** Many PCI devices don't require use of I/O port space (eg Tulip,
 846** NCR720) since they export the same registers to both MMIO and
 847** I/O port space. In general I/O port space is slower than
 848** MMIO since drivers are designed so PIO writes can be posted.
 849**
 850********************************************************/
 851
 852#define LBA_PORT_IN(size, mask) \
 853static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
 854{ \
 855	u##size t; \
 856	t = READ_REG##size(astro_iop_base + addr); \
 857	DBG_PORT(" 0x%x\n", t); \
 858	return (t); \
 859}
 860
 861LBA_PORT_IN( 8, 3)
 862LBA_PORT_IN(16, 2)
 863LBA_PORT_IN(32, 0)
 864
 865
 866
 867/*
 868** BUG X4107:  Ordering broken - DMA RD return can bypass PIO WR
 869**
 870** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
 871** guarantee non-postable completion semantics - not avoid X4107.
 872** The READ_U32 only guarantees the write data gets to elroy but
 873** out to the PCI bus. We can't read stuff from I/O port space
 874** since we don't know what has side-effects. Attempting to read
 875** from configuration space would be suicidal given the number of
 876** bugs in that elroy functionality.
 877**
 878**      Description:
 879**          DMA read results can improperly pass PIO writes (X4107).  The
 880**          result of this bug is that if a processor modifies a location in
 881**          memory after having issued PIO writes, the PIO writes are not
 882**          guaranteed to be completed before a PCI device is allowed to see
 883**          the modified data in a DMA read.
 884**
 885**          Note that IKE bug X3719 in TR1 IKEs will result in the same
 886**          symptom.
 887**
 888**      Workaround:
 889**          The workaround for this bug is to always follow a PIO write with
 890**          a PIO read to the same bus before starting DMA on that PCI bus.
 891**
 892*/
 893#define LBA_PORT_OUT(size, mask) \
 894static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
 895{ \
 896	DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \
 897	WRITE_REG##size(val, astro_iop_base + addr); \
 898	if (LBA_DEV(d)->hw_rev < 3) \
 899		lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
 900}
 901
 902LBA_PORT_OUT( 8, 3)
 903LBA_PORT_OUT(16, 2)
 904LBA_PORT_OUT(32, 0)
 905
 906
 907static struct pci_port_ops lba_astro_port_ops = {
 908	.inb =	lba_astro_in8,
 909	.inw =	lba_astro_in16,
 910	.inl =	lba_astro_in32,
 911	.outb =	lba_astro_out8,
 912	.outw =	lba_astro_out16,
 913	.outl =	lba_astro_out32
 914};
 915
 916
 917#ifdef CONFIG_64BIT
 918#define PIOP_TO_GMMIO(lba, addr) \
 919	((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
 920
 921/*******************************************************
 922**
 923** LBA PAT "I/O Port" Space Accessor Functions
 924**
 925** This set of accessor functions is intended for use with
 926** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
 927**
 928** This uses the PIOP space located in the first 64MB of GMMIO.
 929** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
 930** bits 1:0 stay the same.  bits 15:2 become 25:12.
 931** Then add the base and we can generate an I/O Port cycle.
 932********************************************************/
 933#undef LBA_PORT_IN
 934#define LBA_PORT_IN(size, mask) \
 935static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
 936{ \
 937	u##size t; \
 938	DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \
 939	t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
 940	DBG_PORT(" 0x%x\n", t); \
 941	return (t); \
 942}
 943
 944LBA_PORT_IN( 8, 3)
 945LBA_PORT_IN(16, 2)
 946LBA_PORT_IN(32, 0)
 947
 948
 949#undef LBA_PORT_OUT
 950#define LBA_PORT_OUT(size, mask) \
 951static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
 952{ \
 953	void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \
 954	DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \
 955	WRITE_REG##size(val, where); \
 956	/* flush the I/O down to the elroy at least */ \
 957	lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
 958}
 959
 960LBA_PORT_OUT( 8, 3)
 961LBA_PORT_OUT(16, 2)
 962LBA_PORT_OUT(32, 0)
 963
 964
 965static struct pci_port_ops lba_pat_port_ops = {
 966	.inb =	lba_pat_in8,
 967	.inw =	lba_pat_in16,
 968	.inl =	lba_pat_in32,
 969	.outb =	lba_pat_out8,
 970	.outw =	lba_pat_out16,
 971	.outl =	lba_pat_out32
 972};
 973
 974
 975
 976/*
 977** make range information from PDC available to PCI subsystem.
 978** We make the PDC call here in order to get the PCI bus range
 979** numbers. The rest will get forwarded in pcibios_fixup_bus().
 980** We don't have a struct pci_bus assigned to us yet.
 981*/
 982static void
 983lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
 984{
 985	unsigned long bytecnt;
 986	long io_count;
 987	long status;	/* PDC return status */
 988	long pa_count;
 989	pdc_pat_cell_mod_maddr_block_t *pa_pdc_cell;	/* PA_VIEW */
 990	pdc_pat_cell_mod_maddr_block_t *io_pdc_cell;	/* IO_VIEW */
 991	int i;
 992
 993	pa_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
 994	if (!pa_pdc_cell)
 995		return;
 996
 997	io_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
 998	if (!io_pdc_cell) {
 999		kfree(pa_pdc_cell);
1000		return;
1001	}
1002
1003	/* return cell module (IO view) */
1004	status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1005				PA_VIEW, pa_pdc_cell);
1006	pa_count = pa_pdc_cell->mod[1];
1007
1008	status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1009				IO_VIEW, io_pdc_cell);
1010	io_count = io_pdc_cell->mod[1];
1011
1012	/* We've already done this once for device discovery...*/
1013	if (status != PDC_OK) {
1014		panic("pdc_pat_cell_module() call failed for LBA!\n");
1015	}
1016
1017	if (PAT_GET_ENTITY(pa_pdc_cell->mod_info) != PAT_ENTITY_LBA) {
1018		panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1019	}
1020
1021	/*
1022	** Inspect the resources PAT tells us about
1023	*/
1024	for (i = 0; i < pa_count; i++) {
1025		struct {
1026			unsigned long type;
1027			unsigned long start;
1028			unsigned long end;	/* aka finish */
1029		} *p, *io;
1030		struct resource *r;
1031
1032		p = (void *) &(pa_pdc_cell->mod[2+i*3]);
1033		io = (void *) &(io_pdc_cell->mod[2+i*3]);
1034
1035		/* Convert the PAT range data to PCI "struct resource" */
1036		switch(p->type & 0xff) {
1037		case PAT_PBNUM:
1038			lba_dev->hba.bus_num.start = p->start;
1039			lba_dev->hba.bus_num.end   = p->end;
1040			lba_dev->hba.bus_num.flags = IORESOURCE_BUS;
1041			break;
1042
1043		case PAT_LMMIO:
1044			/* used to fix up pre-initialized MEM BARs */
1045			if (!lba_dev->hba.lmmio_space.flags) {
1046				unsigned long lba_len;
1047
1048				lba_len = ~READ_REG32(lba_dev->hba.base_addr
1049						+ LBA_LMMIO_MASK);
1050				if ((p->end - p->start) != lba_len)
1051					p->end = extend_lmmio_len(p->start,
1052						p->end, lba_len);
1053
1054				sprintf(lba_dev->hba.lmmio_name,
1055						"PCI%02x LMMIO",
1056						(int)lba_dev->hba.bus_num.start);
1057				lba_dev->hba.lmmio_space_offset = p->start -
1058					io->start;
1059				r = &lba_dev->hba.lmmio_space;
1060				r->name = lba_dev->hba.lmmio_name;
1061			} else if (!lba_dev->hba.elmmio_space.flags) {
1062				sprintf(lba_dev->hba.elmmio_name,
1063						"PCI%02x ELMMIO",
1064						(int)lba_dev->hba.bus_num.start);
1065				r = &lba_dev->hba.elmmio_space;
1066				r->name = lba_dev->hba.elmmio_name;
1067			} else {
1068				printk(KERN_WARNING MODULE_NAME
1069					" only supports 2 LMMIO resources!\n");
1070				break;
1071			}
1072
1073			r->start  = p->start;
1074			r->end    = p->end;
1075			r->flags  = IORESOURCE_MEM;
1076			r->parent = r->sibling = r->child = NULL;
1077			break;
1078
1079		case PAT_GMMIO:
1080			/* MMIO space > 4GB phys addr; for 64-bit BAR */
1081			sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
1082					(int)lba_dev->hba.bus_num.start);
1083			r = &lba_dev->hba.gmmio_space;
1084			r->name  = lba_dev->hba.gmmio_name;
1085			r->start  = p->start;
1086			r->end    = p->end;
1087			r->flags  = IORESOURCE_MEM;
1088			r->parent = r->sibling = r->child = NULL;
1089			break;
1090
1091		case PAT_NPIOP:
1092			printk(KERN_WARNING MODULE_NAME
1093				" range[%d] : ignoring NPIOP (0x%lx)\n",
1094				i, p->start);
1095			break;
1096
1097		case PAT_PIOP:
1098			/*
1099			** Postable I/O port space is per PCI host adapter.
1100			** base of 64MB PIOP region
1101			*/
1102			lba_dev->iop_base = ioremap_nocache(p->start, 64 * 1024 * 1024);
1103
1104			sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1105					(int)lba_dev->hba.bus_num.start);
1106			r = &lba_dev->hba.io_space;
1107			r->name  = lba_dev->hba.io_name;
1108			r->start  = HBA_PORT_BASE(lba_dev->hba.hba_num);
1109			r->end    = r->start + HBA_PORT_SPACE_SIZE - 1;
1110			r->flags  = IORESOURCE_IO;
1111			r->parent = r->sibling = r->child = NULL;
1112			break;
1113
1114		default:
1115			printk(KERN_WARNING MODULE_NAME
1116				" range[%d] : unknown pat range type (0x%lx)\n",
1117				i, p->type & 0xff);
1118			break;
1119		}
1120	}
1121
1122	kfree(pa_pdc_cell);
1123	kfree(io_pdc_cell);
1124}
1125#else
1126/* keep compiler from complaining about missing declarations */
1127#define lba_pat_port_ops lba_astro_port_ops
1128#define lba_pat_resources(pa_dev, lba_dev)
1129#endif	/* CONFIG_64BIT */
1130
1131
1132extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
1133extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
1134
1135
1136static void
1137lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1138{
1139	struct resource *r;
1140	int lba_num;
1141
1142	lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1143
1144	/*
1145	** With "legacy" firmware, the lowest byte of FW_SCRATCH
1146	** represents bus->secondary and the second byte represents
1147	** bus->subsidiary (i.e. highest PPB programmed by firmware).
1148	** PCI bus walk *should* end up with the same result.
1149	** FIXME: But we don't have sanity checks in PCI or LBA.
1150	*/
1151	lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
1152	r = &(lba_dev->hba.bus_num);
1153	r->name = "LBA PCI Busses";
1154	r->start = lba_num & 0xff;
1155	r->end = (lba_num>>8) & 0xff;
1156	r->flags = IORESOURCE_BUS;
1157
1158	/* Set up local PCI Bus resources - we don't need them for
1159	** Legacy boxes but it's nice to see in /proc/iomem.
1160	*/
1161	r = &(lba_dev->hba.lmmio_space);
1162	sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1163					(int)lba_dev->hba.bus_num.start);
1164	r->name  = lba_dev->hba.lmmio_name;
1165
1166#if 1
1167	/* We want the CPU -> IO routing of addresses.
1168	 * The SBA BASE/MASK registers control CPU -> IO routing.
1169	 * Ask SBA what is routed to this rope/LBA.
1170	 */
1171	sba_distributed_lmmio(pa_dev, r);
1172#else
1173	/*
1174	 * The LBA BASE/MASK registers control IO -> System routing.
1175	 *
1176	 * The following code works but doesn't get us what we want.
1177	 * Well, only because firmware (v5.0) on C3000 doesn't program
1178	 * the LBA BASE/MASE registers to be the exact inverse of 
1179	 * the corresponding SBA registers. Other Astro/Pluto
1180	 * based platform firmware may do it right.
1181	 *
1182	 * Should someone want to mess with MSI, they may need to
1183	 * reprogram LBA BASE/MASK registers. Thus preserve the code
1184	 * below until MSI is known to work on C3000/A500/N4000/RP3440.
1185	 *
1186	 * Using the code below, /proc/iomem shows:
1187	 * ...
1188	 * f0000000-f0ffffff : PCI00 LMMIO
1189	 *   f05d0000-f05d0000 : lcd_data
1190	 *   f05d0008-f05d0008 : lcd_cmd
1191	 * f1000000-f1ffffff : PCI01 LMMIO
1192	 * f4000000-f4ffffff : PCI02 LMMIO
1193	 *   f4000000-f4001fff : sym53c8xx
1194	 *   f4002000-f4003fff : sym53c8xx
1195	 *   f4004000-f40043ff : sym53c8xx
1196	 *   f4005000-f40053ff : sym53c8xx
1197	 *   f4007000-f4007fff : ohci_hcd
1198	 *   f4008000-f40083ff : tulip
1199	 * f6000000-f6ffffff : PCI03 LMMIO
1200	 * f8000000-fbffffff : PCI00 ELMMIO
1201	 *   fa100000-fa4fffff : stifb mmio
1202	 *   fb000000-fb1fffff : stifb fb
1203	 *
1204	 * But everything listed under PCI02 actually lives under PCI00.
1205	 * This is clearly wrong.
1206	 *
1207	 * Asking SBA how things are routed tells the correct story:
1208	 * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
1209	 * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
1210	 * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
1211	 * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
1212	 * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
1213	 *
1214	 * Which looks like this in /proc/iomem:
1215	 * f4000000-f47fffff : PCI00 LMMIO
1216	 *   f4000000-f4001fff : sym53c8xx
1217	 *   ...[deteled core devices - same as above]...
1218	 *   f4008000-f40083ff : tulip
1219	 * f4800000-f4ffffff : PCI01 LMMIO
1220	 * f6000000-f67fffff : PCI02 LMMIO
1221	 * f7000000-f77fffff : PCI03 LMMIO
1222	 * f9000000-f9ffffff : PCI02 ELMMIO
1223	 * fa000000-fbffffff : PCI03 ELMMIO
1224	 *   fa100000-fa4fffff : stifb mmio
1225	 *   fb000000-fb1fffff : stifb fb
1226	 *
1227	 * ie all Built-in core are under now correctly under PCI00.
1228	 * The "PCI02 ELMMIO" directed range is for:
1229	 *  +-[02]---03.0  3Dfx Interactive, Inc. Voodoo 2
1230	 *
1231	 * All is well now.
1232	 */
1233	r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
1234	if (r->start & 1) {
1235		unsigned long rsize;
1236
1237		r->flags = IORESOURCE_MEM;
1238		/* mmio_mask also clears Enable bit */
1239		r->start &= mmio_mask;
1240		r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1241		rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
1242
1243		/*
1244		** Each rope only gets part of the distributed range.
1245		** Adjust "window" for this rope.
1246		*/
1247		rsize /= ROPES_PER_IOC;
1248		r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start);
1249		r->end = r->start + rsize;
1250	} else {
1251		r->end = r->start = 0;	/* Not enabled. */
1252	}
1253#endif
1254
1255	/*
1256	** "Directed" ranges are used when the "distributed range" isn't
1257	** sufficient for all devices below a given LBA.  Typically devices
1258	** like graphics cards or X25 may need a directed range when the
1259	** bus has multiple slots (ie multiple devices) or the device
1260	** needs more than the typical 4 or 8MB a distributed range offers.
1261	**
1262	** The main reason for ignoring it now frigging complications.
1263	** Directed ranges may overlap (and have precedence) over
1264	** distributed ranges. Or a distributed range assigned to a unused
1265	** rope may be used by a directed range on a different rope.
1266	** Support for graphics devices may require fixing this
1267	** since they may be assigned a directed range which overlaps
1268	** an existing (but unused portion of) distributed range.
1269	*/
1270	r = &(lba_dev->hba.elmmio_space);
1271	sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1272					(int)lba_dev->hba.bus_num.start);
1273	r->name  = lba_dev->hba.elmmio_name;
1274
1275#if 1
1276	/* See comment which precedes call to sba_directed_lmmio() */
1277	sba_directed_lmmio(pa_dev, r);
1278#else
1279	r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
1280
1281	if (r->start & 1) {
1282		unsigned long rsize;
1283		r->flags = IORESOURCE_MEM;
1284		/* mmio_mask also clears Enable bit */
1285		r->start &= mmio_mask;
1286		r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1287		rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
1288		r->end = r->start + ~rsize;
1289	}
1290#endif
1291
1292	r = &(lba_dev->hba.io_space);
1293	sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1294					(int)lba_dev->hba.bus_num.start);
1295	r->name  = lba_dev->hba.io_name;
1296	r->flags = IORESOURCE_IO;
1297	r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
1298	r->end   = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1299
1300	/* Virtualize the I/O Port space ranges */
1301	lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1302	r->start |= lba_num;
1303	r->end   |= lba_num;
1304}
1305
1306
1307/**************************************************************************
1308**
1309**   LBA initialization code (HW and SW)
1310**
1311**   o identify LBA chip itself
1312**   o initialize LBA chip modes (HardFail)
1313**   o FIXME: initialize DMA hints for reasonable defaults
1314**   o enable configuration functions
1315**   o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1316**
1317**************************************************************************/
1318
1319static int __init
1320lba_hw_init(struct lba_device *d)
1321{
1322	u32 stat;
1323	u32 bus_reset;	/* PDC_PAT_BUG */
1324
1325#if 0
1326	printk(KERN_DEBUG "LBA %lx  STAT_CTL %Lx  ERROR_CFG %Lx  STATUS %Lx DMA_CTL %Lx\n",
1327		d->hba.base_addr,
1328		READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1329		READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1330		READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1331		READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1332	printk(KERN_DEBUG "	ARB mask %Lx  pri %Lx  mode %Lx  mtlt %Lx\n",
1333		READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1334		READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1335		READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1336		READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1337	printk(KERN_DEBUG "	HINT cfg 0x%Lx\n",
1338		READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1339	printk(KERN_DEBUG "	HINT reg ");
1340	{ int i;
1341	for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
1342		printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1343	}
1344	printk("\n");
1345#endif	/* DEBUG_LBA_PAT */
1346
1347#ifdef CONFIG_64BIT
1348/*
1349 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1350 * Only N-Class and up can really make use of Get slot status.
1351 * maybe L-class too but I've never played with it there.
1352 */
1353#endif
1354
1355	/* PDC_PAT_BUG: exhibited in rev 40.48  on L2000 */
1356	bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1357	if (bus_reset) {
1358		printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1359	}
1360
1361	stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1362	if (stat & LBA_SMART_MODE) {
1363		printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1364		stat &= ~LBA_SMART_MODE;
1365		WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1366	}
1367
1368	/* Set HF mode as the default (vs. -1 mode). */
1369        stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1370	WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1371
1372	/*
1373	** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1374	** if it's not already set. If we just cleared the PCI Bus Reset
1375	** signal, wait a bit for the PCI devices to recover and setup.
1376	*/
1377	if (bus_reset)
1378		mdelay(pci_post_reset_delay);
1379
1380	if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1381		/*
1382		** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1383		** B2000/C3600/J6000 also have this problem?
1384		** 
1385		** Elroys with hot pluggable slots don't get configured
1386		** correctly if the slot is empty.  ARB_MASK is set to 0
1387		** and we can't master transactions on the bus if it's
1388		** not at least one. 0x3 enables elroy and first slot.
1389		*/
1390		printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1391		WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1392	}
1393
1394	/*
1395	** FIXME: Hint registers are programmed with default hint
1396	** values by firmware. Hints should be sane even if we
1397	** can't reprogram them the way drivers want.
1398	*/
1399	return 0;
1400}
1401
1402/*
1403 * Unfortunately, when firmware numbers busses, it doesn't take into account
1404 * Cardbus bridges.  So we have to renumber the busses to suit ourselves.
1405 * Elroy/Mercury don't actually know what bus number they're attached to;
1406 * we use bus 0 to indicate the directly attached bus and any other bus
1407 * number will be taken care of by the PCI-PCI bridge.
1408 */
1409static unsigned int lba_next_bus = 0;
1410
1411/*
1412 * Determine if lba should claim this chip (return 0) or not (return 1).
1413 * If so, initialize the chip and tell other partners in crime they
1414 * have work to do.
1415 */
1416static int __init
1417lba_driver_probe(struct parisc_device *dev)
1418{
1419	struct lba_device *lba_dev;
1420	LIST_HEAD(resources);
1421	struct pci_bus *lba_bus;
1422	struct pci_ops *cfg_ops;
1423	u32 func_class;
1424	void *tmp_obj;
1425	char *version;
1426	void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096);
1427	int max;
1428
1429	/* Read HW Rev First */
1430	func_class = READ_REG32(addr + LBA_FCLASS);
1431
1432	if (IS_ELROY(dev)) {	
1433		func_class &= 0xf;
1434		switch (func_class) {
1435		case 0:	version = "TR1.0"; break;
1436		case 1:	version = "TR2.0"; break;
1437		case 2:	version = "TR2.1"; break;
1438		case 3:	version = "TR2.2"; break;
1439		case 4:	version = "TR3.0"; break;
1440		case 5:	version = "TR4.0"; break;
1441		default: version = "TR4+";
1442		}
1443
1444		printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n",
1445		       version, func_class & 0xf, (long)dev->hpa.start);
1446
1447		if (func_class < 2) {
1448			printk(KERN_WARNING "Can't support LBA older than "
1449				"TR2.1 - continuing under adversity.\n");
1450		}
1451
1452#if 0
1453/* Elroy TR4.0 should work with simple algorithm.
1454   But it doesn't.  Still missing something. *sigh*
1455*/
1456		if (func_class > 4) {
1457			cfg_ops = &mercury_cfg_ops;
1458		} else
1459#endif
1460		{
1461			cfg_ops = &elroy_cfg_ops;
1462		}
1463
1464	} else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
1465		int major, minor;
1466
1467		func_class &= 0xff;
1468		major = func_class >> 4, minor = func_class & 0xf;
1469
1470		/* We could use one printk for both Elroy and Mercury,
1471                 * but for the mask for func_class.
1472                 */ 
1473		printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n",
1474		       IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major,
1475		       minor, func_class, (long)dev->hpa.start);
1476
1477		cfg_ops = &mercury_cfg_ops;
1478	} else {
1479		printk(KERN_ERR "Unknown LBA found at 0x%lx\n",
1480			(long)dev->hpa.start);
1481		return -ENODEV;
1482	}
1483
1484	/* Tell I/O SAPIC driver we have a IRQ handler/region. */
1485	tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE);
1486
1487	/* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1488	**	have an IRT entry will get NULL back from iosapic code.
1489	*/
1490	
1491	lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL);
1492	if (!lba_dev) {
1493		printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1494		return(1);
1495	}
1496
1497
1498	/* ---------- First : initialize data we already have --------- */
1499
1500	lba_dev->hw_rev = func_class;
1501	lba_dev->hba.base_addr = addr;
1502	lba_dev->hba.dev = dev;
1503	lba_dev->iosapic_obj = tmp_obj;  /* save interrupt handle */
1504	lba_dev->hba.iommu = sba_get_iommu(dev);  /* get iommu data */
1505	parisc_set_drvdata(dev, lba_dev);
1506
1507	/* ------------ Second : initialize common stuff ---------- */
1508	pci_bios = &lba_bios_ops;
1509	pcibios_register_hba(HBA_DATA(lba_dev));
1510	spin_lock_init(&lba_dev->lba_lock);
1511
1512	if (lba_hw_init(lba_dev))
1513		return(1);
1514
1515	/* ---------- Third : setup I/O Port and MMIO resources  --------- */
1516
1517	if (is_pdc_pat()) {
1518		/* PDC PAT firmware uses PIOP region of GMMIO space. */
1519		pci_port = &lba_pat_port_ops;
1520		/* Go ask PDC PAT what resources this LBA has */
1521		lba_pat_resources(dev, lba_dev);
1522	} else {
1523		if (!astro_iop_base) {
1524			/* Sprockets PDC uses NPIOP region */
1525			astro_iop_base = ioremap_nocache(LBA_PORT_BASE, 64 * 1024);
1526			pci_port = &lba_astro_port_ops;
1527		}
1528
1529		/* Poke the chip a bit for /proc output */
1530		lba_legacy_resources(dev, lba_dev);
1531	}
1532
1533	if (lba_dev->hba.bus_num.start < lba_next_bus)
1534		lba_dev->hba.bus_num.start = lba_next_bus;
1535
1536	/*   Overlaps with elmmio can (and should) fail here.
1537	 *   We will prune (or ignore) the distributed range.
1538	 *
1539	 *   FIXME: SBA code should register all elmmio ranges first.
1540	 *      that would take care of elmmio ranges routed
1541	 *	to a different rope (already discovered) from
1542	 *	getting registered *after* LBA code has already
1543	 *	registered it's distributed lmmio range.
1544	 */
1545	if (truncate_pat_collision(&iomem_resource,
1546				   &(lba_dev->hba.lmmio_space))) {
1547		printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n",
1548				(long)lba_dev->hba.lmmio_space.start,
1549				(long)lba_dev->hba.lmmio_space.end);
1550		lba_dev->hba.lmmio_space.flags = 0;
1551	}
1552
1553	pci_add_resource_offset(&resources, &lba_dev->hba.io_space,
1554				HBA_PORT_BASE(lba_dev->hba.hba_num));
1555	if (lba_dev->hba.elmmio_space.flags)
1556		pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space,
1557					lba_dev->hba.lmmio_space_offset);
1558	if (lba_dev->hba.lmmio_space.flags)
1559		pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space,
1560					lba_dev->hba.lmmio_space_offset);
1561	if (lba_dev->hba.gmmio_space.flags) {
1562		/* Not registering GMMIO space - according to docs it's not
1563		 * even used on HP-UX. */
1564		/* pci_add_resource(&resources, &lba_dev->hba.gmmio_space); */
1565	}
1566
1567	pci_add_resource(&resources, &lba_dev->hba.bus_num);
1568
1569	dev->dev.platform_data = lba_dev;
1570	lba_bus = lba_dev->hba.hba_bus =
1571		pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start,
1572				    cfg_ops, NULL, &resources);
1573	if (!lba_bus) {
1574		pci_free_resource_list(&resources);
1575		return 0;
1576	}
1577
1578	max = pci_scan_child_bus(lba_bus);
1579
1580	/* This is in lieu of calling pci_assign_unassigned_resources() */
1581	if (is_pdc_pat()) {
1582		/* assign resources to un-initialized devices */
1583
1584		DBG_PAT("LBA pci_bus_size_bridges()\n");
1585		pci_bus_size_bridges(lba_bus);
1586
1587		DBG_PAT("LBA pci_bus_assign_resources()\n");
1588		pci_bus_assign_resources(lba_bus);
1589
1590#ifdef DEBUG_LBA_PAT
1591		DBG_PAT("\nLBA PIOP resource tree\n");
1592		lba_dump_res(&lba_dev->hba.io_space, 2);
1593		DBG_PAT("\nLBA LMMIO resource tree\n");
1594		lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1595#endif
1596	}
 
1597
1598	/*
1599	** Once PCI register ops has walked the bus, access to config
1600	** space is restricted. Avoids master aborts on config cycles.
1601	** Early LBA revs go fatal on *any* master abort.
1602	*/
1603	if (cfg_ops == &elroy_cfg_ops) {
1604		lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1605	}
1606
1607	lba_next_bus = max + 1;
1608	pci_bus_add_devices(lba_bus);
1609
1610	/* Whew! Finally done! Tell services we got this one covered. */
1611	return 0;
1612}
1613
1614static struct parisc_device_id lba_tbl[] = {
1615	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
1616	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
1617	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
1618	{ 0, }
1619};
1620
1621static struct parisc_driver lba_driver = {
1622	.name =		MODULE_NAME,
1623	.id_table =	lba_tbl,
1624	.probe =	lba_driver_probe,
1625};
1626
1627/*
1628** One time initialization to let the world know the LBA was found.
1629** Must be called exactly once before pci_init().
1630*/
1631void __init lba_init(void)
1632{
1633	register_parisc_driver(&lba_driver);
1634}
1635
1636/*
1637** Initialize the IBASE/IMASK registers for LBA (Elroy).
1638** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1639** sba_iommu is responsible for locking (none needed at init time).
1640*/
1641void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1642{
1643	void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096);
1644
1645	imask <<= 2;	/* adjust for hints - 2 more bits */
1646
1647	/* Make sure we aren't trying to set bits that aren't writeable. */
1648	WARN_ON((ibase & 0x001fffff) != 0);
1649	WARN_ON((imask & 0x001fffff) != 0);
1650	
1651	DBG("%s() ibase 0x%x imask 0x%x\n", __func__, ibase, imask);
1652	WRITE_REG32( imask, base_addr + LBA_IMASK);
1653	WRITE_REG32( ibase, base_addr + LBA_IBASE);
1654	iounmap(base_addr);
1655}
1656