1/*
   2 *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
   3 *
   4 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   5 *  Copyright (C) 2010 ST-Ericsson SA
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 */
  11#include <linux/module.h>
  12#include <linux/moduleparam.h>
  13#include <linux/init.h>
  14#include <linux/ioport.h>
  15#include <linux/device.h>
  16#include <linux/io.h>
  17#include <linux/interrupt.h>
  18#include <linux/kernel.h>
  19#include <linux/slab.h>
  20#include <linux/delay.h>
  21#include <linux/err.h>
  22#include <linux/highmem.h>
  23#include <linux/log2.h>
  24#include <linux/mmc/pm.h>
  25#include <linux/mmc/host.h>
  26#include <linux/mmc/card.h>
  27#include <linux/mmc/slot-gpio.h>
  28#include <linux/amba/bus.h>
  29#include <linux/clk.h>
  30#include <linux/scatterlist.h>
  31#include <linux/gpio.h>
  32#include <linux/of_gpio.h>
  33#include <linux/regulator/consumer.h>
  34#include <linux/dmaengine.h>
  35#include <linux/dma-mapping.h>
  36#include <linux/amba/mmci.h>
  37#include <linux/pm_runtime.h>
  38#include <linux/types.h>
  39#include <linux/pinctrl/consumer.h>
  40
  41#include <asm/div64.h>
  42#include <asm/io.h>
 
  43
  44#include "mmci.h"
  45#include "mmci_qcom_dml.h"
  46
  47#define DRIVER_NAME "mmci-pl18x"
  48
  49static unsigned int fmax = 515633;
  50
  51/**
  52 * struct variant_data - MMCI variant-specific quirks
  53 * @clkreg: default value for MCICLOCK register
  54 * @clkreg_enable: enable value for MMCICLOCK register
  55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
  56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
  57 * @datalength_bits: number of bits in the MMCIDATALENGTH register
  58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
  59 *	      is asserted (likewise for RX)
  60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
  61 *		  is asserted (likewise for RX)
  62 * @data_cmd_enable: enable value for data commands.
  63 * @st_sdio: enable ST specific SDIO logic
  64 * @st_clkdiv: true if using a ST-specific clock divider algorithm
  65 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
  66 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
  67 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
  68 *		     register
  69 * @datactrl_mask_sdio: SDIO enable mask in datactrl register
  70 * @pwrreg_powerup: power up value for MMCIPOWER register
  71 * @f_max: maximum clk frequency supported by the controller.
  72 * @signal_direction: input/out direction of bus signals can be indicated
  73 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
  74 * @busy_detect: true if busy detection on dat0 is supported
  75 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
  76 * @explicit_mclk_control: enable explicit mclk control in driver.
  77 * @qcom_fifo: enables qcom specific fifo pio read logic.
  78 * @qcom_dml: enables qcom specific dma glue for dma transfers.
  79 * @reversed_irq_handling: handle data irq before cmd irq.
  80 */
  81struct variant_data {
  82	unsigned int		clkreg;
  83	unsigned int		clkreg_enable;
  84	unsigned int		clkreg_8bit_bus_enable;
  85	unsigned int		clkreg_neg_edge_enable;
  86	unsigned int		datalength_bits;
  87	unsigned int		fifosize;
  88	unsigned int		fifohalfsize;
  89	unsigned int		data_cmd_enable;
  90	unsigned int		datactrl_mask_ddrmode;
  91	unsigned int		datactrl_mask_sdio;
  92	bool			st_sdio;
  93	bool			st_clkdiv;
  94	bool			blksz_datactrl16;
  95	bool			blksz_datactrl4;
  96	u32			pwrreg_powerup;
  97	u32			f_max;
  98	bool			signal_direction;
  99	bool			pwrreg_clkgate;
 100	bool			busy_detect;
 101	bool			pwrreg_nopower;
 102	bool			explicit_mclk_control;
 103	bool			qcom_fifo;
 104	bool			qcom_dml;
 105	bool			reversed_irq_handling;
 106};
 107
 108static struct variant_data variant_arm = {
 109	.fifosize		= 16 * 4,
 110	.fifohalfsize		= 8 * 4,
 111	.datalength_bits	= 16,
 112	.pwrreg_powerup		= MCI_PWR_UP,
 113	.f_max			= 100000000,
 114	.reversed_irq_handling	= true,
 115};
 116
 117static struct variant_data variant_arm_extended_fifo = {
 118	.fifosize		= 128 * 4,
 119	.fifohalfsize		= 64 * 4,
 120	.datalength_bits	= 16,
 121	.pwrreg_powerup		= MCI_PWR_UP,
 122	.f_max			= 100000000,
 123};
 124
 125static struct variant_data variant_arm_extended_fifo_hwfc = {
 126	.fifosize		= 128 * 4,
 127	.fifohalfsize		= 64 * 4,
 128	.clkreg_enable		= MCI_ARM_HWFCEN,
 129	.datalength_bits	= 16,
 130	.pwrreg_powerup		= MCI_PWR_UP,
 131	.f_max			= 100000000,
 132};
 133
 134static struct variant_data variant_u300 = {
 135	.fifosize		= 16 * 4,
 136	.fifohalfsize		= 8 * 4,
 137	.clkreg_enable		= MCI_ST_U300_HWFCEN,
 138	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 139	.datalength_bits	= 16,
 140	.datactrl_mask_sdio	= MCI_ST_DPSM_SDIOEN,
 141	.st_sdio			= true,
 142	.pwrreg_powerup		= MCI_PWR_ON,
 143	.f_max			= 100000000,
 144	.signal_direction	= true,
 145	.pwrreg_clkgate		= true,
 146	.pwrreg_nopower		= true,
 147};
 148
 149static struct variant_data variant_nomadik = {
 150	.fifosize		= 16 * 4,
 151	.fifohalfsize		= 8 * 4,
 152	.clkreg			= MCI_CLK_ENABLE,
 153	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 154	.datalength_bits	= 24,
 155	.datactrl_mask_sdio	= MCI_ST_DPSM_SDIOEN,
 156	.st_sdio		= true,
 157	.st_clkdiv		= true,
 158	.pwrreg_powerup		= MCI_PWR_ON,
 159	.f_max			= 100000000,
 160	.signal_direction	= true,
 161	.pwrreg_clkgate		= true,
 162	.pwrreg_nopower		= true,
 163};
 164
 165static struct variant_data variant_ux500 = {
 166	.fifosize		= 30 * 4,
 167	.fifohalfsize		= 8 * 4,
 168	.clkreg			= MCI_CLK_ENABLE,
 169	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
 170	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 171	.clkreg_neg_edge_enable	= MCI_ST_UX500_NEG_EDGE,
 172	.datalength_bits	= 24,
 173	.datactrl_mask_sdio	= MCI_ST_DPSM_SDIOEN,
 174	.st_sdio		= true,
 175	.st_clkdiv		= true,
 176	.pwrreg_powerup		= MCI_PWR_ON,
 177	.f_max			= 100000000,
 178	.signal_direction	= true,
 179	.pwrreg_clkgate		= true,
 180	.busy_detect		= true,
 181	.pwrreg_nopower		= true,
 182};
 183
 184static struct variant_data variant_ux500v2 = {
 185	.fifosize		= 30 * 4,
 186	.fifohalfsize		= 8 * 4,
 187	.clkreg			= MCI_CLK_ENABLE,
 188	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
 189	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
 190	.clkreg_neg_edge_enable	= MCI_ST_UX500_NEG_EDGE,
 191	.datactrl_mask_ddrmode	= MCI_ST_DPSM_DDRMODE,
 192	.datalength_bits	= 24,
 193	.datactrl_mask_sdio	= MCI_ST_DPSM_SDIOEN,
 194	.st_sdio		= true,
 195	.st_clkdiv		= true,
 196	.blksz_datactrl16	= true,
 197	.pwrreg_powerup		= MCI_PWR_ON,
 198	.f_max			= 100000000,
 199	.signal_direction	= true,
 200	.pwrreg_clkgate		= true,
 201	.busy_detect		= true,
 202	.pwrreg_nopower		= true,
 203};
 204
 205static struct variant_data variant_qcom = {
 206	.fifosize		= 16 * 4,
 207	.fifohalfsize		= 8 * 4,
 208	.clkreg			= MCI_CLK_ENABLE,
 209	.clkreg_enable		= MCI_QCOM_CLK_FLOWENA |
 210				  MCI_QCOM_CLK_SELECT_IN_FBCLK,
 211	.clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
 212	.datactrl_mask_ddrmode	= MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
 213	.data_cmd_enable	= MCI_QCOM_CSPM_DATCMD,
 214	.blksz_datactrl4	= true,
 215	.datalength_bits	= 24,
 216	.pwrreg_powerup		= MCI_PWR_UP,
 217	.f_max			= 208000000,
 218	.explicit_mclk_control	= true,
 219	.qcom_fifo		= true,
 220	.qcom_dml		= true,
 221};
 222
 223static int mmci_card_busy(struct mmc_host *mmc)
 224{
 225	struct mmci_host *host = mmc_priv(mmc);
 226	unsigned long flags;
 227	int busy = 0;
 228
 229	pm_runtime_get_sync(mmc_dev(mmc));
 230
 231	spin_lock_irqsave(&host->lock, flags);
 232	if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
 233		busy = 1;
 234	spin_unlock_irqrestore(&host->lock, flags);
 235
 236	pm_runtime_mark_last_busy(mmc_dev(mmc));
 237	pm_runtime_put_autosuspend(mmc_dev(mmc));
 238
 239	return busy;
 240}
 241
 242/*
 243 * Validate mmc prerequisites
 244 */
 245static int mmci_validate_data(struct mmci_host *host,
 246			      struct mmc_data *data)
 247{
 248	if (!data)
 249		return 0;
 250
 251	if (!is_power_of_2(data->blksz)) {
 252		dev_err(mmc_dev(host->mmc),
 253			"unsupported block size (%d bytes)\n", data->blksz);
 254		return -EINVAL;
 255	}
 256
 257	return 0;
 258}
 259
 260static void mmci_reg_delay(struct mmci_host *host)
 261{
 262	/*
 263	 * According to the spec, at least three feedback clock cycles
 264	 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
 265	 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
 266	 * Worst delay time during card init is at 100 kHz => 30 us.
 267	 * Worst delay time when up and running is at 25 MHz => 120 ns.
 268	 */
 269	if (host->cclk < 25000000)
 270		udelay(30);
 271	else
 272		ndelay(120);
 273}
 274
 275/*
 276 * This must be called with host->lock held
 277 */
 278static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
 279{
 280	if (host->clk_reg != clk) {
 281		host->clk_reg = clk;
 282		writel(clk, host->base + MMCICLOCK);
 283	}
 284}
 285
 286/*
 287 * This must be called with host->lock held
 288 */
 289static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
 290{
 291	if (host->pwr_reg != pwr) {
 292		host->pwr_reg = pwr;
 293		writel(pwr, host->base + MMCIPOWER);
 294	}
 295}
 296
 297/*
 298 * This must be called with host->lock held
 299 */
 300static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
 301{
 302	/* Keep ST Micro busy mode if enabled */
 303	datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
 304
 305	if (host->datactrl_reg != datactrl) {
 306		host->datactrl_reg = datactrl;
 307		writel(datactrl, host->base + MMCIDATACTRL);
 308	}
 309}
 310
 311/*
 312 * This must be called with host->lock held
 313 */
 314static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 315{
 316	struct variant_data *variant = host->variant;
 317	u32 clk = variant->clkreg;
 318
 319	/* Make sure cclk reflects the current calculated clock */
 320	host->cclk = 0;
 321
 322	if (desired) {
 323		if (variant->explicit_mclk_control) {
 324			host->cclk = host->mclk;
 325		} else if (desired >= host->mclk) {
 326			clk = MCI_CLK_BYPASS;
 327			if (variant->st_clkdiv)
 328				clk |= MCI_ST_UX500_NEG_EDGE;
 329			host->cclk = host->mclk;
 330		} else if (variant->st_clkdiv) {
 331			/*
 332			 * DB8500 TRM says f = mclk / (clkdiv + 2)
 333			 * => clkdiv = (mclk / f) - 2
 334			 * Round the divider up so we don't exceed the max
 335			 * frequency
 336			 */
 337			clk = DIV_ROUND_UP(host->mclk, desired) - 2;
 338			if (clk >= 256)
 339				clk = 255;
 340			host->cclk = host->mclk / (clk + 2);
 341		} else {
 342			/*
 343			 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
 344			 * => clkdiv = mclk / (2 * f) - 1
 345			 */
 346			clk = host->mclk / (2 * desired) - 1;
 347			if (clk >= 256)
 348				clk = 255;
 349			host->cclk = host->mclk / (2 * (clk + 1));
 350		}
 351
 352		clk |= variant->clkreg_enable;
 353		clk |= MCI_CLK_ENABLE;
 354		/* This hasn't proven to be worthwhile */
 355		/* clk |= MCI_CLK_PWRSAVE; */
 356	}
 357
 358	/* Set actual clock for debug */
 359	host->mmc->actual_clock = host->cclk;
 360
 361	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
 362		clk |= MCI_4BIT_BUS;
 363	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
 364		clk |= variant->clkreg_8bit_bus_enable;
 365
 366	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
 367	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
 368		clk |= variant->clkreg_neg_edge_enable;
 369
 370	mmci_write_clkreg(host, clk);
 371}
 372
 373static void
 374mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
 375{
 376	writel(0, host->base + MMCICOMMAND);
 377
 378	BUG_ON(host->data);
 379
 380	host->mrq = NULL;
 381	host->cmd = NULL;
 382
 383	mmc_request_done(host->mmc, mrq);
 384
 385	pm_runtime_mark_last_busy(mmc_dev(host->mmc));
 386	pm_runtime_put_autosuspend(mmc_dev(host->mmc));
 387}
 388
 389static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
 390{
 391	void __iomem *base = host->base;
 392
 393	if (host->singleirq) {
 394		unsigned int mask0 = readl(base + MMCIMASK0);
 395
 396		mask0 &= ~MCI_IRQ1MASK;
 397		mask0 |= mask;
 398
 399		writel(mask0, base + MMCIMASK0);
 400	}
 401
 402	writel(mask, base + MMCIMASK1);
 403}
 404
 405static void mmci_stop_data(struct mmci_host *host)
 406{
 407	mmci_write_datactrlreg(host, 0);
 408	mmci_set_mask1(host, 0);
 409	host->data = NULL;
 410}
 411
 412static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
 413{
 414	unsigned int flags = SG_MITER_ATOMIC;
 415
 416	if (data->flags & MMC_DATA_READ)
 417		flags |= SG_MITER_TO_SG;
 418	else
 419		flags |= SG_MITER_FROM_SG;
 420
 421	sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 422}
 423
 424/*
 425 * All the DMA operation mode stuff goes inside this ifdef.
 426 * This assumes that you have a generic DMA device interface,
 427 * no custom DMA interfaces are supported.
 428 */
 429#ifdef CONFIG_DMA_ENGINE
 430static void mmci_dma_setup(struct mmci_host *host)
 431{
 
 432	const char *rxname, *txname;
 433	struct variant_data *variant = host->variant;
 434
 435	host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
 436	host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
 
 
 437
 438	/* initialize pre request cookie */
 439	host->next_data.cookie = 1;
 440
 
 
 
 
 441	/*
 442	 * If only an RX channel is specified, the driver will
 443	 * attempt to use it bidirectionally, however if it is
 444	 * is specified but cannot be located, DMA will be disabled.
 445	 */
 446	if (host->dma_rx_channel && !host->dma_tx_channel)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 447		host->dma_tx_channel = host->dma_rx_channel;
 
 448
 449	if (host->dma_rx_channel)
 450		rxname = dma_chan_name(host->dma_rx_channel);
 451	else
 452		rxname = "none";
 453
 454	if (host->dma_tx_channel)
 455		txname = dma_chan_name(host->dma_tx_channel);
 456	else
 457		txname = "none";
 458
 459	dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
 460		 rxname, txname);
 461
 462	/*
 463	 * Limit the maximum segment size in any SG entry according to
 464	 * the parameters of the DMA engine device.
 465	 */
 466	if (host->dma_tx_channel) {
 467		struct device *dev = host->dma_tx_channel->device->dev;
 468		unsigned int max_seg_size = dma_get_max_seg_size(dev);
 469
 470		if (max_seg_size < host->mmc->max_seg_size)
 471			host->mmc->max_seg_size = max_seg_size;
 472	}
 473	if (host->dma_rx_channel) {
 474		struct device *dev = host->dma_rx_channel->device->dev;
 475		unsigned int max_seg_size = dma_get_max_seg_size(dev);
 476
 477		if (max_seg_size < host->mmc->max_seg_size)
 478			host->mmc->max_seg_size = max_seg_size;
 479	}
 480
 481	if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel)
 482		if (dml_hw_init(host, host->mmc->parent->of_node))
 483			variant->qcom_dml = false;
 484}
 485
 486/*
 487 * This is used in or so inline it
 488 * so it can be discarded.
 489 */
 490static inline void mmci_dma_release(struct mmci_host *host)
 491{
 
 
 492	if (host->dma_rx_channel)
 493		dma_release_channel(host->dma_rx_channel);
 494	if (host->dma_tx_channel)
 495		dma_release_channel(host->dma_tx_channel);
 496	host->dma_rx_channel = host->dma_tx_channel = NULL;
 497}
 498
 499static void mmci_dma_data_error(struct mmci_host *host)
 500{
 501	dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
 502	dmaengine_terminate_all(host->dma_current);
 503	host->dma_current = NULL;
 504	host->dma_desc_current = NULL;
 505	host->data->host_cookie = 0;
 506}
 507
 508static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
 509{
 510	struct dma_chan *chan;
 511	enum dma_data_direction dir;
 512
 513	if (data->flags & MMC_DATA_READ) {
 514		dir = DMA_FROM_DEVICE;
 515		chan = host->dma_rx_channel;
 516	} else {
 517		dir = DMA_TO_DEVICE;
 518		chan = host->dma_tx_channel;
 519	}
 520
 521	dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
 522}
 523
 524static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
 525{
 526	u32 status;
 527	int i;
 528
 529	/* Wait up to 1ms for the DMA to complete */
 530	for (i = 0; ; i++) {
 531		status = readl(host->base + MMCISTATUS);
 532		if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
 533			break;
 534		udelay(10);
 535	}
 536
 537	/*
 538	 * Check to see whether we still have some data left in the FIFO -
 539	 * this catches DMA controllers which are unable to monitor the
 540	 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
 541	 * contiguous buffers.  On TX, we'll get a FIFO underrun error.
 542	 */
 543	if (status & MCI_RXDATAAVLBLMASK) {
 544		mmci_dma_data_error(host);
 545		if (!data->error)
 546			data->error = -EIO;
 547	}
 548
 
 
 
 
 
 
 549	if (!data->host_cookie)
 550		mmci_dma_unmap(host, data);
 551
 552	/*
 553	 * Use of DMA with scatter-gather is impossible.
 554	 * Give up with DMA and switch back to PIO mode.
 555	 */
 556	if (status & MCI_RXDATAAVLBLMASK) {
 557		dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
 558		mmci_dma_release(host);
 559	}
 
 560
 561	host->dma_current = NULL;
 562	host->dma_desc_current = NULL;
 
 
 563}
 564
 565/* prepares DMA channel and DMA descriptor, returns non-zero on failure */
 566static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
 567				struct dma_chan **dma_chan,
 568				struct dma_async_tx_descriptor **dma_desc)
 569{
 570	struct variant_data *variant = host->variant;
 571	struct dma_slave_config conf = {
 572		.src_addr = host->phybase + MMCIFIFO,
 573		.dst_addr = host->phybase + MMCIFIFO,
 574		.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 575		.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 576		.src_maxburst = variant->fifohalfsize >> 2, /* # of words */
 577		.dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
 578		.device_fc = false,
 579	};
 580	struct dma_chan *chan;
 581	struct dma_device *device;
 582	struct dma_async_tx_descriptor *desc;
 583	enum dma_data_direction buffer_dirn;
 584	int nr_sg;
 585	unsigned long flags = DMA_CTRL_ACK;
 
 
 
 
 
 
 
 
 
 586
 587	if (data->flags & MMC_DATA_READ) {
 588		conf.direction = DMA_DEV_TO_MEM;
 589		buffer_dirn = DMA_FROM_DEVICE;
 590		chan = host->dma_rx_channel;
 591	} else {
 592		conf.direction = DMA_MEM_TO_DEV;
 593		buffer_dirn = DMA_TO_DEVICE;
 594		chan = host->dma_tx_channel;
 595	}
 596
 597	/* If there's no DMA channel, fall back to PIO */
 598	if (!chan)
 599		return -EINVAL;
 600
 601	/* If less than or equal to the fifo size, don't bother with DMA */
 602	if (data->blksz * data->blocks <= variant->fifosize)
 603		return -EINVAL;
 604
 605	device = chan->device;
 606	nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
 607	if (nr_sg == 0)
 608		return -EINVAL;
 609
 610	if (host->variant->qcom_dml)
 611		flags |= DMA_PREP_INTERRUPT;
 612
 613	dmaengine_slave_config(chan, &conf);
 614	desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
 615					    conf.direction, flags);
 616	if (!desc)
 617		goto unmap_exit;
 618
 619	*dma_chan = chan;
 620	*dma_desc = desc;
 
 
 
 
 
 621
 622	return 0;
 623
 624 unmap_exit:
 
 
 625	dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
 626	return -ENOMEM;
 627}
 628
 629static inline int mmci_dma_prep_data(struct mmci_host *host,
 630				     struct mmc_data *data)
 631{
 632	/* Check if next job is already prepared. */
 633	if (host->dma_current && host->dma_desc_current)
 634		return 0;
 635
 636	/* No job were prepared thus do it now. */
 637	return __mmci_dma_prep_data(host, data, &host->dma_current,
 638				    &host->dma_desc_current);
 639}
 640
 641static inline int mmci_dma_prep_next(struct mmci_host *host,
 642				     struct mmc_data *data)
 643{
 644	struct mmci_host_next *nd = &host->next_data;
 645	return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
 646}
 647
 648static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
 649{
 650	int ret;
 651	struct mmc_data *data = host->data;
 652
 653	ret = mmci_dma_prep_data(host, host->data);
 654	if (ret)
 655		return ret;
 656
 657	/* Okay, go for it. */
 658	dev_vdbg(mmc_dev(host->mmc),
 659		 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
 660		 data->sg_len, data->blksz, data->blocks, data->flags);
 661	dmaengine_submit(host->dma_desc_current);
 662	dma_async_issue_pending(host->dma_current);
 663
 664	if (host->variant->qcom_dml)
 665		dml_start_xfer(host, data);
 666
 667	datactrl |= MCI_DPSM_DMAENABLE;
 668
 669	/* Trigger the DMA transfer */
 670	mmci_write_datactrlreg(host, datactrl);
 671
 672	/*
 673	 * Let the MMCI say when the data is ended and it's time
 674	 * to fire next DMA request. When that happens, MMCI will
 675	 * call mmci_data_end()
 676	 */
 677	writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
 678	       host->base + MMCIMASK0);
 679	return 0;
 680}
 681
 682static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
 683{
 684	struct mmci_host_next *next = &host->next_data;
 685
 686	WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
 687	WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
 
 
 
 
 
 
 
 688
 689	host->dma_desc_current = next->dma_desc;
 690	host->dma_current = next->dma_chan;
 
 691	next->dma_desc = NULL;
 692	next->dma_chan = NULL;
 693}
 694
 695static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
 696			     bool is_first_req)
 697{
 698	struct mmci_host *host = mmc_priv(mmc);
 699	struct mmc_data *data = mrq->data;
 700	struct mmci_host_next *nd = &host->next_data;
 701
 702	if (!data)
 703		return;
 704
 705	BUG_ON(data->host_cookie);
 706
 707	if (mmci_validate_data(host, data))
 708		return;
 
 709
 710	if (!mmci_dma_prep_next(host, data))
 711		data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
 
 
 
 
 
 
 712}
 713
 714static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
 715			      int err)
 716{
 717	struct mmci_host *host = mmc_priv(mmc);
 718	struct mmc_data *data = mrq->data;
 
 
 719
 720	if (!data || !data->host_cookie)
 721		return;
 722
 723	mmci_dma_unmap(host, data);
 724
 725	if (err) {
 726		struct mmci_host_next *next = &host->next_data;
 727		struct dma_chan *chan;
 728		if (data->flags & MMC_DATA_READ)
 729			chan = host->dma_rx_channel;
 730		else
 731			chan = host->dma_tx_channel;
 732		dmaengine_terminate_all(chan);
 733
 734		if (host->dma_desc_current == next->dma_desc)
 735			host->dma_desc_current = NULL;
 736
 737		if (host->dma_current == next->dma_chan)
 738			host->dma_current = NULL;
 739
 740		next->dma_desc = NULL;
 741		next->dma_chan = NULL;
 742		data->host_cookie = 0;
 
 
 
 
 
 743	}
 744}
 745
 746#else
 747/* Blank functions if the DMA engine is not available */
 748static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
 749{
 750}
 751static inline void mmci_dma_setup(struct mmci_host *host)
 752{
 753}
 754
 755static inline void mmci_dma_release(struct mmci_host *host)
 756{
 757}
 758
 759static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
 760{
 761}
 762
 763static inline void mmci_dma_finalize(struct mmci_host *host,
 764				     struct mmc_data *data)
 765{
 766}
 767
 768static inline void mmci_dma_data_error(struct mmci_host *host)
 769{
 770}
 771
 772static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
 773{
 774	return -ENOSYS;
 775}
 776
 777#define mmci_pre_request NULL
 778#define mmci_post_request NULL
 779
 780#endif
 781
 782static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 783{
 784	struct variant_data *variant = host->variant;
 785	unsigned int datactrl, timeout, irqmask;
 786	unsigned long long clks;
 787	void __iomem *base;
 788	int blksz_bits;
 789
 790	dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
 791		data->blksz, data->blocks, data->flags);
 792
 793	host->data = data;
 794	host->size = data->blksz * data->blocks;
 795	data->bytes_xfered = 0;
 796
 797	clks = (unsigned long long)data->timeout_ns * host->cclk;
 798	do_div(clks, NSEC_PER_SEC);
 799
 800	timeout = data->timeout_clks + (unsigned int)clks;
 801
 802	base = host->base;
 803	writel(timeout, base + MMCIDATATIMER);
 804	writel(host->size, base + MMCIDATALENGTH);
 805
 806	blksz_bits = ffs(data->blksz) - 1;
 807	BUG_ON(1 << blksz_bits != data->blksz);
 808
 809	if (variant->blksz_datactrl16)
 810		datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
 811	else if (variant->blksz_datactrl4)
 812		datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
 813	else
 814		datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
 815
 816	if (data->flags & MMC_DATA_READ)
 817		datactrl |= MCI_DPSM_DIRECTION;
 818
 819	if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
 820		u32 clk;
 821
 822		datactrl |= variant->datactrl_mask_sdio;
 823
 824		/*
 825		 * The ST Micro variant for SDIO small write transfers
 826		 * needs to have clock H/W flow control disabled,
 827		 * otherwise the transfer will not start. The threshold
 828		 * depends on the rate of MCLK.
 829		 */
 830		if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
 831		    (host->size < 8 ||
 832		     (host->size <= 8 && host->mclk > 50000000)))
 833			clk = host->clk_reg & ~variant->clkreg_enable;
 834		else
 835			clk = host->clk_reg | variant->clkreg_enable;
 836
 837		mmci_write_clkreg(host, clk);
 838	}
 839
 840	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
 841	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
 842		datactrl |= variant->datactrl_mask_ddrmode;
 843
 844	/*
 845	 * Attempt to use DMA operation mode, if this
 846	 * should fail, fall back to PIO mode
 847	 */
 848	if (!mmci_dma_start_data(host, datactrl))
 849		return;
 850
 851	/* IRQ mode, map the SG list for CPU reading/writing */
 852	mmci_init_sg(host, data);
 853
 854	if (data->flags & MMC_DATA_READ) {
 855		irqmask = MCI_RXFIFOHALFFULLMASK;
 856
 857		/*
 858		 * If we have less than the fifo 'half-full' threshold to
 859		 * transfer, trigger a PIO interrupt as soon as any data
 860		 * is available.
 861		 */
 862		if (host->size < variant->fifohalfsize)
 863			irqmask |= MCI_RXDATAAVLBLMASK;
 864	} else {
 865		/*
 866		 * We don't actually need to include "FIFO empty" here
 867		 * since its implicit in "FIFO half empty".
 868		 */
 869		irqmask = MCI_TXFIFOHALFEMPTYMASK;
 870	}
 871
 872	mmci_write_datactrlreg(host, datactrl);
 873	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
 874	mmci_set_mask1(host, irqmask);
 875}
 876
 877static void
 878mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
 879{
 880	void __iomem *base = host->base;
 881
 882	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
 883	    cmd->opcode, cmd->arg, cmd->flags);
 884
 885	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
 886		writel(0, base + MMCICOMMAND);
 887		mmci_reg_delay(host);
 888	}
 889
 890	c |= cmd->opcode | MCI_CPSM_ENABLE;
 891	if (cmd->flags & MMC_RSP_PRESENT) {
 892		if (cmd->flags & MMC_RSP_136)
 893			c |= MCI_CPSM_LONGRSP;
 894		c |= MCI_CPSM_RESPONSE;
 895	}
 896	if (/*interrupt*/0)
 897		c |= MCI_CPSM_INTERRUPT;
 898
 899	if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
 900		c |= host->variant->data_cmd_enable;
 901
 902	host->cmd = cmd;
 903
 904	writel(cmd->arg, base + MMCIARGUMENT);
 905	writel(c, base + MMCICOMMAND);
 906}
 907
 908static void
 909mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 910	      unsigned int status)
 911{
 912	/* Make sure we have data to handle */
 913	if (!data)
 914		return;
 915
 916	/* First check for errors */
 917	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
 918		      MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
 919		u32 remain, success;
 920
 921		/* Terminate the DMA transfer */
 922		if (dma_inprogress(host)) {
 923			mmci_dma_data_error(host);
 924			mmci_dma_unmap(host, data);
 925		}
 926
 927		/*
 928		 * Calculate how far we are into the transfer.  Note that
 929		 * the data counter gives the number of bytes transferred
 930		 * on the MMC bus, not on the host side.  On reads, this
 931		 * can be as much as a FIFO-worth of data ahead.  This
 932		 * matters for FIFO overruns only.
 933		 */
 934		remain = readl(host->base + MMCIDATACNT);
 935		success = data->blksz * data->blocks - remain;
 936
 937		dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
 938			status, success);
 939		if (status & MCI_DATACRCFAIL) {
 940			/* Last block was not successful */
 941			success -= 1;
 942			data->error = -EILSEQ;
 943		} else if (status & MCI_DATATIMEOUT) {
 944			data->error = -ETIMEDOUT;
 945		} else if (status & MCI_STARTBITERR) {
 946			data->error = -ECOMM;
 947		} else if (status & MCI_TXUNDERRUN) {
 948			data->error = -EIO;
 949		} else if (status & MCI_RXOVERRUN) {
 950			if (success > host->variant->fifosize)
 951				success -= host->variant->fifosize;
 952			else
 953				success = 0;
 954			data->error = -EIO;
 955		}
 956		data->bytes_xfered = round_down(success, data->blksz);
 957	}
 958
 959	if (status & MCI_DATABLOCKEND)
 960		dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
 961
 962	if (status & MCI_DATAEND || data->error) {
 963		if (dma_inprogress(host))
 964			mmci_dma_finalize(host, data);
 965		mmci_stop_data(host);
 966
 967		if (!data->error)
 968			/* The error clause is handled above, success! */
 969			data->bytes_xfered = data->blksz * data->blocks;
 970
 971		if (!data->stop || host->mrq->sbc) {
 972			mmci_request_end(host, data->mrq);
 973		} else {
 974			mmci_start_command(host, data->stop, 0);
 975		}
 976	}
 977}
 978
 979static void
 980mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 981	     unsigned int status)
 982{
 983	void __iomem *base = host->base;
 984	bool sbc, busy_resp;
 985
 986	if (!cmd)
 987		return;
 988
 989	sbc = (cmd == host->mrq->sbc);
 990	busy_resp = host->variant->busy_detect && (cmd->flags & MMC_RSP_BUSY);
 991
 992	if (!((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|
 993		MCI_CMDSENT|MCI_CMDRESPEND)))
 994		return;
 995
 996	/* Check if we need to wait for busy completion. */
 997	if (host->busy_status && (status & MCI_ST_CARDBUSY))
 998		return;
 999
1000	/* Enable busy completion if needed and supported. */
1001	if (!host->busy_status && busy_resp &&
1002		!(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1003		(readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) {
1004		writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND,
1005			base + MMCIMASK0);
1006		host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND);
1007		return;
1008	}
1009
1010	/* At busy completion, mask the IRQ and complete the request. */
1011	if (host->busy_status) {
1012		writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND,
1013			base + MMCIMASK0);
1014		host->busy_status = 0;
1015	}
1016
1017	host->cmd = NULL;
1018
1019	if (status & MCI_CMDTIMEOUT) {
1020		cmd->error = -ETIMEDOUT;
1021	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1022		cmd->error = -EILSEQ;
1023	} else {
1024		cmd->resp[0] = readl(base + MMCIRESPONSE0);
1025		cmd->resp[1] = readl(base + MMCIRESPONSE1);
1026		cmd->resp[2] = readl(base + MMCIRESPONSE2);
1027		cmd->resp[3] = readl(base + MMCIRESPONSE3);
1028	}
1029
1030	if ((!sbc && !cmd->data) || cmd->error) {
1031		if (host->data) {
1032			/* Terminate the DMA transfer */
1033			if (dma_inprogress(host)) {
1034				mmci_dma_data_error(host);
1035				mmci_dma_unmap(host, host->data);
1036			}
1037			mmci_stop_data(host);
1038		}
1039		mmci_request_end(host, host->mrq);
1040	} else if (sbc) {
1041		mmci_start_command(host, host->mrq->cmd, 0);
1042	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
1043		mmci_start_data(host, cmd->data);
1044	}
1045}
1046
1047static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1048{
1049	return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1050}
1051
1052static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1053{
1054	/*
1055	 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1056	 * from the fifo range should be used
1057	 */
1058	if (status & MCI_RXFIFOHALFFULL)
1059		return host->variant->fifohalfsize;
1060	else if (status & MCI_RXDATAAVLBL)
1061		return 4;
1062
1063	return 0;
1064}
1065
1066static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1067{
1068	void __iomem *base = host->base;
1069	char *ptr = buffer;
1070	u32 status = readl(host->base + MMCISTATUS);
1071	int host_remain = host->size;
1072
1073	do {
1074		int count = host->get_rx_fifocnt(host, status, host_remain);
1075
1076		if (count > remain)
1077			count = remain;
1078
1079		if (count <= 0)
1080			break;
1081
1082		/*
1083		 * SDIO especially may want to send something that is
1084		 * not divisible by 4 (as opposed to card sectors
1085		 * etc). Therefore make sure to always read the last bytes
1086		 * while only doing full 32-bit reads towards the FIFO.
1087		 */
1088		if (unlikely(count & 0x3)) {
1089			if (count < 4) {
1090				unsigned char buf[4];
1091				ioread32_rep(base + MMCIFIFO, buf, 1);
1092				memcpy(ptr, buf, count);
1093			} else {
1094				ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1095				count &= ~0x3;
1096			}
1097		} else {
1098			ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1099		}
1100
1101		ptr += count;
1102		remain -= count;
1103		host_remain -= count;
1104
1105		if (remain == 0)
1106			break;
1107
1108		status = readl(base + MMCISTATUS);
1109	} while (status & MCI_RXDATAAVLBL);
1110
1111	return ptr - buffer;
1112}
1113
1114static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1115{
1116	struct variant_data *variant = host->variant;
1117	void __iomem *base = host->base;
1118	char *ptr = buffer;
1119
1120	do {
1121		unsigned int count, maxcnt;
1122
1123		maxcnt = status & MCI_TXFIFOEMPTY ?
1124			 variant->fifosize : variant->fifohalfsize;
1125		count = min(remain, maxcnt);
1126
1127		/*
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1128		 * SDIO especially may want to send something that is
1129		 * not divisible by 4 (as opposed to card sectors
1130		 * etc), and the FIFO only accept full 32-bit writes.
1131		 * So compensate by adding +3 on the count, a single
1132		 * byte become a 32bit write, 7 bytes will be two
1133		 * 32bit writes etc.
1134		 */
1135		iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1136
1137		ptr += count;
1138		remain -= count;
1139
1140		if (remain == 0)
1141			break;
1142
1143		status = readl(base + MMCISTATUS);
1144	} while (status & MCI_TXFIFOHALFEMPTY);
1145
1146	return ptr - buffer;
1147}
1148
1149/*
1150 * PIO data transfer IRQ handler.
1151 */
1152static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1153{
1154	struct mmci_host *host = dev_id;
1155	struct sg_mapping_iter *sg_miter = &host->sg_miter;
1156	struct variant_data *variant = host->variant;
1157	void __iomem *base = host->base;
1158	unsigned long flags;
1159	u32 status;
1160
1161	status = readl(base + MMCISTATUS);
1162
1163	dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1164
1165	local_irq_save(flags);
1166
1167	do {
1168		unsigned int remain, len;
1169		char *buffer;
1170
1171		/*
1172		 * For write, we only need to test the half-empty flag
1173		 * here - if the FIFO is completely empty, then by
1174		 * definition it is more than half empty.
1175		 *
1176		 * For read, check for data available.
1177		 */
1178		if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1179			break;
1180
1181		if (!sg_miter_next(sg_miter))
1182			break;
1183
1184		buffer = sg_miter->addr;
1185		remain = sg_miter->length;
1186
1187		len = 0;
1188		if (status & MCI_RXACTIVE)
1189			len = mmci_pio_read(host, buffer, remain);
1190		if (status & MCI_TXACTIVE)
1191			len = mmci_pio_write(host, buffer, remain, status);
1192
1193		sg_miter->consumed = len;
1194
1195		host->size -= len;
1196		remain -= len;
1197
1198		if (remain)
1199			break;
1200
1201		status = readl(base + MMCISTATUS);
1202	} while (1);
1203
1204	sg_miter_stop(sg_miter);
1205
1206	local_irq_restore(flags);
1207
1208	/*
1209	 * If we have less than the fifo 'half-full' threshold to transfer,
1210	 * trigger a PIO interrupt as soon as any data is available.
1211	 */
1212	if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1213		mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1214
1215	/*
1216	 * If we run out of data, disable the data IRQs; this
1217	 * prevents a race where the FIFO becomes empty before
1218	 * the chip itself has disabled the data path, and
1219	 * stops us racing with our data end IRQ.
1220	 */
1221	if (host->size == 0) {
1222		mmci_set_mask1(host, 0);
1223		writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1224	}
1225
1226	return IRQ_HANDLED;
1227}
1228
1229/*
1230 * Handle completion of command and data transfers.
1231 */
1232static irqreturn_t mmci_irq(int irq, void *dev_id)
1233{
1234	struct mmci_host *host = dev_id;
1235	u32 status;
1236	int ret = 0;
1237
1238	spin_lock(&host->lock);
1239
1240	do {
 
 
 
1241		status = readl(host->base + MMCISTATUS);
1242
1243		if (host->singleirq) {
1244			if (status & readl(host->base + MMCIMASK1))
1245				mmci_pio_irq(irq, dev_id);
1246
1247			status &= ~MCI_IRQ1MASK;
1248		}
1249
1250		/*
1251		 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
1252		 * enabled) since the HW seems to be triggering the IRQ on both
1253		 * edges while monitoring DAT0 for busy completion.
1254		 */
1255		status &= readl(host->base + MMCIMASK0);
1256		writel(status, host->base + MMCICLEAR);
1257
1258		dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1259
1260		if (host->variant->reversed_irq_handling) {
1261			mmci_data_irq(host, host->data, status);
1262			mmci_cmd_irq(host, host->cmd, status);
1263		} else {
1264			mmci_cmd_irq(host, host->cmd, status);
1265			mmci_data_irq(host, host->data, status);
1266		}
1267
1268		/* Don't poll for busy completion in irq context. */
1269		if (host->busy_status)
1270			status &= ~MCI_ST_CARDBUSY;
1271
1272		ret = 1;
1273	} while (status);
1274
1275	spin_unlock(&host->lock);
1276
1277	return IRQ_RETVAL(ret);
1278}
1279
1280static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1281{
1282	struct mmci_host *host = mmc_priv(mmc);
1283	unsigned long flags;
1284
1285	WARN_ON(host->mrq != NULL);
1286
1287	mrq->cmd->error = mmci_validate_data(host, mrq->data);
1288	if (mrq->cmd->error) {
 
 
1289		mmc_request_done(mmc, mrq);
1290		return;
1291	}
1292
1293	pm_runtime_get_sync(mmc_dev(mmc));
1294
1295	spin_lock_irqsave(&host->lock, flags);
1296
1297	host->mrq = mrq;
1298
1299	if (mrq->data)
1300		mmci_get_next_data(host, mrq->data);
1301
1302	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1303		mmci_start_data(host, mrq->data);
1304
1305	if (mrq->sbc)
1306		mmci_start_command(host, mrq->sbc, 0);
1307	else
1308		mmci_start_command(host, mrq->cmd, 0);
1309
1310	spin_unlock_irqrestore(&host->lock, flags);
1311}
1312
1313static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1314{
1315	struct mmci_host *host = mmc_priv(mmc);
1316	struct variant_data *variant = host->variant;
1317	u32 pwr = 0;
1318	unsigned long flags;
1319	int ret;
1320
1321	pm_runtime_get_sync(mmc_dev(mmc));
1322
1323	if (host->plat->ios_handler &&
1324		host->plat->ios_handler(mmc_dev(mmc), ios))
1325			dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1326
1327	switch (ios->power_mode) {
1328	case MMC_POWER_OFF:
1329		if (!IS_ERR(mmc->supply.vmmc))
1330			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1331
1332		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1333			regulator_disable(mmc->supply.vqmmc);
1334			host->vqmmc_enabled = false;
1335		}
1336
1337		break;
1338	case MMC_POWER_UP:
1339		if (!IS_ERR(mmc->supply.vmmc))
1340			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1341
 
 
 
 
 
 
 
 
 
 
1342		/*
1343		 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1344		 * and instead uses MCI_PWR_ON so apply whatever value is
1345		 * configured in the variant data.
1346		 */
1347		pwr |= variant->pwrreg_powerup;
1348
1349		break;
1350	case MMC_POWER_ON:
1351		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1352			ret = regulator_enable(mmc->supply.vqmmc);
1353			if (ret < 0)
1354				dev_err(mmc_dev(mmc),
1355					"failed to enable vqmmc regulator\n");
1356			else
1357				host->vqmmc_enabled = true;
1358		}
1359
1360		pwr |= MCI_PWR_ON;
1361		break;
1362	}
1363
1364	if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1365		/*
1366		 * The ST Micro variant has some additional bits
1367		 * indicating signal direction for the signals in
1368		 * the SD/MMC bus and feedback-clock usage.
1369		 */
1370		pwr |= host->pwr_reg_add;
1371
1372		if (ios->bus_width == MMC_BUS_WIDTH_4)
1373			pwr &= ~MCI_ST_DATA74DIREN;
1374		else if (ios->bus_width == MMC_BUS_WIDTH_1)
1375			pwr &= (~MCI_ST_DATA74DIREN &
1376				~MCI_ST_DATA31DIREN &
1377				~MCI_ST_DATA2DIREN);
1378	}
1379
1380	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1381		if (host->hw_designer != AMBA_VENDOR_ST)
1382			pwr |= MCI_ROD;
1383		else {
1384			/*
1385			 * The ST Micro variant use the ROD bit for something
1386			 * else and only has OD (Open Drain).
1387			 */
1388			pwr |= MCI_OD;
1389		}
1390	}
1391
1392	/*
1393	 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1394	 * gating the clock, the MCI_PWR_ON bit is cleared.
1395	 */
1396	if (!ios->clock && variant->pwrreg_clkgate)
1397		pwr &= ~MCI_PWR_ON;
1398
1399	if (host->variant->explicit_mclk_control &&
1400	    ios->clock != host->clock_cache) {
1401		ret = clk_set_rate(host->clk, ios->clock);
1402		if (ret < 0)
1403			dev_err(mmc_dev(host->mmc),
1404				"Error setting clock rate (%d)\n", ret);
1405		else
1406			host->mclk = clk_get_rate(host->clk);
1407	}
1408	host->clock_cache = ios->clock;
1409
1410	spin_lock_irqsave(&host->lock, flags);
1411
1412	mmci_set_clkreg(host, ios->clock);
1413	mmci_write_pwrreg(host, pwr);
1414	mmci_reg_delay(host);
1415
1416	spin_unlock_irqrestore(&host->lock, flags);
1417
 
1418	pm_runtime_mark_last_busy(mmc_dev(mmc));
1419	pm_runtime_put_autosuspend(mmc_dev(mmc));
1420}
1421
 
 
 
 
 
 
 
 
 
 
1422static int mmci_get_cd(struct mmc_host *mmc)
1423{
1424	struct mmci_host *host = mmc_priv(mmc);
1425	struct mmci_platform_data *plat = host->plat;
1426	unsigned int status = mmc_gpio_get_cd(mmc);
1427
1428	if (status == -ENOSYS) {
1429		if (!plat->status)
1430			return 1; /* Assume always present */
1431
1432		status = plat->status(mmc_dev(host->mmc));
1433	}
 
 
 
 
 
 
 
1434	return status;
1435}
1436
1437static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1438{
1439	int ret = 0;
1440
1441	if (!IS_ERR(mmc->supply.vqmmc)) {
1442
1443		pm_runtime_get_sync(mmc_dev(mmc));
1444
1445		switch (ios->signal_voltage) {
1446		case MMC_SIGNAL_VOLTAGE_330:
1447			ret = regulator_set_voltage(mmc->supply.vqmmc,
1448						2700000, 3600000);
1449			break;
1450		case MMC_SIGNAL_VOLTAGE_180:
1451			ret = regulator_set_voltage(mmc->supply.vqmmc,
1452						1700000, 1950000);
1453			break;
1454		case MMC_SIGNAL_VOLTAGE_120:
1455			ret = regulator_set_voltage(mmc->supply.vqmmc,
1456						1100000, 1300000);
1457			break;
1458		}
1459
1460		if (ret)
1461			dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1462
1463		pm_runtime_mark_last_busy(mmc_dev(mmc));
1464		pm_runtime_put_autosuspend(mmc_dev(mmc));
1465	}
1466
1467	return ret;
1468}
1469
1470static struct mmc_host_ops mmci_ops = {
1471	.request	= mmci_request,
1472	.pre_req	= mmci_pre_request,
1473	.post_req	= mmci_post_request,
1474	.set_ios	= mmci_set_ios,
1475	.get_ro		= mmc_gpio_get_ro,
1476	.get_cd		= mmci_get_cd,
1477	.start_signal_voltage_switch = mmci_sig_volt_switch,
1478};
1479
1480static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
 
 
1481{
1482	struct mmci_host *host = mmc_priv(mmc);
1483	int ret = mmc_of_parse(mmc);
1484
1485	if (ret)
1486		return ret;
 
 
 
 
 
1487
1488	if (of_get_property(np, "st,sig-dir-dat0", NULL))
1489		host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1490	if (of_get_property(np, "st,sig-dir-dat2", NULL))
1491		host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1492	if (of_get_property(np, "st,sig-dir-dat31", NULL))
1493		host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1494	if (of_get_property(np, "st,sig-dir-dat74", NULL))
1495		host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1496	if (of_get_property(np, "st,sig-dir-cmd", NULL))
1497		host->pwr_reg_add |= MCI_ST_CMDDIREN;
1498	if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1499		host->pwr_reg_add |= MCI_ST_FBCLKEN;
1500
1501	if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1502		mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1503	if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1504		mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1505
1506	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
1507}
 
 
 
 
 
 
 
1508
1509static int mmci_probe(struct amba_device *dev,
1510	const struct amba_id *id)
1511{
1512	struct mmci_platform_data *plat = dev->dev.platform_data;
1513	struct device_node *np = dev->dev.of_node;
1514	struct variant_data *variant = id->data;
1515	struct mmci_host *host;
1516	struct mmc_host *mmc;
1517	int ret;
1518
1519	/* Must have platform data or Device Tree. */
1520	if (!plat && !np) {
1521		dev_err(&dev->dev, "No plat data or DT found\n");
1522		return -EINVAL;
1523	}
1524
1525	if (!plat) {
1526		plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1527		if (!plat)
1528			return -ENOMEM;
1529	}
1530
1531	mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1532	if (!mmc)
1533		return -ENOMEM;
1534
1535	ret = mmci_of_parse(np, mmc);
1536	if (ret)
1537		goto host_free;
 
 
 
 
 
 
1538
1539	host = mmc_priv(mmc);
1540	host->mmc = mmc;
1541
 
 
 
 
1542	host->hw_designer = amba_manf(dev);
1543	host->hw_revision = amba_rev(dev);
1544	dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1545	dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1546
1547	host->clk = devm_clk_get(&dev->dev, NULL);
1548	if (IS_ERR(host->clk)) {
1549		ret = PTR_ERR(host->clk);
 
1550		goto host_free;
1551	}
1552
1553	ret = clk_prepare_enable(host->clk);
1554	if (ret)
1555		goto host_free;
1556
1557	if (variant->qcom_fifo)
1558		host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1559	else
1560		host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1561
1562	host->plat = plat;
1563	host->variant = variant;
1564	host->mclk = clk_get_rate(host->clk);
1565	/*
1566	 * According to the spec, mclk is max 100 MHz,
1567	 * so we try to adjust the clock down to this,
1568	 * (if possible).
1569	 */
1570	if (host->mclk > variant->f_max) {
1571		ret = clk_set_rate(host->clk, variant->f_max);
1572		if (ret < 0)
1573			goto clk_disable;
1574		host->mclk = clk_get_rate(host->clk);
1575		dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1576			host->mclk);
1577	}
1578
1579	host->phybase = dev->res.start;
1580	host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1581	if (IS_ERR(host->base)) {
1582		ret = PTR_ERR(host->base);
1583		goto clk_disable;
1584	}
1585
 
1586	/*
1587	 * The ARM and ST versions of the block have slightly different
1588	 * clock divider equations which means that the minimum divider
1589	 * differs too.
1590	 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1591	 */
1592	if (variant->st_clkdiv)
1593		mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1594	else if (variant->explicit_mclk_control)
1595		mmc->f_min = clk_round_rate(host->clk, 100000);
1596	else
1597		mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1598	/*
1599	 * If no maximum operating frequency is supplied, fall back to use
1600	 * the module parameter, which has a (low) default value in case it
1601	 * is not specified. Either value must not exceed the clock rate into
1602	 * the block, of course.
 
 
1603	 */
1604	if (mmc->f_max)
1605		mmc->f_max = variant->explicit_mclk_control ?
1606				min(variant->f_max, mmc->f_max) :
1607				min(host->mclk, mmc->f_max);
1608	else
1609		mmc->f_max = variant->explicit_mclk_control ?
1610				fmax : min(host->mclk, fmax);
1611
1612
1613	dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1614
1615	/* Get regulators and the supported OCR mask */
1616	ret = mmc_regulator_get_supply(mmc);
1617	if (ret == -EPROBE_DEFER)
1618		goto clk_disable;
1619
1620	if (!mmc->ocr_avail)
1621		mmc->ocr_avail = plat->ocr_mask;
1622	else if (plat->ocr_mask)
1623		dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1624
1625	/* DT takes precedence over platform data. */
1626	if (!np) {
1627		if (!plat->cd_invert)
1628			mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1629		mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1630	}
1631
1632	/* We support these capabilities. */
1633	mmc->caps |= MMC_CAP_CMD23;
1634
1635	if (variant->busy_detect) {
1636		mmci_ops.card_busy = mmci_card_busy;
1637		mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1638		mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1639		mmc->max_busy_timeout = 0;
1640	}
1641
1642	mmc->ops = &mmci_ops;
1643
1644	/* We support these PM capabilities. */
1645	mmc->pm_caps |= MMC_PM_KEEP_POWER;
 
1646
1647	/*
1648	 * We can do SGIO
1649	 */
1650	mmc->max_segs = NR_SG;
1651
1652	/*
1653	 * Since only a certain number of bits are valid in the data length
1654	 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1655	 * single request.
1656	 */
1657	mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1658
1659	/*
1660	 * Set the maximum segment size.  Since we aren't doing DMA
1661	 * (yet) we are only limited by the data length register.
1662	 */
1663	mmc->max_seg_size = mmc->max_req_size;
1664
1665	/*
1666	 * Block size can be up to 2048 bytes, but must be a power of two.
1667	 */
1668	mmc->max_blk_size = 1 << 11;
1669
1670	/*
1671	 * Limit the number of blocks transferred so that we don't overflow
1672	 * the maximum request size.
1673	 */
1674	mmc->max_blk_count = mmc->max_req_size >> 11;
1675
1676	spin_lock_init(&host->lock);
1677
1678	writel(0, host->base + MMCIMASK0);
1679	writel(0, host->base + MMCIMASK1);
1680	writel(0xfff, host->base + MMCICLEAR);
1681
1682	/*
1683	 * If:
1684	 * - not using DT but using a descriptor table, or
1685	 * - using a table of descriptors ALONGSIDE DT, or
1686	 * look up these descriptors named "cd" and "wp" right here, fail
1687	 * silently of these do not exist and proceed to try platform data
1688	 */
1689	if (!np) {
1690		ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
1691		if (ret < 0) {
1692			if (ret == -EPROBE_DEFER)
1693				goto clk_disable;
1694			else if (gpio_is_valid(plat->gpio_cd)) {
1695				ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1696				if (ret)
1697					goto clk_disable;
1698			}
1699		}
1700
1701		ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
1702		if (ret < 0) {
1703			if (ret == -EPROBE_DEFER)
1704				goto clk_disable;
1705			else if (gpio_is_valid(plat->gpio_wp)) {
1706				ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1707				if (ret)
1708					goto clk_disable;
1709			}
1710		}
1711	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1712
1713	ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1714			DRIVER_NAME " (cmd)", host);
1715	if (ret)
1716		goto clk_disable;
1717
1718	if (!dev->irq[1])
1719		host->singleirq = true;
1720	else {
1721		ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1722				IRQF_SHARED, DRIVER_NAME " (pio)", host);
1723		if (ret)
1724			goto clk_disable;
1725	}
1726
1727	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1728
1729	amba_set_drvdata(dev, mmc);
1730
1731	dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1732		 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1733		 amba_rev(dev), (unsigned long long)dev->res.start,
1734		 dev->irq[0], dev->irq[1]);
1735
1736	mmci_dma_setup(host);
1737
1738	pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1739	pm_runtime_use_autosuspend(&dev->dev);
 
1740
1741	mmc_add_host(mmc);
1742
1743	pm_runtime_put(&dev->dev);
1744	return 0;
1745
 
 
 
 
 
 
 
 
 
 
 
 
1746 clk_disable:
1747	clk_disable_unprepare(host->clk);
 
 
 
 
1748 host_free:
1749	mmc_free_host(mmc);
 
 
 
1750	return ret;
1751}
1752
1753static int mmci_remove(struct amba_device *dev)
1754{
1755	struct mmc_host *mmc = amba_get_drvdata(dev);
1756
 
 
1757	if (mmc) {
1758		struct mmci_host *host = mmc_priv(mmc);
1759
1760		/*
1761		 * Undo pm_runtime_put() in probe.  We use the _sync
1762		 * version here so that we can access the primecell.
1763		 */
1764		pm_runtime_get_sync(&dev->dev);
1765
1766		mmc_remove_host(mmc);
1767
1768		writel(0, host->base + MMCIMASK0);
1769		writel(0, host->base + MMCIMASK1);
1770
1771		writel(0, host->base + MMCICOMMAND);
1772		writel(0, host->base + MMCIDATACTRL);
1773
1774		mmci_dma_release(host);
1775		clk_disable_unprepare(host->clk);
1776		mmc_free_host(mmc);
1777	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1778
1779	return 0;
1780}
1781
1782#ifdef CONFIG_PM
1783static void mmci_save(struct mmci_host *host)
1784{
1785	unsigned long flags;
1786
1787	spin_lock_irqsave(&host->lock, flags);
1788
1789	writel(0, host->base + MMCIMASK0);
1790	if (host->variant->pwrreg_nopower) {
1791		writel(0, host->base + MMCIDATACTRL);
1792		writel(0, host->base + MMCIPOWER);
1793		writel(0, host->base + MMCICLOCK);
1794	}
1795	mmci_reg_delay(host);
1796
1797	spin_unlock_irqrestore(&host->lock, flags);
1798}
1799
1800static void mmci_restore(struct mmci_host *host)
1801{
1802	unsigned long flags;
1803
1804	spin_lock_irqsave(&host->lock, flags);
1805
1806	if (host->variant->pwrreg_nopower) {
1807		writel(host->clk_reg, host->base + MMCICLOCK);
1808		writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1809		writel(host->pwr_reg, host->base + MMCIPOWER);
1810	}
1811	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1812	mmci_reg_delay(host);
1813
1814	spin_unlock_irqrestore(&host->lock, flags);
1815}
1816
1817static int mmci_runtime_suspend(struct device *dev)
 
1818{
1819	struct amba_device *adev = to_amba_device(dev);
1820	struct mmc_host *mmc = amba_get_drvdata(adev);
 
1821
1822	if (mmc) {
1823		struct mmci_host *host = mmc_priv(mmc);
1824		pinctrl_pm_select_sleep_state(dev);
1825		mmci_save(host);
1826		clk_disable_unprepare(host->clk);
 
 
 
1827	}
1828
1829	return 0;
1830}
1831
1832static int mmci_runtime_resume(struct device *dev)
1833{
1834	struct amba_device *adev = to_amba_device(dev);
1835	struct mmc_host *mmc = amba_get_drvdata(adev);
 
1836
1837	if (mmc) {
1838		struct mmci_host *host = mmc_priv(mmc);
1839		clk_prepare_enable(host->clk);
1840		mmci_restore(host);
1841		pinctrl_pm_select_default_state(dev);
 
 
1842	}
1843
1844	return 0;
1845}
1846#endif
1847
1848static const struct dev_pm_ops mmci_dev_pm_ops = {
1849	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1850				pm_runtime_force_resume)
1851	SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1852};
1853
1854static struct amba_id mmci_ids[] = {
1855	{
1856		.id	= 0x00041180,
1857		.mask	= 0xff0fffff,
1858		.data	= &variant_arm,
1859	},
1860	{
1861		.id	= 0x01041180,
1862		.mask	= 0xff0fffff,
1863		.data	= &variant_arm_extended_fifo,
1864	},
1865	{
1866		.id	= 0x02041180,
1867		.mask	= 0xff0fffff,
1868		.data	= &variant_arm_extended_fifo_hwfc,
1869	},
1870	{
1871		.id	= 0x00041181,
1872		.mask	= 0x000fffff,
1873		.data	= &variant_arm,
1874	},
1875	/* ST Micro variants */
1876	{
1877		.id     = 0x00180180,
1878		.mask   = 0x00ffffff,
1879		.data	= &variant_u300,
1880	},
1881	{
1882		.id     = 0x10180180,
1883		.mask   = 0xf0ffffff,
1884		.data	= &variant_nomadik,
1885	},
1886	{
1887		.id     = 0x00280180,
1888		.mask   = 0x00ffffff,
1889		.data	= &variant_nomadik,
1890	},
1891	{
1892		.id     = 0x00480180,
1893		.mask   = 0xf0ffffff,
1894		.data	= &variant_ux500,
1895	},
1896	{
1897		.id     = 0x10480180,
1898		.mask   = 0xf0ffffff,
1899		.data	= &variant_ux500v2,
1900	},
1901	/* Qualcomm variants */
1902	{
1903		.id     = 0x00051180,
1904		.mask	= 0x000fffff,
1905		.data	= &variant_qcom,
1906	},
1907	{ 0, 0 },
1908};
1909
1910MODULE_DEVICE_TABLE(amba, mmci_ids);
1911
1912static struct amba_driver mmci_driver = {
1913	.drv		= {
1914		.name	= DRIVER_NAME,
1915		.pm	= &mmci_dev_pm_ops,
1916	},
1917	.probe		= mmci_probe,
1918	.remove		= mmci_remove,
1919	.id_table	= mmci_ids,
1920};
1921
1922module_amba_driver(mmci_driver);
1923
1924module_param(fmax, uint, 0444);
1925
1926MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1927MODULE_LICENSE("GPL");