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1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#include <linux/device.h>
31#include <linux/acpi.h>
32#include <drm/drmP.h>
33#include <drm/i915_drm.h>
34#include "i915_drv.h"
35#include "i915_trace.h"
36#include "intel_drv.h"
37
38#include <linux/apple-gmux.h>
39#include <linux/console.h>
40#include <linux/module.h>
41#include <linux/pm_runtime.h>
42#include <linux/vgaarb.h>
43#include <linux/vga_switcheroo.h>
44#include <drm/drm_crtc_helper.h>
45
46static struct drm_driver driver;
47
48#define GEN_DEFAULT_PIPEOFFSETS \
49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
50 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
52 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
54
55#define GEN_CHV_PIPEOFFSETS \
56 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
57 CHV_PIPE_C_OFFSET }, \
58 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
59 CHV_TRANSCODER_C_OFFSET, }, \
60 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
61 CHV_PALETTE_C_OFFSET }
62
63#define CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
65
66#define IVB_CURSOR_OFFSETS \
67 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
68
69static const struct intel_device_info intel_i830_info = {
70 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
71 .has_overlay = 1, .overlay_needs_physical = 1,
72 .ring_mask = RENDER_RING,
73 GEN_DEFAULT_PIPEOFFSETS,
74 CURSOR_OFFSETS,
75};
76
77static const struct intel_device_info intel_845g_info = {
78 .gen = 2, .num_pipes = 1,
79 .has_overlay = 1, .overlay_needs_physical = 1,
80 .ring_mask = RENDER_RING,
81 GEN_DEFAULT_PIPEOFFSETS,
82 CURSOR_OFFSETS,
83};
84
85static const struct intel_device_info intel_i85x_info = {
86 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
87 .cursor_needs_physical = 1,
88 .has_overlay = 1, .overlay_needs_physical = 1,
89 .has_fbc = 1,
90 .ring_mask = RENDER_RING,
91 GEN_DEFAULT_PIPEOFFSETS,
92 CURSOR_OFFSETS,
93};
94
95static const struct intel_device_info intel_i865g_info = {
96 .gen = 2, .num_pipes = 1,
97 .has_overlay = 1, .overlay_needs_physical = 1,
98 .ring_mask = RENDER_RING,
99 GEN_DEFAULT_PIPEOFFSETS,
100 CURSOR_OFFSETS,
101};
102
103static const struct intel_device_info intel_i915g_info = {
104 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
105 .has_overlay = 1, .overlay_needs_physical = 1,
106 .ring_mask = RENDER_RING,
107 GEN_DEFAULT_PIPEOFFSETS,
108 CURSOR_OFFSETS,
109};
110static const struct intel_device_info intel_i915gm_info = {
111 .gen = 3, .is_mobile = 1, .num_pipes = 2,
112 .cursor_needs_physical = 1,
113 .has_overlay = 1, .overlay_needs_physical = 1,
114 .supports_tv = 1,
115 .has_fbc = 1,
116 .ring_mask = RENDER_RING,
117 GEN_DEFAULT_PIPEOFFSETS,
118 CURSOR_OFFSETS,
119};
120static const struct intel_device_info intel_i945g_info = {
121 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
122 .has_overlay = 1, .overlay_needs_physical = 1,
123 .ring_mask = RENDER_RING,
124 GEN_DEFAULT_PIPEOFFSETS,
125 CURSOR_OFFSETS,
126};
127static const struct intel_device_info intel_i945gm_info = {
128 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
129 .has_hotplug = 1, .cursor_needs_physical = 1,
130 .has_overlay = 1, .overlay_needs_physical = 1,
131 .supports_tv = 1,
132 .has_fbc = 1,
133 .ring_mask = RENDER_RING,
134 GEN_DEFAULT_PIPEOFFSETS,
135 CURSOR_OFFSETS,
136};
137
138static const struct intel_device_info intel_i965g_info = {
139 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
140 .has_hotplug = 1,
141 .has_overlay = 1,
142 .ring_mask = RENDER_RING,
143 GEN_DEFAULT_PIPEOFFSETS,
144 CURSOR_OFFSETS,
145};
146
147static const struct intel_device_info intel_i965gm_info = {
148 .gen = 4, .is_crestline = 1, .num_pipes = 2,
149 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
150 .has_overlay = 1,
151 .supports_tv = 1,
152 .ring_mask = RENDER_RING,
153 GEN_DEFAULT_PIPEOFFSETS,
154 CURSOR_OFFSETS,
155};
156
157static const struct intel_device_info intel_g33_info = {
158 .gen = 3, .is_g33 = 1, .num_pipes = 2,
159 .need_gfx_hws = 1, .has_hotplug = 1,
160 .has_overlay = 1,
161 .ring_mask = RENDER_RING,
162 GEN_DEFAULT_PIPEOFFSETS,
163 CURSOR_OFFSETS,
164};
165
166static const struct intel_device_info intel_g45_info = {
167 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
168 .has_pipe_cxsr = 1, .has_hotplug = 1,
169 .ring_mask = RENDER_RING | BSD_RING,
170 GEN_DEFAULT_PIPEOFFSETS,
171 CURSOR_OFFSETS,
172};
173
174static const struct intel_device_info intel_gm45_info = {
175 .gen = 4, .is_g4x = 1, .num_pipes = 2,
176 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
177 .has_pipe_cxsr = 1, .has_hotplug = 1,
178 .supports_tv = 1,
179 .ring_mask = RENDER_RING | BSD_RING,
180 GEN_DEFAULT_PIPEOFFSETS,
181 CURSOR_OFFSETS,
182};
183
184static const struct intel_device_info intel_pineview_info = {
185 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
186 .need_gfx_hws = 1, .has_hotplug = 1,
187 .has_overlay = 1,
188 GEN_DEFAULT_PIPEOFFSETS,
189 CURSOR_OFFSETS,
190};
191
192static const struct intel_device_info intel_ironlake_d_info = {
193 .gen = 5, .num_pipes = 2,
194 .need_gfx_hws = 1, .has_hotplug = 1,
195 .ring_mask = RENDER_RING | BSD_RING,
196 GEN_DEFAULT_PIPEOFFSETS,
197 CURSOR_OFFSETS,
198};
199
200static const struct intel_device_info intel_ironlake_m_info = {
201 .gen = 5, .is_mobile = 1, .num_pipes = 2,
202 .need_gfx_hws = 1, .has_hotplug = 1,
203 .has_fbc = 1,
204 .ring_mask = RENDER_RING | BSD_RING,
205 GEN_DEFAULT_PIPEOFFSETS,
206 CURSOR_OFFSETS,
207};
208
209static const struct intel_device_info intel_sandybridge_d_info = {
210 .gen = 6, .num_pipes = 2,
211 .need_gfx_hws = 1, .has_hotplug = 1,
212 .has_fbc = 1,
213 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
214 .has_llc = 1,
215 GEN_DEFAULT_PIPEOFFSETS,
216 CURSOR_OFFSETS,
217};
218
219static const struct intel_device_info intel_sandybridge_m_info = {
220 .gen = 6, .is_mobile = 1, .num_pipes = 2,
221 .need_gfx_hws = 1, .has_hotplug = 1,
222 .has_fbc = 1,
223 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
224 .has_llc = 1,
225 GEN_DEFAULT_PIPEOFFSETS,
226 CURSOR_OFFSETS,
227};
228
229#define GEN7_FEATURES \
230 .gen = 7, .num_pipes = 3, \
231 .need_gfx_hws = 1, .has_hotplug = 1, \
232 .has_fbc = 1, \
233 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
234 .has_llc = 1, \
235 GEN_DEFAULT_PIPEOFFSETS, \
236 IVB_CURSOR_OFFSETS
237
238static const struct intel_device_info intel_ivybridge_d_info = {
239 GEN7_FEATURES,
240 .is_ivybridge = 1,
241};
242
243static const struct intel_device_info intel_ivybridge_m_info = {
244 GEN7_FEATURES,
245 .is_ivybridge = 1,
246 .is_mobile = 1,
247};
248
249static const struct intel_device_info intel_ivybridge_q_info = {
250 GEN7_FEATURES,
251 .is_ivybridge = 1,
252 .num_pipes = 0, /* legal, last one wins */
253};
254
255#define VLV_FEATURES \
256 .gen = 7, .num_pipes = 2, \
257 .need_gfx_hws = 1, .has_hotplug = 1, \
258 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
259 .display_mmio_offset = VLV_DISPLAY_BASE, \
260 GEN_DEFAULT_PIPEOFFSETS, \
261 CURSOR_OFFSETS
262
263static const struct intel_device_info intel_valleyview_m_info = {
264 VLV_FEATURES,
265 .is_valleyview = 1,
266 .is_mobile = 1,
267};
268
269static const struct intel_device_info intel_valleyview_d_info = {
270 VLV_FEATURES,
271 .is_valleyview = 1,
272};
273
274#define HSW_FEATURES \
275 GEN7_FEATURES, \
276 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
277 .has_ddi = 1, \
278 .has_fpga_dbg = 1
279
280static const struct intel_device_info intel_haswell_d_info = {
281 HSW_FEATURES,
282 .is_haswell = 1,
283};
284
285static const struct intel_device_info intel_haswell_m_info = {
286 HSW_FEATURES,
287 .is_haswell = 1,
288 .is_mobile = 1,
289};
290
291static const struct intel_device_info intel_broadwell_d_info = {
292 HSW_FEATURES,
293 .gen = 8,
294};
295
296static const struct intel_device_info intel_broadwell_m_info = {
297 HSW_FEATURES,
298 .gen = 8, .is_mobile = 1,
299};
300
301static const struct intel_device_info intel_broadwell_gt3d_info = {
302 HSW_FEATURES,
303 .gen = 8,
304 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
305};
306
307static const struct intel_device_info intel_broadwell_gt3m_info = {
308 HSW_FEATURES,
309 .gen = 8, .is_mobile = 1,
310 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
311};
312
313static const struct intel_device_info intel_cherryview_info = {
314 .gen = 8, .num_pipes = 3,
315 .need_gfx_hws = 1, .has_hotplug = 1,
316 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
317 .is_cherryview = 1,
318 .display_mmio_offset = VLV_DISPLAY_BASE,
319 GEN_CHV_PIPEOFFSETS,
320 CURSOR_OFFSETS,
321};
322
323static const struct intel_device_info intel_skylake_info = {
324 HSW_FEATURES,
325 .is_skylake = 1,
326 .gen = 9,
327};
328
329static const struct intel_device_info intel_skylake_gt3_info = {
330 HSW_FEATURES,
331 .is_skylake = 1,
332 .gen = 9,
333 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
334};
335
336static const struct intel_device_info intel_broxton_info = {
337 .is_preliminary = 1,
338 .is_broxton = 1,
339 .gen = 9,
340 .need_gfx_hws = 1, .has_hotplug = 1,
341 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
342 .num_pipes = 3,
343 .has_ddi = 1,
344 .has_fpga_dbg = 1,
345 .has_fbc = 1,
346 GEN_DEFAULT_PIPEOFFSETS,
347 IVB_CURSOR_OFFSETS,
348};
349
350static const struct intel_device_info intel_kabylake_info = {
351 HSW_FEATURES,
352 .is_preliminary = 1,
353 .is_kabylake = 1,
354 .gen = 9,
355};
356
357static const struct intel_device_info intel_kabylake_gt3_info = {
358 HSW_FEATURES,
359 .is_preliminary = 1,
360 .is_kabylake = 1,
361 .gen = 9,
362 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
363};
364
365/*
366 * Make sure any device matches here are from most specific to most
367 * general. For example, since the Quanta match is based on the subsystem
368 * and subvendor IDs, we need it to come before the more general IVB
369 * PCI ID matches, otherwise we'll use the wrong info struct above.
370 */
371static const struct pci_device_id pciidlist[] = {
372 INTEL_I830_IDS(&intel_i830_info),
373 INTEL_I845G_IDS(&intel_845g_info),
374 INTEL_I85X_IDS(&intel_i85x_info),
375 INTEL_I865G_IDS(&intel_i865g_info),
376 INTEL_I915G_IDS(&intel_i915g_info),
377 INTEL_I915GM_IDS(&intel_i915gm_info),
378 INTEL_I945G_IDS(&intel_i945g_info),
379 INTEL_I945GM_IDS(&intel_i945gm_info),
380 INTEL_I965G_IDS(&intel_i965g_info),
381 INTEL_G33_IDS(&intel_g33_info),
382 INTEL_I965GM_IDS(&intel_i965gm_info),
383 INTEL_GM45_IDS(&intel_gm45_info),
384 INTEL_G45_IDS(&intel_g45_info),
385 INTEL_PINEVIEW_IDS(&intel_pineview_info),
386 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
387 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
388 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
389 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
390 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
391 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
392 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
393 INTEL_HSW_D_IDS(&intel_haswell_d_info),
394 INTEL_HSW_M_IDS(&intel_haswell_m_info),
395 INTEL_VLV_M_IDS(&intel_valleyview_m_info),
396 INTEL_VLV_D_IDS(&intel_valleyview_d_info),
397 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
398 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
399 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
400 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
401 INTEL_CHV_IDS(&intel_cherryview_info),
402 INTEL_SKL_GT1_IDS(&intel_skylake_info),
403 INTEL_SKL_GT2_IDS(&intel_skylake_info),
404 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
405 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
406 INTEL_BXT_IDS(&intel_broxton_info),
407 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
408 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
409 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
410 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
411 {0, 0, 0}
412};
413
414MODULE_DEVICE_TABLE(pci, pciidlist);
415
416static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
417{
418 enum intel_pch ret = PCH_NOP;
419
420 /*
421 * In a virtualized passthrough environment we can be in a
422 * setup where the ISA bridge is not able to be passed through.
423 * In this case, a south bridge can be emulated and we have to
424 * make an educated guess as to which PCH is really there.
425 */
426
427 if (IS_GEN5(dev)) {
428 ret = PCH_IBX;
429 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
430 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
431 ret = PCH_CPT;
432 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
433 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
434 ret = PCH_LPT;
435 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
436 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
437 ret = PCH_SPT;
438 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
439 }
440
441 return ret;
442}
443
444void intel_detect_pch(struct drm_device *dev)
445{
446 struct drm_i915_private *dev_priv = dev->dev_private;
447 struct pci_dev *pch = NULL;
448
449 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
450 * (which really amounts to a PCH but no South Display).
451 */
452 if (INTEL_INFO(dev)->num_pipes == 0) {
453 dev_priv->pch_type = PCH_NOP;
454 return;
455 }
456
457 /*
458 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
459 * make graphics device passthrough work easy for VMM, that only
460 * need to expose ISA bridge to let driver know the real hardware
461 * underneath. This is a requirement from virtualization team.
462 *
463 * In some virtualized environments (e.g. XEN), there is irrelevant
464 * ISA bridge in the system. To work reliably, we should scan trhough
465 * all the ISA bridge devices and check for the first match, instead
466 * of only checking the first one.
467 */
468 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
469 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
470 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
471 dev_priv->pch_id = id;
472
473 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
474 dev_priv->pch_type = PCH_IBX;
475 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
476 WARN_ON(!IS_GEN5(dev));
477 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
478 dev_priv->pch_type = PCH_CPT;
479 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
480 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
481 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
482 /* PantherPoint is CPT compatible */
483 dev_priv->pch_type = PCH_CPT;
484 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
485 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
486 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
487 dev_priv->pch_type = PCH_LPT;
488 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
489 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
490 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
491 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
492 dev_priv->pch_type = PCH_LPT;
493 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
494 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
495 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
496 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
497 dev_priv->pch_type = PCH_SPT;
498 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
499 WARN_ON(!IS_SKYLAKE(dev) &&
500 !IS_KABYLAKE(dev));
501 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
502 dev_priv->pch_type = PCH_SPT;
503 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
504 WARN_ON(!IS_SKYLAKE(dev) &&
505 !IS_KABYLAKE(dev));
506 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
507 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
508 pch->subsystem_vendor == 0x1af4 &&
509 pch->subsystem_device == 0x1100)) {
510 dev_priv->pch_type = intel_virt_detect_pch(dev);
511 } else
512 continue;
513
514 break;
515 }
516 }
517 if (!pch)
518 DRM_DEBUG_KMS("No PCH found.\n");
519
520 pci_dev_put(pch);
521}
522
523bool i915_semaphore_is_enabled(struct drm_device *dev)
524{
525 if (INTEL_INFO(dev)->gen < 6)
526 return false;
527
528 if (i915.semaphores >= 0)
529 return i915.semaphores;
530
531 /* TODO: make semaphores and Execlists play nicely together */
532 if (i915.enable_execlists)
533 return false;
534
535 /* Until we get further testing... */
536 if (IS_GEN8(dev))
537 return false;
538
539#ifdef CONFIG_INTEL_IOMMU
540 /* Enable semaphores on SNB when IO remapping is off */
541 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
542 return false;
543#endif
544
545 return true;
546}
547
548static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
549{
550 struct drm_device *dev = dev_priv->dev;
551 struct intel_encoder *encoder;
552
553 drm_modeset_lock_all(dev);
554 for_each_intel_encoder(dev, encoder)
555 if (encoder->suspend)
556 encoder->suspend(encoder);
557 drm_modeset_unlock_all(dev);
558}
559
560static int intel_suspend_complete(struct drm_i915_private *dev_priv);
561static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
562 bool rpm_resume);
563static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
564
565static bool suspend_to_idle(struct drm_i915_private *dev_priv)
566{
567#if IS_ENABLED(CONFIG_ACPI_SLEEP)
568 if (acpi_target_system_state() < ACPI_STATE_S3)
569 return true;
570#endif
571 return false;
572}
573
574static int i915_drm_suspend(struct drm_device *dev)
575{
576 struct drm_i915_private *dev_priv = dev->dev_private;
577 pci_power_t opregion_target_state;
578 int error;
579
580 /* ignore lid events during suspend */
581 mutex_lock(&dev_priv->modeset_restore_lock);
582 dev_priv->modeset_restore = MODESET_SUSPENDED;
583 mutex_unlock(&dev_priv->modeset_restore_lock);
584
585 disable_rpm_wakeref_asserts(dev_priv);
586
587 /* We do a lot of poking in a lot of registers, make sure they work
588 * properly. */
589 intel_display_set_init_power(dev_priv, true);
590
591 drm_kms_helper_poll_disable(dev);
592
593 pci_save_state(dev->pdev);
594
595 error = i915_gem_suspend(dev);
596 if (error) {
597 dev_err(&dev->pdev->dev,
598 "GEM idle failed, resume might fail\n");
599 goto out;
600 }
601
602 intel_guc_suspend(dev);
603
604 intel_suspend_gt_powersave(dev);
605
606 intel_display_suspend(dev);
607
608 intel_dp_mst_suspend(dev);
609
610 intel_runtime_pm_disable_interrupts(dev_priv);
611 intel_hpd_cancel_work(dev_priv);
612
613 intel_suspend_encoders(dev_priv);
614
615 intel_suspend_hw(dev);
616
617 i915_gem_suspend_gtt_mappings(dev);
618
619 i915_save_state(dev);
620
621 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
622 intel_opregion_notify_adapter(dev, opregion_target_state);
623
624 intel_uncore_forcewake_reset(dev, false);
625 intel_opregion_fini(dev);
626
627 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
628
629 dev_priv->suspend_count++;
630
631 intel_display_set_init_power(dev_priv, false);
632
633 if (HAS_CSR(dev_priv))
634 flush_work(&dev_priv->csr.work);
635
636out:
637 enable_rpm_wakeref_asserts(dev_priv);
638
639 return error;
640}
641
642static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
643{
644 struct drm_i915_private *dev_priv = drm_dev->dev_private;
645 bool fw_csr;
646 int ret;
647
648 disable_rpm_wakeref_asserts(dev_priv);
649
650 fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
651 /*
652 * In case of firmware assisted context save/restore don't manually
653 * deinit the power domains. This also means the CSR/DMC firmware will
654 * stay active, it will power down any HW resources as required and
655 * also enable deeper system power states that would be blocked if the
656 * firmware was inactive.
657 */
658 if (!fw_csr)
659 intel_power_domains_suspend(dev_priv);
660
661 ret = intel_suspend_complete(dev_priv);
662
663 if (ret) {
664 DRM_ERROR("Suspend complete failed: %d\n", ret);
665 if (!fw_csr)
666 intel_power_domains_init_hw(dev_priv, true);
667
668 goto out;
669 }
670
671 pci_disable_device(drm_dev->pdev);
672 /*
673 * During hibernation on some platforms the BIOS may try to access
674 * the device even though it's already in D3 and hang the machine. So
675 * leave the device in D0 on those platforms and hope the BIOS will
676 * power down the device properly. The issue was seen on multiple old
677 * GENs with different BIOS vendors, so having an explicit blacklist
678 * is inpractical; apply the workaround on everything pre GEN6. The
679 * platforms where the issue was seen:
680 * Lenovo Thinkpad X301, X61s, X60, T60, X41
681 * Fujitsu FSC S7110
682 * Acer Aspire 1830T
683 */
684 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
685 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
686
687 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
688
689out:
690 enable_rpm_wakeref_asserts(dev_priv);
691
692 return ret;
693}
694
695int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
696{
697 int error;
698
699 if (!dev || !dev->dev_private) {
700 DRM_ERROR("dev: %p\n", dev);
701 DRM_ERROR("DRM not initialized, aborting suspend.\n");
702 return -ENODEV;
703 }
704
705 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
706 state.event != PM_EVENT_FREEZE))
707 return -EINVAL;
708
709 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
710 return 0;
711
712 error = i915_drm_suspend(dev);
713 if (error)
714 return error;
715
716 return i915_drm_suspend_late(dev, false);
717}
718
719static int i915_drm_resume(struct drm_device *dev)
720{
721 struct drm_i915_private *dev_priv = dev->dev_private;
722
723 disable_rpm_wakeref_asserts(dev_priv);
724
725 mutex_lock(&dev->struct_mutex);
726 i915_gem_restore_gtt_mappings(dev);
727 mutex_unlock(&dev->struct_mutex);
728
729 i915_restore_state(dev);
730 intel_opregion_setup(dev);
731
732 intel_init_pch_refclk(dev);
733 drm_mode_config_reset(dev);
734
735 /*
736 * Interrupts have to be enabled before any batches are run. If not the
737 * GPU will hang. i915_gem_init_hw() will initiate batches to
738 * update/restore the context.
739 *
740 * Modeset enabling in intel_modeset_init_hw() also needs working
741 * interrupts.
742 */
743 intel_runtime_pm_enable_interrupts(dev_priv);
744
745 mutex_lock(&dev->struct_mutex);
746 if (i915_gem_init_hw(dev)) {
747 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
748 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
749 }
750 mutex_unlock(&dev->struct_mutex);
751
752 intel_guc_resume(dev);
753
754 intel_modeset_init_hw(dev);
755
756 spin_lock_irq(&dev_priv->irq_lock);
757 if (dev_priv->display.hpd_irq_setup)
758 dev_priv->display.hpd_irq_setup(dev);
759 spin_unlock_irq(&dev_priv->irq_lock);
760
761 intel_dp_mst_resume(dev);
762
763 intel_display_resume(dev);
764
765 /*
766 * ... but also need to make sure that hotplug processing
767 * doesn't cause havoc. Like in the driver load code we don't
768 * bother with the tiny race here where we might loose hotplug
769 * notifications.
770 * */
771 intel_hpd_init(dev_priv);
772 /* Config may have changed between suspend and resume */
773 drm_helper_hpd_irq_event(dev);
774
775 intel_opregion_init(dev);
776
777 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
778
779 mutex_lock(&dev_priv->modeset_restore_lock);
780 dev_priv->modeset_restore = MODESET_DONE;
781 mutex_unlock(&dev_priv->modeset_restore_lock);
782
783 intel_opregion_notify_adapter(dev, PCI_D0);
784
785 drm_kms_helper_poll_enable(dev);
786
787 enable_rpm_wakeref_asserts(dev_priv);
788
789 return 0;
790}
791
792static int i915_drm_resume_early(struct drm_device *dev)
793{
794 struct drm_i915_private *dev_priv = dev->dev_private;
795 int ret;
796
797 /*
798 * We have a resume ordering issue with the snd-hda driver also
799 * requiring our device to be power up. Due to the lack of a
800 * parent/child relationship we currently solve this with an early
801 * resume hook.
802 *
803 * FIXME: This should be solved with a special hdmi sink device or
804 * similar so that power domains can be employed.
805 */
806
807 /*
808 * Note that we need to set the power state explicitly, since we
809 * powered off the device during freeze and the PCI core won't power
810 * it back up for us during thaw. Powering off the device during
811 * freeze is not a hard requirement though, and during the
812 * suspend/resume phases the PCI core makes sure we get here with the
813 * device powered on. So in case we change our freeze logic and keep
814 * the device powered we can also remove the following set power state
815 * call.
816 */
817 ret = pci_set_power_state(dev->pdev, PCI_D0);
818 if (ret) {
819 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
820 goto out;
821 }
822
823 /*
824 * Note that pci_enable_device() first enables any parent bridge
825 * device and only then sets the power state for this device. The
826 * bridge enabling is a nop though, since bridge devices are resumed
827 * first. The order of enabling power and enabling the device is
828 * imposed by the PCI core as described above, so here we preserve the
829 * same order for the freeze/thaw phases.
830 *
831 * TODO: eventually we should remove pci_disable_device() /
832 * pci_enable_enable_device() from suspend/resume. Due to how they
833 * depend on the device enable refcount we can't anyway depend on them
834 * disabling/enabling the device.
835 */
836 if (pci_enable_device(dev->pdev)) {
837 ret = -EIO;
838 goto out;
839 }
840
841 pci_set_master(dev->pdev);
842
843 disable_rpm_wakeref_asserts(dev_priv);
844
845 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
846 ret = vlv_resume_prepare(dev_priv, false);
847 if (ret)
848 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
849 ret);
850
851 intel_uncore_early_sanitize(dev, true);
852
853 if (IS_BROXTON(dev))
854 ret = bxt_resume_prepare(dev_priv);
855 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
856 hsw_disable_pc8(dev_priv);
857
858 intel_uncore_sanitize(dev);
859
860 if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
861 intel_power_domains_init_hw(dev_priv, true);
862
863out:
864 dev_priv->suspended_to_idle = false;
865
866 enable_rpm_wakeref_asserts(dev_priv);
867
868 return ret;
869}
870
871int i915_resume_switcheroo(struct drm_device *dev)
872{
873 int ret;
874
875 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
876 return 0;
877
878 ret = i915_drm_resume_early(dev);
879 if (ret)
880 return ret;
881
882 return i915_drm_resume(dev);
883}
884
885/**
886 * i915_reset - reset chip after a hang
887 * @dev: drm device to reset
888 *
889 * Reset the chip. Useful if a hang is detected. Returns zero on successful
890 * reset or otherwise an error code.
891 *
892 * Procedure is fairly simple:
893 * - reset the chip using the reset reg
894 * - re-init context state
895 * - re-init hardware status page
896 * - re-init ring buffer
897 * - re-init interrupt state
898 * - re-init display
899 */
900int i915_reset(struct drm_device *dev)
901{
902 struct drm_i915_private *dev_priv = dev->dev_private;
903 bool simulated;
904 int ret;
905
906 intel_reset_gt_powersave(dev);
907
908 mutex_lock(&dev->struct_mutex);
909
910 i915_gem_reset(dev);
911
912 simulated = dev_priv->gpu_error.stop_rings != 0;
913
914 ret = intel_gpu_reset(dev);
915
916 /* Also reset the gpu hangman. */
917 if (simulated) {
918 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
919 dev_priv->gpu_error.stop_rings = 0;
920 if (ret == -ENODEV) {
921 DRM_INFO("Reset not implemented, but ignoring "
922 "error for simulated gpu hangs\n");
923 ret = 0;
924 }
925 }
926
927 if (i915_stop_ring_allow_warn(dev_priv))
928 pr_notice("drm/i915: Resetting chip after gpu hang\n");
929
930 if (ret) {
931 DRM_ERROR("Failed to reset chip: %i\n", ret);
932 mutex_unlock(&dev->struct_mutex);
933 return ret;
934 }
935
936 intel_overlay_reset(dev_priv);
937
938 /* Ok, now get things going again... */
939
940 /*
941 * Everything depends on having the GTT running, so we need to start
942 * there. Fortunately we don't need to do this unless we reset the
943 * chip at a PCI level.
944 *
945 * Next we need to restore the context, but we don't use those
946 * yet either...
947 *
948 * Ring buffer needs to be re-initialized in the KMS case, or if X
949 * was running at the time of the reset (i.e. we weren't VT
950 * switched away).
951 */
952
953 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
954 dev_priv->gpu_error.reload_in_reset = true;
955
956 ret = i915_gem_init_hw(dev);
957
958 dev_priv->gpu_error.reload_in_reset = false;
959
960 mutex_unlock(&dev->struct_mutex);
961 if (ret) {
962 DRM_ERROR("Failed hw init on reset %d\n", ret);
963 return ret;
964 }
965
966 /*
967 * rps/rc6 re-init is necessary to restore state lost after the
968 * reset and the re-install of gt irqs. Skip for ironlake per
969 * previous concerns that it doesn't respond well to some forms
970 * of re-init after reset.
971 */
972 if (INTEL_INFO(dev)->gen > 5)
973 intel_enable_gt_powersave(dev);
974
975 return 0;
976}
977
978static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
979{
980 struct intel_device_info *intel_info =
981 (struct intel_device_info *) ent->driver_data;
982
983 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
984 DRM_INFO("This hardware requires preliminary hardware support.\n"
985 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
986 return -ENODEV;
987 }
988
989 /* Only bind to function 0 of the device. Early generations
990 * used function 1 as a placeholder for multi-head. This causes
991 * us confusion instead, especially on the systems where both
992 * functions have the same PCI-ID!
993 */
994 if (PCI_FUNC(pdev->devfn))
995 return -ENODEV;
996
997 /*
998 * apple-gmux is needed on dual GPU MacBook Pro
999 * to probe the panel if we're the inactive GPU.
1000 */
1001 if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
1002 apple_gmux_present() && pdev != vga_default_device() &&
1003 !vga_switcheroo_handler_flags())
1004 return -EPROBE_DEFER;
1005
1006 return drm_get_pci_dev(pdev, ent, &driver);
1007}
1008
1009static void
1010i915_pci_remove(struct pci_dev *pdev)
1011{
1012 struct drm_device *dev = pci_get_drvdata(pdev);
1013
1014 drm_put_dev(dev);
1015}
1016
1017static int i915_pm_suspend(struct device *dev)
1018{
1019 struct pci_dev *pdev = to_pci_dev(dev);
1020 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1021
1022 if (!drm_dev || !drm_dev->dev_private) {
1023 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1024 return -ENODEV;
1025 }
1026
1027 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1028 return 0;
1029
1030 return i915_drm_suspend(drm_dev);
1031}
1032
1033static int i915_pm_suspend_late(struct device *dev)
1034{
1035 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1036
1037 /*
1038 * We have a suspend ordering issue with the snd-hda driver also
1039 * requiring our device to be power up. Due to the lack of a
1040 * parent/child relationship we currently solve this with an late
1041 * suspend hook.
1042 *
1043 * FIXME: This should be solved with a special hdmi sink device or
1044 * similar so that power domains can be employed.
1045 */
1046 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1047 return 0;
1048
1049 return i915_drm_suspend_late(drm_dev, false);
1050}
1051
1052static int i915_pm_poweroff_late(struct device *dev)
1053{
1054 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1055
1056 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1057 return 0;
1058
1059 return i915_drm_suspend_late(drm_dev, true);
1060}
1061
1062static int i915_pm_resume_early(struct device *dev)
1063{
1064 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1065
1066 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1067 return 0;
1068
1069 return i915_drm_resume_early(drm_dev);
1070}
1071
1072static int i915_pm_resume(struct device *dev)
1073{
1074 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1075
1076 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1077 return 0;
1078
1079 return i915_drm_resume(drm_dev);
1080}
1081
1082static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1083{
1084 hsw_enable_pc8(dev_priv);
1085
1086 return 0;
1087}
1088
1089static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1090{
1091 struct drm_device *dev = dev_priv->dev;
1092
1093 /* TODO: when DC5 support is added disable DC5 here. */
1094
1095 broxton_ddi_phy_uninit(dev);
1096 broxton_uninit_cdclk(dev);
1097 bxt_enable_dc9(dev_priv);
1098
1099 return 0;
1100}
1101
1102static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1103{
1104 struct drm_device *dev = dev_priv->dev;
1105
1106 /* TODO: when CSR FW support is added make sure the FW is loaded */
1107
1108 bxt_disable_dc9(dev_priv);
1109
1110 /*
1111 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1112 * is available.
1113 */
1114 broxton_init_cdclk(dev);
1115 broxton_ddi_phy_init(dev);
1116
1117 return 0;
1118}
1119
1120/*
1121 * Save all Gunit registers that may be lost after a D3 and a subsequent
1122 * S0i[R123] transition. The list of registers needing a save/restore is
1123 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1124 * registers in the following way:
1125 * - Driver: saved/restored by the driver
1126 * - Punit : saved/restored by the Punit firmware
1127 * - No, w/o marking: no need to save/restore, since the register is R/O or
1128 * used internally by the HW in a way that doesn't depend
1129 * keeping the content across a suspend/resume.
1130 * - Debug : used for debugging
1131 *
1132 * We save/restore all registers marked with 'Driver', with the following
1133 * exceptions:
1134 * - Registers out of use, including also registers marked with 'Debug'.
1135 * These have no effect on the driver's operation, so we don't save/restore
1136 * them to reduce the overhead.
1137 * - Registers that are fully setup by an initialization function called from
1138 * the resume path. For example many clock gating and RPS/RC6 registers.
1139 * - Registers that provide the right functionality with their reset defaults.
1140 *
1141 * TODO: Except for registers that based on the above 3 criteria can be safely
1142 * ignored, we save/restore all others, practically treating the HW context as
1143 * a black-box for the driver. Further investigation is needed to reduce the
1144 * saved/restored registers even further, by following the same 3 criteria.
1145 */
1146static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1147{
1148 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1149 int i;
1150
1151 /* GAM 0x4000-0x4770 */
1152 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1153 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1154 s->arb_mode = I915_READ(ARB_MODE);
1155 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1156 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1157
1158 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1159 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1160
1161 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1162 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1163
1164 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1165 s->ecochk = I915_READ(GAM_ECOCHK);
1166 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1167 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1168
1169 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1170
1171 /* MBC 0x9024-0x91D0, 0x8500 */
1172 s->g3dctl = I915_READ(VLV_G3DCTL);
1173 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1174 s->mbctl = I915_READ(GEN6_MBCTL);
1175
1176 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1177 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1178 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1179 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1180 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1181 s->rstctl = I915_READ(GEN6_RSTCTL);
1182 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1183
1184 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1185 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1186 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1187 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1188 s->ecobus = I915_READ(ECOBUS);
1189 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1190 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1191 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1192 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1193 s->rcedata = I915_READ(VLV_RCEDATA);
1194 s->spare2gh = I915_READ(VLV_SPAREG2H);
1195
1196 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1197 s->gt_imr = I915_READ(GTIMR);
1198 s->gt_ier = I915_READ(GTIER);
1199 s->pm_imr = I915_READ(GEN6_PMIMR);
1200 s->pm_ier = I915_READ(GEN6_PMIER);
1201
1202 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1203 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1204
1205 /* GT SA CZ domain, 0x100000-0x138124 */
1206 s->tilectl = I915_READ(TILECTL);
1207 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1208 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1209 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1210 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1211
1212 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1213 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1214 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1215 s->pcbr = I915_READ(VLV_PCBR);
1216 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1217
1218 /*
1219 * Not saving any of:
1220 * DFT, 0x9800-0x9EC0
1221 * SARB, 0xB000-0xB1FC
1222 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1223 * PCI CFG
1224 */
1225}
1226
1227static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1228{
1229 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1230 u32 val;
1231 int i;
1232
1233 /* GAM 0x4000-0x4770 */
1234 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1235 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1236 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1237 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1238 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1239
1240 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1241 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1242
1243 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1244 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1245
1246 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1247 I915_WRITE(GAM_ECOCHK, s->ecochk);
1248 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1249 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1250
1251 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1252
1253 /* MBC 0x9024-0x91D0, 0x8500 */
1254 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1255 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1256 I915_WRITE(GEN6_MBCTL, s->mbctl);
1257
1258 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1259 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1260 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1261 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1262 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1263 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1264 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1265
1266 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1267 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1268 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1269 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1270 I915_WRITE(ECOBUS, s->ecobus);
1271 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1272 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1273 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1274 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1275 I915_WRITE(VLV_RCEDATA, s->rcedata);
1276 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1277
1278 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1279 I915_WRITE(GTIMR, s->gt_imr);
1280 I915_WRITE(GTIER, s->gt_ier);
1281 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1282 I915_WRITE(GEN6_PMIER, s->pm_ier);
1283
1284 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1285 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1286
1287 /* GT SA CZ domain, 0x100000-0x138124 */
1288 I915_WRITE(TILECTL, s->tilectl);
1289 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1290 /*
1291 * Preserve the GT allow wake and GFX force clock bit, they are not
1292 * be restored, as they are used to control the s0ix suspend/resume
1293 * sequence by the caller.
1294 */
1295 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1296 val &= VLV_GTLC_ALLOWWAKEREQ;
1297 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1298 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1299
1300 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1301 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1302 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1303 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1304
1305 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1306
1307 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1308 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1309 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1310 I915_WRITE(VLV_PCBR, s->pcbr);
1311 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1312}
1313
1314int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1315{
1316 u32 val;
1317 int err;
1318
1319#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1320
1321 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1322 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1323 if (force_on)
1324 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1325 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1326
1327 if (!force_on)
1328 return 0;
1329
1330 err = wait_for(COND, 20);
1331 if (err)
1332 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1333 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1334
1335 return err;
1336#undef COND
1337}
1338
1339static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1340{
1341 u32 val;
1342 int err = 0;
1343
1344 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1345 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1346 if (allow)
1347 val |= VLV_GTLC_ALLOWWAKEREQ;
1348 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1349 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1350
1351#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1352 allow)
1353 err = wait_for(COND, 1);
1354 if (err)
1355 DRM_ERROR("timeout disabling GT waking\n");
1356 return err;
1357#undef COND
1358}
1359
1360static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1361 bool wait_for_on)
1362{
1363 u32 mask;
1364 u32 val;
1365 int err;
1366
1367 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1368 val = wait_for_on ? mask : 0;
1369#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1370 if (COND)
1371 return 0;
1372
1373 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1374 onoff(wait_for_on),
1375 I915_READ(VLV_GTLC_PW_STATUS));
1376
1377 /*
1378 * RC6 transitioning can be delayed up to 2 msec (see
1379 * valleyview_enable_rps), use 3 msec for safety.
1380 */
1381 err = wait_for(COND, 3);
1382 if (err)
1383 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1384 onoff(wait_for_on));
1385
1386 return err;
1387#undef COND
1388}
1389
1390static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1391{
1392 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1393 return;
1394
1395 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1396 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1397}
1398
1399static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1400{
1401 u32 mask;
1402 int err;
1403
1404 /*
1405 * Bspec defines the following GT well on flags as debug only, so
1406 * don't treat them as hard failures.
1407 */
1408 (void)vlv_wait_for_gt_wells(dev_priv, false);
1409
1410 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1411 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1412
1413 vlv_check_no_gt_access(dev_priv);
1414
1415 err = vlv_force_gfx_clock(dev_priv, true);
1416 if (err)
1417 goto err1;
1418
1419 err = vlv_allow_gt_wake(dev_priv, false);
1420 if (err)
1421 goto err2;
1422
1423 if (!IS_CHERRYVIEW(dev_priv->dev))
1424 vlv_save_gunit_s0ix_state(dev_priv);
1425
1426 err = vlv_force_gfx_clock(dev_priv, false);
1427 if (err)
1428 goto err2;
1429
1430 return 0;
1431
1432err2:
1433 /* For safety always re-enable waking and disable gfx clock forcing */
1434 vlv_allow_gt_wake(dev_priv, true);
1435err1:
1436 vlv_force_gfx_clock(dev_priv, false);
1437
1438 return err;
1439}
1440
1441static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1442 bool rpm_resume)
1443{
1444 struct drm_device *dev = dev_priv->dev;
1445 int err;
1446 int ret;
1447
1448 /*
1449 * If any of the steps fail just try to continue, that's the best we
1450 * can do at this point. Return the first error code (which will also
1451 * leave RPM permanently disabled).
1452 */
1453 ret = vlv_force_gfx_clock(dev_priv, true);
1454
1455 if (!IS_CHERRYVIEW(dev_priv->dev))
1456 vlv_restore_gunit_s0ix_state(dev_priv);
1457
1458 err = vlv_allow_gt_wake(dev_priv, true);
1459 if (!ret)
1460 ret = err;
1461
1462 err = vlv_force_gfx_clock(dev_priv, false);
1463 if (!ret)
1464 ret = err;
1465
1466 vlv_check_no_gt_access(dev_priv);
1467
1468 if (rpm_resume) {
1469 intel_init_clock_gating(dev);
1470 i915_gem_restore_fences(dev);
1471 }
1472
1473 return ret;
1474}
1475
1476static int intel_runtime_suspend(struct device *device)
1477{
1478 struct pci_dev *pdev = to_pci_dev(device);
1479 struct drm_device *dev = pci_get_drvdata(pdev);
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 int ret;
1482
1483 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1484 return -ENODEV;
1485
1486 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1487 return -ENODEV;
1488
1489 DRM_DEBUG_KMS("Suspending device\n");
1490
1491 /*
1492 * We could deadlock here in case another thread holding struct_mutex
1493 * calls RPM suspend concurrently, since the RPM suspend will wait
1494 * first for this RPM suspend to finish. In this case the concurrent
1495 * RPM resume will be followed by its RPM suspend counterpart. Still
1496 * for consistency return -EAGAIN, which will reschedule this suspend.
1497 */
1498 if (!mutex_trylock(&dev->struct_mutex)) {
1499 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1500 /*
1501 * Bump the expiration timestamp, otherwise the suspend won't
1502 * be rescheduled.
1503 */
1504 pm_runtime_mark_last_busy(device);
1505
1506 return -EAGAIN;
1507 }
1508
1509 disable_rpm_wakeref_asserts(dev_priv);
1510
1511 /*
1512 * We are safe here against re-faults, since the fault handler takes
1513 * an RPM reference.
1514 */
1515 i915_gem_release_all_mmaps(dev_priv);
1516 mutex_unlock(&dev->struct_mutex);
1517
1518 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1519
1520 intel_guc_suspend(dev);
1521
1522 intel_suspend_gt_powersave(dev);
1523 intel_runtime_pm_disable_interrupts(dev_priv);
1524
1525 ret = intel_suspend_complete(dev_priv);
1526 if (ret) {
1527 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1528 intel_runtime_pm_enable_interrupts(dev_priv);
1529
1530 enable_rpm_wakeref_asserts(dev_priv);
1531
1532 return ret;
1533 }
1534
1535 intel_uncore_forcewake_reset(dev, false);
1536
1537 enable_rpm_wakeref_asserts(dev_priv);
1538 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1539
1540 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1541 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1542
1543 dev_priv->pm.suspended = true;
1544
1545 /*
1546 * FIXME: We really should find a document that references the arguments
1547 * used below!
1548 */
1549 if (IS_BROADWELL(dev)) {
1550 /*
1551 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1552 * being detected, and the call we do at intel_runtime_resume()
1553 * won't be able to restore them. Since PCI_D3hot matches the
1554 * actual specification and appears to be working, use it.
1555 */
1556 intel_opregion_notify_adapter(dev, PCI_D3hot);
1557 } else {
1558 /*
1559 * current versions of firmware which depend on this opregion
1560 * notification have repurposed the D1 definition to mean
1561 * "runtime suspended" vs. what you would normally expect (D3)
1562 * to distinguish it from notifications that might be sent via
1563 * the suspend path.
1564 */
1565 intel_opregion_notify_adapter(dev, PCI_D1);
1566 }
1567
1568 assert_forcewakes_inactive(dev_priv);
1569
1570 DRM_DEBUG_KMS("Device suspended\n");
1571 return 0;
1572}
1573
1574static int intel_runtime_resume(struct device *device)
1575{
1576 struct pci_dev *pdev = to_pci_dev(device);
1577 struct drm_device *dev = pci_get_drvdata(pdev);
1578 struct drm_i915_private *dev_priv = dev->dev_private;
1579 int ret = 0;
1580
1581 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1582 return -ENODEV;
1583
1584 DRM_DEBUG_KMS("Resuming device\n");
1585
1586 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1587 disable_rpm_wakeref_asserts(dev_priv);
1588
1589 intel_opregion_notify_adapter(dev, PCI_D0);
1590 dev_priv->pm.suspended = false;
1591 if (intel_uncore_unclaimed_mmio(dev_priv))
1592 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1593
1594 intel_guc_resume(dev);
1595
1596 if (IS_GEN6(dev_priv))
1597 intel_init_pch_refclk(dev);
1598
1599 if (IS_BROXTON(dev))
1600 ret = bxt_resume_prepare(dev_priv);
1601 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1602 hsw_disable_pc8(dev_priv);
1603 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1604 ret = vlv_resume_prepare(dev_priv, true);
1605
1606 /*
1607 * No point of rolling back things in case of an error, as the best
1608 * we can do is to hope that things will still work (and disable RPM).
1609 */
1610 i915_gem_init_swizzling(dev);
1611 gen6_update_ring_freq(dev);
1612
1613 intel_runtime_pm_enable_interrupts(dev_priv);
1614
1615 /*
1616 * On VLV/CHV display interrupts are part of the display
1617 * power well, so hpd is reinitialized from there. For
1618 * everyone else do it here.
1619 */
1620 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1621 intel_hpd_init(dev_priv);
1622
1623 intel_enable_gt_powersave(dev);
1624
1625 enable_rpm_wakeref_asserts(dev_priv);
1626
1627 if (ret)
1628 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1629 else
1630 DRM_DEBUG_KMS("Device resumed\n");
1631
1632 return ret;
1633}
1634
1635/*
1636 * This function implements common functionality of runtime and system
1637 * suspend sequence.
1638 */
1639static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1640{
1641 int ret;
1642
1643 if (IS_BROXTON(dev_priv))
1644 ret = bxt_suspend_complete(dev_priv);
1645 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1646 ret = hsw_suspend_complete(dev_priv);
1647 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1648 ret = vlv_suspend_complete(dev_priv);
1649 else
1650 ret = 0;
1651
1652 return ret;
1653}
1654
1655static const struct dev_pm_ops i915_pm_ops = {
1656 /*
1657 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1658 * PMSG_RESUME]
1659 */
1660 .suspend = i915_pm_suspend,
1661 .suspend_late = i915_pm_suspend_late,
1662 .resume_early = i915_pm_resume_early,
1663 .resume = i915_pm_resume,
1664
1665 /*
1666 * S4 event handlers
1667 * @freeze, @freeze_late : called (1) before creating the
1668 * hibernation image [PMSG_FREEZE] and
1669 * (2) after rebooting, before restoring
1670 * the image [PMSG_QUIESCE]
1671 * @thaw, @thaw_early : called (1) after creating the hibernation
1672 * image, before writing it [PMSG_THAW]
1673 * and (2) after failing to create or
1674 * restore the image [PMSG_RECOVER]
1675 * @poweroff, @poweroff_late: called after writing the hibernation
1676 * image, before rebooting [PMSG_HIBERNATE]
1677 * @restore, @restore_early : called after rebooting and restoring the
1678 * hibernation image [PMSG_RESTORE]
1679 */
1680 .freeze = i915_pm_suspend,
1681 .freeze_late = i915_pm_suspend_late,
1682 .thaw_early = i915_pm_resume_early,
1683 .thaw = i915_pm_resume,
1684 .poweroff = i915_pm_suspend,
1685 .poweroff_late = i915_pm_poweroff_late,
1686 .restore_early = i915_pm_resume_early,
1687 .restore = i915_pm_resume,
1688
1689 /* S0ix (via runtime suspend) event handlers */
1690 .runtime_suspend = intel_runtime_suspend,
1691 .runtime_resume = intel_runtime_resume,
1692};
1693
1694static const struct vm_operations_struct i915_gem_vm_ops = {
1695 .fault = i915_gem_fault,
1696 .open = drm_gem_vm_open,
1697 .close = drm_gem_vm_close,
1698};
1699
1700static const struct file_operations i915_driver_fops = {
1701 .owner = THIS_MODULE,
1702 .open = drm_open,
1703 .release = drm_release,
1704 .unlocked_ioctl = drm_ioctl,
1705 .mmap = drm_gem_mmap,
1706 .poll = drm_poll,
1707 .read = drm_read,
1708#ifdef CONFIG_COMPAT
1709 .compat_ioctl = i915_compat_ioctl,
1710#endif
1711 .llseek = noop_llseek,
1712};
1713
1714static struct drm_driver driver = {
1715 /* Don't use MTRRs here; the Xserver or userspace app should
1716 * deal with them for Intel hardware.
1717 */
1718 .driver_features =
1719 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1720 DRIVER_RENDER | DRIVER_MODESET,
1721 .load = i915_driver_load,
1722 .unload = i915_driver_unload,
1723 .open = i915_driver_open,
1724 .lastclose = i915_driver_lastclose,
1725 .preclose = i915_driver_preclose,
1726 .postclose = i915_driver_postclose,
1727 .set_busid = drm_pci_set_busid,
1728
1729#if defined(CONFIG_DEBUG_FS)
1730 .debugfs_init = i915_debugfs_init,
1731 .debugfs_cleanup = i915_debugfs_cleanup,
1732#endif
1733 .gem_free_object = i915_gem_free_object,
1734 .gem_vm_ops = &i915_gem_vm_ops,
1735
1736 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1737 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1738 .gem_prime_export = i915_gem_prime_export,
1739 .gem_prime_import = i915_gem_prime_import,
1740
1741 .dumb_create = i915_gem_dumb_create,
1742 .dumb_map_offset = i915_gem_mmap_gtt,
1743 .dumb_destroy = drm_gem_dumb_destroy,
1744 .ioctls = i915_ioctls,
1745 .fops = &i915_driver_fops,
1746 .name = DRIVER_NAME,
1747 .desc = DRIVER_DESC,
1748 .date = DRIVER_DATE,
1749 .major = DRIVER_MAJOR,
1750 .minor = DRIVER_MINOR,
1751 .patchlevel = DRIVER_PATCHLEVEL,
1752};
1753
1754static struct pci_driver i915_pci_driver = {
1755 .name = DRIVER_NAME,
1756 .id_table = pciidlist,
1757 .probe = i915_pci_probe,
1758 .remove = i915_pci_remove,
1759 .driver.pm = &i915_pm_ops,
1760};
1761
1762static int __init i915_init(void)
1763{
1764 driver.num_ioctls = i915_max_ioctl;
1765
1766 /*
1767 * Enable KMS by default, unless explicitly overriden by
1768 * either the i915.modeset prarameter or by the
1769 * vga_text_mode_force boot option.
1770 */
1771
1772 if (i915.modeset == 0)
1773 driver.driver_features &= ~DRIVER_MODESET;
1774
1775#ifdef CONFIG_VGA_CONSOLE
1776 if (vgacon_text_force() && i915.modeset == -1)
1777 driver.driver_features &= ~DRIVER_MODESET;
1778#endif
1779
1780 if (!(driver.driver_features & DRIVER_MODESET)) {
1781 /* Silently fail loading to not upset userspace. */
1782 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1783 return 0;
1784 }
1785
1786 if (i915.nuclear_pageflip)
1787 driver.driver_features |= DRIVER_ATOMIC;
1788
1789 return drm_pci_init(&driver, &i915_pci_driver);
1790}
1791
1792static void __exit i915_exit(void)
1793{
1794 if (!(driver.driver_features & DRIVER_MODESET))
1795 return; /* Never loaded a driver. */
1796
1797 drm_pci_exit(&driver, &i915_pci_driver);
1798}
1799
1800module_init(i915_init);
1801module_exit(i915_exit);
1802
1803MODULE_AUTHOR("Tungsten Graphics, Inc.");
1804MODULE_AUTHOR("Intel Corporation");
1805
1806MODULE_DESCRIPTION(DRIVER_DESC);
1807MODULE_LICENSE("GPL and additional rights");
1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#include <linux/device.h>
31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
35#include "intel_drv.h"
36
37#include <linux/console.h>
38#include <linux/module.h>
39#include "drm_crtc_helper.h"
40
41static int i915_modeset __read_mostly = -1;
42module_param_named(modeset, i915_modeset, int, 0400);
43MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
46
47unsigned int i915_fbpercrtc __always_unused = 0;
48module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50int i915_panel_ignore_lid __read_mostly = 0;
51module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect [default], 1=lid open, "
54 "-1=lid closed)");
55
56unsigned int i915_powersave __read_mostly = 1;
57module_param_named(powersave, i915_powersave, int, 0600);
58MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61int i915_semaphores __read_mostly = -1;
62module_param_named(semaphores, i915_semaphores, int, 0600);
63MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66int i915_enable_rc6 __read_mostly = -1;
67module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
74
75int i915_enable_fbc __read_mostly = -1;
76module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
80
81unsigned int i915_lvds_downclock __read_mostly = 0;
82module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
86
87int i915_lvds_channel_mode __read_mostly;
88module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
93int i915_panel_use_ssc __read_mostly = -1;
94module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
98
99int i915_vbt_sdvo_panel_type __read_mostly = -1;
100module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
104
105static bool i915_try_reset __read_mostly = true;
106module_param_named(reset, i915_try_reset, bool, 0600);
107MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
108
109bool i915_enable_hangcheck __read_mostly = true;
110module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
115
116int i915_enable_ppgtt __read_mostly = -1;
117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
121static struct drm_driver driver;
122extern int intel_agp_enabled;
123
124#define INTEL_VGA_DEVICE(id, info) { \
125 .class = PCI_BASE_CLASS_DISPLAY << 16, \
126 .class_mask = 0xff0000, \
127 .vendor = 0x8086, \
128 .device = id, \
129 .subvendor = PCI_ANY_ID, \
130 .subdevice = PCI_ANY_ID, \
131 .driver_data = (unsigned long) info }
132
133static const struct intel_device_info intel_i830_info = {
134 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
135 .has_overlay = 1, .overlay_needs_physical = 1,
136};
137
138static const struct intel_device_info intel_845g_info = {
139 .gen = 2,
140 .has_overlay = 1, .overlay_needs_physical = 1,
141};
142
143static const struct intel_device_info intel_i85x_info = {
144 .gen = 2, .is_i85x = 1, .is_mobile = 1,
145 .cursor_needs_physical = 1,
146 .has_overlay = 1, .overlay_needs_physical = 1,
147};
148
149static const struct intel_device_info intel_i865g_info = {
150 .gen = 2,
151 .has_overlay = 1, .overlay_needs_physical = 1,
152};
153
154static const struct intel_device_info intel_i915g_info = {
155 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
156 .has_overlay = 1, .overlay_needs_physical = 1,
157};
158static const struct intel_device_info intel_i915gm_info = {
159 .gen = 3, .is_mobile = 1,
160 .cursor_needs_physical = 1,
161 .has_overlay = 1, .overlay_needs_physical = 1,
162 .supports_tv = 1,
163};
164static const struct intel_device_info intel_i945g_info = {
165 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
166 .has_overlay = 1, .overlay_needs_physical = 1,
167};
168static const struct intel_device_info intel_i945gm_info = {
169 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
170 .has_hotplug = 1, .cursor_needs_physical = 1,
171 .has_overlay = 1, .overlay_needs_physical = 1,
172 .supports_tv = 1,
173};
174
175static const struct intel_device_info intel_i965g_info = {
176 .gen = 4, .is_broadwater = 1,
177 .has_hotplug = 1,
178 .has_overlay = 1,
179};
180
181static const struct intel_device_info intel_i965gm_info = {
182 .gen = 4, .is_crestline = 1,
183 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
184 .has_overlay = 1,
185 .supports_tv = 1,
186};
187
188static const struct intel_device_info intel_g33_info = {
189 .gen = 3, .is_g33 = 1,
190 .need_gfx_hws = 1, .has_hotplug = 1,
191 .has_overlay = 1,
192};
193
194static const struct intel_device_info intel_g45_info = {
195 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
196 .has_pipe_cxsr = 1, .has_hotplug = 1,
197 .has_bsd_ring = 1,
198};
199
200static const struct intel_device_info intel_gm45_info = {
201 .gen = 4, .is_g4x = 1,
202 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
203 .has_pipe_cxsr = 1, .has_hotplug = 1,
204 .supports_tv = 1,
205 .has_bsd_ring = 1,
206};
207
208static const struct intel_device_info intel_pineview_info = {
209 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
210 .need_gfx_hws = 1, .has_hotplug = 1,
211 .has_overlay = 1,
212};
213
214static const struct intel_device_info intel_ironlake_d_info = {
215 .gen = 5,
216 .need_gfx_hws = 1, .has_hotplug = 1,
217 .has_bsd_ring = 1,
218 .has_pch_split = 1,
219};
220
221static const struct intel_device_info intel_ironlake_m_info = {
222 .gen = 5, .is_mobile = 1,
223 .need_gfx_hws = 1, .has_hotplug = 1,
224 .has_fbc = 1,
225 .has_bsd_ring = 1,
226 .has_pch_split = 1,
227};
228
229static const struct intel_device_info intel_sandybridge_d_info = {
230 .gen = 6,
231 .need_gfx_hws = 1, .has_hotplug = 1,
232 .has_bsd_ring = 1,
233 .has_blt_ring = 1,
234 .has_llc = 1,
235 .has_pch_split = 1,
236 .has_force_wake = 1,
237};
238
239static const struct intel_device_info intel_sandybridge_m_info = {
240 .gen = 6, .is_mobile = 1,
241 .need_gfx_hws = 1, .has_hotplug = 1,
242 .has_fbc = 1,
243 .has_bsd_ring = 1,
244 .has_blt_ring = 1,
245 .has_llc = 1,
246 .has_pch_split = 1,
247 .has_force_wake = 1,
248};
249
250static const struct intel_device_info intel_ivybridge_d_info = {
251 .is_ivybridge = 1, .gen = 7,
252 .need_gfx_hws = 1, .has_hotplug = 1,
253 .has_bsd_ring = 1,
254 .has_blt_ring = 1,
255 .has_llc = 1,
256 .has_pch_split = 1,
257 .has_force_wake = 1,
258};
259
260static const struct intel_device_info intel_ivybridge_m_info = {
261 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
262 .need_gfx_hws = 1, .has_hotplug = 1,
263 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
264 .has_bsd_ring = 1,
265 .has_blt_ring = 1,
266 .has_llc = 1,
267 .has_pch_split = 1,
268 .has_force_wake = 1,
269};
270
271static const struct intel_device_info intel_valleyview_m_info = {
272 .gen = 7, .is_mobile = 1,
273 .need_gfx_hws = 1, .has_hotplug = 1,
274 .has_fbc = 0,
275 .has_bsd_ring = 1,
276 .has_blt_ring = 1,
277 .is_valleyview = 1,
278};
279
280static const struct intel_device_info intel_valleyview_d_info = {
281 .gen = 7,
282 .need_gfx_hws = 1, .has_hotplug = 1,
283 .has_fbc = 0,
284 .has_bsd_ring = 1,
285 .has_blt_ring = 1,
286 .is_valleyview = 1,
287};
288
289static const struct intel_device_info intel_haswell_d_info = {
290 .is_haswell = 1, .gen = 7,
291 .need_gfx_hws = 1, .has_hotplug = 1,
292 .has_bsd_ring = 1,
293 .has_blt_ring = 1,
294 .has_llc = 1,
295 .has_pch_split = 1,
296 .has_force_wake = 1,
297};
298
299static const struct intel_device_info intel_haswell_m_info = {
300 .is_haswell = 1, .gen = 7, .is_mobile = 1,
301 .need_gfx_hws = 1, .has_hotplug = 1,
302 .has_bsd_ring = 1,
303 .has_blt_ring = 1,
304 .has_llc = 1,
305 .has_pch_split = 1,
306 .has_force_wake = 1,
307};
308
309static const struct pci_device_id pciidlist[] = { /* aka */
310 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
311 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
312 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
313 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
314 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
315 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
316 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
317 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
318 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
319 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
320 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
321 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
322 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
323 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
324 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
325 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
326 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
327 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
328 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
329 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
330 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
331 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
332 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
333 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
334 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
335 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
336 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
337 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
338 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
339 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
340 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
341 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
342 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
343 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
344 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
345 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
346 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
347 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
348 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
349 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
350 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
351 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
352 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
353 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
354 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
355 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
356 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
357 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
358 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
359 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
360 INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
361 {0, 0, 0}
362};
363
364#if defined(CONFIG_DRM_I915_KMS)
365MODULE_DEVICE_TABLE(pci, pciidlist);
366#endif
367
368#define INTEL_PCH_DEVICE_ID_MASK 0xff00
369#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
370#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
371#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
372#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
373
374void intel_detect_pch(struct drm_device *dev)
375{
376 struct drm_i915_private *dev_priv = dev->dev_private;
377 struct pci_dev *pch;
378
379 /*
380 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
381 * make graphics device passthrough work easy for VMM, that only
382 * need to expose ISA bridge to let driver know the real hardware
383 * underneath. This is a requirement from virtualization team.
384 */
385 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
386 if (pch) {
387 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
388 int id;
389 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
390
391 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
392 dev_priv->pch_type = PCH_IBX;
393 dev_priv->num_pch_pll = 2;
394 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
395 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
396 dev_priv->pch_type = PCH_CPT;
397 dev_priv->num_pch_pll = 2;
398 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
399 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
400 /* PantherPoint is CPT compatible */
401 dev_priv->pch_type = PCH_CPT;
402 dev_priv->num_pch_pll = 2;
403 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
404 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
405 dev_priv->pch_type = PCH_LPT;
406 dev_priv->num_pch_pll = 0;
407 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
408 }
409 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
410 }
411 pci_dev_put(pch);
412 }
413}
414
415bool i915_semaphore_is_enabled(struct drm_device *dev)
416{
417 if (INTEL_INFO(dev)->gen < 6)
418 return 0;
419
420 if (i915_semaphores >= 0)
421 return i915_semaphores;
422
423#ifdef CONFIG_INTEL_IOMMU
424 /* Enable semaphores on SNB when IO remapping is off */
425 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
426 return false;
427#endif
428
429 return 1;
430}
431
432void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
433{
434 int count;
435
436 count = 0;
437 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
438 udelay(10);
439
440 I915_WRITE_NOTRACE(FORCEWAKE, 1);
441 POSTING_READ(FORCEWAKE);
442
443 count = 0;
444 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
445 udelay(10);
446}
447
448void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
449{
450 int count;
451
452 count = 0;
453 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
454 udelay(10);
455
456 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
457 POSTING_READ(FORCEWAKE_MT);
458
459 count = 0;
460 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
461 udelay(10);
462}
463
464/*
465 * Generally this is called implicitly by the register read function. However,
466 * if some sequence requires the GT to not power down then this function should
467 * be called at the beginning of the sequence followed by a call to
468 * gen6_gt_force_wake_put() at the end of the sequence.
469 */
470void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
471{
472 unsigned long irqflags;
473
474 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
475 if (dev_priv->forcewake_count++ == 0)
476 dev_priv->display.force_wake_get(dev_priv);
477 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
478}
479
480static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
481{
482 u32 gtfifodbg;
483 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
484 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
485 "MMIO read or write has been dropped %x\n", gtfifodbg))
486 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
487}
488
489void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
490{
491 I915_WRITE_NOTRACE(FORCEWAKE, 0);
492 /* The below doubles as a POSTING_READ */
493 gen6_gt_check_fifodbg(dev_priv);
494}
495
496void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
497{
498 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
499 /* The below doubles as a POSTING_READ */
500 gen6_gt_check_fifodbg(dev_priv);
501}
502
503/*
504 * see gen6_gt_force_wake_get()
505 */
506void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
507{
508 unsigned long irqflags;
509
510 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
511 if (--dev_priv->forcewake_count == 0)
512 dev_priv->display.force_wake_put(dev_priv);
513 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
514}
515
516int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
517{
518 int ret = 0;
519
520 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
521 int loop = 500;
522 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
523 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
524 udelay(10);
525 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
526 }
527 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
528 ++ret;
529 dev_priv->gt_fifo_count = fifo;
530 }
531 dev_priv->gt_fifo_count--;
532
533 return ret;
534}
535
536void vlv_force_wake_get(struct drm_i915_private *dev_priv)
537{
538 int count;
539
540 count = 0;
541
542 /* Already awake? */
543 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
544 return;
545
546 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
547 POSTING_READ(FORCEWAKE_VLV);
548
549 count = 0;
550 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
551 udelay(10);
552}
553
554void vlv_force_wake_put(struct drm_i915_private *dev_priv)
555{
556 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
557 /* FIXME: confirm VLV behavior with Punit folks */
558 POSTING_READ(FORCEWAKE_VLV);
559}
560
561static int i915_drm_freeze(struct drm_device *dev)
562{
563 struct drm_i915_private *dev_priv = dev->dev_private;
564
565 drm_kms_helper_poll_disable(dev);
566
567 pci_save_state(dev->pdev);
568
569 /* If KMS is active, we do the leavevt stuff here */
570 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
571 int error = i915_gem_idle(dev);
572 if (error) {
573 dev_err(&dev->pdev->dev,
574 "GEM idle failed, resume might fail\n");
575 return error;
576 }
577 drm_irq_uninstall(dev);
578 }
579
580 i915_save_state(dev);
581
582 intel_opregion_fini(dev);
583
584 /* Modeset on resume, not lid events */
585 dev_priv->modeset_on_lid = 0;
586
587 console_lock();
588 intel_fbdev_set_suspend(dev, 1);
589 console_unlock();
590
591 return 0;
592}
593
594int i915_suspend(struct drm_device *dev, pm_message_t state)
595{
596 int error;
597
598 if (!dev || !dev->dev_private) {
599 DRM_ERROR("dev: %p\n", dev);
600 DRM_ERROR("DRM not initialized, aborting suspend.\n");
601 return -ENODEV;
602 }
603
604 if (state.event == PM_EVENT_PRETHAW)
605 return 0;
606
607
608 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
609 return 0;
610
611 error = i915_drm_freeze(dev);
612 if (error)
613 return error;
614
615 if (state.event == PM_EVENT_SUSPEND) {
616 /* Shut down the device */
617 pci_disable_device(dev->pdev);
618 pci_set_power_state(dev->pdev, PCI_D3hot);
619 }
620
621 return 0;
622}
623
624static int i915_drm_thaw(struct drm_device *dev)
625{
626 struct drm_i915_private *dev_priv = dev->dev_private;
627 int error = 0;
628
629 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
630 mutex_lock(&dev->struct_mutex);
631 i915_gem_restore_gtt_mappings(dev);
632 mutex_unlock(&dev->struct_mutex);
633 }
634
635 i915_restore_state(dev);
636 intel_opregion_setup(dev);
637
638 /* KMS EnterVT equivalent */
639 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
640 if (HAS_PCH_SPLIT(dev))
641 ironlake_init_pch_refclk(dev);
642
643 mutex_lock(&dev->struct_mutex);
644 dev_priv->mm.suspended = 0;
645
646 error = i915_gem_init_hw(dev);
647 mutex_unlock(&dev->struct_mutex);
648
649 intel_modeset_init_hw(dev);
650 drm_mode_config_reset(dev);
651 drm_irq_install(dev);
652
653 /* Resume the modeset for every activated CRTC */
654 mutex_lock(&dev->mode_config.mutex);
655 drm_helper_resume_force_mode(dev);
656 mutex_unlock(&dev->mode_config.mutex);
657 }
658
659 intel_opregion_init(dev);
660
661 dev_priv->modeset_on_lid = 0;
662
663 console_lock();
664 intel_fbdev_set_suspend(dev, 0);
665 console_unlock();
666 return error;
667}
668
669int i915_resume(struct drm_device *dev)
670{
671 int ret;
672
673 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
674 return 0;
675
676 if (pci_enable_device(dev->pdev))
677 return -EIO;
678
679 pci_set_master(dev->pdev);
680
681 ret = i915_drm_thaw(dev);
682 if (ret)
683 return ret;
684
685 drm_kms_helper_poll_enable(dev);
686 return 0;
687}
688
689static int i8xx_do_reset(struct drm_device *dev)
690{
691 struct drm_i915_private *dev_priv = dev->dev_private;
692
693 if (IS_I85X(dev))
694 return -ENODEV;
695
696 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
697 POSTING_READ(D_STATE);
698
699 if (IS_I830(dev) || IS_845G(dev)) {
700 I915_WRITE(DEBUG_RESET_I830,
701 DEBUG_RESET_DISPLAY |
702 DEBUG_RESET_RENDER |
703 DEBUG_RESET_FULL);
704 POSTING_READ(DEBUG_RESET_I830);
705 msleep(1);
706
707 I915_WRITE(DEBUG_RESET_I830, 0);
708 POSTING_READ(DEBUG_RESET_I830);
709 }
710
711 msleep(1);
712
713 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
714 POSTING_READ(D_STATE);
715
716 return 0;
717}
718
719static int i965_reset_complete(struct drm_device *dev)
720{
721 u8 gdrst;
722 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
723 return (gdrst & GRDOM_RESET_ENABLE) == 0;
724}
725
726static int i965_do_reset(struct drm_device *dev)
727{
728 int ret;
729 u8 gdrst;
730
731 /*
732 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
733 * well as the reset bit (GR/bit 0). Setting the GR bit
734 * triggers the reset; when done, the hardware will clear it.
735 */
736 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
737 pci_write_config_byte(dev->pdev, I965_GDRST,
738 gdrst | GRDOM_RENDER |
739 GRDOM_RESET_ENABLE);
740 ret = wait_for(i965_reset_complete(dev), 500);
741 if (ret)
742 return ret;
743
744 /* We can't reset render&media without also resetting display ... */
745 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
746 pci_write_config_byte(dev->pdev, I965_GDRST,
747 gdrst | GRDOM_MEDIA |
748 GRDOM_RESET_ENABLE);
749
750 return wait_for(i965_reset_complete(dev), 500);
751}
752
753static int ironlake_do_reset(struct drm_device *dev)
754{
755 struct drm_i915_private *dev_priv = dev->dev_private;
756 u32 gdrst;
757 int ret;
758
759 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
760 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
761 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
762 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
763 if (ret)
764 return ret;
765
766 /* We can't reset render&media without also resetting display ... */
767 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
768 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
769 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
770 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
771}
772
773static int gen6_do_reset(struct drm_device *dev)
774{
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 int ret;
777 unsigned long irqflags;
778
779 /* Hold gt_lock across reset to prevent any register access
780 * with forcewake not set correctly
781 */
782 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
783
784 /* Reset the chip */
785
786 /* GEN6_GDRST is not in the gt power well, no need to check
787 * for fifo space for the write or forcewake the chip for
788 * the read
789 */
790 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
791
792 /* Spin waiting for the device to ack the reset request */
793 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
794
795 /* If reset with a user forcewake, try to restore, otherwise turn it off */
796 if (dev_priv->forcewake_count)
797 dev_priv->display.force_wake_get(dev_priv);
798 else
799 dev_priv->display.force_wake_put(dev_priv);
800
801 /* Restore fifo count */
802 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
803
804 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
805 return ret;
806}
807
808static int intel_gpu_reset(struct drm_device *dev)
809{
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 int ret = -ENODEV;
812
813 switch (INTEL_INFO(dev)->gen) {
814 case 7:
815 case 6:
816 ret = gen6_do_reset(dev);
817 break;
818 case 5:
819 ret = ironlake_do_reset(dev);
820 break;
821 case 4:
822 ret = i965_do_reset(dev);
823 break;
824 case 2:
825 ret = i8xx_do_reset(dev);
826 break;
827 }
828
829 /* Also reset the gpu hangman. */
830 if (dev_priv->stop_rings) {
831 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
832 dev_priv->stop_rings = 0;
833 if (ret == -ENODEV) {
834 DRM_ERROR("Reset not implemented, but ignoring "
835 "error for simulated gpu hangs\n");
836 ret = 0;
837 }
838 }
839
840 return ret;
841}
842
843/**
844 * i915_reset - reset chip after a hang
845 * @dev: drm device to reset
846 *
847 * Reset the chip. Useful if a hang is detected. Returns zero on successful
848 * reset or otherwise an error code.
849 *
850 * Procedure is fairly simple:
851 * - reset the chip using the reset reg
852 * - re-init context state
853 * - re-init hardware status page
854 * - re-init ring buffer
855 * - re-init interrupt state
856 * - re-init display
857 */
858int i915_reset(struct drm_device *dev)
859{
860 drm_i915_private_t *dev_priv = dev->dev_private;
861 int ret;
862
863 if (!i915_try_reset)
864 return 0;
865
866 if (!mutex_trylock(&dev->struct_mutex))
867 return -EBUSY;
868
869 dev_priv->stop_rings = 0;
870
871 i915_gem_reset(dev);
872
873 ret = -ENODEV;
874 if (get_seconds() - dev_priv->last_gpu_reset < 5)
875 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
876 else
877 ret = intel_gpu_reset(dev);
878
879 dev_priv->last_gpu_reset = get_seconds();
880 if (ret) {
881 DRM_ERROR("Failed to reset chip.\n");
882 mutex_unlock(&dev->struct_mutex);
883 return ret;
884 }
885
886 /* Ok, now get things going again... */
887
888 /*
889 * Everything depends on having the GTT running, so we need to start
890 * there. Fortunately we don't need to do this unless we reset the
891 * chip at a PCI level.
892 *
893 * Next we need to restore the context, but we don't use those
894 * yet either...
895 *
896 * Ring buffer needs to be re-initialized in the KMS case, or if X
897 * was running at the time of the reset (i.e. we weren't VT
898 * switched away).
899 */
900 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
901 !dev_priv->mm.suspended) {
902 struct intel_ring_buffer *ring;
903 int i;
904
905 dev_priv->mm.suspended = 0;
906
907 i915_gem_init_swizzling(dev);
908
909 for_each_ring(ring, dev_priv, i)
910 ring->init(ring);
911
912 i915_gem_init_ppgtt(dev);
913
914 mutex_unlock(&dev->struct_mutex);
915
916 if (drm_core_check_feature(dev, DRIVER_MODESET))
917 intel_modeset_init_hw(dev);
918
919 drm_irq_uninstall(dev);
920 drm_irq_install(dev);
921 } else {
922 mutex_unlock(&dev->struct_mutex);
923 }
924
925 return 0;
926}
927
928
929static int __devinit
930i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
931{
932 /* Only bind to function 0 of the device. Early generations
933 * used function 1 as a placeholder for multi-head. This causes
934 * us confusion instead, especially on the systems where both
935 * functions have the same PCI-ID!
936 */
937 if (PCI_FUNC(pdev->devfn))
938 return -ENODEV;
939
940 return drm_get_pci_dev(pdev, ent, &driver);
941}
942
943static void
944i915_pci_remove(struct pci_dev *pdev)
945{
946 struct drm_device *dev = pci_get_drvdata(pdev);
947
948 drm_put_dev(dev);
949}
950
951static int i915_pm_suspend(struct device *dev)
952{
953 struct pci_dev *pdev = to_pci_dev(dev);
954 struct drm_device *drm_dev = pci_get_drvdata(pdev);
955 int error;
956
957 if (!drm_dev || !drm_dev->dev_private) {
958 dev_err(dev, "DRM not initialized, aborting suspend.\n");
959 return -ENODEV;
960 }
961
962 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
963 return 0;
964
965 error = i915_drm_freeze(drm_dev);
966 if (error)
967 return error;
968
969 pci_disable_device(pdev);
970 pci_set_power_state(pdev, PCI_D3hot);
971
972 return 0;
973}
974
975static int i915_pm_resume(struct device *dev)
976{
977 struct pci_dev *pdev = to_pci_dev(dev);
978 struct drm_device *drm_dev = pci_get_drvdata(pdev);
979
980 return i915_resume(drm_dev);
981}
982
983static int i915_pm_freeze(struct device *dev)
984{
985 struct pci_dev *pdev = to_pci_dev(dev);
986 struct drm_device *drm_dev = pci_get_drvdata(pdev);
987
988 if (!drm_dev || !drm_dev->dev_private) {
989 dev_err(dev, "DRM not initialized, aborting suspend.\n");
990 return -ENODEV;
991 }
992
993 return i915_drm_freeze(drm_dev);
994}
995
996static int i915_pm_thaw(struct device *dev)
997{
998 struct pci_dev *pdev = to_pci_dev(dev);
999 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1000
1001 return i915_drm_thaw(drm_dev);
1002}
1003
1004static int i915_pm_poweroff(struct device *dev)
1005{
1006 struct pci_dev *pdev = to_pci_dev(dev);
1007 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1008
1009 return i915_drm_freeze(drm_dev);
1010}
1011
1012static const struct dev_pm_ops i915_pm_ops = {
1013 .suspend = i915_pm_suspend,
1014 .resume = i915_pm_resume,
1015 .freeze = i915_pm_freeze,
1016 .thaw = i915_pm_thaw,
1017 .poweroff = i915_pm_poweroff,
1018 .restore = i915_pm_resume,
1019};
1020
1021static const struct vm_operations_struct i915_gem_vm_ops = {
1022 .fault = i915_gem_fault,
1023 .open = drm_gem_vm_open,
1024 .close = drm_gem_vm_close,
1025};
1026
1027static const struct file_operations i915_driver_fops = {
1028 .owner = THIS_MODULE,
1029 .open = drm_open,
1030 .release = drm_release,
1031 .unlocked_ioctl = drm_ioctl,
1032 .mmap = drm_gem_mmap,
1033 .poll = drm_poll,
1034 .fasync = drm_fasync,
1035 .read = drm_read,
1036#ifdef CONFIG_COMPAT
1037 .compat_ioctl = i915_compat_ioctl,
1038#endif
1039 .llseek = noop_llseek,
1040};
1041
1042static struct drm_driver driver = {
1043 /* Don't use MTRRs here; the Xserver or userspace app should
1044 * deal with them for Intel hardware.
1045 */
1046 .driver_features =
1047 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1048 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1049 .load = i915_driver_load,
1050 .unload = i915_driver_unload,
1051 .open = i915_driver_open,
1052 .lastclose = i915_driver_lastclose,
1053 .preclose = i915_driver_preclose,
1054 .postclose = i915_driver_postclose,
1055
1056 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1057 .suspend = i915_suspend,
1058 .resume = i915_resume,
1059
1060 .device_is_agp = i915_driver_device_is_agp,
1061 .reclaim_buffers = drm_core_reclaim_buffers,
1062 .master_create = i915_master_create,
1063 .master_destroy = i915_master_destroy,
1064#if defined(CONFIG_DEBUG_FS)
1065 .debugfs_init = i915_debugfs_init,
1066 .debugfs_cleanup = i915_debugfs_cleanup,
1067#endif
1068 .gem_init_object = i915_gem_init_object,
1069 .gem_free_object = i915_gem_free_object,
1070 .gem_vm_ops = &i915_gem_vm_ops,
1071
1072 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1073 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1074 .gem_prime_export = i915_gem_prime_export,
1075 .gem_prime_import = i915_gem_prime_import,
1076
1077 .dumb_create = i915_gem_dumb_create,
1078 .dumb_map_offset = i915_gem_mmap_gtt,
1079 .dumb_destroy = i915_gem_dumb_destroy,
1080 .ioctls = i915_ioctls,
1081 .fops = &i915_driver_fops,
1082 .name = DRIVER_NAME,
1083 .desc = DRIVER_DESC,
1084 .date = DRIVER_DATE,
1085 .major = DRIVER_MAJOR,
1086 .minor = DRIVER_MINOR,
1087 .patchlevel = DRIVER_PATCHLEVEL,
1088};
1089
1090static struct pci_driver i915_pci_driver = {
1091 .name = DRIVER_NAME,
1092 .id_table = pciidlist,
1093 .probe = i915_pci_probe,
1094 .remove = i915_pci_remove,
1095 .driver.pm = &i915_pm_ops,
1096};
1097
1098static int __init i915_init(void)
1099{
1100 if (!intel_agp_enabled) {
1101 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1102 return -ENODEV;
1103 }
1104
1105 driver.num_ioctls = i915_max_ioctl;
1106
1107 /*
1108 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1109 * explicitly disabled with the module pararmeter.
1110 *
1111 * Otherwise, just follow the parameter (defaulting to off).
1112 *
1113 * Allow optional vga_text_mode_force boot option to override
1114 * the default behavior.
1115 */
1116#if defined(CONFIG_DRM_I915_KMS)
1117 if (i915_modeset != 0)
1118 driver.driver_features |= DRIVER_MODESET;
1119#endif
1120 if (i915_modeset == 1)
1121 driver.driver_features |= DRIVER_MODESET;
1122
1123#ifdef CONFIG_VGA_CONSOLE
1124 if (vgacon_text_force() && i915_modeset == -1)
1125 driver.driver_features &= ~DRIVER_MODESET;
1126#endif
1127
1128 if (!(driver.driver_features & DRIVER_MODESET))
1129 driver.get_vblank_timestamp = NULL;
1130
1131 return drm_pci_init(&driver, &i915_pci_driver);
1132}
1133
1134static void __exit i915_exit(void)
1135{
1136 drm_pci_exit(&driver, &i915_pci_driver);
1137}
1138
1139module_init(i915_init);
1140module_exit(i915_exit);
1141
1142MODULE_AUTHOR(DRIVER_AUTHOR);
1143MODULE_DESCRIPTION(DRIVER_DESC);
1144MODULE_LICENSE("GPL and additional rights");
1145
1146/* We give fast paths for the really cool registers */
1147#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1148 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1149 ((reg) < 0x40000) && \
1150 ((reg) != FORCEWAKE))
1151
1152#define __i915_read(x, y) \
1153u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1154 u##x val = 0; \
1155 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1156 unsigned long irqflags; \
1157 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1158 if (dev_priv->forcewake_count == 0) \
1159 dev_priv->display.force_wake_get(dev_priv); \
1160 val = read##y(dev_priv->regs + reg); \
1161 if (dev_priv->forcewake_count == 0) \
1162 dev_priv->display.force_wake_put(dev_priv); \
1163 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1164 } else { \
1165 val = read##y(dev_priv->regs + reg); \
1166 } \
1167 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1168 return val; \
1169}
1170
1171__i915_read(8, b)
1172__i915_read(16, w)
1173__i915_read(32, l)
1174__i915_read(64, q)
1175#undef __i915_read
1176
1177#define __i915_write(x, y) \
1178void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1179 u32 __fifo_ret = 0; \
1180 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1181 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1182 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1183 } \
1184 write##y(val, dev_priv->regs + reg); \
1185 if (unlikely(__fifo_ret)) { \
1186 gen6_gt_check_fifodbg(dev_priv); \
1187 } \
1188}
1189__i915_write(8, b)
1190__i915_write(16, w)
1191__i915_write(32, l)
1192__i915_write(64, q)
1193#undef __i915_write