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1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/mixer_reg.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include <drm/drmP.h>
18
19#include "regs-mixer.h"
20#include "regs-vp.h"
21
22#include <linux/kernel.h>
23#include <linux/spinlock.h>
24#include <linux/wait.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/delay.h>
30#include <linux/pm_runtime.h>
31#include <linux/clk.h>
32#include <linux/regulator/consumer.h>
33#include <linux/of.h>
34#include <linux/component.h>
35
36#include <drm/exynos_drm.h>
37
38#include "exynos_drm_drv.h"
39#include "exynos_drm_crtc.h"
40#include "exynos_drm_fb.h"
41#include "exynos_drm_plane.h"
42#include "exynos_drm_iommu.h"
43
44#define MIXER_WIN_NR 3
45#define VP_DEFAULT_WIN 2
46
47/* The pixelformats that are natively supported by the mixer. */
48#define MXR_FORMAT_RGB565 4
49#define MXR_FORMAT_ARGB1555 5
50#define MXR_FORMAT_ARGB4444 6
51#define MXR_FORMAT_ARGB8888 7
52
53struct mixer_resources {
54 int irq;
55 void __iomem *mixer_regs;
56 void __iomem *vp_regs;
57 spinlock_t reg_slock;
58 struct clk *mixer;
59 struct clk *vp;
60 struct clk *hdmi;
61 struct clk *sclk_mixer;
62 struct clk *sclk_hdmi;
63 struct clk *mout_mixer;
64};
65
66enum mixer_version_id {
67 MXR_VER_0_0_0_16,
68 MXR_VER_16_0_33_0,
69 MXR_VER_128_0_0_184,
70};
71
72enum mixer_flag_bits {
73 MXR_BIT_POWERED,
74 MXR_BIT_VSYNC,
75};
76
77static const uint32_t mixer_formats[] = {
78 DRM_FORMAT_XRGB4444,
79 DRM_FORMAT_ARGB4444,
80 DRM_FORMAT_XRGB1555,
81 DRM_FORMAT_ARGB1555,
82 DRM_FORMAT_RGB565,
83 DRM_FORMAT_XRGB8888,
84 DRM_FORMAT_ARGB8888,
85};
86
87static const uint32_t vp_formats[] = {
88 DRM_FORMAT_NV12,
89 DRM_FORMAT_NV21,
90};
91
92struct mixer_context {
93 struct platform_device *pdev;
94 struct device *dev;
95 struct drm_device *drm_dev;
96 struct exynos_drm_crtc *crtc;
97 struct exynos_drm_plane planes[MIXER_WIN_NR];
98 int pipe;
99 unsigned long flags;
100 bool interlace;
101 bool vp_enabled;
102 bool has_sclk;
103
104 struct mixer_resources mixer_res;
105 enum mixer_version_id mxr_ver;
106 wait_queue_head_t wait_vsync_queue;
107 atomic_t wait_vsync_event;
108};
109
110struct mixer_drv_data {
111 enum mixer_version_id version;
112 bool is_vp_enabled;
113 bool has_sclk;
114};
115
116static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = {
117 {
118 .zpos = 0,
119 .type = DRM_PLANE_TYPE_PRIMARY,
120 .pixel_formats = mixer_formats,
121 .num_pixel_formats = ARRAY_SIZE(mixer_formats),
122 .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
123 EXYNOS_DRM_PLANE_CAP_ZPOS,
124 }, {
125 .zpos = 1,
126 .type = DRM_PLANE_TYPE_CURSOR,
127 .pixel_formats = mixer_formats,
128 .num_pixel_formats = ARRAY_SIZE(mixer_formats),
129 .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
130 EXYNOS_DRM_PLANE_CAP_ZPOS,
131 }, {
132 .zpos = 2,
133 .type = DRM_PLANE_TYPE_OVERLAY,
134 .pixel_formats = vp_formats,
135 .num_pixel_formats = ARRAY_SIZE(vp_formats),
136 .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE |
137 EXYNOS_DRM_PLANE_CAP_ZPOS,
138 },
139};
140
141static const u8 filter_y_horiz_tap8[] = {
142 0, -1, -1, -1, -1, -1, -1, -1,
143 -1, -1, -1, -1, -1, 0, 0, 0,
144 0, 2, 4, 5, 6, 6, 6, 6,
145 6, 5, 5, 4, 3, 2, 1, 1,
146 0, -6, -12, -16, -18, -20, -21, -20,
147 -20, -18, -16, -13, -10, -8, -5, -2,
148 127, 126, 125, 121, 114, 107, 99, 89,
149 79, 68, 57, 46, 35, 25, 16, 8,
150};
151
152static const u8 filter_y_vert_tap4[] = {
153 0, -3, -6, -8, -8, -8, -8, -7,
154 -6, -5, -4, -3, -2, -1, -1, 0,
155 127, 126, 124, 118, 111, 102, 92, 81,
156 70, 59, 48, 37, 27, 19, 11, 5,
157 0, 5, 11, 19, 27, 37, 48, 59,
158 70, 81, 92, 102, 111, 118, 124, 126,
159 0, 0, -1, -1, -2, -3, -4, -5,
160 -6, -7, -8, -8, -8, -8, -6, -3,
161};
162
163static const u8 filter_cr_horiz_tap4[] = {
164 0, -3, -6, -8, -8, -8, -8, -7,
165 -6, -5, -4, -3, -2, -1, -1, 0,
166 127, 126, 124, 118, 111, 102, 92, 81,
167 70, 59, 48, 37, 27, 19, 11, 5,
168};
169
170static inline bool is_alpha_format(unsigned int pixel_format)
171{
172 switch (pixel_format) {
173 case DRM_FORMAT_ARGB8888:
174 case DRM_FORMAT_ARGB1555:
175 case DRM_FORMAT_ARGB4444:
176 return true;
177 default:
178 return false;
179 }
180}
181
182static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)
183{
184 return readl(res->vp_regs + reg_id);
185}
186
187static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,
188 u32 val)
189{
190 writel(val, res->vp_regs + reg_id);
191}
192
193static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,
194 u32 val, u32 mask)
195{
196 u32 old = vp_reg_read(res, reg_id);
197
198 val = (val & mask) | (old & ~mask);
199 writel(val, res->vp_regs + reg_id);
200}
201
202static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)
203{
204 return readl(res->mixer_regs + reg_id);
205}
206
207static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,
208 u32 val)
209{
210 writel(val, res->mixer_regs + reg_id);
211}
212
213static inline void mixer_reg_writemask(struct mixer_resources *res,
214 u32 reg_id, u32 val, u32 mask)
215{
216 u32 old = mixer_reg_read(res, reg_id);
217
218 val = (val & mask) | (old & ~mask);
219 writel(val, res->mixer_regs + reg_id);
220}
221
222static void mixer_regs_dump(struct mixer_context *ctx)
223{
224#define DUMPREG(reg_id) \
225do { \
226 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
227 (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \
228} while (0)
229
230 DUMPREG(MXR_STATUS);
231 DUMPREG(MXR_CFG);
232 DUMPREG(MXR_INT_EN);
233 DUMPREG(MXR_INT_STATUS);
234
235 DUMPREG(MXR_LAYER_CFG);
236 DUMPREG(MXR_VIDEO_CFG);
237
238 DUMPREG(MXR_GRAPHIC0_CFG);
239 DUMPREG(MXR_GRAPHIC0_BASE);
240 DUMPREG(MXR_GRAPHIC0_SPAN);
241 DUMPREG(MXR_GRAPHIC0_WH);
242 DUMPREG(MXR_GRAPHIC0_SXY);
243 DUMPREG(MXR_GRAPHIC0_DXY);
244
245 DUMPREG(MXR_GRAPHIC1_CFG);
246 DUMPREG(MXR_GRAPHIC1_BASE);
247 DUMPREG(MXR_GRAPHIC1_SPAN);
248 DUMPREG(MXR_GRAPHIC1_WH);
249 DUMPREG(MXR_GRAPHIC1_SXY);
250 DUMPREG(MXR_GRAPHIC1_DXY);
251#undef DUMPREG
252}
253
254static void vp_regs_dump(struct mixer_context *ctx)
255{
256#define DUMPREG(reg_id) \
257do { \
258 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
259 (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \
260} while (0)
261
262 DUMPREG(VP_ENABLE);
263 DUMPREG(VP_SRESET);
264 DUMPREG(VP_SHADOW_UPDATE);
265 DUMPREG(VP_FIELD_ID);
266 DUMPREG(VP_MODE);
267 DUMPREG(VP_IMG_SIZE_Y);
268 DUMPREG(VP_IMG_SIZE_C);
269 DUMPREG(VP_PER_RATE_CTRL);
270 DUMPREG(VP_TOP_Y_PTR);
271 DUMPREG(VP_BOT_Y_PTR);
272 DUMPREG(VP_TOP_C_PTR);
273 DUMPREG(VP_BOT_C_PTR);
274 DUMPREG(VP_ENDIAN_MODE);
275 DUMPREG(VP_SRC_H_POSITION);
276 DUMPREG(VP_SRC_V_POSITION);
277 DUMPREG(VP_SRC_WIDTH);
278 DUMPREG(VP_SRC_HEIGHT);
279 DUMPREG(VP_DST_H_POSITION);
280 DUMPREG(VP_DST_V_POSITION);
281 DUMPREG(VP_DST_WIDTH);
282 DUMPREG(VP_DST_HEIGHT);
283 DUMPREG(VP_H_RATIO);
284 DUMPREG(VP_V_RATIO);
285
286#undef DUMPREG
287}
288
289static inline void vp_filter_set(struct mixer_resources *res,
290 int reg_id, const u8 *data, unsigned int size)
291{
292 /* assure 4-byte align */
293 BUG_ON(size & 3);
294 for (; size; size -= 4, reg_id += 4, data += 4) {
295 u32 val = (data[0] << 24) | (data[1] << 16) |
296 (data[2] << 8) | data[3];
297 vp_reg_write(res, reg_id, val);
298 }
299}
300
301static void vp_default_filter(struct mixer_resources *res)
302{
303 vp_filter_set(res, VP_POLY8_Y0_LL,
304 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
305 vp_filter_set(res, VP_POLY4_Y0_LL,
306 filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
307 vp_filter_set(res, VP_POLY4_C0_LL,
308 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
309}
310
311static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
312 bool alpha)
313{
314 struct mixer_resources *res = &ctx->mixer_res;
315 u32 val;
316
317 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
318 if (alpha) {
319 /* blending based on pixel alpha */
320 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
321 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
322 }
323 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
324 val, MXR_GRP_CFG_MISC_MASK);
325}
326
327static void mixer_cfg_vp_blend(struct mixer_context *ctx)
328{
329 struct mixer_resources *res = &ctx->mixer_res;
330 u32 val;
331
332 /*
333 * No blending at the moment since the NV12/NV21 pixelformats don't
334 * have an alpha channel. However the mixer supports a global alpha
335 * value for a layer. Once this functionality is exposed, we can
336 * support blending of the video layer through this.
337 */
338 val = 0;
339 mixer_reg_write(res, MXR_VIDEO_CFG, val);
340}
341
342static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
343{
344 struct mixer_resources *res = &ctx->mixer_res;
345
346 /* block update on vsync */
347 mixer_reg_writemask(res, MXR_STATUS, enable ?
348 MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
349
350 if (ctx->vp_enabled)
351 vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
352 VP_SHADOW_UPDATE_ENABLE : 0);
353}
354
355static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
356{
357 struct mixer_resources *res = &ctx->mixer_res;
358 u32 val;
359
360 /* choosing between interlace and progressive mode */
361 val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE :
362 MXR_CFG_SCAN_PROGRESSIVE);
363
364 if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
365 /* choosing between proper HD and SD mode */
366 if (height <= 480)
367 val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
368 else if (height <= 576)
369 val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
370 else if (height <= 720)
371 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
372 else if (height <= 1080)
373 val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
374 else
375 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
376 }
377
378 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
379}
380
381static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
382{
383 struct mixer_resources *res = &ctx->mixer_res;
384 u32 val;
385
386 if (height == 480) {
387 val = MXR_CFG_RGB601_0_255;
388 } else if (height == 576) {
389 val = MXR_CFG_RGB601_0_255;
390 } else if (height == 720) {
391 val = MXR_CFG_RGB709_16_235;
392 mixer_reg_write(res, MXR_CM_COEFF_Y,
393 (1 << 30) | (94 << 20) | (314 << 10) |
394 (32 << 0));
395 mixer_reg_write(res, MXR_CM_COEFF_CB,
396 (972 << 20) | (851 << 10) | (225 << 0));
397 mixer_reg_write(res, MXR_CM_COEFF_CR,
398 (225 << 20) | (820 << 10) | (1004 << 0));
399 } else if (height == 1080) {
400 val = MXR_CFG_RGB709_16_235;
401 mixer_reg_write(res, MXR_CM_COEFF_Y,
402 (1 << 30) | (94 << 20) | (314 << 10) |
403 (32 << 0));
404 mixer_reg_write(res, MXR_CM_COEFF_CB,
405 (972 << 20) | (851 << 10) | (225 << 0));
406 mixer_reg_write(res, MXR_CM_COEFF_CR,
407 (225 << 20) | (820 << 10) | (1004 << 0));
408 } else {
409 val = MXR_CFG_RGB709_16_235;
410 mixer_reg_write(res, MXR_CM_COEFF_Y,
411 (1 << 30) | (94 << 20) | (314 << 10) |
412 (32 << 0));
413 mixer_reg_write(res, MXR_CM_COEFF_CB,
414 (972 << 20) | (851 << 10) | (225 << 0));
415 mixer_reg_write(res, MXR_CM_COEFF_CR,
416 (225 << 20) | (820 << 10) | (1004 << 0));
417 }
418
419 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
420}
421
422static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
423 unsigned int priority, bool enable)
424{
425 struct mixer_resources *res = &ctx->mixer_res;
426 u32 val = enable ? ~0 : 0;
427
428 switch (win) {
429 case 0:
430 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
431 mixer_reg_writemask(res, MXR_LAYER_CFG,
432 MXR_LAYER_CFG_GRP0_VAL(priority),
433 MXR_LAYER_CFG_GRP0_MASK);
434 break;
435 case 1:
436 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
437 mixer_reg_writemask(res, MXR_LAYER_CFG,
438 MXR_LAYER_CFG_GRP1_VAL(priority),
439 MXR_LAYER_CFG_GRP1_MASK);
440 break;
441 case VP_DEFAULT_WIN:
442 if (ctx->vp_enabled) {
443 vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
444 mixer_reg_writemask(res, MXR_CFG, val,
445 MXR_CFG_VP_ENABLE);
446 mixer_reg_writemask(res, MXR_LAYER_CFG,
447 MXR_LAYER_CFG_VP_VAL(priority),
448 MXR_LAYER_CFG_VP_MASK);
449 }
450 break;
451 }
452}
453
454static void mixer_run(struct mixer_context *ctx)
455{
456 struct mixer_resources *res = &ctx->mixer_res;
457
458 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
459}
460
461static void mixer_stop(struct mixer_context *ctx)
462{
463 struct mixer_resources *res = &ctx->mixer_res;
464 int timeout = 20;
465
466 mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
467
468 while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
469 --timeout)
470 usleep_range(10000, 12000);
471}
472
473static void vp_video_buffer(struct mixer_context *ctx,
474 struct exynos_drm_plane *plane)
475{
476 struct exynos_drm_plane_state *state =
477 to_exynos_plane_state(plane->base.state);
478 struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode;
479 struct mixer_resources *res = &ctx->mixer_res;
480 struct drm_framebuffer *fb = state->base.fb;
481 unsigned long flags;
482 dma_addr_t luma_addr[2], chroma_addr[2];
483 bool tiled_mode = false;
484 bool crcb_mode = false;
485 u32 val;
486
487 switch (fb->pixel_format) {
488 case DRM_FORMAT_NV12:
489 crcb_mode = false;
490 break;
491 case DRM_FORMAT_NV21:
492 crcb_mode = true;
493 break;
494 default:
495 DRM_ERROR("pixel format for vp is wrong [%d].\n",
496 fb->pixel_format);
497 return;
498 }
499
500 luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0);
501 chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);
502
503 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
504 ctx->interlace = true;
505 if (tiled_mode) {
506 luma_addr[1] = luma_addr[0] + 0x40;
507 chroma_addr[1] = chroma_addr[0] + 0x40;
508 } else {
509 luma_addr[1] = luma_addr[0] + fb->pitches[0];
510 chroma_addr[1] = chroma_addr[0] + fb->pitches[0];
511 }
512 } else {
513 ctx->interlace = false;
514 luma_addr[1] = 0;
515 chroma_addr[1] = 0;
516 }
517
518 spin_lock_irqsave(&res->reg_slock, flags);
519
520 /* interlace or progressive scan mode */
521 val = (ctx->interlace ? ~0 : 0);
522 vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
523
524 /* setup format */
525 val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
526 val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
527 vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
528
529 /* setting size of input image */
530 vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
531 VP_IMG_VSIZE(fb->height));
532 /* chroma height has to reduced by 2 to avoid chroma distorions */
533 vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) |
534 VP_IMG_VSIZE(fb->height / 2));
535
536 vp_reg_write(res, VP_SRC_WIDTH, state->src.w);
537 vp_reg_write(res, VP_SRC_HEIGHT, state->src.h);
538 vp_reg_write(res, VP_SRC_H_POSITION,
539 VP_SRC_H_POSITION_VAL(state->src.x));
540 vp_reg_write(res, VP_SRC_V_POSITION, state->src.y);
541
542 vp_reg_write(res, VP_DST_WIDTH, state->crtc.w);
543 vp_reg_write(res, VP_DST_H_POSITION, state->crtc.x);
544 if (ctx->interlace) {
545 vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h / 2);
546 vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y / 2);
547 } else {
548 vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h);
549 vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y);
550 }
551
552 vp_reg_write(res, VP_H_RATIO, state->h_ratio);
553 vp_reg_write(res, VP_V_RATIO, state->v_ratio);
554
555 vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
556
557 /* set buffer address to vp */
558 vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);
559 vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);
560 vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);
561 vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);
562
563 mixer_cfg_scan(ctx, mode->vdisplay);
564 mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
565 mixer_cfg_layer(ctx, plane->index, state->zpos + 1, true);
566 mixer_cfg_vp_blend(ctx);
567 mixer_run(ctx);
568
569 spin_unlock_irqrestore(&res->reg_slock, flags);
570
571 mixer_regs_dump(ctx);
572 vp_regs_dump(ctx);
573}
574
575static void mixer_layer_update(struct mixer_context *ctx)
576{
577 struct mixer_resources *res = &ctx->mixer_res;
578
579 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
580}
581
582static void mixer_graph_buffer(struct mixer_context *ctx,
583 struct exynos_drm_plane *plane)
584{
585 struct exynos_drm_plane_state *state =
586 to_exynos_plane_state(plane->base.state);
587 struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode;
588 struct mixer_resources *res = &ctx->mixer_res;
589 struct drm_framebuffer *fb = state->base.fb;
590 unsigned long flags;
591 unsigned int win = plane->index;
592 unsigned int x_ratio = 0, y_ratio = 0;
593 unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
594 dma_addr_t dma_addr;
595 unsigned int fmt;
596 u32 val;
597
598 switch (fb->pixel_format) {
599 case DRM_FORMAT_XRGB4444:
600 case DRM_FORMAT_ARGB4444:
601 fmt = MXR_FORMAT_ARGB4444;
602 break;
603
604 case DRM_FORMAT_XRGB1555:
605 case DRM_FORMAT_ARGB1555:
606 fmt = MXR_FORMAT_ARGB1555;
607 break;
608
609 case DRM_FORMAT_RGB565:
610 fmt = MXR_FORMAT_RGB565;
611 break;
612
613 case DRM_FORMAT_XRGB8888:
614 case DRM_FORMAT_ARGB8888:
615 fmt = MXR_FORMAT_ARGB8888;
616 break;
617
618 default:
619 DRM_DEBUG_KMS("pixelformat unsupported by mixer\n");
620 return;
621 }
622
623 /* ratio is already checked by common plane code */
624 x_ratio = state->h_ratio == (1 << 15);
625 y_ratio = state->v_ratio == (1 << 15);
626
627 dst_x_offset = state->crtc.x;
628 dst_y_offset = state->crtc.y;
629
630 /* converting dma address base and source offset */
631 dma_addr = exynos_drm_fb_dma_addr(fb, 0)
632 + (state->src.x * fb->bits_per_pixel >> 3)
633 + (state->src.y * fb->pitches[0]);
634 src_x_offset = 0;
635 src_y_offset = 0;
636
637 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
638 ctx->interlace = true;
639 else
640 ctx->interlace = false;
641
642 spin_lock_irqsave(&res->reg_slock, flags);
643
644 /* setup format */
645 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
646 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);
647
648 /* setup geometry */
649 mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
650 fb->pitches[0] / (fb->bits_per_pixel >> 3));
651
652 /* setup display size */
653 if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
654 win == DEFAULT_WIN) {
655 val = MXR_MXR_RES_HEIGHT(mode->vdisplay);
656 val |= MXR_MXR_RES_WIDTH(mode->hdisplay);
657 mixer_reg_write(res, MXR_RESOLUTION, val);
658 }
659
660 val = MXR_GRP_WH_WIDTH(state->src.w);
661 val |= MXR_GRP_WH_HEIGHT(state->src.h);
662 val |= MXR_GRP_WH_H_SCALE(x_ratio);
663 val |= MXR_GRP_WH_V_SCALE(y_ratio);
664 mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);
665
666 /* setup offsets in source image */
667 val = MXR_GRP_SXY_SX(src_x_offset);
668 val |= MXR_GRP_SXY_SY(src_y_offset);
669 mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val);
670
671 /* setup offsets in display image */
672 val = MXR_GRP_DXY_DX(dst_x_offset);
673 val |= MXR_GRP_DXY_DY(dst_y_offset);
674 mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);
675
676 /* set buffer address to mixer */
677 mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);
678
679 mixer_cfg_scan(ctx, mode->vdisplay);
680 mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
681 mixer_cfg_layer(ctx, win, state->zpos + 1, true);
682 mixer_cfg_gfx_blend(ctx, win, is_alpha_format(fb->pixel_format));
683
684 /* layer update mandatory for mixer 16.0.33.0 */
685 if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
686 ctx->mxr_ver == MXR_VER_128_0_0_184)
687 mixer_layer_update(ctx);
688
689 mixer_run(ctx);
690
691 spin_unlock_irqrestore(&res->reg_slock, flags);
692
693 mixer_regs_dump(ctx);
694}
695
696static void vp_win_reset(struct mixer_context *ctx)
697{
698 struct mixer_resources *res = &ctx->mixer_res;
699 int tries = 100;
700
701 vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);
702 for (tries = 100; tries; --tries) {
703 /* waiting until VP_SRESET_PROCESSING is 0 */
704 if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
705 break;
706 mdelay(10);
707 }
708 WARN(tries == 0, "failed to reset Video Processor\n");
709}
710
711static void mixer_win_reset(struct mixer_context *ctx)
712{
713 struct mixer_resources *res = &ctx->mixer_res;
714 unsigned long flags;
715
716 spin_lock_irqsave(&res->reg_slock, flags);
717
718 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
719
720 /* set output in RGB888 mode */
721 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
722
723 /* 16 beat burst in DMA */
724 mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
725 MXR_STATUS_BURST_MASK);
726
727 /* reset default layer priority */
728 mixer_reg_write(res, MXR_LAYER_CFG, 0);
729
730 /* setting background color */
731 mixer_reg_write(res, MXR_BG_COLOR0, 0x008080);
732 mixer_reg_write(res, MXR_BG_COLOR1, 0x008080);
733 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
734
735 if (ctx->vp_enabled) {
736 /* configuration of Video Processor Registers */
737 vp_win_reset(ctx);
738 vp_default_filter(res);
739 }
740
741 /* disable all layers */
742 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
743 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
744 if (ctx->vp_enabled)
745 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
746
747 spin_unlock_irqrestore(&res->reg_slock, flags);
748}
749
750static irqreturn_t mixer_irq_handler(int irq, void *arg)
751{
752 struct mixer_context *ctx = arg;
753 struct mixer_resources *res = &ctx->mixer_res;
754 u32 val, base, shadow;
755 int win;
756
757 spin_lock(&res->reg_slock);
758
759 /* read interrupt status for handling and clearing flags for VSYNC */
760 val = mixer_reg_read(res, MXR_INT_STATUS);
761
762 /* handling VSYNC */
763 if (val & MXR_INT_STATUS_VSYNC) {
764 /* vsync interrupt use different bit for read and clear */
765 val |= MXR_INT_CLEAR_VSYNC;
766 val &= ~MXR_INT_STATUS_VSYNC;
767
768 /* interlace scan need to check shadow register */
769 if (ctx->interlace) {
770 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
771 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
772 if (base != shadow)
773 goto out;
774
775 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
776 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
777 if (base != shadow)
778 goto out;
779 }
780
781 drm_crtc_handle_vblank(&ctx->crtc->base);
782 for (win = 0 ; win < MIXER_WIN_NR ; win++) {
783 struct exynos_drm_plane *plane = &ctx->planes[win];
784
785 if (!plane->pending_fb)
786 continue;
787
788 exynos_drm_crtc_finish_update(ctx->crtc, plane);
789 }
790
791 /* set wait vsync event to zero and wake up queue. */
792 if (atomic_read(&ctx->wait_vsync_event)) {
793 atomic_set(&ctx->wait_vsync_event, 0);
794 wake_up(&ctx->wait_vsync_queue);
795 }
796 }
797
798out:
799 /* clear interrupts */
800 mixer_reg_write(res, MXR_INT_STATUS, val);
801
802 spin_unlock(&res->reg_slock);
803
804 return IRQ_HANDLED;
805}
806
807static int mixer_resources_init(struct mixer_context *mixer_ctx)
808{
809 struct device *dev = &mixer_ctx->pdev->dev;
810 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
811 struct resource *res;
812 int ret;
813
814 spin_lock_init(&mixer_res->reg_slock);
815
816 mixer_res->mixer = devm_clk_get(dev, "mixer");
817 if (IS_ERR(mixer_res->mixer)) {
818 dev_err(dev, "failed to get clock 'mixer'\n");
819 return -ENODEV;
820 }
821
822 mixer_res->hdmi = devm_clk_get(dev, "hdmi");
823 if (IS_ERR(mixer_res->hdmi)) {
824 dev_err(dev, "failed to get clock 'hdmi'\n");
825 return PTR_ERR(mixer_res->hdmi);
826 }
827
828 mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
829 if (IS_ERR(mixer_res->sclk_hdmi)) {
830 dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
831 return -ENODEV;
832 }
833 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 0);
834 if (res == NULL) {
835 dev_err(dev, "get memory resource failed.\n");
836 return -ENXIO;
837 }
838
839 mixer_res->mixer_regs = devm_ioremap(dev, res->start,
840 resource_size(res));
841 if (mixer_res->mixer_regs == NULL) {
842 dev_err(dev, "register mapping failed.\n");
843 return -ENXIO;
844 }
845
846 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_IRQ, 0);
847 if (res == NULL) {
848 dev_err(dev, "get interrupt resource failed.\n");
849 return -ENXIO;
850 }
851
852 ret = devm_request_irq(dev, res->start, mixer_irq_handler,
853 0, "drm_mixer", mixer_ctx);
854 if (ret) {
855 dev_err(dev, "request interrupt failed.\n");
856 return ret;
857 }
858 mixer_res->irq = res->start;
859
860 return 0;
861}
862
863static int vp_resources_init(struct mixer_context *mixer_ctx)
864{
865 struct device *dev = &mixer_ctx->pdev->dev;
866 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
867 struct resource *res;
868
869 mixer_res->vp = devm_clk_get(dev, "vp");
870 if (IS_ERR(mixer_res->vp)) {
871 dev_err(dev, "failed to get clock 'vp'\n");
872 return -ENODEV;
873 }
874
875 if (mixer_ctx->has_sclk) {
876 mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
877 if (IS_ERR(mixer_res->sclk_mixer)) {
878 dev_err(dev, "failed to get clock 'sclk_mixer'\n");
879 return -ENODEV;
880 }
881 mixer_res->mout_mixer = devm_clk_get(dev, "mout_mixer");
882 if (IS_ERR(mixer_res->mout_mixer)) {
883 dev_err(dev, "failed to get clock 'mout_mixer'\n");
884 return -ENODEV;
885 }
886
887 if (mixer_res->sclk_hdmi && mixer_res->mout_mixer)
888 clk_set_parent(mixer_res->mout_mixer,
889 mixer_res->sclk_hdmi);
890 }
891
892 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1);
893 if (res == NULL) {
894 dev_err(dev, "get memory resource failed.\n");
895 return -ENXIO;
896 }
897
898 mixer_res->vp_regs = devm_ioremap(dev, res->start,
899 resource_size(res));
900 if (mixer_res->vp_regs == NULL) {
901 dev_err(dev, "register mapping failed.\n");
902 return -ENXIO;
903 }
904
905 return 0;
906}
907
908static int mixer_initialize(struct mixer_context *mixer_ctx,
909 struct drm_device *drm_dev)
910{
911 int ret;
912 struct exynos_drm_private *priv;
913 priv = drm_dev->dev_private;
914
915 mixer_ctx->drm_dev = drm_dev;
916 mixer_ctx->pipe = priv->pipe++;
917
918 /* acquire resources: regs, irqs, clocks */
919 ret = mixer_resources_init(mixer_ctx);
920 if (ret) {
921 DRM_ERROR("mixer_resources_init failed ret=%d\n", ret);
922 return ret;
923 }
924
925 if (mixer_ctx->vp_enabled) {
926 /* acquire vp resources: regs, irqs, clocks */
927 ret = vp_resources_init(mixer_ctx);
928 if (ret) {
929 DRM_ERROR("vp_resources_init failed ret=%d\n", ret);
930 return ret;
931 }
932 }
933
934 ret = drm_iommu_attach_device(drm_dev, mixer_ctx->dev);
935 if (ret)
936 priv->pipe--;
937
938 return ret;
939}
940
941static void mixer_ctx_remove(struct mixer_context *mixer_ctx)
942{
943 drm_iommu_detach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
944}
945
946static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
947{
948 struct mixer_context *mixer_ctx = crtc->ctx;
949 struct mixer_resources *res = &mixer_ctx->mixer_res;
950
951 __set_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
952 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
953 return 0;
954
955 /* enable vsync interrupt */
956 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
957 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
958
959 return 0;
960}
961
962static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
963{
964 struct mixer_context *mixer_ctx = crtc->ctx;
965 struct mixer_resources *res = &mixer_ctx->mixer_res;
966
967 __clear_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
968
969 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
970 return;
971
972 /* disable vsync interrupt */
973 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
974 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
975}
976
977static void mixer_atomic_begin(struct exynos_drm_crtc *crtc)
978{
979 struct mixer_context *mixer_ctx = crtc->ctx;
980
981 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
982 return;
983
984 mixer_vsync_set_update(mixer_ctx, false);
985}
986
987static void mixer_update_plane(struct exynos_drm_crtc *crtc,
988 struct exynos_drm_plane *plane)
989{
990 struct mixer_context *mixer_ctx = crtc->ctx;
991
992 DRM_DEBUG_KMS("win: %d\n", plane->index);
993
994 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
995 return;
996
997 if (plane->index == VP_DEFAULT_WIN)
998 vp_video_buffer(mixer_ctx, plane);
999 else
1000 mixer_graph_buffer(mixer_ctx, plane);
1001}
1002
1003static void mixer_disable_plane(struct exynos_drm_crtc *crtc,
1004 struct exynos_drm_plane *plane)
1005{
1006 struct mixer_context *mixer_ctx = crtc->ctx;
1007 struct mixer_resources *res = &mixer_ctx->mixer_res;
1008 unsigned long flags;
1009
1010 DRM_DEBUG_KMS("win: %d\n", plane->index);
1011
1012 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
1013 return;
1014
1015 spin_lock_irqsave(&res->reg_slock, flags);
1016 mixer_cfg_layer(mixer_ctx, plane->index, 0, false);
1017 spin_unlock_irqrestore(&res->reg_slock, flags);
1018}
1019
1020static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
1021{
1022 struct mixer_context *mixer_ctx = crtc->ctx;
1023
1024 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
1025 return;
1026
1027 mixer_vsync_set_update(mixer_ctx, true);
1028}
1029
1030static void mixer_wait_for_vblank(struct exynos_drm_crtc *crtc)
1031{
1032 struct mixer_context *mixer_ctx = crtc->ctx;
1033 int err;
1034
1035 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
1036 return;
1037
1038 err = drm_vblank_get(mixer_ctx->drm_dev, mixer_ctx->pipe);
1039 if (err < 0) {
1040 DRM_DEBUG_KMS("failed to acquire vblank counter\n");
1041 return;
1042 }
1043
1044 atomic_set(&mixer_ctx->wait_vsync_event, 1);
1045
1046 /*
1047 * wait for MIXER to signal VSYNC interrupt or return after
1048 * timeout which is set to 50ms (refresh rate of 20).
1049 */
1050 if (!wait_event_timeout(mixer_ctx->wait_vsync_queue,
1051 !atomic_read(&mixer_ctx->wait_vsync_event),
1052 HZ/20))
1053 DRM_DEBUG_KMS("vblank wait timed out.\n");
1054
1055 drm_vblank_put(mixer_ctx->drm_dev, mixer_ctx->pipe);
1056}
1057
1058static void mixer_enable(struct exynos_drm_crtc *crtc)
1059{
1060 struct mixer_context *ctx = crtc->ctx;
1061 struct mixer_resources *res = &ctx->mixer_res;
1062
1063 if (test_bit(MXR_BIT_POWERED, &ctx->flags))
1064 return;
1065
1066 pm_runtime_get_sync(ctx->dev);
1067
1068 mixer_vsync_set_update(ctx, false);
1069
1070 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
1071
1072 if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) {
1073 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
1074 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
1075 }
1076 mixer_win_reset(ctx);
1077
1078 mixer_vsync_set_update(ctx, true);
1079
1080 set_bit(MXR_BIT_POWERED, &ctx->flags);
1081}
1082
1083static void mixer_disable(struct exynos_drm_crtc *crtc)
1084{
1085 struct mixer_context *ctx = crtc->ctx;
1086 int i;
1087
1088 if (!test_bit(MXR_BIT_POWERED, &ctx->flags))
1089 return;
1090
1091 mixer_stop(ctx);
1092 mixer_regs_dump(ctx);
1093
1094 for (i = 0; i < MIXER_WIN_NR; i++)
1095 mixer_disable_plane(crtc, &ctx->planes[i]);
1096
1097 pm_runtime_put(ctx->dev);
1098
1099 clear_bit(MXR_BIT_POWERED, &ctx->flags);
1100}
1101
1102/* Only valid for Mixer version 16.0.33.0 */
1103static int mixer_atomic_check(struct exynos_drm_crtc *crtc,
1104 struct drm_crtc_state *state)
1105{
1106 struct drm_display_mode *mode = &state->adjusted_mode;
1107 u32 w, h;
1108
1109 w = mode->hdisplay;
1110 h = mode->vdisplay;
1111
1112 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n",
1113 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1114 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1115
1116 if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) ||
1117 (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) ||
1118 (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
1119 return 0;
1120
1121 return -EINVAL;
1122}
1123
1124static const struct exynos_drm_crtc_ops mixer_crtc_ops = {
1125 .enable = mixer_enable,
1126 .disable = mixer_disable,
1127 .enable_vblank = mixer_enable_vblank,
1128 .disable_vblank = mixer_disable_vblank,
1129 .wait_for_vblank = mixer_wait_for_vblank,
1130 .atomic_begin = mixer_atomic_begin,
1131 .update_plane = mixer_update_plane,
1132 .disable_plane = mixer_disable_plane,
1133 .atomic_flush = mixer_atomic_flush,
1134 .atomic_check = mixer_atomic_check,
1135};
1136
1137static struct mixer_drv_data exynos5420_mxr_drv_data = {
1138 .version = MXR_VER_128_0_0_184,
1139 .is_vp_enabled = 0,
1140};
1141
1142static struct mixer_drv_data exynos5250_mxr_drv_data = {
1143 .version = MXR_VER_16_0_33_0,
1144 .is_vp_enabled = 0,
1145};
1146
1147static struct mixer_drv_data exynos4212_mxr_drv_data = {
1148 .version = MXR_VER_0_0_0_16,
1149 .is_vp_enabled = 1,
1150};
1151
1152static struct mixer_drv_data exynos4210_mxr_drv_data = {
1153 .version = MXR_VER_0_0_0_16,
1154 .is_vp_enabled = 1,
1155 .has_sclk = 1,
1156};
1157
1158static const struct platform_device_id mixer_driver_types[] = {
1159 {
1160 .name = "s5p-mixer",
1161 .driver_data = (unsigned long)&exynos4210_mxr_drv_data,
1162 }, {
1163 .name = "exynos5-mixer",
1164 .driver_data = (unsigned long)&exynos5250_mxr_drv_data,
1165 }, {
1166 /* end node */
1167 }
1168};
1169
1170static struct of_device_id mixer_match_types[] = {
1171 {
1172 .compatible = "samsung,exynos4210-mixer",
1173 .data = &exynos4210_mxr_drv_data,
1174 }, {
1175 .compatible = "samsung,exynos4212-mixer",
1176 .data = &exynos4212_mxr_drv_data,
1177 }, {
1178 .compatible = "samsung,exynos5-mixer",
1179 .data = &exynos5250_mxr_drv_data,
1180 }, {
1181 .compatible = "samsung,exynos5250-mixer",
1182 .data = &exynos5250_mxr_drv_data,
1183 }, {
1184 .compatible = "samsung,exynos5420-mixer",
1185 .data = &exynos5420_mxr_drv_data,
1186 }, {
1187 /* end node */
1188 }
1189};
1190MODULE_DEVICE_TABLE(of, mixer_match_types);
1191
1192static int mixer_bind(struct device *dev, struct device *manager, void *data)
1193{
1194 struct mixer_context *ctx = dev_get_drvdata(dev);
1195 struct drm_device *drm_dev = data;
1196 struct exynos_drm_plane *exynos_plane;
1197 unsigned int i;
1198 int ret;
1199
1200 ret = mixer_initialize(ctx, drm_dev);
1201 if (ret)
1202 return ret;
1203
1204 for (i = 0; i < MIXER_WIN_NR; i++) {
1205 if (i == VP_DEFAULT_WIN && !ctx->vp_enabled)
1206 continue;
1207
1208 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1209 1 << ctx->pipe, &plane_configs[i]);
1210 if (ret)
1211 return ret;
1212 }
1213
1214 exynos_plane = &ctx->planes[DEFAULT_WIN];
1215 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1216 ctx->pipe, EXYNOS_DISPLAY_TYPE_HDMI,
1217 &mixer_crtc_ops, ctx);
1218 if (IS_ERR(ctx->crtc)) {
1219 mixer_ctx_remove(ctx);
1220 ret = PTR_ERR(ctx->crtc);
1221 goto free_ctx;
1222 }
1223
1224 return 0;
1225
1226free_ctx:
1227 devm_kfree(dev, ctx);
1228 return ret;
1229}
1230
1231static void mixer_unbind(struct device *dev, struct device *master, void *data)
1232{
1233 struct mixer_context *ctx = dev_get_drvdata(dev);
1234
1235 mixer_ctx_remove(ctx);
1236}
1237
1238static const struct component_ops mixer_component_ops = {
1239 .bind = mixer_bind,
1240 .unbind = mixer_unbind,
1241};
1242
1243static int mixer_probe(struct platform_device *pdev)
1244{
1245 struct device *dev = &pdev->dev;
1246 struct mixer_drv_data *drv;
1247 struct mixer_context *ctx;
1248 int ret;
1249
1250 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
1251 if (!ctx) {
1252 DRM_ERROR("failed to alloc mixer context.\n");
1253 return -ENOMEM;
1254 }
1255
1256 if (dev->of_node) {
1257 const struct of_device_id *match;
1258
1259 match = of_match_node(mixer_match_types, dev->of_node);
1260 drv = (struct mixer_drv_data *)match->data;
1261 } else {
1262 drv = (struct mixer_drv_data *)
1263 platform_get_device_id(pdev)->driver_data;
1264 }
1265
1266 ctx->pdev = pdev;
1267 ctx->dev = dev;
1268 ctx->vp_enabled = drv->is_vp_enabled;
1269 ctx->has_sclk = drv->has_sclk;
1270 ctx->mxr_ver = drv->version;
1271 init_waitqueue_head(&ctx->wait_vsync_queue);
1272 atomic_set(&ctx->wait_vsync_event, 0);
1273
1274 platform_set_drvdata(pdev, ctx);
1275
1276 ret = component_add(&pdev->dev, &mixer_component_ops);
1277 if (!ret)
1278 pm_runtime_enable(dev);
1279
1280 return ret;
1281}
1282
1283static int mixer_remove(struct platform_device *pdev)
1284{
1285 pm_runtime_disable(&pdev->dev);
1286
1287 component_del(&pdev->dev, &mixer_component_ops);
1288
1289 return 0;
1290}
1291
1292static int __maybe_unused exynos_mixer_suspend(struct device *dev)
1293{
1294 struct mixer_context *ctx = dev_get_drvdata(dev);
1295 struct mixer_resources *res = &ctx->mixer_res;
1296
1297 clk_disable_unprepare(res->hdmi);
1298 clk_disable_unprepare(res->mixer);
1299 if (ctx->vp_enabled) {
1300 clk_disable_unprepare(res->vp);
1301 if (ctx->has_sclk)
1302 clk_disable_unprepare(res->sclk_mixer);
1303 }
1304
1305 return 0;
1306}
1307
1308static int __maybe_unused exynos_mixer_resume(struct device *dev)
1309{
1310 struct mixer_context *ctx = dev_get_drvdata(dev);
1311 struct mixer_resources *res = &ctx->mixer_res;
1312 int ret;
1313
1314 ret = clk_prepare_enable(res->mixer);
1315 if (ret < 0) {
1316 DRM_ERROR("Failed to prepare_enable the mixer clk [%d]\n", ret);
1317 return ret;
1318 }
1319 ret = clk_prepare_enable(res->hdmi);
1320 if (ret < 0) {
1321 DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret);
1322 return ret;
1323 }
1324 if (ctx->vp_enabled) {
1325 ret = clk_prepare_enable(res->vp);
1326 if (ret < 0) {
1327 DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n",
1328 ret);
1329 return ret;
1330 }
1331 if (ctx->has_sclk) {
1332 ret = clk_prepare_enable(res->sclk_mixer);
1333 if (ret < 0) {
1334 DRM_ERROR("Failed to prepare_enable the " \
1335 "sclk_mixer clk [%d]\n",
1336 ret);
1337 return ret;
1338 }
1339 }
1340 }
1341
1342 return 0;
1343}
1344
1345static const struct dev_pm_ops exynos_mixer_pm_ops = {
1346 SET_RUNTIME_PM_OPS(exynos_mixer_suspend, exynos_mixer_resume, NULL)
1347};
1348
1349struct platform_driver mixer_driver = {
1350 .driver = {
1351 .name = "exynos-mixer",
1352 .owner = THIS_MODULE,
1353 .pm = &exynos_mixer_pm_ops,
1354 .of_match_table = mixer_match_types,
1355 },
1356 .probe = mixer_probe,
1357 .remove = mixer_remove,
1358 .id_table = mixer_driver_types,
1359};
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/mixer_reg.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include "drmP.h"
18
19#include "regs-mixer.h"
20#include "regs-vp.h"
21
22#include <linux/kernel.h>
23#include <linux/spinlock.h>
24#include <linux/wait.h>
25#include <linux/i2c.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <linux/delay.h>
31#include <linux/pm_runtime.h>
32#include <linux/clk.h>
33#include <linux/regulator/consumer.h>
34
35#include <drm/exynos_drm.h>
36
37#include "exynos_drm_drv.h"
38#include "exynos_drm_hdmi.h"
39
40#define get_mixer_context(dev) platform_get_drvdata(to_platform_device(dev))
41
42struct hdmi_win_data {
43 dma_addr_t dma_addr;
44 void __iomem *vaddr;
45 dma_addr_t chroma_dma_addr;
46 void __iomem *chroma_vaddr;
47 uint32_t pixel_format;
48 unsigned int bpp;
49 unsigned int crtc_x;
50 unsigned int crtc_y;
51 unsigned int crtc_width;
52 unsigned int crtc_height;
53 unsigned int fb_x;
54 unsigned int fb_y;
55 unsigned int fb_width;
56 unsigned int fb_height;
57 unsigned int src_width;
58 unsigned int src_height;
59 unsigned int mode_width;
60 unsigned int mode_height;
61 unsigned int scan_flags;
62};
63
64struct mixer_resources {
65 int irq;
66 void __iomem *mixer_regs;
67 void __iomem *vp_regs;
68 spinlock_t reg_slock;
69 struct clk *mixer;
70 struct clk *vp;
71 struct clk *sclk_mixer;
72 struct clk *sclk_hdmi;
73 struct clk *sclk_dac;
74};
75
76struct mixer_context {
77 struct device *dev;
78 int pipe;
79 bool interlace;
80 bool powered;
81 u32 int_en;
82
83 struct mutex mixer_mutex;
84 struct mixer_resources mixer_res;
85 struct hdmi_win_data win_data[MIXER_WIN_NR];
86};
87
88static const u8 filter_y_horiz_tap8[] = {
89 0, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, 0, 0, 0,
91 0, 2, 4, 5, 6, 6, 6, 6,
92 6, 5, 5, 4, 3, 2, 1, 1,
93 0, -6, -12, -16, -18, -20, -21, -20,
94 -20, -18, -16, -13, -10, -8, -5, -2,
95 127, 126, 125, 121, 114, 107, 99, 89,
96 79, 68, 57, 46, 35, 25, 16, 8,
97};
98
99static const u8 filter_y_vert_tap4[] = {
100 0, -3, -6, -8, -8, -8, -8, -7,
101 -6, -5, -4, -3, -2, -1, -1, 0,
102 127, 126, 124, 118, 111, 102, 92, 81,
103 70, 59, 48, 37, 27, 19, 11, 5,
104 0, 5, 11, 19, 27, 37, 48, 59,
105 70, 81, 92, 102, 111, 118, 124, 126,
106 0, 0, -1, -1, -2, -3, -4, -5,
107 -6, -7, -8, -8, -8, -8, -6, -3,
108};
109
110static const u8 filter_cr_horiz_tap4[] = {
111 0, -3, -6, -8, -8, -8, -8, -7,
112 -6, -5, -4, -3, -2, -1, -1, 0,
113 127, 126, 124, 118, 111, 102, 92, 81,
114 70, 59, 48, 37, 27, 19, 11, 5,
115};
116
117static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)
118{
119 return readl(res->vp_regs + reg_id);
120}
121
122static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,
123 u32 val)
124{
125 writel(val, res->vp_regs + reg_id);
126}
127
128static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,
129 u32 val, u32 mask)
130{
131 u32 old = vp_reg_read(res, reg_id);
132
133 val = (val & mask) | (old & ~mask);
134 writel(val, res->vp_regs + reg_id);
135}
136
137static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)
138{
139 return readl(res->mixer_regs + reg_id);
140}
141
142static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,
143 u32 val)
144{
145 writel(val, res->mixer_regs + reg_id);
146}
147
148static inline void mixer_reg_writemask(struct mixer_resources *res,
149 u32 reg_id, u32 val, u32 mask)
150{
151 u32 old = mixer_reg_read(res, reg_id);
152
153 val = (val & mask) | (old & ~mask);
154 writel(val, res->mixer_regs + reg_id);
155}
156
157static void mixer_regs_dump(struct mixer_context *ctx)
158{
159#define DUMPREG(reg_id) \
160do { \
161 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
162 (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \
163} while (0)
164
165 DUMPREG(MXR_STATUS);
166 DUMPREG(MXR_CFG);
167 DUMPREG(MXR_INT_EN);
168 DUMPREG(MXR_INT_STATUS);
169
170 DUMPREG(MXR_LAYER_CFG);
171 DUMPREG(MXR_VIDEO_CFG);
172
173 DUMPREG(MXR_GRAPHIC0_CFG);
174 DUMPREG(MXR_GRAPHIC0_BASE);
175 DUMPREG(MXR_GRAPHIC0_SPAN);
176 DUMPREG(MXR_GRAPHIC0_WH);
177 DUMPREG(MXR_GRAPHIC0_SXY);
178 DUMPREG(MXR_GRAPHIC0_DXY);
179
180 DUMPREG(MXR_GRAPHIC1_CFG);
181 DUMPREG(MXR_GRAPHIC1_BASE);
182 DUMPREG(MXR_GRAPHIC1_SPAN);
183 DUMPREG(MXR_GRAPHIC1_WH);
184 DUMPREG(MXR_GRAPHIC1_SXY);
185 DUMPREG(MXR_GRAPHIC1_DXY);
186#undef DUMPREG
187}
188
189static void vp_regs_dump(struct mixer_context *ctx)
190{
191#define DUMPREG(reg_id) \
192do { \
193 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
194 (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \
195} while (0)
196
197 DUMPREG(VP_ENABLE);
198 DUMPREG(VP_SRESET);
199 DUMPREG(VP_SHADOW_UPDATE);
200 DUMPREG(VP_FIELD_ID);
201 DUMPREG(VP_MODE);
202 DUMPREG(VP_IMG_SIZE_Y);
203 DUMPREG(VP_IMG_SIZE_C);
204 DUMPREG(VP_PER_RATE_CTRL);
205 DUMPREG(VP_TOP_Y_PTR);
206 DUMPREG(VP_BOT_Y_PTR);
207 DUMPREG(VP_TOP_C_PTR);
208 DUMPREG(VP_BOT_C_PTR);
209 DUMPREG(VP_ENDIAN_MODE);
210 DUMPREG(VP_SRC_H_POSITION);
211 DUMPREG(VP_SRC_V_POSITION);
212 DUMPREG(VP_SRC_WIDTH);
213 DUMPREG(VP_SRC_HEIGHT);
214 DUMPREG(VP_DST_H_POSITION);
215 DUMPREG(VP_DST_V_POSITION);
216 DUMPREG(VP_DST_WIDTH);
217 DUMPREG(VP_DST_HEIGHT);
218 DUMPREG(VP_H_RATIO);
219 DUMPREG(VP_V_RATIO);
220
221#undef DUMPREG
222}
223
224static inline void vp_filter_set(struct mixer_resources *res,
225 int reg_id, const u8 *data, unsigned int size)
226{
227 /* assure 4-byte align */
228 BUG_ON(size & 3);
229 for (; size; size -= 4, reg_id += 4, data += 4) {
230 u32 val = (data[0] << 24) | (data[1] << 16) |
231 (data[2] << 8) | data[3];
232 vp_reg_write(res, reg_id, val);
233 }
234}
235
236static void vp_default_filter(struct mixer_resources *res)
237{
238 vp_filter_set(res, VP_POLY8_Y0_LL,
239 filter_y_horiz_tap8, sizeof filter_y_horiz_tap8);
240 vp_filter_set(res, VP_POLY4_Y0_LL,
241 filter_y_vert_tap4, sizeof filter_y_vert_tap4);
242 vp_filter_set(res, VP_POLY4_C0_LL,
243 filter_cr_horiz_tap4, sizeof filter_cr_horiz_tap4);
244}
245
246static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
247{
248 struct mixer_resources *res = &ctx->mixer_res;
249
250 /* block update on vsync */
251 mixer_reg_writemask(res, MXR_STATUS, enable ?
252 MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
253
254 vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
255 VP_SHADOW_UPDATE_ENABLE : 0);
256}
257
258static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
259{
260 struct mixer_resources *res = &ctx->mixer_res;
261 u32 val;
262
263 /* choosing between interlace and progressive mode */
264 val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE :
265 MXR_CFG_SCAN_PROGRASSIVE);
266
267 /* choosing between porper HD and SD mode */
268 if (height == 480)
269 val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
270 else if (height == 576)
271 val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
272 else if (height == 720)
273 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
274 else if (height == 1080)
275 val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
276 else
277 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
278
279 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
280}
281
282static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
283{
284 struct mixer_resources *res = &ctx->mixer_res;
285 u32 val;
286
287 if (height == 480) {
288 val = MXR_CFG_RGB601_0_255;
289 } else if (height == 576) {
290 val = MXR_CFG_RGB601_0_255;
291 } else if (height == 720) {
292 val = MXR_CFG_RGB709_16_235;
293 mixer_reg_write(res, MXR_CM_COEFF_Y,
294 (1 << 30) | (94 << 20) | (314 << 10) |
295 (32 << 0));
296 mixer_reg_write(res, MXR_CM_COEFF_CB,
297 (972 << 20) | (851 << 10) | (225 << 0));
298 mixer_reg_write(res, MXR_CM_COEFF_CR,
299 (225 << 20) | (820 << 10) | (1004 << 0));
300 } else if (height == 1080) {
301 val = MXR_CFG_RGB709_16_235;
302 mixer_reg_write(res, MXR_CM_COEFF_Y,
303 (1 << 30) | (94 << 20) | (314 << 10) |
304 (32 << 0));
305 mixer_reg_write(res, MXR_CM_COEFF_CB,
306 (972 << 20) | (851 << 10) | (225 << 0));
307 mixer_reg_write(res, MXR_CM_COEFF_CR,
308 (225 << 20) | (820 << 10) | (1004 << 0));
309 } else {
310 val = MXR_CFG_RGB709_16_235;
311 mixer_reg_write(res, MXR_CM_COEFF_Y,
312 (1 << 30) | (94 << 20) | (314 << 10) |
313 (32 << 0));
314 mixer_reg_write(res, MXR_CM_COEFF_CB,
315 (972 << 20) | (851 << 10) | (225 << 0));
316 mixer_reg_write(res, MXR_CM_COEFF_CR,
317 (225 << 20) | (820 << 10) | (1004 << 0));
318 }
319
320 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
321}
322
323static void mixer_cfg_layer(struct mixer_context *ctx, int win, bool enable)
324{
325 struct mixer_resources *res = &ctx->mixer_res;
326 u32 val = enable ? ~0 : 0;
327
328 switch (win) {
329 case 0:
330 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
331 break;
332 case 1:
333 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
334 break;
335 case 2:
336 vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
337 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_VP_ENABLE);
338 break;
339 }
340}
341
342static void mixer_run(struct mixer_context *ctx)
343{
344 struct mixer_resources *res = &ctx->mixer_res;
345
346 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
347
348 mixer_regs_dump(ctx);
349}
350
351static void vp_video_buffer(struct mixer_context *ctx, int win)
352{
353 struct mixer_resources *res = &ctx->mixer_res;
354 unsigned long flags;
355 struct hdmi_win_data *win_data;
356 unsigned int x_ratio, y_ratio;
357 unsigned int buf_num;
358 dma_addr_t luma_addr[2], chroma_addr[2];
359 bool tiled_mode = false;
360 bool crcb_mode = false;
361 u32 val;
362
363 win_data = &ctx->win_data[win];
364
365 switch (win_data->pixel_format) {
366 case DRM_FORMAT_NV12MT:
367 tiled_mode = true;
368 case DRM_FORMAT_NV12:
369 crcb_mode = false;
370 buf_num = 2;
371 break;
372 /* TODO: single buffer format NV12, NV21 */
373 default:
374 /* ignore pixel format at disable time */
375 if (!win_data->dma_addr)
376 break;
377
378 DRM_ERROR("pixel format for vp is wrong [%d].\n",
379 win_data->pixel_format);
380 return;
381 }
382
383 /* scaling feature: (src << 16) / dst */
384 x_ratio = (win_data->src_width << 16) / win_data->crtc_width;
385 y_ratio = (win_data->src_height << 16) / win_data->crtc_height;
386
387 if (buf_num == 2) {
388 luma_addr[0] = win_data->dma_addr;
389 chroma_addr[0] = win_data->chroma_dma_addr;
390 } else {
391 luma_addr[0] = win_data->dma_addr;
392 chroma_addr[0] = win_data->dma_addr
393 + (win_data->fb_width * win_data->fb_height);
394 }
395
396 if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE) {
397 ctx->interlace = true;
398 if (tiled_mode) {
399 luma_addr[1] = luma_addr[0] + 0x40;
400 chroma_addr[1] = chroma_addr[0] + 0x40;
401 } else {
402 luma_addr[1] = luma_addr[0] + win_data->fb_width;
403 chroma_addr[1] = chroma_addr[0] + win_data->fb_width;
404 }
405 } else {
406 ctx->interlace = false;
407 luma_addr[1] = 0;
408 chroma_addr[1] = 0;
409 }
410
411 spin_lock_irqsave(&res->reg_slock, flags);
412 mixer_vsync_set_update(ctx, false);
413
414 /* interlace or progressive scan mode */
415 val = (ctx->interlace ? ~0 : 0);
416 vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
417
418 /* setup format */
419 val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
420 val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
421 vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
422
423 /* setting size of input image */
424 vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(win_data->fb_width) |
425 VP_IMG_VSIZE(win_data->fb_height));
426 /* chroma height has to reduced by 2 to avoid chroma distorions */
427 vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(win_data->fb_width) |
428 VP_IMG_VSIZE(win_data->fb_height / 2));
429
430 vp_reg_write(res, VP_SRC_WIDTH, win_data->src_width);
431 vp_reg_write(res, VP_SRC_HEIGHT, win_data->src_height);
432 vp_reg_write(res, VP_SRC_H_POSITION,
433 VP_SRC_H_POSITION_VAL(win_data->fb_x));
434 vp_reg_write(res, VP_SRC_V_POSITION, win_data->fb_y);
435
436 vp_reg_write(res, VP_DST_WIDTH, win_data->crtc_width);
437 vp_reg_write(res, VP_DST_H_POSITION, win_data->crtc_x);
438 if (ctx->interlace) {
439 vp_reg_write(res, VP_DST_HEIGHT, win_data->crtc_height / 2);
440 vp_reg_write(res, VP_DST_V_POSITION, win_data->crtc_y / 2);
441 } else {
442 vp_reg_write(res, VP_DST_HEIGHT, win_data->crtc_height);
443 vp_reg_write(res, VP_DST_V_POSITION, win_data->crtc_y);
444 }
445
446 vp_reg_write(res, VP_H_RATIO, x_ratio);
447 vp_reg_write(res, VP_V_RATIO, y_ratio);
448
449 vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
450
451 /* set buffer address to vp */
452 vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);
453 vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);
454 vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);
455 vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);
456
457 mixer_cfg_scan(ctx, win_data->mode_height);
458 mixer_cfg_rgb_fmt(ctx, win_data->mode_height);
459 mixer_cfg_layer(ctx, win, true);
460 mixer_run(ctx);
461
462 mixer_vsync_set_update(ctx, true);
463 spin_unlock_irqrestore(&res->reg_slock, flags);
464
465 vp_regs_dump(ctx);
466}
467
468static void mixer_graph_buffer(struct mixer_context *ctx, int win)
469{
470 struct mixer_resources *res = &ctx->mixer_res;
471 unsigned long flags;
472 struct hdmi_win_data *win_data;
473 unsigned int x_ratio, y_ratio;
474 unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
475 dma_addr_t dma_addr;
476 unsigned int fmt;
477 u32 val;
478
479 win_data = &ctx->win_data[win];
480
481 #define RGB565 4
482 #define ARGB1555 5
483 #define ARGB4444 6
484 #define ARGB8888 7
485
486 switch (win_data->bpp) {
487 case 16:
488 fmt = ARGB4444;
489 break;
490 case 32:
491 fmt = ARGB8888;
492 break;
493 default:
494 fmt = ARGB8888;
495 }
496
497 /* 2x scaling feature */
498 x_ratio = 0;
499 y_ratio = 0;
500
501 dst_x_offset = win_data->crtc_x;
502 dst_y_offset = win_data->crtc_y;
503
504 /* converting dma address base and source offset */
505 dma_addr = win_data->dma_addr
506 + (win_data->fb_x * win_data->bpp >> 3)
507 + (win_data->fb_y * win_data->fb_width * win_data->bpp >> 3);
508 src_x_offset = 0;
509 src_y_offset = 0;
510
511 if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE)
512 ctx->interlace = true;
513 else
514 ctx->interlace = false;
515
516 spin_lock_irqsave(&res->reg_slock, flags);
517 mixer_vsync_set_update(ctx, false);
518
519 /* setup format */
520 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
521 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);
522
523 /* setup geometry */
524 mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width);
525
526 val = MXR_GRP_WH_WIDTH(win_data->crtc_width);
527 val |= MXR_GRP_WH_HEIGHT(win_data->crtc_height);
528 val |= MXR_GRP_WH_H_SCALE(x_ratio);
529 val |= MXR_GRP_WH_V_SCALE(y_ratio);
530 mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);
531
532 /* setup offsets in source image */
533 val = MXR_GRP_SXY_SX(src_x_offset);
534 val |= MXR_GRP_SXY_SY(src_y_offset);
535 mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val);
536
537 /* setup offsets in display image */
538 val = MXR_GRP_DXY_DX(dst_x_offset);
539 val |= MXR_GRP_DXY_DY(dst_y_offset);
540 mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);
541
542 /* set buffer address to mixer */
543 mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);
544
545 mixer_cfg_scan(ctx, win_data->mode_height);
546 mixer_cfg_rgb_fmt(ctx, win_data->mode_height);
547 mixer_cfg_layer(ctx, win, true);
548 mixer_run(ctx);
549
550 mixer_vsync_set_update(ctx, true);
551 spin_unlock_irqrestore(&res->reg_slock, flags);
552}
553
554static void vp_win_reset(struct mixer_context *ctx)
555{
556 struct mixer_resources *res = &ctx->mixer_res;
557 int tries = 100;
558
559 vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);
560 for (tries = 100; tries; --tries) {
561 /* waiting until VP_SRESET_PROCESSING is 0 */
562 if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
563 break;
564 mdelay(10);
565 }
566 WARN(tries == 0, "failed to reset Video Processor\n");
567}
568
569static void mixer_win_reset(struct mixer_context *ctx)
570{
571 struct mixer_resources *res = &ctx->mixer_res;
572 unsigned long flags;
573 u32 val; /* value stored to register */
574
575 spin_lock_irqsave(&res->reg_slock, flags);
576 mixer_vsync_set_update(ctx, false);
577
578 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
579
580 /* set output in RGB888 mode */
581 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
582
583 /* 16 beat burst in DMA */
584 mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
585 MXR_STATUS_BURST_MASK);
586
587 /* setting default layer priority: layer1 > layer0 > video
588 * because typical usage scenario would be
589 * layer1 - OSD
590 * layer0 - framebuffer
591 * video - video overlay
592 */
593 val = MXR_LAYER_CFG_GRP1_VAL(3);
594 val |= MXR_LAYER_CFG_GRP0_VAL(2);
595 val |= MXR_LAYER_CFG_VP_VAL(1);
596 mixer_reg_write(res, MXR_LAYER_CFG, val);
597
598 /* setting background color */
599 mixer_reg_write(res, MXR_BG_COLOR0, 0x008080);
600 mixer_reg_write(res, MXR_BG_COLOR1, 0x008080);
601 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
602
603 /* setting graphical layers */
604 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
605 val |= MXR_GRP_CFG_WIN_BLEND_EN;
606 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
607 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
608 val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
609
610 /* the same configuration for both layers */
611 mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
612 mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
613
614 /* setting video layers */
615 val = MXR_GRP_CFG_ALPHA_VAL(0);
616 mixer_reg_write(res, MXR_VIDEO_CFG, val);
617
618 /* configuration of Video Processor Registers */
619 vp_win_reset(ctx);
620 vp_default_filter(res);
621
622 /* disable all layers */
623 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
624 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
625 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
626
627 mixer_vsync_set_update(ctx, true);
628 spin_unlock_irqrestore(&res->reg_slock, flags);
629}
630
631static void mixer_poweron(struct mixer_context *ctx)
632{
633 struct mixer_resources *res = &ctx->mixer_res;
634
635 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
636
637 mutex_lock(&ctx->mixer_mutex);
638 if (ctx->powered) {
639 mutex_unlock(&ctx->mixer_mutex);
640 return;
641 }
642 ctx->powered = true;
643 mutex_unlock(&ctx->mixer_mutex);
644
645 pm_runtime_get_sync(ctx->dev);
646
647 clk_enable(res->mixer);
648 clk_enable(res->vp);
649 clk_enable(res->sclk_mixer);
650
651 mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
652 mixer_win_reset(ctx);
653}
654
655static void mixer_poweroff(struct mixer_context *ctx)
656{
657 struct mixer_resources *res = &ctx->mixer_res;
658
659 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
660
661 mutex_lock(&ctx->mixer_mutex);
662 if (!ctx->powered)
663 goto out;
664 mutex_unlock(&ctx->mixer_mutex);
665
666 ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
667
668 clk_disable(res->mixer);
669 clk_disable(res->vp);
670 clk_disable(res->sclk_mixer);
671
672 pm_runtime_put_sync(ctx->dev);
673
674 mutex_lock(&ctx->mixer_mutex);
675 ctx->powered = false;
676
677out:
678 mutex_unlock(&ctx->mixer_mutex);
679}
680
681static int mixer_enable_vblank(void *ctx, int pipe)
682{
683 struct mixer_context *mixer_ctx = ctx;
684 struct mixer_resources *res = &mixer_ctx->mixer_res;
685
686 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
687
688 mixer_ctx->pipe = pipe;
689
690 /* enable vsync interrupt */
691 mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
692 MXR_INT_EN_VSYNC);
693
694 return 0;
695}
696
697static void mixer_disable_vblank(void *ctx)
698{
699 struct mixer_context *mixer_ctx = ctx;
700 struct mixer_resources *res = &mixer_ctx->mixer_res;
701
702 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
703
704 /* disable vsync interrupt */
705 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
706}
707
708static void mixer_dpms(void *ctx, int mode)
709{
710 struct mixer_context *mixer_ctx = ctx;
711
712 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
713
714 switch (mode) {
715 case DRM_MODE_DPMS_ON:
716 mixer_poweron(mixer_ctx);
717 break;
718 case DRM_MODE_DPMS_STANDBY:
719 case DRM_MODE_DPMS_SUSPEND:
720 case DRM_MODE_DPMS_OFF:
721 mixer_poweroff(mixer_ctx);
722 break;
723 default:
724 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
725 break;
726 }
727}
728
729static void mixer_win_mode_set(void *ctx,
730 struct exynos_drm_overlay *overlay)
731{
732 struct mixer_context *mixer_ctx = ctx;
733 struct hdmi_win_data *win_data;
734 int win;
735
736 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
737
738 if (!overlay) {
739 DRM_ERROR("overlay is NULL\n");
740 return;
741 }
742
743 DRM_DEBUG_KMS("set [%d]x[%d] at (%d,%d) to [%d]x[%d] at (%d,%d)\n",
744 overlay->fb_width, overlay->fb_height,
745 overlay->fb_x, overlay->fb_y,
746 overlay->crtc_width, overlay->crtc_height,
747 overlay->crtc_x, overlay->crtc_y);
748
749 win = overlay->zpos;
750 if (win == DEFAULT_ZPOS)
751 win = MIXER_DEFAULT_WIN;
752
753 if (win < 0 || win > MIXER_WIN_NR) {
754 DRM_ERROR("mixer window[%d] is wrong\n", win);
755 return;
756 }
757
758 win_data = &mixer_ctx->win_data[win];
759
760 win_data->dma_addr = overlay->dma_addr[0];
761 win_data->vaddr = overlay->vaddr[0];
762 win_data->chroma_dma_addr = overlay->dma_addr[1];
763 win_data->chroma_vaddr = overlay->vaddr[1];
764 win_data->pixel_format = overlay->pixel_format;
765 win_data->bpp = overlay->bpp;
766
767 win_data->crtc_x = overlay->crtc_x;
768 win_data->crtc_y = overlay->crtc_y;
769 win_data->crtc_width = overlay->crtc_width;
770 win_data->crtc_height = overlay->crtc_height;
771
772 win_data->fb_x = overlay->fb_x;
773 win_data->fb_y = overlay->fb_y;
774 win_data->fb_width = overlay->fb_width;
775 win_data->fb_height = overlay->fb_height;
776 win_data->src_width = overlay->src_width;
777 win_data->src_height = overlay->src_height;
778
779 win_data->mode_width = overlay->mode_width;
780 win_data->mode_height = overlay->mode_height;
781
782 win_data->scan_flags = overlay->scan_flag;
783}
784
785static void mixer_win_commit(void *ctx, int win)
786{
787 struct mixer_context *mixer_ctx = ctx;
788
789 DRM_DEBUG_KMS("[%d] %s, win: %d\n", __LINE__, __func__, win);
790
791 if (win > 1)
792 vp_video_buffer(mixer_ctx, win);
793 else
794 mixer_graph_buffer(mixer_ctx, win);
795}
796
797static void mixer_win_disable(void *ctx, int win)
798{
799 struct mixer_context *mixer_ctx = ctx;
800 struct mixer_resources *res = &mixer_ctx->mixer_res;
801 unsigned long flags;
802
803 DRM_DEBUG_KMS("[%d] %s, win: %d\n", __LINE__, __func__, win);
804
805 spin_lock_irqsave(&res->reg_slock, flags);
806 mixer_vsync_set_update(mixer_ctx, false);
807
808 mixer_cfg_layer(mixer_ctx, win, false);
809
810 mixer_vsync_set_update(mixer_ctx, true);
811 spin_unlock_irqrestore(&res->reg_slock, flags);
812}
813
814static struct exynos_mixer_ops mixer_ops = {
815 /* manager */
816 .enable_vblank = mixer_enable_vblank,
817 .disable_vblank = mixer_disable_vblank,
818 .dpms = mixer_dpms,
819
820 /* overlay */
821 .win_mode_set = mixer_win_mode_set,
822 .win_commit = mixer_win_commit,
823 .win_disable = mixer_win_disable,
824};
825
826/* for pageflip event */
827static void mixer_finish_pageflip(struct drm_device *drm_dev, int crtc)
828{
829 struct exynos_drm_private *dev_priv = drm_dev->dev_private;
830 struct drm_pending_vblank_event *e, *t;
831 struct timeval now;
832 unsigned long flags;
833 bool is_checked = false;
834
835 spin_lock_irqsave(&drm_dev->event_lock, flags);
836
837 list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
838 base.link) {
839 /* if event's pipe isn't same as crtc then ignore it. */
840 if (crtc != e->pipe)
841 continue;
842
843 is_checked = true;
844 do_gettimeofday(&now);
845 e->event.sequence = 0;
846 e->event.tv_sec = now.tv_sec;
847 e->event.tv_usec = now.tv_usec;
848
849 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
850 wake_up_interruptible(&e->base.file_priv->event_wait);
851 }
852
853 if (is_checked)
854 /*
855 * call drm_vblank_put only in case that drm_vblank_get was
856 * called.
857 */
858 if (atomic_read(&drm_dev->vblank_refcount[crtc]) > 0)
859 drm_vblank_put(drm_dev, crtc);
860
861 spin_unlock_irqrestore(&drm_dev->event_lock, flags);
862}
863
864static irqreturn_t mixer_irq_handler(int irq, void *arg)
865{
866 struct exynos_drm_hdmi_context *drm_hdmi_ctx = arg;
867 struct mixer_context *ctx = drm_hdmi_ctx->ctx;
868 struct mixer_resources *res = &ctx->mixer_res;
869 u32 val, base, shadow;
870
871 spin_lock(&res->reg_slock);
872
873 /* read interrupt status for handling and clearing flags for VSYNC */
874 val = mixer_reg_read(res, MXR_INT_STATUS);
875
876 /* handling VSYNC */
877 if (val & MXR_INT_STATUS_VSYNC) {
878 /* interlace scan need to check shadow register */
879 if (ctx->interlace) {
880 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
881 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
882 if (base != shadow)
883 goto out;
884
885 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
886 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
887 if (base != shadow)
888 goto out;
889 }
890
891 drm_handle_vblank(drm_hdmi_ctx->drm_dev, ctx->pipe);
892 mixer_finish_pageflip(drm_hdmi_ctx->drm_dev, ctx->pipe);
893 }
894
895out:
896 /* clear interrupts */
897 if (~val & MXR_INT_EN_VSYNC) {
898 /* vsync interrupt use different bit for read and clear */
899 val &= ~MXR_INT_EN_VSYNC;
900 val |= MXR_INT_CLEAR_VSYNC;
901 }
902 mixer_reg_write(res, MXR_INT_STATUS, val);
903
904 spin_unlock(&res->reg_slock);
905
906 return IRQ_HANDLED;
907}
908
909static int __devinit mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
910 struct platform_device *pdev)
911{
912 struct mixer_context *mixer_ctx = ctx->ctx;
913 struct device *dev = &pdev->dev;
914 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
915 struct resource *res;
916 int ret;
917
918 spin_lock_init(&mixer_res->reg_slock);
919
920 mixer_res->mixer = clk_get(dev, "mixer");
921 if (IS_ERR_OR_NULL(mixer_res->mixer)) {
922 dev_err(dev, "failed to get clock 'mixer'\n");
923 ret = -ENODEV;
924 goto fail;
925 }
926 mixer_res->vp = clk_get(dev, "vp");
927 if (IS_ERR_OR_NULL(mixer_res->vp)) {
928 dev_err(dev, "failed to get clock 'vp'\n");
929 ret = -ENODEV;
930 goto fail;
931 }
932 mixer_res->sclk_mixer = clk_get(dev, "sclk_mixer");
933 if (IS_ERR_OR_NULL(mixer_res->sclk_mixer)) {
934 dev_err(dev, "failed to get clock 'sclk_mixer'\n");
935 ret = -ENODEV;
936 goto fail;
937 }
938 mixer_res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
939 if (IS_ERR_OR_NULL(mixer_res->sclk_hdmi)) {
940 dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
941 ret = -ENODEV;
942 goto fail;
943 }
944 mixer_res->sclk_dac = clk_get(dev, "sclk_dac");
945 if (IS_ERR_OR_NULL(mixer_res->sclk_dac)) {
946 dev_err(dev, "failed to get clock 'sclk_dac'\n");
947 ret = -ENODEV;
948 goto fail;
949 }
950 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mxr");
951 if (res == NULL) {
952 dev_err(dev, "get memory resource failed.\n");
953 ret = -ENXIO;
954 goto fail;
955 }
956
957 clk_set_parent(mixer_res->sclk_mixer, mixer_res->sclk_hdmi);
958
959 mixer_res->mixer_regs = ioremap(res->start, resource_size(res));
960 if (mixer_res->mixer_regs == NULL) {
961 dev_err(dev, "register mapping failed.\n");
962 ret = -ENXIO;
963 goto fail;
964 }
965
966 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vp");
967 if (res == NULL) {
968 dev_err(dev, "get memory resource failed.\n");
969 ret = -ENXIO;
970 goto fail_mixer_regs;
971 }
972
973 mixer_res->vp_regs = ioremap(res->start, resource_size(res));
974 if (mixer_res->vp_regs == NULL) {
975 dev_err(dev, "register mapping failed.\n");
976 ret = -ENXIO;
977 goto fail_mixer_regs;
978 }
979
980 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq");
981 if (res == NULL) {
982 dev_err(dev, "get interrupt resource failed.\n");
983 ret = -ENXIO;
984 goto fail_vp_regs;
985 }
986
987 ret = request_irq(res->start, mixer_irq_handler, 0, "drm_mixer", ctx);
988 if (ret) {
989 dev_err(dev, "request interrupt failed.\n");
990 goto fail_vp_regs;
991 }
992 mixer_res->irq = res->start;
993
994 return 0;
995
996fail_vp_regs:
997 iounmap(mixer_res->vp_regs);
998
999fail_mixer_regs:
1000 iounmap(mixer_res->mixer_regs);
1001
1002fail:
1003 if (!IS_ERR_OR_NULL(mixer_res->sclk_dac))
1004 clk_put(mixer_res->sclk_dac);
1005 if (!IS_ERR_OR_NULL(mixer_res->sclk_hdmi))
1006 clk_put(mixer_res->sclk_hdmi);
1007 if (!IS_ERR_OR_NULL(mixer_res->sclk_mixer))
1008 clk_put(mixer_res->sclk_mixer);
1009 if (!IS_ERR_OR_NULL(mixer_res->vp))
1010 clk_put(mixer_res->vp);
1011 if (!IS_ERR_OR_NULL(mixer_res->mixer))
1012 clk_put(mixer_res->mixer);
1013 return ret;
1014}
1015
1016static void mixer_resources_cleanup(struct mixer_context *ctx)
1017{
1018 struct mixer_resources *res = &ctx->mixer_res;
1019
1020 free_irq(res->irq, ctx);
1021
1022 iounmap(res->vp_regs);
1023 iounmap(res->mixer_regs);
1024}
1025
1026static int __devinit mixer_probe(struct platform_device *pdev)
1027{
1028 struct device *dev = &pdev->dev;
1029 struct exynos_drm_hdmi_context *drm_hdmi_ctx;
1030 struct mixer_context *ctx;
1031 int ret;
1032
1033 dev_info(dev, "probe start\n");
1034
1035 drm_hdmi_ctx = kzalloc(sizeof(*drm_hdmi_ctx), GFP_KERNEL);
1036 if (!drm_hdmi_ctx) {
1037 DRM_ERROR("failed to allocate common hdmi context.\n");
1038 return -ENOMEM;
1039 }
1040
1041 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1042 if (!ctx) {
1043 DRM_ERROR("failed to alloc mixer context.\n");
1044 kfree(drm_hdmi_ctx);
1045 return -ENOMEM;
1046 }
1047
1048 mutex_init(&ctx->mixer_mutex);
1049
1050 ctx->dev = &pdev->dev;
1051 drm_hdmi_ctx->ctx = (void *)ctx;
1052
1053 platform_set_drvdata(pdev, drm_hdmi_ctx);
1054
1055 /* acquire resources: regs, irqs, clocks */
1056 ret = mixer_resources_init(drm_hdmi_ctx, pdev);
1057 if (ret)
1058 goto fail;
1059
1060 /* register specific callback point to common hdmi. */
1061 exynos_mixer_ops_register(&mixer_ops);
1062
1063 pm_runtime_enable(dev);
1064
1065 return 0;
1066
1067
1068fail:
1069 dev_info(dev, "probe failed\n");
1070 return ret;
1071}
1072
1073static int mixer_remove(struct platform_device *pdev)
1074{
1075 struct device *dev = &pdev->dev;
1076 struct exynos_drm_hdmi_context *drm_hdmi_ctx =
1077 platform_get_drvdata(pdev);
1078 struct mixer_context *ctx = drm_hdmi_ctx->ctx;
1079
1080 dev_info(dev, "remove successful\n");
1081
1082 pm_runtime_disable(&pdev->dev);
1083
1084 mixer_resources_cleanup(ctx);
1085
1086 return 0;
1087}
1088
1089#ifdef CONFIG_PM_SLEEP
1090static int mixer_suspend(struct device *dev)
1091{
1092 struct exynos_drm_hdmi_context *drm_hdmi_ctx = get_mixer_context(dev);
1093 struct mixer_context *ctx = drm_hdmi_ctx->ctx;
1094
1095 mixer_poweroff(ctx);
1096
1097 return 0;
1098}
1099#endif
1100
1101static SIMPLE_DEV_PM_OPS(mixer_pm_ops, mixer_suspend, NULL);
1102
1103struct platform_driver mixer_driver = {
1104 .driver = {
1105 .name = "s5p-mixer",
1106 .owner = THIS_MODULE,
1107 .pm = &mixer_pm_ops,
1108 },
1109 .probe = mixer_probe,
1110 .remove = __devexit_p(mixer_remove),
1111};