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1/*
2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2016 Freescale Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_gpio.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/slab.h>
22#include <linux/irq.h>
23#include <linux/gpio/driver.h>
24
25#define MPC8XXX_GPIO_PINS 32
26
27#define GPIO_DIR 0x00
28#define GPIO_ODR 0x04
29#define GPIO_DAT 0x08
30#define GPIO_IER 0x0c
31#define GPIO_IMR 0x10
32#define GPIO_ICR 0x14
33#define GPIO_ICR2 0x18
34
35struct mpc8xxx_gpio_chip {
36 struct gpio_chip gc;
37 void __iomem *regs;
38 raw_spinlock_t lock;
39
40 int (*direction_output)(struct gpio_chip *chip,
41 unsigned offset, int value);
42
43 struct irq_domain *irq;
44 unsigned int irqn;
45};
46
47/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
48 * defined as output cannot be determined by reading GPDAT register,
49 * so we use shadow data register instead. The status of input pins
50 * is determined by reading GPDAT register.
51 */
52static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
53{
54 u32 val;
55 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
56 u32 out_mask, out_shadow;
57
58 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
59 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
60 out_shadow = gc->bgpio_data & out_mask;
61
62 return !!((val | out_shadow) & gc->pin2mask(gc, gpio));
63}
64
65static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
66 unsigned int gpio, int val)
67{
68 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
69 /* GPIO 28..31 are input only on MPC5121 */
70 if (gpio >= 28)
71 return -EINVAL;
72
73 return mpc8xxx_gc->direction_output(gc, gpio, val);
74}
75
76static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
77 unsigned int gpio, int val)
78{
79 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
80 /* GPIO 0..3 are input only on MPC5125 */
81 if (gpio <= 3)
82 return -EINVAL;
83
84 return mpc8xxx_gc->direction_output(gc, gpio, val);
85}
86
87static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
88{
89 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
90
91 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
92 return irq_create_mapping(mpc8xxx_gc->irq, offset);
93 else
94 return -ENXIO;
95}
96
97static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
98{
99 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
100 struct irq_chip *chip = irq_desc_get_chip(desc);
101 struct gpio_chip *gc = &mpc8xxx_gc->gc;
102 unsigned int mask;
103
104 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
105 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
106 if (mask)
107 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
108 32 - ffs(mask)));
109 if (chip->irq_eoi)
110 chip->irq_eoi(&desc->irq_data);
111}
112
113static void mpc8xxx_irq_unmask(struct irq_data *d)
114{
115 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
116 struct gpio_chip *gc = &mpc8xxx_gc->gc;
117 unsigned long flags;
118
119 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
120
121 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
122 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
123 | gc->pin2mask(gc, irqd_to_hwirq(d)));
124
125 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
126}
127
128static void mpc8xxx_irq_mask(struct irq_data *d)
129{
130 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
131 struct gpio_chip *gc = &mpc8xxx_gc->gc;
132 unsigned long flags;
133
134 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
135
136 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
137 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
138 & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
139
140 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
141}
142
143static void mpc8xxx_irq_ack(struct irq_data *d)
144{
145 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
146 struct gpio_chip *gc = &mpc8xxx_gc->gc;
147
148 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
149 gc->pin2mask(gc, irqd_to_hwirq(d)));
150}
151
152static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
153{
154 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
155 struct gpio_chip *gc = &mpc8xxx_gc->gc;
156 unsigned long flags;
157
158 switch (flow_type) {
159 case IRQ_TYPE_EDGE_FALLING:
160 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
161 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
162 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
163 | gc->pin2mask(gc, irqd_to_hwirq(d)));
164 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
165 break;
166
167 case IRQ_TYPE_EDGE_BOTH:
168 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
169 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
170 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
171 & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
172 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
173 break;
174
175 default:
176 return -EINVAL;
177 }
178
179 return 0;
180}
181
182static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
183{
184 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
185 struct gpio_chip *gc = &mpc8xxx_gc->gc;
186 unsigned long gpio = irqd_to_hwirq(d);
187 void __iomem *reg;
188 unsigned int shift;
189 unsigned long flags;
190
191 if (gpio < 16) {
192 reg = mpc8xxx_gc->regs + GPIO_ICR;
193 shift = (15 - gpio) * 2;
194 } else {
195 reg = mpc8xxx_gc->regs + GPIO_ICR2;
196 shift = (15 - (gpio % 16)) * 2;
197 }
198
199 switch (flow_type) {
200 case IRQ_TYPE_EDGE_FALLING:
201 case IRQ_TYPE_LEVEL_LOW:
202 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
203 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
204 | (2 << shift));
205 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
206 break;
207
208 case IRQ_TYPE_EDGE_RISING:
209 case IRQ_TYPE_LEVEL_HIGH:
210 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
211 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
212 | (1 << shift));
213 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
214 break;
215
216 case IRQ_TYPE_EDGE_BOTH:
217 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
218 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
219 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
220 break;
221
222 default:
223 return -EINVAL;
224 }
225
226 return 0;
227}
228
229static struct irq_chip mpc8xxx_irq_chip = {
230 .name = "mpc8xxx-gpio",
231 .irq_unmask = mpc8xxx_irq_unmask,
232 .irq_mask = mpc8xxx_irq_mask,
233 .irq_ack = mpc8xxx_irq_ack,
234 /* this might get overwritten in mpc8xxx_probe() */
235 .irq_set_type = mpc8xxx_irq_set_type,
236};
237
238static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
239 irq_hw_number_t hwirq)
240{
241 irq_set_chip_data(irq, h->host_data);
242 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
243
244 return 0;
245}
246
247static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
248 .map = mpc8xxx_gpio_irq_map,
249 .xlate = irq_domain_xlate_twocell,
250};
251
252struct mpc8xxx_gpio_devtype {
253 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
254 int (*gpio_get)(struct gpio_chip *, unsigned int);
255 int (*irq_set_type)(struct irq_data *, unsigned int);
256};
257
258static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
259 .gpio_dir_out = mpc5121_gpio_dir_out,
260 .irq_set_type = mpc512x_irq_set_type,
261};
262
263static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
264 .gpio_dir_out = mpc5125_gpio_dir_out,
265 .irq_set_type = mpc512x_irq_set_type,
266};
267
268static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
269 .gpio_get = mpc8572_gpio_get,
270};
271
272static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
273 .irq_set_type = mpc8xxx_irq_set_type,
274};
275
276static const struct of_device_id mpc8xxx_gpio_ids[] = {
277 { .compatible = "fsl,mpc8349-gpio", },
278 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
279 { .compatible = "fsl,mpc8610-gpio", },
280 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
281 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
282 { .compatible = "fsl,pq3-gpio", },
283 { .compatible = "fsl,qoriq-gpio", },
284 {}
285};
286
287static int mpc8xxx_probe(struct platform_device *pdev)
288{
289 struct device_node *np = pdev->dev.of_node;
290 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
291 struct gpio_chip *gc;
292 const struct mpc8xxx_gpio_devtype *devtype =
293 of_device_get_match_data(&pdev->dev);
294 int ret;
295
296 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
297 if (!mpc8xxx_gc)
298 return -ENOMEM;
299
300 platform_set_drvdata(pdev, mpc8xxx_gc);
301
302 raw_spin_lock_init(&mpc8xxx_gc->lock);
303
304 mpc8xxx_gc->regs = of_iomap(np, 0);
305 if (!mpc8xxx_gc->regs)
306 return -ENOMEM;
307
308 gc = &mpc8xxx_gc->gc;
309
310 if (of_property_read_bool(np, "little-endian")) {
311 ret = bgpio_init(gc, &pdev->dev, 4,
312 mpc8xxx_gc->regs + GPIO_DAT,
313 NULL, NULL,
314 mpc8xxx_gc->regs + GPIO_DIR, NULL,
315 BGPIOF_BIG_ENDIAN);
316 if (ret)
317 goto err;
318 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
319 } else {
320 ret = bgpio_init(gc, &pdev->dev, 4,
321 mpc8xxx_gc->regs + GPIO_DAT,
322 NULL, NULL,
323 mpc8xxx_gc->regs + GPIO_DIR, NULL,
324 BGPIOF_BIG_ENDIAN
325 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
326 if (ret)
327 goto err;
328 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
329 }
330
331 mpc8xxx_gc->direction_output = gc->direction_output;
332
333 if (!devtype)
334 devtype = &mpc8xxx_gpio_devtype_default;
335
336 /*
337 * It's assumed that only a single type of gpio controller is available
338 * on the current machine, so overwriting global data is fine.
339 */
340 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
341
342 if (devtype->gpio_dir_out)
343 gc->direction_output = devtype->gpio_dir_out;
344 if (devtype->gpio_get)
345 gc->get = devtype->gpio_get;
346
347 gc->to_irq = mpc8xxx_gpio_to_irq;
348
349 ret = gpiochip_add_data(gc, mpc8xxx_gc);
350 if (ret) {
351 pr_err("%s: GPIO chip registration failed with status %d\n",
352 np->full_name, ret);
353 goto err;
354 }
355
356 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
357 if (!mpc8xxx_gc->irqn)
358 return 0;
359
360 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
361 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
362 if (!mpc8xxx_gc->irq)
363 return 0;
364
365 /* ack and mask all irqs */
366 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
367 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
368
369 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
370 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
371 return 0;
372err:
373 iounmap(mpc8xxx_gc->regs);
374 return ret;
375}
376
377static int mpc8xxx_remove(struct platform_device *pdev)
378{
379 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
380
381 if (mpc8xxx_gc->irq) {
382 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
383 irq_domain_remove(mpc8xxx_gc->irq);
384 }
385
386 gpiochip_remove(&mpc8xxx_gc->gc);
387 iounmap(mpc8xxx_gc->regs);
388
389 return 0;
390}
391
392static struct platform_driver mpc8xxx_plat_driver = {
393 .probe = mpc8xxx_probe,
394 .remove = mpc8xxx_remove,
395 .driver = {
396 .name = "gpio-mpc8xxx",
397 .of_match_table = mpc8xxx_gpio_ids,
398 },
399};
400
401static int __init mpc8xxx_init(void)
402{
403 return platform_driver_register(&mpc8xxx_plat_driver);
404}
405
406arch_initcall(mpc8xxx_init);
1/*
2 * GPIOs on MPC512x/8349/8572/8610 and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
17#include <linux/gpio.h>
18#include <linux/slab.h>
19#include <linux/irq.h>
20
21#define MPC8XXX_GPIO_PINS 32
22
23#define GPIO_DIR 0x00
24#define GPIO_ODR 0x04
25#define GPIO_DAT 0x08
26#define GPIO_IER 0x0c
27#define GPIO_IMR 0x10
28#define GPIO_ICR 0x14
29#define GPIO_ICR2 0x18
30
31struct mpc8xxx_gpio_chip {
32 struct of_mm_gpio_chip mm_gc;
33 spinlock_t lock;
34
35 /*
36 * shadowed data register to be able to clear/set output pins in
37 * open drain mode safely
38 */
39 u32 data;
40 struct irq_domain *irq;
41 void *of_dev_id_data;
42};
43
44static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
45{
46 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
47}
48
49static inline struct mpc8xxx_gpio_chip *
50to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
51{
52 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
53}
54
55static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
56{
57 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
58
59 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
60}
61
62/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
63 * defined as output cannot be determined by reading GPDAT register,
64 * so we use shadow data register instead. The status of input pins
65 * is determined by reading GPDAT register.
66 */
67static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
68{
69 u32 val;
70 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
72
73 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
74
75 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
76}
77
78static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
79{
80 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
81
82 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
83}
84
85static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
86{
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
89 unsigned long flags;
90
91 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
92
93 if (val)
94 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
95 else
96 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
97
98 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
99
100 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
101}
102
103static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
104{
105 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
106 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
107 unsigned long flags;
108
109 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
110
111 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
112
113 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
114
115 return 0;
116}
117
118static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
119{
120 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
121 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
122 unsigned long flags;
123
124 mpc8xxx_gpio_set(gc, gpio, val);
125
126 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
127
128 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
129
130 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
131
132 return 0;
133}
134
135static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
136{
137 /* GPIO 28..31 are input only on MPC5121 */
138 if (gpio >= 28)
139 return -EINVAL;
140
141 return mpc8xxx_gpio_dir_out(gc, gpio, val);
142}
143
144static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
145{
146 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
147 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
148
149 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
150 return irq_create_mapping(mpc8xxx_gc->irq, offset);
151 else
152 return -ENXIO;
153}
154
155static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
156{
157 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
158 struct irq_chip *chip = irq_desc_get_chip(desc);
159 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
160 unsigned int mask;
161
162 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
163 if (mask)
164 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
165 32 - ffs(mask)));
166 if (chip->irq_eoi)
167 chip->irq_eoi(&desc->irq_data);
168}
169
170static void mpc8xxx_irq_unmask(struct irq_data *d)
171{
172 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
173 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
174 unsigned long flags;
175
176 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
177
178 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
179
180 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
181}
182
183static void mpc8xxx_irq_mask(struct irq_data *d)
184{
185 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
186 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
187 unsigned long flags;
188
189 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
190
191 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
192
193 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
194}
195
196static void mpc8xxx_irq_ack(struct irq_data *d)
197{
198 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
199 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
200
201 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
202}
203
204static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
205{
206 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
207 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
208 unsigned long flags;
209
210 switch (flow_type) {
211 case IRQ_TYPE_EDGE_FALLING:
212 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
213 setbits32(mm->regs + GPIO_ICR,
214 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
215 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
216 break;
217
218 case IRQ_TYPE_EDGE_BOTH:
219 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
220 clrbits32(mm->regs + GPIO_ICR,
221 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
222 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
223 break;
224
225 default:
226 return -EINVAL;
227 }
228
229 return 0;
230}
231
232static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
233{
234 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
235 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
236 unsigned long gpio = irqd_to_hwirq(d);
237 void __iomem *reg;
238 unsigned int shift;
239 unsigned long flags;
240
241 if (gpio < 16) {
242 reg = mm->regs + GPIO_ICR;
243 shift = (15 - gpio) * 2;
244 } else {
245 reg = mm->regs + GPIO_ICR2;
246 shift = (15 - (gpio % 16)) * 2;
247 }
248
249 switch (flow_type) {
250 case IRQ_TYPE_EDGE_FALLING:
251 case IRQ_TYPE_LEVEL_LOW:
252 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
253 clrsetbits_be32(reg, 3 << shift, 2 << shift);
254 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
255 break;
256
257 case IRQ_TYPE_EDGE_RISING:
258 case IRQ_TYPE_LEVEL_HIGH:
259 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
260 clrsetbits_be32(reg, 3 << shift, 1 << shift);
261 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
262 break;
263
264 case IRQ_TYPE_EDGE_BOTH:
265 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
266 clrbits32(reg, 3 << shift);
267 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
268 break;
269
270 default:
271 return -EINVAL;
272 }
273
274 return 0;
275}
276
277static struct irq_chip mpc8xxx_irq_chip = {
278 .name = "mpc8xxx-gpio",
279 .irq_unmask = mpc8xxx_irq_unmask,
280 .irq_mask = mpc8xxx_irq_mask,
281 .irq_ack = mpc8xxx_irq_ack,
282 .irq_set_type = mpc8xxx_irq_set_type,
283};
284
285static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
286 irq_hw_number_t hw)
287{
288 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
289
290 if (mpc8xxx_gc->of_dev_id_data)
291 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
292
293 irq_set_chip_data(virq, h->host_data);
294 irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
295 irq_set_irq_type(virq, IRQ_TYPE_NONE);
296
297 return 0;
298}
299
300static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
301 .map = mpc8xxx_gpio_irq_map,
302 .xlate = irq_domain_xlate_twocell,
303};
304
305static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
306 { .compatible = "fsl,mpc8349-gpio", },
307 { .compatible = "fsl,mpc8572-gpio", },
308 { .compatible = "fsl,mpc8610-gpio", },
309 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
310 { .compatible = "fsl,pq3-gpio", },
311 { .compatible = "fsl,qoriq-gpio", },
312 {}
313};
314
315static void __init mpc8xxx_add_controller(struct device_node *np)
316{
317 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
318 struct of_mm_gpio_chip *mm_gc;
319 struct gpio_chip *gc;
320 const struct of_device_id *id;
321 unsigned hwirq;
322 int ret;
323
324 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
325 if (!mpc8xxx_gc) {
326 ret = -ENOMEM;
327 goto err;
328 }
329
330 spin_lock_init(&mpc8xxx_gc->lock);
331
332 mm_gc = &mpc8xxx_gc->mm_gc;
333 gc = &mm_gc->gc;
334
335 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
336 gc->ngpio = MPC8XXX_GPIO_PINS;
337 gc->direction_input = mpc8xxx_gpio_dir_in;
338 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
339 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
340 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
341 mpc8572_gpio_get : mpc8xxx_gpio_get;
342 gc->set = mpc8xxx_gpio_set;
343 gc->to_irq = mpc8xxx_gpio_to_irq;
344
345 ret = of_mm_gpiochip_add(np, mm_gc);
346 if (ret)
347 goto err;
348
349 hwirq = irq_of_parse_and_map(np, 0);
350 if (hwirq == NO_IRQ)
351 goto skip_irq;
352
353 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
354 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
355 if (!mpc8xxx_gc->irq)
356 goto skip_irq;
357
358 id = of_match_node(mpc8xxx_gpio_ids, np);
359 if (id)
360 mpc8xxx_gc->of_dev_id_data = id->data;
361
362 /* ack and mask all irqs */
363 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
364 out_be32(mm_gc->regs + GPIO_IMR, 0);
365
366 irq_set_handler_data(hwirq, mpc8xxx_gc);
367 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
368
369skip_irq:
370 return;
371
372err:
373 pr_err("%s: registration failed with status %d\n",
374 np->full_name, ret);
375 kfree(mpc8xxx_gc);
376
377 return;
378}
379
380static int __init mpc8xxx_add_gpiochips(void)
381{
382 struct device_node *np;
383
384 for_each_matching_node(np, mpc8xxx_gpio_ids)
385 mpc8xxx_add_controller(np);
386
387 return 0;
388}
389arch_initcall(mpc8xxx_add_gpiochips);