Loading...
1#include <linux/kernel.h>
2
3#include <linux/string.h>
4#include <linux/bitops.h>
5#include <linux/smp.h>
6#include <linux/sched.h>
7#include <linux/thread_info.h>
8#include <linux/module.h>
9#include <linux/uaccess.h>
10
11#include <asm/cpufeature.h>
12#include <asm/pgtable.h>
13#include <asm/msr.h>
14#include <asm/bugs.h>
15#include <asm/cpu.h>
16
17#ifdef CONFIG_X86_64
18#include <linux/topology.h>
19#endif
20
21#include "cpu.h"
22
23#ifdef CONFIG_X86_LOCAL_APIC
24#include <asm/mpspec.h>
25#include <asm/apic.h>
26#endif
27
28static void early_init_intel(struct cpuinfo_x86 *c)
29{
30 u64 misc_enable;
31
32 /* Unmask CPUID levels if masked: */
33 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
34 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
35 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
36 c->cpuid_level = cpuid_eax(0);
37 get_cpu_cap(c);
38 }
39 }
40
41 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
42 (c->x86 == 0x6 && c->x86_model >= 0x0e))
43 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
44
45 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
46 unsigned lower_word;
47
48 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
49 /* Required by the SDM */
50 sync_core();
51 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
52 }
53
54 /*
55 * Atom erratum AAE44/AAF40/AAG38/AAH41:
56 *
57 * A race condition between speculative fetches and invalidating
58 * a large page. This is worked around in microcode, but we
59 * need the microcode to have already been loaded... so if it is
60 * not, recommend a BIOS update and disable large pages.
61 */
62 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
63 c->microcode < 0x20e) {
64 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
65 clear_cpu_cap(c, X86_FEATURE_PSE);
66 }
67
68#ifdef CONFIG_X86_64
69 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
70#else
71 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
72 if (c->x86 == 15 && c->x86_cache_alignment == 64)
73 c->x86_cache_alignment = 128;
74#endif
75
76 /* CPUID workaround for 0F33/0F34 CPU */
77 if (c->x86 == 0xF && c->x86_model == 0x3
78 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
79 c->x86_phys_bits = 36;
80
81 /*
82 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83 * with P/T states and does not stop in deep C-states.
84 *
85 * It is also reliable across cores and sockets. (but not across
86 * cabinets - we turn it off in that case explicitly.)
87 */
88 if (c->x86_power & (1 << 8)) {
89 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
90 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
91 if (!check_tsc_unstable())
92 set_sched_clock_stable();
93 }
94
95 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
96 if (c->x86 == 6) {
97 switch (c->x86_model) {
98 case 0x27: /* Penwell */
99 case 0x35: /* Cloverview */
100 case 0x4a: /* Merrifield */
101 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
102 break;
103 default:
104 break;
105 }
106 }
107
108 /*
109 * There is a known erratum on Pentium III and Core Solo
110 * and Core Duo CPUs.
111 * " Page with PAT set to WC while associated MTRR is UC
112 * may consolidate to UC "
113 * Because of this erratum, it is better to stick with
114 * setting WC in MTRR rather than using PAT on these CPUs.
115 *
116 * Enable PAT WC only on P4, Core 2 or later CPUs.
117 */
118 if (c->x86 == 6 && c->x86_model < 15)
119 clear_cpu_cap(c, X86_FEATURE_PAT);
120
121#ifdef CONFIG_KMEMCHECK
122 /*
123 * P4s have a "fast strings" feature which causes single-
124 * stepping REP instructions to only generate a #DB on
125 * cache-line boundaries.
126 *
127 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
128 * (model 2) with the same problem.
129 */
130 if (c->x86 == 15)
131 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
132 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
133 pr_info("kmemcheck: Disabling fast string operations\n");
134#endif
135
136 /*
137 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
138 * clear the fast string and enhanced fast string CPU capabilities.
139 */
140 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
141 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
142 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
143 pr_info("Disabled fast string operations\n");
144 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
145 setup_clear_cpu_cap(X86_FEATURE_ERMS);
146 }
147 }
148
149 /*
150 * Intel Quark Core DevMan_001.pdf section 6.4.11
151 * "The operating system also is required to invalidate (i.e., flush)
152 * the TLB when any changes are made to any of the page table entries.
153 * The operating system must reload CR3 to cause the TLB to be flushed"
154 *
155 * As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should
156 * be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
157 * to be modified
158 */
159 if (c->x86 == 5 && c->x86_model == 9) {
160 pr_info("Disabling PGE capability bit\n");
161 setup_clear_cpu_cap(X86_FEATURE_PGE);
162 }
163
164 if (c->cpuid_level >= 0x00000001) {
165 u32 eax, ebx, ecx, edx;
166
167 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
168 /*
169 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
170 * apicids which are reserved per package. Store the resulting
171 * shift value for the package management code.
172 */
173 if (edx & (1U << 28))
174 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
175 }
176}
177
178#ifdef CONFIG_X86_32
179/*
180 * Early probe support logic for ppro memory erratum #50
181 *
182 * This is called before we do cpu ident work
183 */
184
185int ppro_with_ram_bug(void)
186{
187 /* Uses data from early_cpu_detect now */
188 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
189 boot_cpu_data.x86 == 6 &&
190 boot_cpu_data.x86_model == 1 &&
191 boot_cpu_data.x86_mask < 8) {
192 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
193 return 1;
194 }
195 return 0;
196}
197
198static void intel_smp_check(struct cpuinfo_x86 *c)
199{
200 /* calling is from identify_secondary_cpu() ? */
201 if (!c->cpu_index)
202 return;
203
204 /*
205 * Mask B, Pentium, but not Pentium MMX
206 */
207 if (c->x86 == 5 &&
208 c->x86_mask >= 1 && c->x86_mask <= 4 &&
209 c->x86_model <= 3) {
210 /*
211 * Remember we have B step Pentia with bugs
212 */
213 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
214 "with B stepping processors.\n");
215 }
216}
217
218static int forcepae;
219static int __init forcepae_setup(char *__unused)
220{
221 forcepae = 1;
222 return 1;
223}
224__setup("forcepae", forcepae_setup);
225
226static void intel_workarounds(struct cpuinfo_x86 *c)
227{
228#ifdef CONFIG_X86_F00F_BUG
229 /*
230 * All models of Pentium and Pentium with MMX technology CPUs
231 * have the F0 0F bug, which lets nonprivileged users lock up the
232 * system. Announce that the fault handler will be checking for it.
233 * The Quark is also family 5, but does not have the same bug.
234 */
235 clear_cpu_bug(c, X86_BUG_F00F);
236 if (!paravirt_enabled() && c->x86 == 5 && c->x86_model < 9) {
237 static int f00f_workaround_enabled;
238
239 set_cpu_bug(c, X86_BUG_F00F);
240 if (!f00f_workaround_enabled) {
241 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
242 f00f_workaround_enabled = 1;
243 }
244 }
245#endif
246
247 /*
248 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
249 * model 3 mask 3
250 */
251 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
252 clear_cpu_cap(c, X86_FEATURE_SEP);
253
254 /*
255 * PAE CPUID issue: many Pentium M report no PAE but may have a
256 * functionally usable PAE implementation.
257 * Forcefully enable PAE if kernel parameter "forcepae" is present.
258 */
259 if (forcepae) {
260 pr_warn("PAE forced!\n");
261 set_cpu_cap(c, X86_FEATURE_PAE);
262 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
263 }
264
265 /*
266 * P4 Xeon errata 037 workaround.
267 * Hardware prefetcher may cause stale data to be loaded into the cache.
268 */
269 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
270 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
271 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
272 > 0) {
273 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
274 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
275 }
276 }
277
278 /*
279 * See if we have a good local APIC by checking for buggy Pentia,
280 * i.e. all B steppings and the C2 stepping of P54C when using their
281 * integrated APIC (see 11AP erratum in "Pentium Processor
282 * Specification Update").
283 */
284 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
285 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
286 set_cpu_bug(c, X86_BUG_11AP);
287
288
289#ifdef CONFIG_X86_INTEL_USERCOPY
290 /*
291 * Set up the preferred alignment for movsl bulk memory moves
292 */
293 switch (c->x86) {
294 case 4: /* 486: untested */
295 break;
296 case 5: /* Old Pentia: untested */
297 break;
298 case 6: /* PII/PIII only like movsl with 8-byte alignment */
299 movsl_mask.mask = 7;
300 break;
301 case 15: /* P4 is OK down to 8-byte alignment */
302 movsl_mask.mask = 7;
303 break;
304 }
305#endif
306
307 intel_smp_check(c);
308}
309#else
310static void intel_workarounds(struct cpuinfo_x86 *c)
311{
312}
313#endif
314
315static void srat_detect_node(struct cpuinfo_x86 *c)
316{
317#ifdef CONFIG_NUMA
318 unsigned node;
319 int cpu = smp_processor_id();
320
321 /* Don't do the funky fallback heuristics the AMD version employs
322 for now. */
323 node = numa_cpu_node(cpu);
324 if (node == NUMA_NO_NODE || !node_online(node)) {
325 /* reuse the value from init_cpu_to_node() */
326 node = cpu_to_node(cpu);
327 }
328 numa_set_node(cpu, node);
329#endif
330}
331
332/*
333 * find out the number of processor cores on the die
334 */
335static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
336{
337 unsigned int eax, ebx, ecx, edx;
338
339 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
340 return 1;
341
342 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
343 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
344 if (eax & 0x1f)
345 return (eax >> 26) + 1;
346 else
347 return 1;
348}
349
350static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
351{
352 /* Intel VMX MSR indicated features */
353#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
354#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
355#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
356#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
357#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
358#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
359
360 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
361
362 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
363 clear_cpu_cap(c, X86_FEATURE_VNMI);
364 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
365 clear_cpu_cap(c, X86_FEATURE_EPT);
366 clear_cpu_cap(c, X86_FEATURE_VPID);
367
368 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
369 msr_ctl = vmx_msr_high | vmx_msr_low;
370 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
371 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
372 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
373 set_cpu_cap(c, X86_FEATURE_VNMI);
374 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
375 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
376 vmx_msr_low, vmx_msr_high);
377 msr_ctl2 = vmx_msr_high | vmx_msr_low;
378 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
379 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
380 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
381 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
382 set_cpu_cap(c, X86_FEATURE_EPT);
383 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
384 set_cpu_cap(c, X86_FEATURE_VPID);
385 }
386}
387
388static void init_intel_energy_perf(struct cpuinfo_x86 *c)
389{
390 u64 epb;
391
392 /*
393 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
394 * (x86_energy_perf_policy(8) is available to change it at run-time.)
395 */
396 if (!cpu_has(c, X86_FEATURE_EPB))
397 return;
398
399 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
400 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
401 return;
402
403 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
404 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
405 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
406 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
407}
408
409static void intel_bsp_resume(struct cpuinfo_x86 *c)
410{
411 /*
412 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
413 * so reinitialize it properly like during bootup:
414 */
415 init_intel_energy_perf(c);
416}
417
418static void init_intel(struct cpuinfo_x86 *c)
419{
420 unsigned int l2 = 0;
421
422 early_init_intel(c);
423
424 intel_workarounds(c);
425
426 /*
427 * Detect the extended topology information if available. This
428 * will reinitialise the initial_apicid which will be used
429 * in init_intel_cacheinfo()
430 */
431 detect_extended_topology(c);
432
433 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
434 /*
435 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
436 * detection.
437 */
438 c->x86_max_cores = intel_num_cpu_cores(c);
439#ifdef CONFIG_X86_32
440 detect_ht(c);
441#endif
442 }
443
444 l2 = init_intel_cacheinfo(c);
445
446 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
447 if (l2 == 0) {
448 cpu_detect_cache_sizes(c);
449 l2 = c->x86_cache_size;
450 }
451
452 if (c->cpuid_level > 9) {
453 unsigned eax = cpuid_eax(10);
454 /* Check for version and the number of counters */
455 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
456 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
457 }
458
459 if (cpu_has_xmm2)
460 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
461
462 if (boot_cpu_has(X86_FEATURE_DS)) {
463 unsigned int l1;
464 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
465 if (!(l1 & (1<<11)))
466 set_cpu_cap(c, X86_FEATURE_BTS);
467 if (!(l1 & (1<<12)))
468 set_cpu_cap(c, X86_FEATURE_PEBS);
469 }
470
471 if (c->x86 == 6 && cpu_has_clflush &&
472 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
473 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
474
475#ifdef CONFIG_X86_64
476 if (c->x86 == 15)
477 c->x86_cache_alignment = c->x86_clflush_size * 2;
478 if (c->x86 == 6)
479 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
480#else
481 /*
482 * Names for the Pentium II/Celeron processors
483 * detectable only by also checking the cache size.
484 * Dixon is NOT a Celeron.
485 */
486 if (c->x86 == 6) {
487 char *p = NULL;
488
489 switch (c->x86_model) {
490 case 5:
491 if (l2 == 0)
492 p = "Celeron (Covington)";
493 else if (l2 == 256)
494 p = "Mobile Pentium II (Dixon)";
495 break;
496
497 case 6:
498 if (l2 == 128)
499 p = "Celeron (Mendocino)";
500 else if (c->x86_mask == 0 || c->x86_mask == 5)
501 p = "Celeron-A";
502 break;
503
504 case 8:
505 if (l2 == 128)
506 p = "Celeron (Coppermine)";
507 break;
508 }
509
510 if (p)
511 strcpy(c->x86_model_id, p);
512 }
513
514 if (c->x86 == 15)
515 set_cpu_cap(c, X86_FEATURE_P4);
516 if (c->x86 == 6)
517 set_cpu_cap(c, X86_FEATURE_P3);
518#endif
519
520 /* Work around errata */
521 srat_detect_node(c);
522
523 if (cpu_has(c, X86_FEATURE_VMX))
524 detect_vmx_virtcap(c);
525
526 init_intel_energy_perf(c);
527}
528
529#ifdef CONFIG_X86_32
530static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
531{
532 /*
533 * Intel PIII Tualatin. This comes in two flavours.
534 * One has 256kb of cache, the other 512. We have no way
535 * to determine which, so we use a boottime override
536 * for the 512kb model, and assume 256 otherwise.
537 */
538 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
539 size = 256;
540
541 /*
542 * Intel Quark SoC X1000 contains a 4-way set associative
543 * 16K cache with a 16 byte cache line and 256 lines per tag
544 */
545 if ((c->x86 == 5) && (c->x86_model == 9))
546 size = 16;
547 return size;
548}
549#endif
550
551#define TLB_INST_4K 0x01
552#define TLB_INST_4M 0x02
553#define TLB_INST_2M_4M 0x03
554
555#define TLB_INST_ALL 0x05
556#define TLB_INST_1G 0x06
557
558#define TLB_DATA_4K 0x11
559#define TLB_DATA_4M 0x12
560#define TLB_DATA_2M_4M 0x13
561#define TLB_DATA_4K_4M 0x14
562
563#define TLB_DATA_1G 0x16
564
565#define TLB_DATA0_4K 0x21
566#define TLB_DATA0_4M 0x22
567#define TLB_DATA0_2M_4M 0x23
568
569#define STLB_4K 0x41
570#define STLB_4K_2M 0x42
571
572static const struct _tlb_table intel_tlb_table[] = {
573 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
574 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
575 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
576 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
577 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
578 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
579 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
580 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
581 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
582 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
583 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
584 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
585 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
586 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
587 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
588 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
589 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
590 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
591 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
592 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
593 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
594 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
595 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
596 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
597 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
598 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
599 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
600 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
601 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
602 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
603 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
604 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
605 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
606 { 0x00, 0, 0 }
607};
608
609static void intel_tlb_lookup(const unsigned char desc)
610{
611 unsigned char k;
612 if (desc == 0)
613 return;
614
615 /* look up this descriptor in the table */
616 for (k = 0; intel_tlb_table[k].descriptor != desc && \
617 intel_tlb_table[k].descriptor != 0; k++)
618 ;
619
620 if (intel_tlb_table[k].tlb_type == 0)
621 return;
622
623 switch (intel_tlb_table[k].tlb_type) {
624 case STLB_4K:
625 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
626 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
627 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
628 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
629 break;
630 case STLB_4K_2M:
631 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
632 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
633 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
634 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
635 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
636 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
637 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
638 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
639 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
640 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
641 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
642 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
643 break;
644 case TLB_INST_ALL:
645 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
646 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
647 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
648 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
649 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
650 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
651 break;
652 case TLB_INST_4K:
653 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
654 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
655 break;
656 case TLB_INST_4M:
657 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
658 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
659 break;
660 case TLB_INST_2M_4M:
661 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
662 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
663 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
664 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
665 break;
666 case TLB_DATA_4K:
667 case TLB_DATA0_4K:
668 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
669 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
670 break;
671 case TLB_DATA_4M:
672 case TLB_DATA0_4M:
673 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
674 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
675 break;
676 case TLB_DATA_2M_4M:
677 case TLB_DATA0_2M_4M:
678 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
679 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
680 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
681 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
682 break;
683 case TLB_DATA_4K_4M:
684 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
685 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
686 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
687 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
688 break;
689 case TLB_DATA_1G:
690 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
691 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
692 break;
693 }
694}
695
696static void intel_detect_tlb(struct cpuinfo_x86 *c)
697{
698 int i, j, n;
699 unsigned int regs[4];
700 unsigned char *desc = (unsigned char *)regs;
701
702 if (c->cpuid_level < 2)
703 return;
704
705 /* Number of times to iterate */
706 n = cpuid_eax(2) & 0xFF;
707
708 for (i = 0 ; i < n ; i++) {
709 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
710
711 /* If bit 31 is set, this is an unknown format */
712 for (j = 0 ; j < 3 ; j++)
713 if (regs[j] & (1 << 31))
714 regs[j] = 0;
715
716 /* Byte 0 is level count, not a descriptor */
717 for (j = 1 ; j < 16 ; j++)
718 intel_tlb_lookup(desc[j]);
719 }
720}
721
722static const struct cpu_dev intel_cpu_dev = {
723 .c_vendor = "Intel",
724 .c_ident = { "GenuineIntel" },
725#ifdef CONFIG_X86_32
726 .legacy_models = {
727 { .family = 4, .model_names =
728 {
729 [0] = "486 DX-25/33",
730 [1] = "486 DX-50",
731 [2] = "486 SX",
732 [3] = "486 DX/2",
733 [4] = "486 SL",
734 [5] = "486 SX/2",
735 [7] = "486 DX/2-WB",
736 [8] = "486 DX/4",
737 [9] = "486 DX/4-WB"
738 }
739 },
740 { .family = 5, .model_names =
741 {
742 [0] = "Pentium 60/66 A-step",
743 [1] = "Pentium 60/66",
744 [2] = "Pentium 75 - 200",
745 [3] = "OverDrive PODP5V83",
746 [4] = "Pentium MMX",
747 [7] = "Mobile Pentium 75 - 200",
748 [8] = "Mobile Pentium MMX",
749 [9] = "Quark SoC X1000",
750 }
751 },
752 { .family = 6, .model_names =
753 {
754 [0] = "Pentium Pro A-step",
755 [1] = "Pentium Pro",
756 [3] = "Pentium II (Klamath)",
757 [4] = "Pentium II (Deschutes)",
758 [5] = "Pentium II (Deschutes)",
759 [6] = "Mobile Pentium II",
760 [7] = "Pentium III (Katmai)",
761 [8] = "Pentium III (Coppermine)",
762 [10] = "Pentium III (Cascades)",
763 [11] = "Pentium III (Tualatin)",
764 }
765 },
766 { .family = 15, .model_names =
767 {
768 [0] = "Pentium 4 (Unknown)",
769 [1] = "Pentium 4 (Willamette)",
770 [2] = "Pentium 4 (Northwood)",
771 [4] = "Pentium 4 (Foster)",
772 [5] = "Pentium 4 (Foster)",
773 }
774 },
775 },
776 .legacy_cache_size = intel_size_cache,
777#endif
778 .c_detect_tlb = intel_detect_tlb,
779 .c_early_init = early_init_intel,
780 .c_init = init_intel,
781 .c_bsp_resume = intel_bsp_resume,
782 .c_x86_vendor = X86_VENDOR_INTEL,
783};
784
785cpu_dev_register(intel_cpu_dev);
786
1#include <linux/init.h>
2#include <linux/kernel.h>
3
4#include <linux/string.h>
5#include <linux/bitops.h>
6#include <linux/smp.h>
7#include <linux/sched.h>
8#include <linux/thread_info.h>
9#include <linux/module.h>
10#include <linux/uaccess.h>
11
12#include <asm/processor.h>
13#include <asm/pgtable.h>
14#include <asm/msr.h>
15#include <asm/bugs.h>
16#include <asm/cpu.h>
17
18#ifdef CONFIG_X86_64
19#include <linux/topology.h>
20#include <asm/numa_64.h>
21#endif
22
23#include "cpu.h"
24
25#ifdef CONFIG_X86_LOCAL_APIC
26#include <asm/mpspec.h>
27#include <asm/apic.h>
28#endif
29
30static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
31{
32 u64 misc_enable;
33
34 /* Unmask CPUID levels if masked: */
35 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
36 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
37
38 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
39 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
40 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
41 c->cpuid_level = cpuid_eax(0);
42 get_cpu_cap(c);
43 }
44 }
45
46 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
47 (c->x86 == 0x6 && c->x86_model >= 0x0e))
48 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
49
50 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
51 unsigned lower_word;
52
53 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
54 /* Required by the SDM */
55 sync_core();
56 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
57 }
58
59 /*
60 * Atom erratum AAE44/AAF40/AAG38/AAH41:
61 *
62 * A race condition between speculative fetches and invalidating
63 * a large page. This is worked around in microcode, but we
64 * need the microcode to have already been loaded... so if it is
65 * not, recommend a BIOS update and disable large pages.
66 */
67 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
68 c->microcode < 0x20e) {
69 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
70 clear_cpu_cap(c, X86_FEATURE_PSE);
71 }
72
73#ifdef CONFIG_X86_64
74 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
75#else
76 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
77 if (c->x86 == 15 && c->x86_cache_alignment == 64)
78 c->x86_cache_alignment = 128;
79#endif
80
81 /* CPUID workaround for 0F33/0F34 CPU */
82 if (c->x86 == 0xF && c->x86_model == 0x3
83 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
84 c->x86_phys_bits = 36;
85
86 /*
87 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
88 * with P/T states and does not stop in deep C-states.
89 *
90 * It is also reliable across cores and sockets. (but not across
91 * cabinets - we turn it off in that case explicitly.)
92 */
93 if (c->x86_power & (1 << 8)) {
94 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
95 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
96 if (!check_tsc_unstable())
97 sched_clock_stable = 1;
98 }
99
100 /*
101 * There is a known erratum on Pentium III and Core Solo
102 * and Core Duo CPUs.
103 * " Page with PAT set to WC while associated MTRR is UC
104 * may consolidate to UC "
105 * Because of this erratum, it is better to stick with
106 * setting WC in MTRR rather than using PAT on these CPUs.
107 *
108 * Enable PAT WC only on P4, Core 2 or later CPUs.
109 */
110 if (c->x86 == 6 && c->x86_model < 15)
111 clear_cpu_cap(c, X86_FEATURE_PAT);
112
113#ifdef CONFIG_KMEMCHECK
114 /*
115 * P4s have a "fast strings" feature which causes single-
116 * stepping REP instructions to only generate a #DB on
117 * cache-line boundaries.
118 *
119 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
120 * (model 2) with the same problem.
121 */
122 if (c->x86 == 15) {
123 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
124
125 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
126 printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
127
128 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
129 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
130 }
131 }
132#endif
133
134 /*
135 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
136 * clear the fast string and enhanced fast string CPU capabilities.
137 */
138 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
139 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
140 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
141 printk(KERN_INFO "Disabled fast string operations\n");
142 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
143 setup_clear_cpu_cap(X86_FEATURE_ERMS);
144 }
145 }
146}
147
148#ifdef CONFIG_X86_32
149/*
150 * Early probe support logic for ppro memory erratum #50
151 *
152 * This is called before we do cpu ident work
153 */
154
155int __cpuinit ppro_with_ram_bug(void)
156{
157 /* Uses data from early_cpu_detect now */
158 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
159 boot_cpu_data.x86 == 6 &&
160 boot_cpu_data.x86_model == 1 &&
161 boot_cpu_data.x86_mask < 8) {
162 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
163 return 1;
164 }
165 return 0;
166}
167
168#ifdef CONFIG_X86_F00F_BUG
169static void __cpuinit trap_init_f00f_bug(void)
170{
171 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
172
173 /*
174 * Update the IDT descriptor and reload the IDT so that
175 * it uses the read-only mapped virtual address.
176 */
177 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
178 load_idt(&idt_descr);
179}
180#endif
181
182static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
183{
184 /* calling is from identify_secondary_cpu() ? */
185 if (!c->cpu_index)
186 return;
187
188 /*
189 * Mask B, Pentium, but not Pentium MMX
190 */
191 if (c->x86 == 5 &&
192 c->x86_mask >= 1 && c->x86_mask <= 4 &&
193 c->x86_model <= 3) {
194 /*
195 * Remember we have B step Pentia with bugs
196 */
197 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
198 "with B stepping processors.\n");
199 }
200}
201
202static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
203{
204 unsigned long lo, hi;
205
206#ifdef CONFIG_X86_F00F_BUG
207 /*
208 * All current models of Pentium and Pentium with MMX technology CPUs
209 * have the F0 0F bug, which lets nonprivileged users lock up the
210 * system.
211 * Note that the workaround only should be initialized once...
212 */
213 c->f00f_bug = 0;
214 if (!paravirt_enabled() && c->x86 == 5) {
215 static int f00f_workaround_enabled;
216
217 c->f00f_bug = 1;
218 if (!f00f_workaround_enabled) {
219 trap_init_f00f_bug();
220 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
221 f00f_workaround_enabled = 1;
222 }
223 }
224#endif
225
226 /*
227 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
228 * model 3 mask 3
229 */
230 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
231 clear_cpu_cap(c, X86_FEATURE_SEP);
232
233 /*
234 * P4 Xeon errata 037 workaround.
235 * Hardware prefetcher may cause stale data to be loaded into the cache.
236 */
237 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
238 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
239 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
240 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
241 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
242 lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
243 wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
244 }
245 }
246
247 /*
248 * See if we have a good local APIC by checking for buggy Pentia,
249 * i.e. all B steppings and the C2 stepping of P54C when using their
250 * integrated APIC (see 11AP erratum in "Pentium Processor
251 * Specification Update").
252 */
253 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
254 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
255 set_cpu_cap(c, X86_FEATURE_11AP);
256
257
258#ifdef CONFIG_X86_INTEL_USERCOPY
259 /*
260 * Set up the preferred alignment for movsl bulk memory moves
261 */
262 switch (c->x86) {
263 case 4: /* 486: untested */
264 break;
265 case 5: /* Old Pentia: untested */
266 break;
267 case 6: /* PII/PIII only like movsl with 8-byte alignment */
268 movsl_mask.mask = 7;
269 break;
270 case 15: /* P4 is OK down to 8-byte alignment */
271 movsl_mask.mask = 7;
272 break;
273 }
274#endif
275
276#ifdef CONFIG_X86_NUMAQ
277 numaq_tsc_disable();
278#endif
279
280 intel_smp_check(c);
281}
282#else
283static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
284{
285}
286#endif
287
288static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
289{
290#ifdef CONFIG_NUMA
291 unsigned node;
292 int cpu = smp_processor_id();
293
294 /* Don't do the funky fallback heuristics the AMD version employs
295 for now. */
296 node = numa_cpu_node(cpu);
297 if (node == NUMA_NO_NODE || !node_online(node)) {
298 /* reuse the value from init_cpu_to_node() */
299 node = cpu_to_node(cpu);
300 }
301 numa_set_node(cpu, node);
302#endif
303}
304
305/*
306 * find out the number of processor cores on the die
307 */
308static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
309{
310 unsigned int eax, ebx, ecx, edx;
311
312 if (c->cpuid_level < 4)
313 return 1;
314
315 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
316 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
317 if (eax & 0x1f)
318 return (eax >> 26) + 1;
319 else
320 return 1;
321}
322
323static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
324{
325 /* Intel VMX MSR indicated features */
326#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
327#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
328#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
329#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
330#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
331#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
332
333 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
334
335 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
336 clear_cpu_cap(c, X86_FEATURE_VNMI);
337 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
338 clear_cpu_cap(c, X86_FEATURE_EPT);
339 clear_cpu_cap(c, X86_FEATURE_VPID);
340
341 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
342 msr_ctl = vmx_msr_high | vmx_msr_low;
343 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
344 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
345 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
346 set_cpu_cap(c, X86_FEATURE_VNMI);
347 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
348 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
349 vmx_msr_low, vmx_msr_high);
350 msr_ctl2 = vmx_msr_high | vmx_msr_low;
351 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
352 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
353 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
354 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
355 set_cpu_cap(c, X86_FEATURE_EPT);
356 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
357 set_cpu_cap(c, X86_FEATURE_VPID);
358 }
359}
360
361static void __cpuinit init_intel(struct cpuinfo_x86 *c)
362{
363 unsigned int l2 = 0;
364
365 early_init_intel(c);
366
367 intel_workarounds(c);
368
369 /*
370 * Detect the extended topology information if available. This
371 * will reinitialise the initial_apicid which will be used
372 * in init_intel_cacheinfo()
373 */
374 detect_extended_topology(c);
375
376 l2 = init_intel_cacheinfo(c);
377 if (c->cpuid_level > 9) {
378 unsigned eax = cpuid_eax(10);
379 /* Check for version and the number of counters */
380 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
381 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
382 }
383
384 if (cpu_has_xmm2)
385 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
386 if (cpu_has_ds) {
387 unsigned int l1;
388 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
389 if (!(l1 & (1<<11)))
390 set_cpu_cap(c, X86_FEATURE_BTS);
391 if (!(l1 & (1<<12)))
392 set_cpu_cap(c, X86_FEATURE_PEBS);
393 }
394
395 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
396 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
397
398#ifdef CONFIG_X86_64
399 if (c->x86 == 15)
400 c->x86_cache_alignment = c->x86_clflush_size * 2;
401 if (c->x86 == 6)
402 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
403#else
404 /*
405 * Names for the Pentium II/Celeron processors
406 * detectable only by also checking the cache size.
407 * Dixon is NOT a Celeron.
408 */
409 if (c->x86 == 6) {
410 char *p = NULL;
411
412 switch (c->x86_model) {
413 case 5:
414 if (l2 == 0)
415 p = "Celeron (Covington)";
416 else if (l2 == 256)
417 p = "Mobile Pentium II (Dixon)";
418 break;
419
420 case 6:
421 if (l2 == 128)
422 p = "Celeron (Mendocino)";
423 else if (c->x86_mask == 0 || c->x86_mask == 5)
424 p = "Celeron-A";
425 break;
426
427 case 8:
428 if (l2 == 128)
429 p = "Celeron (Coppermine)";
430 break;
431 }
432
433 if (p)
434 strcpy(c->x86_model_id, p);
435 }
436
437 if (c->x86 == 15)
438 set_cpu_cap(c, X86_FEATURE_P4);
439 if (c->x86 == 6)
440 set_cpu_cap(c, X86_FEATURE_P3);
441#endif
442
443 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
444 /*
445 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
446 * detection.
447 */
448 c->x86_max_cores = intel_num_cpu_cores(c);
449#ifdef CONFIG_X86_32
450 detect_ht(c);
451#endif
452 }
453
454 /* Work around errata */
455 srat_detect_node(c);
456
457 if (cpu_has(c, X86_FEATURE_VMX))
458 detect_vmx_virtcap(c);
459
460 /*
461 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
462 * x86_energy_perf_policy(8) is available to change it at run-time
463 */
464 if (cpu_has(c, X86_FEATURE_EPB)) {
465 u64 epb;
466
467 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
468 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
469 printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
470 " Set to 'normal', was 'performance'\n"
471 "ENERGY_PERF_BIAS: View and update with"
472 " x86_energy_perf_policy(8)\n");
473 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
474 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
475 }
476 }
477}
478
479#ifdef CONFIG_X86_32
480static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
481{
482 /*
483 * Intel PIII Tualatin. This comes in two flavours.
484 * One has 256kb of cache, the other 512. We have no way
485 * to determine which, so we use a boottime override
486 * for the 512kb model, and assume 256 otherwise.
487 */
488 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
489 size = 256;
490 return size;
491}
492#endif
493
494static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
495 .c_vendor = "Intel",
496 .c_ident = { "GenuineIntel" },
497#ifdef CONFIG_X86_32
498 .c_models = {
499 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
500 {
501 [0] = "486 DX-25/33",
502 [1] = "486 DX-50",
503 [2] = "486 SX",
504 [3] = "486 DX/2",
505 [4] = "486 SL",
506 [5] = "486 SX/2",
507 [7] = "486 DX/2-WB",
508 [8] = "486 DX/4",
509 [9] = "486 DX/4-WB"
510 }
511 },
512 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
513 {
514 [0] = "Pentium 60/66 A-step",
515 [1] = "Pentium 60/66",
516 [2] = "Pentium 75 - 200",
517 [3] = "OverDrive PODP5V83",
518 [4] = "Pentium MMX",
519 [7] = "Mobile Pentium 75 - 200",
520 [8] = "Mobile Pentium MMX"
521 }
522 },
523 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
524 {
525 [0] = "Pentium Pro A-step",
526 [1] = "Pentium Pro",
527 [3] = "Pentium II (Klamath)",
528 [4] = "Pentium II (Deschutes)",
529 [5] = "Pentium II (Deschutes)",
530 [6] = "Mobile Pentium II",
531 [7] = "Pentium III (Katmai)",
532 [8] = "Pentium III (Coppermine)",
533 [10] = "Pentium III (Cascades)",
534 [11] = "Pentium III (Tualatin)",
535 }
536 },
537 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
538 {
539 [0] = "Pentium 4 (Unknown)",
540 [1] = "Pentium 4 (Willamette)",
541 [2] = "Pentium 4 (Northwood)",
542 [4] = "Pentium 4 (Foster)",
543 [5] = "Pentium 4 (Foster)",
544 }
545 },
546 },
547 .c_size_cache = intel_size_cache,
548#endif
549 .c_early_init = early_init_intel,
550 .c_init = init_intel,
551 .c_x86_vendor = X86_VENDOR_INTEL,
552};
553
554cpu_dev_register(intel_cpu_dev);
555