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1/*
2 * hp6x0 Power Management Routines
3 *
4 * Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License.
8 */
9#include <linux/init.h>
10#include <linux/suspend.h>
11#include <linux/errno.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14#include <linux/gfp.h>
15#include <asm/io.h>
16#include <asm/hd64461.h>
17#include <asm/bl_bit.h>
18#include <mach/hp6xx.h>
19#include <cpu/dac.h>
20#include <asm/freq.h>
21#include <asm/watchdog.h>
22
23#define INTR_OFFSET 0x600
24
25#define STBCR 0xffffff82
26#define STBCR2 0xffffff88
27
28#define STBCR_STBY 0x80
29#define STBCR_MSTP2 0x04
30
31#define MCR 0xffffff68
32#define RTCNT 0xffffff70
33
34#define MCR_RMODE 2
35#define MCR_RFSH 4
36
37extern u8 wakeup_start;
38extern u8 wakeup_end;
39
40static void pm_enter(void)
41{
42 u8 stbcr, csr;
43 u16 frqcr, mcr;
44 u32 vbr_new, vbr_old;
45
46 set_bl_bit();
47
48 /* set wdt */
49 csr = sh_wdt_read_csr();
50 csr &= ~WTCSR_TME;
51 csr |= WTCSR_CKS_4096;
52 sh_wdt_write_csr(csr);
53 csr = sh_wdt_read_csr();
54 sh_wdt_write_cnt(0);
55
56 /* disable PLL1 */
57 frqcr = __raw_readw(FRQCR);
58 frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
59 __raw_writew(frqcr, FRQCR);
60
61 /* enable standby */
62 stbcr = __raw_readb(STBCR);
63 __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
64
65 /* set self-refresh */
66 mcr = __raw_readw(MCR);
67 __raw_writew(mcr & ~MCR_RFSH, MCR);
68
69 /* set interrupt handler */
70 asm volatile("stc vbr, %0" : "=r" (vbr_old));
71 vbr_new = get_zeroed_page(GFP_ATOMIC);
72 udelay(50);
73 memcpy((void*)(vbr_new + INTR_OFFSET),
74 &wakeup_start, &wakeup_end - &wakeup_start);
75 asm volatile("ldc %0, vbr" : : "r" (vbr_new));
76
77 __raw_writew(0, RTCNT);
78 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
79
80 cpu_sleep();
81
82 asm volatile("ldc %0, vbr" : : "r" (vbr_old));
83
84 free_page(vbr_new);
85
86 /* enable PLL1 */
87 frqcr = __raw_readw(FRQCR);
88 frqcr |= FRQCR_PSTBY;
89 __raw_writew(frqcr, FRQCR);
90 udelay(50);
91 frqcr |= FRQCR_PLLEN;
92 __raw_writew(frqcr, FRQCR);
93
94 __raw_writeb(stbcr, STBCR);
95
96 clear_bl_bit();
97}
98
99static int hp6x0_pm_enter(suspend_state_t state)
100{
101 u8 stbcr, stbcr2;
102#ifdef CONFIG_HD64461_ENABLER
103 u8 scr;
104 u16 hd64461_stbcr;
105#endif
106
107#ifdef CONFIG_HD64461_ENABLER
108 outb(0, HD64461_PCC1CSCIER);
109
110 scr = inb(HD64461_PCC1SCR);
111 scr |= HD64461_PCCSCR_VCC1;
112 outb(scr, HD64461_PCC1SCR);
113
114 hd64461_stbcr = inw(HD64461_STBCR);
115 hd64461_stbcr |= HD64461_STBCR_SPC1ST;
116 outw(hd64461_stbcr, HD64461_STBCR);
117#endif
118
119 __raw_writeb(0x1f, DACR);
120
121 stbcr = __raw_readb(STBCR);
122 __raw_writeb(0x01, STBCR);
123
124 stbcr2 = __raw_readb(STBCR2);
125 __raw_writeb(0x7f , STBCR2);
126
127 outw(0xf07f, HD64461_SCPUCR);
128
129 pm_enter();
130
131 outw(0, HD64461_SCPUCR);
132 __raw_writeb(stbcr, STBCR);
133 __raw_writeb(stbcr2, STBCR2);
134
135#ifdef CONFIG_HD64461_ENABLER
136 hd64461_stbcr = inw(HD64461_STBCR);
137 hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
138 outw(hd64461_stbcr, HD64461_STBCR);
139
140 outb(0x4c, HD64461_PCC1CSCIER);
141 outb(0x00, HD64461_PCC1CSCR);
142#endif
143
144 return 0;
145}
146
147static const struct platform_suspend_ops hp6x0_pm_ops = {
148 .enter = hp6x0_pm_enter,
149 .valid = suspend_valid_only_mem,
150};
151
152static int __init hp6x0_pm_init(void)
153{
154 suspend_set_ops(&hp6x0_pm_ops);
155 return 0;
156}
157
158late_initcall(hp6x0_pm_init);
1/*
2 * hp6x0 Power Management Routines
3 *
4 * Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License.
8 */
9#include <linux/init.h>
10#include <linux/suspend.h>
11#include <linux/errno.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14#include <linux/gfp.h>
15#include <asm/io.h>
16#include <asm/hd64461.h>
17#include <asm/bl_bit.h>
18#include <mach/hp6xx.h>
19#include <cpu/dac.h>
20#include <asm/freq.h>
21#include <asm/watchdog.h>
22
23#define INTR_OFFSET 0x600
24
25#define STBCR 0xffffff82
26#define STBCR2 0xffffff88
27
28#define STBCR_STBY 0x80
29#define STBCR_MSTP2 0x04
30
31#define MCR 0xffffff68
32#define RTCNT 0xffffff70
33
34#define MCR_RMODE 2
35#define MCR_RFSH 4
36
37extern u8 wakeup_start;
38extern u8 wakeup_end;
39
40static void pm_enter(void)
41{
42 u8 stbcr, csr;
43 u16 frqcr, mcr;
44 u32 vbr_new, vbr_old;
45
46 set_bl_bit();
47
48 /* set wdt */
49 csr = sh_wdt_read_csr();
50 csr &= ~WTCSR_TME;
51 csr |= WTCSR_CKS_4096;
52 sh_wdt_write_csr(csr);
53 csr = sh_wdt_read_csr();
54 sh_wdt_write_cnt(0);
55
56 /* disable PLL1 */
57 frqcr = __raw_readw(FRQCR);
58 frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
59 __raw_writew(frqcr, FRQCR);
60
61 /* enable standby */
62 stbcr = __raw_readb(STBCR);
63 __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
64
65 /* set self-refresh */
66 mcr = __raw_readw(MCR);
67 __raw_writew(mcr & ~MCR_RFSH, MCR);
68
69 /* set interrupt handler */
70 asm volatile("stc vbr, %0" : "=r" (vbr_old));
71 vbr_new = get_zeroed_page(GFP_ATOMIC);
72 udelay(50);
73 memcpy((void*)(vbr_new + INTR_OFFSET),
74 &wakeup_start, &wakeup_end - &wakeup_start);
75 asm volatile("ldc %0, vbr" : : "r" (vbr_new));
76
77 __raw_writew(0, RTCNT);
78 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
79
80 cpu_sleep();
81
82 asm volatile("ldc %0, vbr" : : "r" (vbr_old));
83
84 free_page(vbr_new);
85
86 /* enable PLL1 */
87 frqcr = __raw_readw(FRQCR);
88 frqcr |= FRQCR_PSTBY;
89 __raw_writew(frqcr, FRQCR);
90 udelay(50);
91 frqcr |= FRQCR_PLLEN;
92 __raw_writew(frqcr, FRQCR);
93
94 __raw_writeb(stbcr, STBCR);
95
96 clear_bl_bit();
97}
98
99static int hp6x0_pm_enter(suspend_state_t state)
100{
101 u8 stbcr, stbcr2;
102#ifdef CONFIG_HD64461_ENABLER
103 u8 scr;
104 u16 hd64461_stbcr;
105#endif
106
107#ifdef CONFIG_HD64461_ENABLER
108 outb(0, HD64461_PCC1CSCIER);
109
110 scr = inb(HD64461_PCC1SCR);
111 scr |= HD64461_PCCSCR_VCC1;
112 outb(scr, HD64461_PCC1SCR);
113
114 hd64461_stbcr = inw(HD64461_STBCR);
115 hd64461_stbcr |= HD64461_STBCR_SPC1ST;
116 outw(hd64461_stbcr, HD64461_STBCR);
117#endif
118
119 __raw_writeb(0x1f, DACR);
120
121 stbcr = __raw_readb(STBCR);
122 __raw_writeb(0x01, STBCR);
123
124 stbcr2 = __raw_readb(STBCR2);
125 __raw_writeb(0x7f , STBCR2);
126
127 outw(0xf07f, HD64461_SCPUCR);
128
129 pm_enter();
130
131 outw(0, HD64461_SCPUCR);
132 __raw_writeb(stbcr, STBCR);
133 __raw_writeb(stbcr2, STBCR2);
134
135#ifdef CONFIG_HD64461_ENABLER
136 hd64461_stbcr = inw(HD64461_STBCR);
137 hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
138 outw(hd64461_stbcr, HD64461_STBCR);
139
140 outb(0x4c, HD64461_PCC1CSCIER);
141 outb(0x00, HD64461_PCC1CSCR);
142#endif
143
144 return 0;
145}
146
147static const struct platform_suspend_ops hp6x0_pm_ops = {
148 .enter = hp6x0_pm_enter,
149 .valid = suspend_valid_only_mem,
150};
151
152static int __init hp6x0_pm_init(void)
153{
154 suspend_set_ops(&hp6x0_pm_ops);
155 return 0;
156}
157
158late_initcall(hp6x0_pm_init);