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1#undef DEBUG
2
3/*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
8 *
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
11 * code.
12 */
13#define pr_fmt(fmt) "hw perfevents: " fmt
14
15#include <linux/bitmap.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/export.h>
19#include <linux/perf_event.h>
20#include <linux/platform_device.h>
21#include <linux/spinlock.h>
22#include <linux/uaccess.h>
23
24#include <asm/cputype.h>
25#include <asm/irq.h>
26#include <asm/irq_regs.h>
27#include <asm/pmu.h>
28#include <asm/stacktrace.h>
29
30/*
31 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
32 * another platform that supports more, we need to increase this to be the
33 * largest of all platforms.
34 *
35 * ARMv7 supports up to 32 events:
36 * cycle counter CCNT + 31 events counters CNT0..30.
37 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
38 */
39#define ARMPMU_MAX_HWEVENTS 32
40
41static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
42static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
43static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
44
45#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
46
47/* Set at runtime when we know what CPU type we are. */
48static struct arm_pmu *cpu_pmu;
49
50enum arm_perf_pmu_ids
51armpmu_get_pmu_id(void)
52{
53 int id = -ENODEV;
54
55 if (cpu_pmu != NULL)
56 id = cpu_pmu->id;
57
58 return id;
59}
60EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
61
62int perf_num_counters(void)
63{
64 int max_events = 0;
65
66 if (cpu_pmu != NULL)
67 max_events = cpu_pmu->num_events;
68
69 return max_events;
70}
71EXPORT_SYMBOL_GPL(perf_num_counters);
72
73#define HW_OP_UNSUPPORTED 0xFFFF
74
75#define C(_x) \
76 PERF_COUNT_HW_CACHE_##_x
77
78#define CACHE_OP_UNSUPPORTED 0xFFFF
79
80static int
81armpmu_map_cache_event(const unsigned (*cache_map)
82 [PERF_COUNT_HW_CACHE_MAX]
83 [PERF_COUNT_HW_CACHE_OP_MAX]
84 [PERF_COUNT_HW_CACHE_RESULT_MAX],
85 u64 config)
86{
87 unsigned int cache_type, cache_op, cache_result, ret;
88
89 cache_type = (config >> 0) & 0xff;
90 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
91 return -EINVAL;
92
93 cache_op = (config >> 8) & 0xff;
94 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
95 return -EINVAL;
96
97 cache_result = (config >> 16) & 0xff;
98 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
99 return -EINVAL;
100
101 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
102
103 if (ret == CACHE_OP_UNSUPPORTED)
104 return -ENOENT;
105
106 return ret;
107}
108
109static int
110armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
111{
112 int mapping = (*event_map)[config];
113 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
114}
115
116static int
117armpmu_map_raw_event(u32 raw_event_mask, u64 config)
118{
119 return (int)(config & raw_event_mask);
120}
121
122static int map_cpu_event(struct perf_event *event,
123 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
124 const unsigned (*cache_map)
125 [PERF_COUNT_HW_CACHE_MAX]
126 [PERF_COUNT_HW_CACHE_OP_MAX]
127 [PERF_COUNT_HW_CACHE_RESULT_MAX],
128 u32 raw_event_mask)
129{
130 u64 config = event->attr.config;
131
132 switch (event->attr.type) {
133 case PERF_TYPE_HARDWARE:
134 return armpmu_map_event(event_map, config);
135 case PERF_TYPE_HW_CACHE:
136 return armpmu_map_cache_event(cache_map, config);
137 case PERF_TYPE_RAW:
138 return armpmu_map_raw_event(raw_event_mask, config);
139 }
140
141 return -ENOENT;
142}
143
144int
145armpmu_event_set_period(struct perf_event *event,
146 struct hw_perf_event *hwc,
147 int idx)
148{
149 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
150 s64 left = local64_read(&hwc->period_left);
151 s64 period = hwc->sample_period;
152 int ret = 0;
153
154 if (unlikely(left <= -period)) {
155 left = period;
156 local64_set(&hwc->period_left, left);
157 hwc->last_period = period;
158 ret = 1;
159 }
160
161 if (unlikely(left <= 0)) {
162 left += period;
163 local64_set(&hwc->period_left, left);
164 hwc->last_period = period;
165 ret = 1;
166 }
167
168 if (left > (s64)armpmu->max_period)
169 left = armpmu->max_period;
170
171 local64_set(&hwc->prev_count, (u64)-left);
172
173 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
174
175 perf_event_update_userpage(event);
176
177 return ret;
178}
179
180u64
181armpmu_event_update(struct perf_event *event,
182 struct hw_perf_event *hwc,
183 int idx)
184{
185 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
186 u64 delta, prev_raw_count, new_raw_count;
187
188again:
189 prev_raw_count = local64_read(&hwc->prev_count);
190 new_raw_count = armpmu->read_counter(idx);
191
192 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
193 new_raw_count) != prev_raw_count)
194 goto again;
195
196 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
197
198 local64_add(delta, &event->count);
199 local64_sub(delta, &hwc->period_left);
200
201 return new_raw_count;
202}
203
204static void
205armpmu_read(struct perf_event *event)
206{
207 struct hw_perf_event *hwc = &event->hw;
208
209 /* Don't read disabled counters! */
210 if (hwc->idx < 0)
211 return;
212
213 armpmu_event_update(event, hwc, hwc->idx);
214}
215
216static void
217armpmu_stop(struct perf_event *event, int flags)
218{
219 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
220 struct hw_perf_event *hwc = &event->hw;
221
222 /*
223 * ARM pmu always has to update the counter, so ignore
224 * PERF_EF_UPDATE, see comments in armpmu_start().
225 */
226 if (!(hwc->state & PERF_HES_STOPPED)) {
227 armpmu->disable(hwc, hwc->idx);
228 barrier(); /* why? */
229 armpmu_event_update(event, hwc, hwc->idx);
230 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
231 }
232}
233
234static void
235armpmu_start(struct perf_event *event, int flags)
236{
237 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
238 struct hw_perf_event *hwc = &event->hw;
239
240 /*
241 * ARM pmu always has to reprogram the period, so ignore
242 * PERF_EF_RELOAD, see the comment below.
243 */
244 if (flags & PERF_EF_RELOAD)
245 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
246
247 hwc->state = 0;
248 /*
249 * Set the period again. Some counters can't be stopped, so when we
250 * were stopped we simply disabled the IRQ source and the counter
251 * may have been left counting. If we don't do this step then we may
252 * get an interrupt too soon or *way* too late if the overflow has
253 * happened since disabling.
254 */
255 armpmu_event_set_period(event, hwc, hwc->idx);
256 armpmu->enable(hwc, hwc->idx);
257}
258
259static void
260armpmu_del(struct perf_event *event, int flags)
261{
262 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
263 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
264 struct hw_perf_event *hwc = &event->hw;
265 int idx = hwc->idx;
266
267 WARN_ON(idx < 0);
268
269 armpmu_stop(event, PERF_EF_UPDATE);
270 hw_events->events[idx] = NULL;
271 clear_bit(idx, hw_events->used_mask);
272
273 perf_event_update_userpage(event);
274}
275
276static int
277armpmu_add(struct perf_event *event, int flags)
278{
279 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
280 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
281 struct hw_perf_event *hwc = &event->hw;
282 int idx;
283 int err = 0;
284
285 perf_pmu_disable(event->pmu);
286
287 /* If we don't have a space for the counter then finish early. */
288 idx = armpmu->get_event_idx(hw_events, hwc);
289 if (idx < 0) {
290 err = idx;
291 goto out;
292 }
293
294 /*
295 * If there is an event in the counter we are going to use then make
296 * sure it is disabled.
297 */
298 event->hw.idx = idx;
299 armpmu->disable(hwc, idx);
300 hw_events->events[idx] = event;
301
302 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
303 if (flags & PERF_EF_START)
304 armpmu_start(event, PERF_EF_RELOAD);
305
306 /* Propagate our changes to the userspace mapping. */
307 perf_event_update_userpage(event);
308
309out:
310 perf_pmu_enable(event->pmu);
311 return err;
312}
313
314static int
315validate_event(struct pmu_hw_events *hw_events,
316 struct perf_event *event)
317{
318 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
319 struct hw_perf_event fake_event = event->hw;
320 struct pmu *leader_pmu = event->group_leader->pmu;
321
322 if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
323 return 1;
324
325 return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
326}
327
328static int
329validate_group(struct perf_event *event)
330{
331 struct perf_event *sibling, *leader = event->group_leader;
332 struct pmu_hw_events fake_pmu;
333 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
334
335 /*
336 * Initialise the fake PMU. We only need to populate the
337 * used_mask for the purposes of validation.
338 */
339 memset(fake_used_mask, 0, sizeof(fake_used_mask));
340 fake_pmu.used_mask = fake_used_mask;
341
342 if (!validate_event(&fake_pmu, leader))
343 return -EINVAL;
344
345 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
346 if (!validate_event(&fake_pmu, sibling))
347 return -EINVAL;
348 }
349
350 if (!validate_event(&fake_pmu, event))
351 return -EINVAL;
352
353 return 0;
354}
355
356static irqreturn_t armpmu_platform_irq(int irq, void *dev)
357{
358 struct arm_pmu *armpmu = (struct arm_pmu *) dev;
359 struct platform_device *plat_device = armpmu->plat_device;
360 struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
361
362 return plat->handle_irq(irq, dev, armpmu->handle_irq);
363}
364
365static void
366armpmu_release_hardware(struct arm_pmu *armpmu)
367{
368 int i, irq, irqs;
369 struct platform_device *pmu_device = armpmu->plat_device;
370 struct arm_pmu_platdata *plat =
371 dev_get_platdata(&pmu_device->dev);
372
373 irqs = min(pmu_device->num_resources, num_possible_cpus());
374
375 for (i = 0; i < irqs; ++i) {
376 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
377 continue;
378 irq = platform_get_irq(pmu_device, i);
379 if (irq >= 0) {
380 if (plat && plat->disable_irq)
381 plat->disable_irq(irq);
382 free_irq(irq, armpmu);
383 }
384 }
385
386 release_pmu(armpmu->type);
387}
388
389static int
390armpmu_reserve_hardware(struct arm_pmu *armpmu)
391{
392 struct arm_pmu_platdata *plat;
393 irq_handler_t handle_irq;
394 int i, err, irq, irqs;
395 struct platform_device *pmu_device = armpmu->plat_device;
396
397 if (!pmu_device)
398 return -ENODEV;
399
400 err = reserve_pmu(armpmu->type);
401 if (err) {
402 pr_warning("unable to reserve pmu\n");
403 return err;
404 }
405
406 plat = dev_get_platdata(&pmu_device->dev);
407 if (plat && plat->handle_irq)
408 handle_irq = armpmu_platform_irq;
409 else
410 handle_irq = armpmu->handle_irq;
411
412 irqs = min(pmu_device->num_resources, num_possible_cpus());
413 if (irqs < 1) {
414 pr_err("no irqs for PMUs defined\n");
415 return -ENODEV;
416 }
417
418 for (i = 0; i < irqs; ++i) {
419 err = 0;
420 irq = platform_get_irq(pmu_device, i);
421 if (irq < 0)
422 continue;
423
424 /*
425 * If we have a single PMU interrupt that we can't shift,
426 * assume that we're running on a uniprocessor machine and
427 * continue. Otherwise, continue without this interrupt.
428 */
429 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
430 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
431 irq, i);
432 continue;
433 }
434
435 err = request_irq(irq, handle_irq,
436 IRQF_DISABLED | IRQF_NOBALANCING,
437 "arm-pmu", armpmu);
438 if (err) {
439 pr_err("unable to request IRQ%d for ARM PMU counters\n",
440 irq);
441 armpmu_release_hardware(armpmu);
442 return err;
443 } else if (plat && plat->enable_irq)
444 plat->enable_irq(irq);
445
446 cpumask_set_cpu(i, &armpmu->active_irqs);
447 }
448
449 return 0;
450}
451
452static void
453hw_perf_event_destroy(struct perf_event *event)
454{
455 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
456 atomic_t *active_events = &armpmu->active_events;
457 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
458
459 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
460 armpmu_release_hardware(armpmu);
461 mutex_unlock(pmu_reserve_mutex);
462 }
463}
464
465static int
466event_requires_mode_exclusion(struct perf_event_attr *attr)
467{
468 return attr->exclude_idle || attr->exclude_user ||
469 attr->exclude_kernel || attr->exclude_hv;
470}
471
472static int
473__hw_perf_event_init(struct perf_event *event)
474{
475 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
476 struct hw_perf_event *hwc = &event->hw;
477 int mapping, err;
478
479 mapping = armpmu->map_event(event);
480
481 if (mapping < 0) {
482 pr_debug("event %x:%llx not supported\n", event->attr.type,
483 event->attr.config);
484 return mapping;
485 }
486
487 /*
488 * We don't assign an index until we actually place the event onto
489 * hardware. Use -1 to signify that we haven't decided where to put it
490 * yet. For SMP systems, each core has it's own PMU so we can't do any
491 * clever allocation or constraints checking at this point.
492 */
493 hwc->idx = -1;
494 hwc->config_base = 0;
495 hwc->config = 0;
496 hwc->event_base = 0;
497
498 /*
499 * Check whether we need to exclude the counter from certain modes.
500 */
501 if ((!armpmu->set_event_filter ||
502 armpmu->set_event_filter(hwc, &event->attr)) &&
503 event_requires_mode_exclusion(&event->attr)) {
504 pr_debug("ARM performance counters do not support "
505 "mode exclusion\n");
506 return -EOPNOTSUPP;
507 }
508
509 /*
510 * Store the event encoding into the config_base field.
511 */
512 hwc->config_base |= (unsigned long)mapping;
513
514 if (!hwc->sample_period) {
515 /*
516 * For non-sampling runs, limit the sample_period to half
517 * of the counter width. That way, the new counter value
518 * is far less likely to overtake the previous one unless
519 * you have some serious IRQ latency issues.
520 */
521 hwc->sample_period = armpmu->max_period >> 1;
522 hwc->last_period = hwc->sample_period;
523 local64_set(&hwc->period_left, hwc->sample_period);
524 }
525
526 err = 0;
527 if (event->group_leader != event) {
528 err = validate_group(event);
529 if (err)
530 return -EINVAL;
531 }
532
533 return err;
534}
535
536static int armpmu_event_init(struct perf_event *event)
537{
538 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
539 int err = 0;
540 atomic_t *active_events = &armpmu->active_events;
541
542 /* does not support taken branch sampling */
543 if (has_branch_stack(event))
544 return -EOPNOTSUPP;
545
546 if (armpmu->map_event(event) == -ENOENT)
547 return -ENOENT;
548
549 event->destroy = hw_perf_event_destroy;
550
551 if (!atomic_inc_not_zero(active_events)) {
552 mutex_lock(&armpmu->reserve_mutex);
553 if (atomic_read(active_events) == 0)
554 err = armpmu_reserve_hardware(armpmu);
555
556 if (!err)
557 atomic_inc(active_events);
558 mutex_unlock(&armpmu->reserve_mutex);
559 }
560
561 if (err)
562 return err;
563
564 err = __hw_perf_event_init(event);
565 if (err)
566 hw_perf_event_destroy(event);
567
568 return err;
569}
570
571static void armpmu_enable(struct pmu *pmu)
572{
573 struct arm_pmu *armpmu = to_arm_pmu(pmu);
574 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
575 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
576
577 if (enabled)
578 armpmu->start();
579}
580
581static void armpmu_disable(struct pmu *pmu)
582{
583 struct arm_pmu *armpmu = to_arm_pmu(pmu);
584 armpmu->stop();
585}
586
587static void __init armpmu_init(struct arm_pmu *armpmu)
588{
589 atomic_set(&armpmu->active_events, 0);
590 mutex_init(&armpmu->reserve_mutex);
591
592 armpmu->pmu = (struct pmu) {
593 .pmu_enable = armpmu_enable,
594 .pmu_disable = armpmu_disable,
595 .event_init = armpmu_event_init,
596 .add = armpmu_add,
597 .del = armpmu_del,
598 .start = armpmu_start,
599 .stop = armpmu_stop,
600 .read = armpmu_read,
601 };
602}
603
604int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
605{
606 armpmu_init(armpmu);
607 return perf_pmu_register(&armpmu->pmu, name, type);
608}
609
610/* Include the PMU-specific implementations. */
611#include "perf_event_xscale.c"
612#include "perf_event_v6.c"
613#include "perf_event_v7.c"
614
615/*
616 * Ensure the PMU has sane values out of reset.
617 * This requires SMP to be available, so exists as a separate initcall.
618 */
619static int __init
620cpu_pmu_reset(void)
621{
622 if (cpu_pmu && cpu_pmu->reset)
623 return on_each_cpu(cpu_pmu->reset, NULL, 1);
624 return 0;
625}
626arch_initcall(cpu_pmu_reset);
627
628/*
629 * PMU platform driver and devicetree bindings.
630 */
631static struct of_device_id armpmu_of_device_ids[] = {
632 {.compatible = "arm,cortex-a9-pmu"},
633 {.compatible = "arm,cortex-a8-pmu"},
634 {.compatible = "arm,arm1136-pmu"},
635 {.compatible = "arm,arm1176-pmu"},
636 {},
637};
638
639static struct platform_device_id armpmu_plat_device_ids[] = {
640 {.name = "arm-pmu"},
641 {},
642};
643
644static int __devinit armpmu_device_probe(struct platform_device *pdev)
645{
646 if (!cpu_pmu)
647 return -ENODEV;
648
649 cpu_pmu->plat_device = pdev;
650 return 0;
651}
652
653static struct platform_driver armpmu_driver = {
654 .driver = {
655 .name = "arm-pmu",
656 .of_match_table = armpmu_of_device_ids,
657 },
658 .probe = armpmu_device_probe,
659 .id_table = armpmu_plat_device_ids,
660};
661
662static int __init register_pmu_driver(void)
663{
664 return platform_driver_register(&armpmu_driver);
665}
666device_initcall(register_pmu_driver);
667
668static struct pmu_hw_events *armpmu_get_cpu_events(void)
669{
670 return &__get_cpu_var(cpu_hw_events);
671}
672
673static void __init cpu_pmu_init(struct arm_pmu *armpmu)
674{
675 int cpu;
676 for_each_possible_cpu(cpu) {
677 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
678 events->events = per_cpu(hw_events, cpu);
679 events->used_mask = per_cpu(used_mask, cpu);
680 raw_spin_lock_init(&events->pmu_lock);
681 }
682 armpmu->get_hw_events = armpmu_get_cpu_events;
683 armpmu->type = ARM_PMU_DEVICE_CPU;
684}
685
686/*
687 * PMU hardware loses all context when a CPU goes offline.
688 * When a CPU is hotplugged back in, since some hardware registers are
689 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
690 * junk values out of them.
691 */
692static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
693 unsigned long action, void *hcpu)
694{
695 if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
696 return NOTIFY_DONE;
697
698 if (cpu_pmu && cpu_pmu->reset)
699 cpu_pmu->reset(NULL);
700
701 return NOTIFY_OK;
702}
703
704static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
705 .notifier_call = pmu_cpu_notify,
706};
707
708/*
709 * CPU PMU identification and registration.
710 */
711static int __init
712init_hw_perf_events(void)
713{
714 unsigned long cpuid = read_cpuid_id();
715 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
716 unsigned long part_number = (cpuid & 0xFFF0);
717
718 /* ARM Ltd CPUs. */
719 if (0x41 == implementor) {
720 switch (part_number) {
721 case 0xB360: /* ARM1136 */
722 case 0xB560: /* ARM1156 */
723 case 0xB760: /* ARM1176 */
724 cpu_pmu = armv6pmu_init();
725 break;
726 case 0xB020: /* ARM11mpcore */
727 cpu_pmu = armv6mpcore_pmu_init();
728 break;
729 case 0xC080: /* Cortex-A8 */
730 cpu_pmu = armv7_a8_pmu_init();
731 break;
732 case 0xC090: /* Cortex-A9 */
733 cpu_pmu = armv7_a9_pmu_init();
734 break;
735 case 0xC050: /* Cortex-A5 */
736 cpu_pmu = armv7_a5_pmu_init();
737 break;
738 case 0xC0F0: /* Cortex-A15 */
739 cpu_pmu = armv7_a15_pmu_init();
740 break;
741 case 0xC070: /* Cortex-A7 */
742 cpu_pmu = armv7_a7_pmu_init();
743 break;
744 }
745 /* Intel CPUs [xscale]. */
746 } else if (0x69 == implementor) {
747 part_number = (cpuid >> 13) & 0x7;
748 switch (part_number) {
749 case 1:
750 cpu_pmu = xscale1pmu_init();
751 break;
752 case 2:
753 cpu_pmu = xscale2pmu_init();
754 break;
755 }
756 }
757
758 if (cpu_pmu) {
759 pr_info("enabled with %s PMU driver, %d counters available\n",
760 cpu_pmu->name, cpu_pmu->num_events);
761 cpu_pmu_init(cpu_pmu);
762 register_cpu_notifier(&pmu_cpu_notifier);
763 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
764 } else {
765 pr_info("no hardware support available\n");
766 }
767
768 return 0;
769}
770early_initcall(init_hw_perf_events);
771
772/*
773 * Callchain handling code.
774 */
775
776/*
777 * The registers we're interested in are at the end of the variable
778 * length saved register structure. The fp points at the end of this
779 * structure so the address of this struct is:
780 * (struct frame_tail *)(xxx->fp)-1
781 *
782 * This code has been adapted from the ARM OProfile support.
783 */
784struct frame_tail {
785 struct frame_tail __user *fp;
786 unsigned long sp;
787 unsigned long lr;
788} __attribute__((packed));
789
790/*
791 * Get the return address for a single stackframe and return a pointer to the
792 * next frame tail.
793 */
794static struct frame_tail __user *
795user_backtrace(struct frame_tail __user *tail,
796 struct perf_callchain_entry *entry)
797{
798 struct frame_tail buftail;
799
800 /* Also check accessibility of one struct frame_tail beyond */
801 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
802 return NULL;
803 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
804 return NULL;
805
806 perf_callchain_store(entry, buftail.lr);
807
808 /*
809 * Frame pointers should strictly progress back up the stack
810 * (towards higher addresses).
811 */
812 if (tail + 1 >= buftail.fp)
813 return NULL;
814
815 return buftail.fp - 1;
816}
817
818void
819perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
820{
821 struct frame_tail __user *tail;
822
823
824 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
825
826 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
827 tail && !((unsigned long)tail & 0x3))
828 tail = user_backtrace(tail, entry);
829}
830
831/*
832 * Gets called by walk_stackframe() for every stackframe. This will be called
833 * whist unwinding the stackframe and is like a subroutine return so we use
834 * the PC.
835 */
836static int
837callchain_trace(struct stackframe *fr,
838 void *data)
839{
840 struct perf_callchain_entry *entry = data;
841 perf_callchain_store(entry, fr->pc);
842 return 0;
843}
844
845void
846perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
847{
848 struct stackframe fr;
849
850 fr.fp = regs->ARM_fp;
851 fr.sp = regs->ARM_sp;
852 fr.lr = regs->ARM_lr;
853 fr.pc = regs->ARM_pc;
854 walk_stackframe(&fr, callchain_trace, entry);
855}