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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23
24#include <linux/slab.h>
25#include <asm/unaligned.h>
26
27#include "xhci.h"
28#include "xhci-trace.h"
29
30#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
33
34/* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
36 */
37static u8 usb_bos_descriptor [] = {
38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
49 USB 3.0 speed only */
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x1c, /* bLength 28, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
58 0x01, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
65};
66
67static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
68 u16 wLength)
69{
70 int i, ssa_count;
71 u32 temp;
72 u16 desc_size, ssp_cap_size, ssa_size = 0;
73 bool usb3_1 = false;
74
75 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
76 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
77
78 /* does xhci support USB 3.1 Enhanced SuperSpeed */
79 if (xhci->usb3_rhub.min_rev >= 0x01) {
80 /* does xhci provide a PSI table for SSA speed attributes? */
81 if (xhci->usb3_rhub.psi_count) {
82 /* two SSA entries for each unique PSI ID, RX and TX */
83 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
84 ssa_size = ssa_count * sizeof(u32);
85 ssp_cap_size -= 16; /* skip copying the default SSA */
86 }
87 desc_size += ssp_cap_size;
88 usb3_1 = true;
89 }
90 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
91
92 if (usb3_1) {
93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
94 buf[4] += 1;
95 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
96 }
97
98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
99 return wLength;
100
101 /* Indicate whether the host has LTM support. */
102 temp = readl(&xhci->cap_regs->hcc_params);
103 if (HCC_LTC(temp))
104 buf[8] |= USB_LTM_SUPPORT;
105
106 /* Set the U1 and U2 exit latencies. */
107 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
108 temp = readl(&xhci->cap_regs->hcs_params3);
109 buf[12] = HCS_U1_LATENCY(temp);
110 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
111 }
112
113 /* If PSI table exists, add the custom speed attributes from it */
114 if (usb3_1 && xhci->usb3_rhub.psi_count) {
115 u32 ssp_cap_base, bm_attrib, psi;
116 int offset;
117
118 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
119
120 if (wLength < desc_size)
121 return wLength;
122 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
123
124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
125 bm_attrib = (ssa_count - 1) & 0x1f;
126 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
127 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
128
129 if (wLength < desc_size + ssa_size)
130 return wLength;
131 /*
132 * Create the Sublink Speed Attributes (SSA) array.
133 * The xhci PSI field and USB 3.1 SSA fields are very similar,
134 * but link type bits 7:6 differ for values 01b and 10b.
135 * xhci has also only one PSI entry for a symmetric link when
136 * USB 3.1 requires two SSA entries (RX and TX) for every link
137 */
138 offset = desc_size;
139 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
140 psi = xhci->usb3_rhub.psi[i];
141 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
142 if ((psi & PLT_MASK) == PLT_SYM) {
143 /* Symmetric, create SSA RX and TX from one PSI entry */
144 put_unaligned_le32(psi, &buf[offset]);
145 psi |= 1 << 7; /* turn entry to TX */
146 offset += 4;
147 if (offset >= desc_size + ssa_size)
148 return desc_size + ssa_size;
149 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
150 /* Asymetric RX, flip bits 7:6 for SSA */
151 psi ^= PLT_MASK;
152 }
153 put_unaligned_le32(psi, &buf[offset]);
154 offset += 4;
155 if (offset >= desc_size + ssa_size)
156 return desc_size + ssa_size;
157 }
158 }
159 /* ssa_size is 0 for other than usb 3.1 hosts */
160 return desc_size + ssa_size;
161}
162
163static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
164 struct usb_hub_descriptor *desc, int ports)
165{
166 u16 temp;
167
168 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
169 desc->bHubContrCurrent = 0;
170
171 desc->bNbrPorts = ports;
172 temp = 0;
173 /* Bits 1:0 - support per-port power switching, or power always on */
174 if (HCC_PPC(xhci->hcc_params))
175 temp |= HUB_CHAR_INDV_PORT_LPSM;
176 else
177 temp |= HUB_CHAR_NO_LPSM;
178 /* Bit 2 - root hubs are not part of a compound device */
179 /* Bits 4:3 - individual port over current protection */
180 temp |= HUB_CHAR_INDV_PORT_OCPM;
181 /* Bits 6:5 - no TTs in root ports */
182 /* Bit 7 - no port indicators */
183 desc->wHubCharacteristics = cpu_to_le16(temp);
184}
185
186/* Fill in the USB 2.0 roothub descriptor */
187static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
188 struct usb_hub_descriptor *desc)
189{
190 int ports;
191 u16 temp;
192 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
193 u32 portsc;
194 unsigned int i;
195
196 ports = xhci->num_usb2_ports;
197
198 xhci_common_hub_descriptor(xhci, desc, ports);
199 desc->bDescriptorType = USB_DT_HUB;
200 temp = 1 + (ports / 8);
201 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
202
203 /* The Device Removable bits are reported on a byte granularity.
204 * If the port doesn't exist within that byte, the bit is set to 0.
205 */
206 memset(port_removable, 0, sizeof(port_removable));
207 for (i = 0; i < ports; i++) {
208 portsc = readl(xhci->usb2_ports[i]);
209 /* If a device is removable, PORTSC reports a 0, same as in the
210 * hub descriptor DeviceRemovable bits.
211 */
212 if (portsc & PORT_DEV_REMOVE)
213 /* This math is hairy because bit 0 of DeviceRemovable
214 * is reserved, and bit 1 is for port 1, etc.
215 */
216 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
217 }
218
219 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
220 * ports on it. The USB 2.0 specification says that there are two
221 * variable length fields at the end of the hub descriptor:
222 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
223 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
224 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
225 * 0xFF, so we initialize the both arrays (DeviceRemovable and
226 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
227 * set of ports that actually exist.
228 */
229 memset(desc->u.hs.DeviceRemovable, 0xff,
230 sizeof(desc->u.hs.DeviceRemovable));
231 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
232 sizeof(desc->u.hs.PortPwrCtrlMask));
233
234 for (i = 0; i < (ports + 1 + 7) / 8; i++)
235 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
236 sizeof(__u8));
237}
238
239/* Fill in the USB 3.0 roothub descriptor */
240static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
241 struct usb_hub_descriptor *desc)
242{
243 int ports;
244 u16 port_removable;
245 u32 portsc;
246 unsigned int i;
247
248 ports = xhci->num_usb3_ports;
249 xhci_common_hub_descriptor(xhci, desc, ports);
250 desc->bDescriptorType = USB_DT_SS_HUB;
251 desc->bDescLength = USB_DT_SS_HUB_SIZE;
252
253 /* header decode latency should be zero for roothubs,
254 * see section 4.23.5.2.
255 */
256 desc->u.ss.bHubHdrDecLat = 0;
257 desc->u.ss.wHubDelay = 0;
258
259 port_removable = 0;
260 /* bit 0 is reserved, bit 1 is for port 1, etc. */
261 for (i = 0; i < ports; i++) {
262 portsc = readl(xhci->usb3_ports[i]);
263 if (portsc & PORT_DEV_REMOVE)
264 port_removable |= 1 << (i + 1);
265 }
266
267 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
268}
269
270static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
271 struct usb_hub_descriptor *desc)
272{
273
274 if (hcd->speed >= HCD_USB3)
275 xhci_usb3_hub_descriptor(hcd, xhci, desc);
276 else
277 xhci_usb2_hub_descriptor(hcd, xhci, desc);
278
279}
280
281static unsigned int xhci_port_speed(unsigned int port_status)
282{
283 if (DEV_LOWSPEED(port_status))
284 return USB_PORT_STAT_LOW_SPEED;
285 if (DEV_HIGHSPEED(port_status))
286 return USB_PORT_STAT_HIGH_SPEED;
287 /*
288 * FIXME: Yes, we should check for full speed, but the core uses that as
289 * a default in portspeed() in usb/core/hub.c (which is the only place
290 * USB_PORT_STAT_*_SPEED is used).
291 */
292 return 0;
293}
294
295/*
296 * These bits are Read Only (RO) and should be saved and written to the
297 * registers: 0, 3, 10:13, 30
298 * connect status, over-current status, port speed, and device removable.
299 * connect status and port speed are also sticky - meaning they're in
300 * the AUX well and they aren't changed by a hot, warm, or cold reset.
301 */
302#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
303/*
304 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
305 * bits 5:8, 9, 14:15, 25:27
306 * link state, port power, port indicator state, "wake on" enable state
307 */
308#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
309/*
310 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
311 * bit 4 (port reset)
312 */
313#define XHCI_PORT_RW1S ((1<<4))
314/*
315 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
316 * bits 1, 17, 18, 19, 20, 21, 22, 23
317 * port enable/disable, and
318 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
319 * over-current, reset, link state, and L1 change
320 */
321#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
322/*
323 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
324 * latched in
325 */
326#define XHCI_PORT_RW ((1<<16))
327/*
328 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
329 * bits 2, 24, 28:31
330 */
331#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
332
333/*
334 * Given a port state, this function returns a value that would result in the
335 * port being in the same state, if the value was written to the port status
336 * control register.
337 * Save Read Only (RO) bits and save read/write bits where
338 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
339 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
340 */
341u32 xhci_port_state_to_neutral(u32 state)
342{
343 /* Save read-only status and port state */
344 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
345}
346
347/*
348 * find slot id based on port number.
349 * @port: The one-based port number from one of the two split roothubs.
350 */
351int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
352 u16 port)
353{
354 int slot_id;
355 int i;
356 enum usb_device_speed speed;
357
358 slot_id = 0;
359 for (i = 0; i < MAX_HC_SLOTS; i++) {
360 if (!xhci->devs[i])
361 continue;
362 speed = xhci->devs[i]->udev->speed;
363 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
364 && xhci->devs[i]->fake_port == port) {
365 slot_id = i;
366 break;
367 }
368 }
369
370 return slot_id;
371}
372
373/*
374 * Stop device
375 * It issues stop endpoint command for EP 0 to 30. And wait the last command
376 * to complete.
377 * suspend will set to 1, if suspend bit need to set in command.
378 */
379static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
380{
381 struct xhci_virt_device *virt_dev;
382 struct xhci_command *cmd;
383 unsigned long flags;
384 int ret;
385 int i;
386
387 ret = 0;
388 virt_dev = xhci->devs[slot_id];
389 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
390 if (!cmd) {
391 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
392 return -ENOMEM;
393 }
394
395 spin_lock_irqsave(&xhci->lock, flags);
396 for (i = LAST_EP_INDEX; i > 0; i--) {
397 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
398 struct xhci_command *command;
399 command = xhci_alloc_command(xhci, false, false,
400 GFP_NOWAIT);
401 if (!command) {
402 spin_unlock_irqrestore(&xhci->lock, flags);
403 xhci_free_command(xhci, cmd);
404 return -ENOMEM;
405
406 }
407 xhci_queue_stop_endpoint(xhci, command, slot_id, i,
408 suspend);
409 }
410 }
411 xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
412 xhci_ring_cmd_db(xhci);
413 spin_unlock_irqrestore(&xhci->lock, flags);
414
415 /* Wait for last stop endpoint command to finish */
416 wait_for_completion(cmd->completion);
417
418 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
419 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
420 ret = -ETIME;
421 }
422 xhci_free_command(xhci, cmd);
423 return ret;
424}
425
426/*
427 * Ring device, it rings the all doorbells unconditionally.
428 */
429void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
430{
431 int i, s;
432 struct xhci_virt_ep *ep;
433
434 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
435 ep = &xhci->devs[slot_id]->eps[i];
436
437 if (ep->ep_state & EP_HAS_STREAMS) {
438 for (s = 1; s < ep->stream_info->num_streams; s++)
439 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
440 } else if (ep->ring && ep->ring->dequeue) {
441 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
442 }
443 }
444
445 return;
446}
447
448static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
449 u16 wIndex, __le32 __iomem *addr, u32 port_status)
450{
451 /* Don't allow the USB core to disable SuperSpeed ports. */
452 if (hcd->speed >= HCD_USB3) {
453 xhci_dbg(xhci, "Ignoring request to disable "
454 "SuperSpeed port.\n");
455 return;
456 }
457
458 /* Write 1 to disable the port */
459 writel(port_status | PORT_PE, addr);
460 port_status = readl(addr);
461 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
462 wIndex, port_status);
463}
464
465static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
466 u16 wIndex, __le32 __iomem *addr, u32 port_status)
467{
468 char *port_change_bit;
469 u32 status;
470
471 switch (wValue) {
472 case USB_PORT_FEAT_C_RESET:
473 status = PORT_RC;
474 port_change_bit = "reset";
475 break;
476 case USB_PORT_FEAT_C_BH_PORT_RESET:
477 status = PORT_WRC;
478 port_change_bit = "warm(BH) reset";
479 break;
480 case USB_PORT_FEAT_C_CONNECTION:
481 status = PORT_CSC;
482 port_change_bit = "connect";
483 break;
484 case USB_PORT_FEAT_C_OVER_CURRENT:
485 status = PORT_OCC;
486 port_change_bit = "over-current";
487 break;
488 case USB_PORT_FEAT_C_ENABLE:
489 status = PORT_PEC;
490 port_change_bit = "enable/disable";
491 break;
492 case USB_PORT_FEAT_C_SUSPEND:
493 status = PORT_PLC;
494 port_change_bit = "suspend/resume";
495 break;
496 case USB_PORT_FEAT_C_PORT_LINK_STATE:
497 status = PORT_PLC;
498 port_change_bit = "link state";
499 break;
500 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
501 status = PORT_CEC;
502 port_change_bit = "config error";
503 break;
504 default:
505 /* Should never happen */
506 return;
507 }
508 /* Change bits are all write 1 to clear */
509 writel(port_status | status, addr);
510 port_status = readl(addr);
511 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
512 port_change_bit, wIndex, port_status);
513}
514
515static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
516{
517 int max_ports;
518 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
519
520 if (hcd->speed >= HCD_USB3) {
521 max_ports = xhci->num_usb3_ports;
522 *port_array = xhci->usb3_ports;
523 } else {
524 max_ports = xhci->num_usb2_ports;
525 *port_array = xhci->usb2_ports;
526 }
527
528 return max_ports;
529}
530
531void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
532 int port_id, u32 link_state)
533{
534 u32 temp;
535
536 temp = readl(port_array[port_id]);
537 temp = xhci_port_state_to_neutral(temp);
538 temp &= ~PORT_PLS_MASK;
539 temp |= PORT_LINK_STROBE | link_state;
540 writel(temp, port_array[port_id]);
541}
542
543static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
544 __le32 __iomem **port_array, int port_id, u16 wake_mask)
545{
546 u32 temp;
547
548 temp = readl(port_array[port_id]);
549 temp = xhci_port_state_to_neutral(temp);
550
551 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
552 temp |= PORT_WKCONN_E;
553 else
554 temp &= ~PORT_WKCONN_E;
555
556 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
557 temp |= PORT_WKDISC_E;
558 else
559 temp &= ~PORT_WKDISC_E;
560
561 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
562 temp |= PORT_WKOC_E;
563 else
564 temp &= ~PORT_WKOC_E;
565
566 writel(temp, port_array[port_id]);
567}
568
569/* Test and clear port RWC bit */
570void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
571 int port_id, u32 port_bit)
572{
573 u32 temp;
574
575 temp = readl(port_array[port_id]);
576 if (temp & port_bit) {
577 temp = xhci_port_state_to_neutral(temp);
578 temp |= port_bit;
579 writel(temp, port_array[port_id]);
580 }
581}
582
583/* Updates Link Status for USB 2.1 port */
584static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
585{
586 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
587 *status |= USB_PORT_STAT_L1;
588}
589
590/* Updates Link Status for super Speed port */
591static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
592 u32 *status, u32 status_reg)
593{
594 u32 pls = status_reg & PORT_PLS_MASK;
595
596 /* resume state is a xHCI internal state.
597 * Do not report it to usb core, instead, pretend to be U3,
598 * thus usb core knows it's not ready for transfer
599 */
600 if (pls == XDEV_RESUME) {
601 *status |= USB_SS_PORT_LS_U3;
602 return;
603 }
604
605 /* When the CAS bit is set then warm reset
606 * should be performed on port
607 */
608 if (status_reg & PORT_CAS) {
609 /* The CAS bit can be set while the port is
610 * in any link state.
611 * Only roothubs have CAS bit, so we
612 * pretend to be in compliance mode
613 * unless we're already in compliance
614 * or the inactive state.
615 */
616 if (pls != USB_SS_PORT_LS_COMP_MOD &&
617 pls != USB_SS_PORT_LS_SS_INACTIVE) {
618 pls = USB_SS_PORT_LS_COMP_MOD;
619 }
620 /* Return also connection bit -
621 * hub state machine resets port
622 * when this bit is set.
623 */
624 pls |= USB_PORT_STAT_CONNECTION;
625 } else {
626 /*
627 * If CAS bit isn't set but the Port is already at
628 * Compliance Mode, fake a connection so the USB core
629 * notices the Compliance state and resets the port.
630 * This resolves an issue generated by the SN65LVPE502CP
631 * in which sometimes the port enters compliance mode
632 * caused by a delay on the host-device negotiation.
633 */
634 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
635 (pls == USB_SS_PORT_LS_COMP_MOD))
636 pls |= USB_PORT_STAT_CONNECTION;
637 }
638
639 /* update status field */
640 *status |= pls;
641}
642
643/*
644 * Function for Compliance Mode Quirk.
645 *
646 * This Function verifies if all xhc USB3 ports have entered U0, if so,
647 * the compliance mode timer is deleted. A port won't enter
648 * compliance mode if it has previously entered U0.
649 */
650static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
651 u16 wIndex)
652{
653 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
654 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
655
656 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
657 return;
658
659 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
660 xhci->port_status_u0 |= 1 << wIndex;
661 if (xhci->port_status_u0 == all_ports_seen_u0) {
662 del_timer_sync(&xhci->comp_mode_recovery_timer);
663 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
664 "All USB3 ports have entered U0 already!");
665 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
666 "Compliance Mode Recovery Timer Deleted.");
667 }
668 }
669}
670
671static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
672{
673 u32 ext_stat = 0;
674 int speed_id;
675
676 /* only support rx and tx lane counts of 1 in usb3.1 spec */
677 speed_id = DEV_PORT_SPEED(raw_port_status);
678 ext_stat |= speed_id; /* bits 3:0, RX speed id */
679 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
680
681 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
682 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
683
684 return ext_stat;
685}
686
687/*
688 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
689 * 3.0 hubs use.
690 *
691 * Possible side effects:
692 * - Mark a port as being done with device resume,
693 * and ring the endpoint doorbells.
694 * - Stop the Synopsys redriver Compliance Mode polling.
695 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
696 */
697static u32 xhci_get_port_status(struct usb_hcd *hcd,
698 struct xhci_bus_state *bus_state,
699 __le32 __iomem **port_array,
700 u16 wIndex, u32 raw_port_status,
701 unsigned long flags)
702 __releases(&xhci->lock)
703 __acquires(&xhci->lock)
704{
705 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
706 u32 status = 0;
707 int slot_id;
708
709 /* wPortChange bits */
710 if (raw_port_status & PORT_CSC)
711 status |= USB_PORT_STAT_C_CONNECTION << 16;
712 if (raw_port_status & PORT_PEC)
713 status |= USB_PORT_STAT_C_ENABLE << 16;
714 if ((raw_port_status & PORT_OCC))
715 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
716 if ((raw_port_status & PORT_RC))
717 status |= USB_PORT_STAT_C_RESET << 16;
718 /* USB3.0 only */
719 if (hcd->speed >= HCD_USB3) {
720 /* Port link change with port in resume state should not be
721 * reported to usbcore, as this is an internal state to be
722 * handled by xhci driver. Reporting PLC to usbcore may
723 * cause usbcore clearing PLC first and port change event
724 * irq won't be generated.
725 */
726 if ((raw_port_status & PORT_PLC) &&
727 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
728 status |= USB_PORT_STAT_C_LINK_STATE << 16;
729 if ((raw_port_status & PORT_WRC))
730 status |= USB_PORT_STAT_C_BH_RESET << 16;
731 if ((raw_port_status & PORT_CEC))
732 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
733 }
734
735 if (hcd->speed < HCD_USB3) {
736 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
737 && (raw_port_status & PORT_POWER))
738 status |= USB_PORT_STAT_SUSPEND;
739 }
740 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
741 !DEV_SUPERSPEED_ANY(raw_port_status)) {
742 if ((raw_port_status & PORT_RESET) ||
743 !(raw_port_status & PORT_PE))
744 return 0xffffffff;
745 /* did port event handler already start resume timing? */
746 if (!bus_state->resume_done[wIndex]) {
747 /* If not, maybe we are in a host initated resume? */
748 if (test_bit(wIndex, &bus_state->resuming_ports)) {
749 /* Host initated resume doesn't time the resume
750 * signalling using resume_done[].
751 * It manually sets RESUME state, sleeps 20ms
752 * and sets U0 state. This should probably be
753 * changed, but not right now.
754 */
755 } else {
756 /* port resume was discovered now and here,
757 * start resume timing
758 */
759 unsigned long timeout = jiffies +
760 msecs_to_jiffies(USB_RESUME_TIMEOUT);
761
762 set_bit(wIndex, &bus_state->resuming_ports);
763 bus_state->resume_done[wIndex] = timeout;
764 mod_timer(&hcd->rh_timer, timeout);
765 }
766 /* Has resume been signalled for USB_RESUME_TIME yet? */
767 } else if (time_after_eq(jiffies,
768 bus_state->resume_done[wIndex])) {
769 int time_left;
770
771 xhci_dbg(xhci, "Resume USB2 port %d\n",
772 wIndex + 1);
773 bus_state->resume_done[wIndex] = 0;
774 clear_bit(wIndex, &bus_state->resuming_ports);
775
776 set_bit(wIndex, &bus_state->rexit_ports);
777 xhci_set_link_state(xhci, port_array, wIndex,
778 XDEV_U0);
779
780 spin_unlock_irqrestore(&xhci->lock, flags);
781 time_left = wait_for_completion_timeout(
782 &bus_state->rexit_done[wIndex],
783 msecs_to_jiffies(
784 XHCI_MAX_REXIT_TIMEOUT));
785 spin_lock_irqsave(&xhci->lock, flags);
786
787 if (time_left) {
788 slot_id = xhci_find_slot_id_by_port(hcd,
789 xhci, wIndex + 1);
790 if (!slot_id) {
791 xhci_dbg(xhci, "slot_id is zero\n");
792 return 0xffffffff;
793 }
794 xhci_ring_device(xhci, slot_id);
795 } else {
796 int port_status = readl(port_array[wIndex]);
797 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
798 XHCI_MAX_REXIT_TIMEOUT,
799 port_status);
800 status |= USB_PORT_STAT_SUSPEND;
801 clear_bit(wIndex, &bus_state->rexit_ports);
802 }
803
804 bus_state->port_c_suspend |= 1 << wIndex;
805 bus_state->suspended_ports &= ~(1 << wIndex);
806 } else {
807 /*
808 * The resume has been signaling for less than
809 * USB_RESUME_TIME. Report the port status as SUSPEND,
810 * let the usbcore check port status again and clear
811 * resume signaling later.
812 */
813 status |= USB_PORT_STAT_SUSPEND;
814 }
815 }
816 /*
817 * Clear stale usb2 resume signalling variables in case port changed
818 * state during resume signalling. For example on error
819 */
820 if ((bus_state->resume_done[wIndex] ||
821 test_bit(wIndex, &bus_state->resuming_ports)) &&
822 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
823 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
824 bus_state->resume_done[wIndex] = 0;
825 clear_bit(wIndex, &bus_state->resuming_ports);
826 }
827
828
829 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
830 (raw_port_status & PORT_POWER)) {
831 if (bus_state->suspended_ports & (1 << wIndex)) {
832 bus_state->suspended_ports &= ~(1 << wIndex);
833 if (hcd->speed < HCD_USB3)
834 bus_state->port_c_suspend |= 1 << wIndex;
835 }
836 bus_state->resume_done[wIndex] = 0;
837 clear_bit(wIndex, &bus_state->resuming_ports);
838 }
839 if (raw_port_status & PORT_CONNECT) {
840 status |= USB_PORT_STAT_CONNECTION;
841 status |= xhci_port_speed(raw_port_status);
842 }
843 if (raw_port_status & PORT_PE)
844 status |= USB_PORT_STAT_ENABLE;
845 if (raw_port_status & PORT_OC)
846 status |= USB_PORT_STAT_OVERCURRENT;
847 if (raw_port_status & PORT_RESET)
848 status |= USB_PORT_STAT_RESET;
849 if (raw_port_status & PORT_POWER) {
850 if (hcd->speed >= HCD_USB3)
851 status |= USB_SS_PORT_STAT_POWER;
852 else
853 status |= USB_PORT_STAT_POWER;
854 }
855 /* Update Port Link State */
856 if (hcd->speed >= HCD_USB3) {
857 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
858 /*
859 * Verify if all USB3 Ports Have entered U0 already.
860 * Delete Compliance Mode Timer if so.
861 */
862 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
863 } else {
864 xhci_hub_report_usb2_link_state(&status, raw_port_status);
865 }
866 if (bus_state->port_c_suspend & (1 << wIndex))
867 status |= USB_PORT_STAT_C_SUSPEND << 16;
868
869 return status;
870}
871
872int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
873 u16 wIndex, char *buf, u16 wLength)
874{
875 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
876 int max_ports;
877 unsigned long flags;
878 u32 temp, status;
879 int retval = 0;
880 __le32 __iomem **port_array;
881 int slot_id;
882 struct xhci_bus_state *bus_state;
883 u16 link_state = 0;
884 u16 wake_mask = 0;
885 u16 timeout = 0;
886
887 max_ports = xhci_get_ports(hcd, &port_array);
888 bus_state = &xhci->bus_state[hcd_index(hcd)];
889
890 spin_lock_irqsave(&xhci->lock, flags);
891 switch (typeReq) {
892 case GetHubStatus:
893 /* No power source, over-current reported per port */
894 memset(buf, 0, 4);
895 break;
896 case GetHubDescriptor:
897 /* Check to make sure userspace is asking for the USB 3.0 hub
898 * descriptor for the USB 3.0 roothub. If not, we stall the
899 * endpoint, like external hubs do.
900 */
901 if (hcd->speed >= HCD_USB3 &&
902 (wLength < USB_DT_SS_HUB_SIZE ||
903 wValue != (USB_DT_SS_HUB << 8))) {
904 xhci_dbg(xhci, "Wrong hub descriptor type for "
905 "USB 3.0 roothub.\n");
906 goto error;
907 }
908 xhci_hub_descriptor(hcd, xhci,
909 (struct usb_hub_descriptor *) buf);
910 break;
911 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
912 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
913 goto error;
914
915 if (hcd->speed < HCD_USB3)
916 goto error;
917
918 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
919 spin_unlock_irqrestore(&xhci->lock, flags);
920 return retval;
921 case GetPortStatus:
922 if (!wIndex || wIndex > max_ports)
923 goto error;
924 wIndex--;
925 temp = readl(port_array[wIndex]);
926 if (temp == 0xffffffff) {
927 retval = -ENODEV;
928 break;
929 }
930 status = xhci_get_port_status(hcd, bus_state, port_array,
931 wIndex, temp, flags);
932 if (status == 0xffffffff)
933 goto error;
934
935 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
936 wIndex, temp);
937 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
938
939 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
940 /* if USB 3.1 extended port status return additional 4 bytes */
941 if (wValue == 0x02) {
942 u32 port_li;
943
944 if (hcd->speed < HCD_USB31 || wLength != 8) {
945 xhci_err(xhci, "get ext port status invalid parameter\n");
946 retval = -EINVAL;
947 break;
948 }
949 port_li = readl(port_array[wIndex] + PORTLI);
950 status = xhci_get_ext_port_status(temp, port_li);
951 put_unaligned_le32(cpu_to_le32(status), &buf[4]);
952 }
953 break;
954 case SetPortFeature:
955 if (wValue == USB_PORT_FEAT_LINK_STATE)
956 link_state = (wIndex & 0xff00) >> 3;
957 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
958 wake_mask = wIndex & 0xff00;
959 /* The MSB of wIndex is the U1/U2 timeout */
960 timeout = (wIndex & 0xff00) >> 8;
961 wIndex &= 0xff;
962 if (!wIndex || wIndex > max_ports)
963 goto error;
964 wIndex--;
965 temp = readl(port_array[wIndex]);
966 if (temp == 0xffffffff) {
967 retval = -ENODEV;
968 break;
969 }
970 temp = xhci_port_state_to_neutral(temp);
971 /* FIXME: What new port features do we need to support? */
972 switch (wValue) {
973 case USB_PORT_FEAT_SUSPEND:
974 temp = readl(port_array[wIndex]);
975 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
976 /* Resume the port to U0 first */
977 xhci_set_link_state(xhci, port_array, wIndex,
978 XDEV_U0);
979 spin_unlock_irqrestore(&xhci->lock, flags);
980 msleep(10);
981 spin_lock_irqsave(&xhci->lock, flags);
982 }
983 /* In spec software should not attempt to suspend
984 * a port unless the port reports that it is in the
985 * enabled (PED = ‘1’,PLS < ‘3’) state.
986 */
987 temp = readl(port_array[wIndex]);
988 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
989 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
990 xhci_warn(xhci, "USB core suspending device "
991 "not in U0/U1/U2.\n");
992 goto error;
993 }
994
995 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
996 wIndex + 1);
997 if (!slot_id) {
998 xhci_warn(xhci, "slot_id is zero\n");
999 goto error;
1000 }
1001 /* unlock to execute stop endpoint commands */
1002 spin_unlock_irqrestore(&xhci->lock, flags);
1003 xhci_stop_device(xhci, slot_id, 1);
1004 spin_lock_irqsave(&xhci->lock, flags);
1005
1006 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1007
1008 spin_unlock_irqrestore(&xhci->lock, flags);
1009 msleep(10); /* wait device to enter */
1010 spin_lock_irqsave(&xhci->lock, flags);
1011
1012 temp = readl(port_array[wIndex]);
1013 bus_state->suspended_ports |= 1 << wIndex;
1014 break;
1015 case USB_PORT_FEAT_LINK_STATE:
1016 temp = readl(port_array[wIndex]);
1017
1018 /* Disable port */
1019 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1020 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1021 temp = xhci_port_state_to_neutral(temp);
1022 /*
1023 * Clear all change bits, so that we get a new
1024 * connection event.
1025 */
1026 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1027 PORT_OCC | PORT_RC | PORT_PLC |
1028 PORT_CEC;
1029 writel(temp | PORT_PE, port_array[wIndex]);
1030 temp = readl(port_array[wIndex]);
1031 break;
1032 }
1033
1034 /* Put link in RxDetect (enable port) */
1035 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1036 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1037 xhci_set_link_state(xhci, port_array, wIndex,
1038 link_state);
1039 temp = readl(port_array[wIndex]);
1040 break;
1041 }
1042
1043 /* Software should not attempt to set
1044 * port link state above '3' (U3) and the port
1045 * must be enabled.
1046 */
1047 if ((temp & PORT_PE) == 0 ||
1048 (link_state > USB_SS_PORT_LS_U3)) {
1049 xhci_warn(xhci, "Cannot set link state.\n");
1050 goto error;
1051 }
1052
1053 if (link_state == USB_SS_PORT_LS_U3) {
1054 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1055 wIndex + 1);
1056 if (slot_id) {
1057 /* unlock to execute stop endpoint
1058 * commands */
1059 spin_unlock_irqrestore(&xhci->lock,
1060 flags);
1061 xhci_stop_device(xhci, slot_id, 1);
1062 spin_lock_irqsave(&xhci->lock, flags);
1063 }
1064 }
1065
1066 xhci_set_link_state(xhci, port_array, wIndex,
1067 link_state);
1068
1069 spin_unlock_irqrestore(&xhci->lock, flags);
1070 msleep(20); /* wait device to enter */
1071 spin_lock_irqsave(&xhci->lock, flags);
1072
1073 temp = readl(port_array[wIndex]);
1074 if (link_state == USB_SS_PORT_LS_U3)
1075 bus_state->suspended_ports |= 1 << wIndex;
1076 break;
1077 case USB_PORT_FEAT_POWER:
1078 /*
1079 * Turn on ports, even if there isn't per-port switching.
1080 * HC will report connect events even before this is set.
1081 * However, hub_wq will ignore the roothub events until
1082 * the roothub is registered.
1083 */
1084 writel(temp | PORT_POWER, port_array[wIndex]);
1085
1086 temp = readl(port_array[wIndex]);
1087 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
1088
1089 spin_unlock_irqrestore(&xhci->lock, flags);
1090 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1091 wIndex);
1092 if (temp)
1093 usb_acpi_set_power_state(hcd->self.root_hub,
1094 wIndex, true);
1095 spin_lock_irqsave(&xhci->lock, flags);
1096 break;
1097 case USB_PORT_FEAT_RESET:
1098 temp = (temp | PORT_RESET);
1099 writel(temp, port_array[wIndex]);
1100
1101 temp = readl(port_array[wIndex]);
1102 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1103 break;
1104 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1105 xhci_set_remote_wake_mask(xhci, port_array,
1106 wIndex, wake_mask);
1107 temp = readl(port_array[wIndex]);
1108 xhci_dbg(xhci, "set port remote wake mask, "
1109 "actual port %d status = 0x%x\n",
1110 wIndex, temp);
1111 break;
1112 case USB_PORT_FEAT_BH_PORT_RESET:
1113 temp |= PORT_WR;
1114 writel(temp, port_array[wIndex]);
1115
1116 temp = readl(port_array[wIndex]);
1117 break;
1118 case USB_PORT_FEAT_U1_TIMEOUT:
1119 if (hcd->speed < HCD_USB3)
1120 goto error;
1121 temp = readl(port_array[wIndex] + PORTPMSC);
1122 temp &= ~PORT_U1_TIMEOUT_MASK;
1123 temp |= PORT_U1_TIMEOUT(timeout);
1124 writel(temp, port_array[wIndex] + PORTPMSC);
1125 break;
1126 case USB_PORT_FEAT_U2_TIMEOUT:
1127 if (hcd->speed < HCD_USB3)
1128 goto error;
1129 temp = readl(port_array[wIndex] + PORTPMSC);
1130 temp &= ~PORT_U2_TIMEOUT_MASK;
1131 temp |= PORT_U2_TIMEOUT(timeout);
1132 writel(temp, port_array[wIndex] + PORTPMSC);
1133 break;
1134 default:
1135 goto error;
1136 }
1137 /* unblock any posted writes */
1138 temp = readl(port_array[wIndex]);
1139 break;
1140 case ClearPortFeature:
1141 if (!wIndex || wIndex > max_ports)
1142 goto error;
1143 wIndex--;
1144 temp = readl(port_array[wIndex]);
1145 if (temp == 0xffffffff) {
1146 retval = -ENODEV;
1147 break;
1148 }
1149 /* FIXME: What new port features do we need to support? */
1150 temp = xhci_port_state_to_neutral(temp);
1151 switch (wValue) {
1152 case USB_PORT_FEAT_SUSPEND:
1153 temp = readl(port_array[wIndex]);
1154 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1155 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1156 if (temp & PORT_RESET)
1157 goto error;
1158 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1159 if ((temp & PORT_PE) == 0)
1160 goto error;
1161
1162 set_bit(wIndex, &bus_state->resuming_ports);
1163 xhci_set_link_state(xhci, port_array, wIndex,
1164 XDEV_RESUME);
1165 spin_unlock_irqrestore(&xhci->lock, flags);
1166 msleep(20);
1167 spin_lock_irqsave(&xhci->lock, flags);
1168 xhci_set_link_state(xhci, port_array, wIndex,
1169 XDEV_U0);
1170 clear_bit(wIndex, &bus_state->resuming_ports);
1171 }
1172 bus_state->port_c_suspend |= 1 << wIndex;
1173
1174 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1175 wIndex + 1);
1176 if (!slot_id) {
1177 xhci_dbg(xhci, "slot_id is zero\n");
1178 goto error;
1179 }
1180 xhci_ring_device(xhci, slot_id);
1181 break;
1182 case USB_PORT_FEAT_C_SUSPEND:
1183 bus_state->port_c_suspend &= ~(1 << wIndex);
1184 case USB_PORT_FEAT_C_RESET:
1185 case USB_PORT_FEAT_C_BH_PORT_RESET:
1186 case USB_PORT_FEAT_C_CONNECTION:
1187 case USB_PORT_FEAT_C_OVER_CURRENT:
1188 case USB_PORT_FEAT_C_ENABLE:
1189 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1190 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1191 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1192 port_array[wIndex], temp);
1193 break;
1194 case USB_PORT_FEAT_ENABLE:
1195 xhci_disable_port(hcd, xhci, wIndex,
1196 port_array[wIndex], temp);
1197 break;
1198 case USB_PORT_FEAT_POWER:
1199 writel(temp & ~PORT_POWER, port_array[wIndex]);
1200
1201 spin_unlock_irqrestore(&xhci->lock, flags);
1202 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1203 wIndex);
1204 if (temp)
1205 usb_acpi_set_power_state(hcd->self.root_hub,
1206 wIndex, false);
1207 spin_lock_irqsave(&xhci->lock, flags);
1208 break;
1209 default:
1210 goto error;
1211 }
1212 break;
1213 default:
1214error:
1215 /* "stall" on error */
1216 retval = -EPIPE;
1217 }
1218 spin_unlock_irqrestore(&xhci->lock, flags);
1219 return retval;
1220}
1221
1222/*
1223 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1224 * Ports are 0-indexed from the HCD point of view,
1225 * and 1-indexed from the USB core pointer of view.
1226 *
1227 * Note that the status change bits will be cleared as soon as a port status
1228 * change event is generated, so we use the saved status from that event.
1229 */
1230int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1231{
1232 unsigned long flags;
1233 u32 temp, status;
1234 u32 mask;
1235 int i, retval;
1236 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1237 int max_ports;
1238 __le32 __iomem **port_array;
1239 struct xhci_bus_state *bus_state;
1240 bool reset_change = false;
1241
1242 max_ports = xhci_get_ports(hcd, &port_array);
1243 bus_state = &xhci->bus_state[hcd_index(hcd)];
1244
1245 /* Initial status is no changes */
1246 retval = (max_ports + 8) / 8;
1247 memset(buf, 0, retval);
1248
1249 /*
1250 * Inform the usbcore about resume-in-progress by returning
1251 * a non-zero value even if there are no status changes.
1252 */
1253 status = bus_state->resuming_ports;
1254
1255 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1256
1257 spin_lock_irqsave(&xhci->lock, flags);
1258 /* For each port, did anything change? If so, set that bit in buf. */
1259 for (i = 0; i < max_ports; i++) {
1260 temp = readl(port_array[i]);
1261 if (temp == 0xffffffff) {
1262 retval = -ENODEV;
1263 break;
1264 }
1265 if ((temp & mask) != 0 ||
1266 (bus_state->port_c_suspend & 1 << i) ||
1267 (bus_state->resume_done[i] && time_after_eq(
1268 jiffies, bus_state->resume_done[i]))) {
1269 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1270 status = 1;
1271 }
1272 if ((temp & PORT_RC))
1273 reset_change = true;
1274 }
1275 if (!status && !reset_change) {
1276 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1277 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1278 }
1279 spin_unlock_irqrestore(&xhci->lock, flags);
1280 return status ? retval : 0;
1281}
1282
1283#ifdef CONFIG_PM
1284
1285int xhci_bus_suspend(struct usb_hcd *hcd)
1286{
1287 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1288 int max_ports, port_index;
1289 __le32 __iomem **port_array;
1290 struct xhci_bus_state *bus_state;
1291 unsigned long flags;
1292
1293 max_ports = xhci_get_ports(hcd, &port_array);
1294 bus_state = &xhci->bus_state[hcd_index(hcd)];
1295
1296 spin_lock_irqsave(&xhci->lock, flags);
1297
1298 if (hcd->self.root_hub->do_remote_wakeup) {
1299 if (bus_state->resuming_ports || /* USB2 */
1300 bus_state->port_remote_wakeup) { /* USB3 */
1301 spin_unlock_irqrestore(&xhci->lock, flags);
1302 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1303 return -EBUSY;
1304 }
1305 }
1306
1307 port_index = max_ports;
1308 bus_state->bus_suspended = 0;
1309 while (port_index--) {
1310 /* suspend the port if the port is not suspended */
1311 u32 t1, t2;
1312 int slot_id;
1313
1314 t1 = readl(port_array[port_index]);
1315 t2 = xhci_port_state_to_neutral(t1);
1316
1317 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1318 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1319 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1320 port_index + 1);
1321 if (slot_id) {
1322 spin_unlock_irqrestore(&xhci->lock, flags);
1323 xhci_stop_device(xhci, slot_id, 1);
1324 spin_lock_irqsave(&xhci->lock, flags);
1325 }
1326 t2 &= ~PORT_PLS_MASK;
1327 t2 |= PORT_LINK_STROBE | XDEV_U3;
1328 set_bit(port_index, &bus_state->bus_suspended);
1329 }
1330 /* USB core sets remote wake mask for USB 3.0 hubs,
1331 * including the USB 3.0 roothub, but only if CONFIG_PM
1332 * is enabled, so also enable remote wake here.
1333 */
1334 if (hcd->self.root_hub->do_remote_wakeup) {
1335 if (t1 & PORT_CONNECT) {
1336 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1337 t2 &= ~PORT_WKCONN_E;
1338 } else {
1339 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1340 t2 &= ~PORT_WKDISC_E;
1341 }
1342 } else
1343 t2 &= ~PORT_WAKE_BITS;
1344
1345 t1 = xhci_port_state_to_neutral(t1);
1346 if (t1 != t2)
1347 writel(t2, port_array[port_index]);
1348 }
1349 hcd->state = HC_STATE_SUSPENDED;
1350 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1351 spin_unlock_irqrestore(&xhci->lock, flags);
1352 return 0;
1353}
1354
1355int xhci_bus_resume(struct usb_hcd *hcd)
1356{
1357 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1358 int max_ports, port_index;
1359 __le32 __iomem **port_array;
1360 struct xhci_bus_state *bus_state;
1361 u32 temp;
1362 unsigned long flags;
1363 unsigned long port_was_suspended = 0;
1364 bool need_usb2_u3_exit = false;
1365 int slot_id;
1366 int sret;
1367
1368 max_ports = xhci_get_ports(hcd, &port_array);
1369 bus_state = &xhci->bus_state[hcd_index(hcd)];
1370
1371 if (time_before(jiffies, bus_state->next_statechange))
1372 msleep(5);
1373
1374 spin_lock_irqsave(&xhci->lock, flags);
1375 if (!HCD_HW_ACCESSIBLE(hcd)) {
1376 spin_unlock_irqrestore(&xhci->lock, flags);
1377 return -ESHUTDOWN;
1378 }
1379
1380 /* delay the irqs */
1381 temp = readl(&xhci->op_regs->command);
1382 temp &= ~CMD_EIE;
1383 writel(temp, &xhci->op_regs->command);
1384
1385 port_index = max_ports;
1386 while (port_index--) {
1387 /* Check whether need resume ports. If needed
1388 resume port and disable remote wakeup */
1389 u32 temp;
1390
1391 temp = readl(port_array[port_index]);
1392 if (DEV_SUPERSPEED_ANY(temp))
1393 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1394 else
1395 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1396 if (test_bit(port_index, &bus_state->bus_suspended) &&
1397 (temp & PORT_PLS_MASK)) {
1398 set_bit(port_index, &port_was_suspended);
1399 if (!DEV_SUPERSPEED_ANY(temp)) {
1400 xhci_set_link_state(xhci, port_array,
1401 port_index, XDEV_RESUME);
1402 need_usb2_u3_exit = true;
1403 }
1404 } else
1405 writel(temp, port_array[port_index]);
1406 }
1407
1408 if (need_usb2_u3_exit) {
1409 spin_unlock_irqrestore(&xhci->lock, flags);
1410 msleep(20);
1411 spin_lock_irqsave(&xhci->lock, flags);
1412 }
1413
1414 port_index = max_ports;
1415 while (port_index--) {
1416 if (!(port_was_suspended & BIT(port_index)))
1417 continue;
1418 /* Clear PLC to poll it later after XDEV_U0 */
1419 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1420 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1421 }
1422
1423 port_index = max_ports;
1424 while (port_index--) {
1425 if (!(port_was_suspended & BIT(port_index)))
1426 continue;
1427 /* Poll and Clear PLC */
1428 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1429 PORT_PLC, 10 * 1000);
1430 if (sret)
1431 xhci_warn(xhci, "port %d resume PLC timeout\n",
1432 port_index);
1433 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1434 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1435 if (slot_id)
1436 xhci_ring_device(xhci, slot_id);
1437 }
1438
1439 (void) readl(&xhci->op_regs->command);
1440
1441 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1442 /* re-enable irqs */
1443 temp = readl(&xhci->op_regs->command);
1444 temp |= CMD_EIE;
1445 writel(temp, &xhci->op_regs->command);
1446 temp = readl(&xhci->op_regs->command);
1447
1448 spin_unlock_irqrestore(&xhci->lock, flags);
1449 return 0;
1450}
1451
1452#endif /* CONFIG_PM */
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/gfp.h>
24#include <asm/unaligned.h>
25
26#include "xhci.h"
27
28#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
29#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
30 PORT_RC | PORT_PLC | PORT_PE)
31
32/* usb 1.1 root hub device descriptor */
33static u8 usb_bos_descriptor [] = {
34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
35 USB_DT_BOS, /* __u8 bDescriptorType */
36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
37 0x1, /* __u8 bNumDeviceCaps */
38 /* First device capability */
39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
42 0x00, /* bmAttributes, LTM off by default */
43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
44 0x03, /* bFunctionalitySupport,
45 USB 3.0 speed only */
46 0x00, /* bU1DevExitLat, set later. */
47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
48};
49
50
51static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
52 struct usb_hub_descriptor *desc, int ports)
53{
54 u16 temp;
55
56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
57 desc->bHubContrCurrent = 0;
58
59 desc->bNbrPorts = ports;
60 temp = 0;
61 /* Bits 1:0 - support per-port power switching, or power always on */
62 if (HCC_PPC(xhci->hcc_params))
63 temp |= HUB_CHAR_INDV_PORT_LPSM;
64 else
65 temp |= HUB_CHAR_NO_LPSM;
66 /* Bit 2 - root hubs are not part of a compound device */
67 /* Bits 4:3 - individual port over current protection */
68 temp |= HUB_CHAR_INDV_PORT_OCPM;
69 /* Bits 6:5 - no TTs in root ports */
70 /* Bit 7 - no port indicators */
71 desc->wHubCharacteristics = cpu_to_le16(temp);
72}
73
74/* Fill in the USB 2.0 roothub descriptor */
75static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
76 struct usb_hub_descriptor *desc)
77{
78 int ports;
79 u16 temp;
80 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
81 u32 portsc;
82 unsigned int i;
83
84 ports = xhci->num_usb2_ports;
85
86 xhci_common_hub_descriptor(xhci, desc, ports);
87 desc->bDescriptorType = USB_DT_HUB;
88 temp = 1 + (ports / 8);
89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
90
91 /* The Device Removable bits are reported on a byte granularity.
92 * If the port doesn't exist within that byte, the bit is set to 0.
93 */
94 memset(port_removable, 0, sizeof(port_removable));
95 for (i = 0; i < ports; i++) {
96 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
97 /* If a device is removable, PORTSC reports a 0, same as in the
98 * hub descriptor DeviceRemovable bits.
99 */
100 if (portsc & PORT_DEV_REMOVE)
101 /* This math is hairy because bit 0 of DeviceRemovable
102 * is reserved, and bit 1 is for port 1, etc.
103 */
104 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
105 }
106
107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
108 * ports on it. The USB 2.0 specification says that there are two
109 * variable length fields at the end of the hub descriptor:
110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
113 * 0xFF, so we initialize the both arrays (DeviceRemovable and
114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
115 * set of ports that actually exist.
116 */
117 memset(desc->u.hs.DeviceRemovable, 0xff,
118 sizeof(desc->u.hs.DeviceRemovable));
119 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
120 sizeof(desc->u.hs.PortPwrCtrlMask));
121
122 for (i = 0; i < (ports + 1 + 7) / 8; i++)
123 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
124 sizeof(__u8));
125}
126
127/* Fill in the USB 3.0 roothub descriptor */
128static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
129 struct usb_hub_descriptor *desc)
130{
131 int ports;
132 u16 port_removable;
133 u32 portsc;
134 unsigned int i;
135
136 ports = xhci->num_usb3_ports;
137 xhci_common_hub_descriptor(xhci, desc, ports);
138 desc->bDescriptorType = USB_DT_SS_HUB;
139 desc->bDescLength = USB_DT_SS_HUB_SIZE;
140
141 /* header decode latency should be zero for roothubs,
142 * see section 4.23.5.2.
143 */
144 desc->u.ss.bHubHdrDecLat = 0;
145 desc->u.ss.wHubDelay = 0;
146
147 port_removable = 0;
148 /* bit 0 is reserved, bit 1 is for port 1, etc. */
149 for (i = 0; i < ports; i++) {
150 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
151 if (portsc & PORT_DEV_REMOVE)
152 port_removable |= 1 << (i + 1);
153 }
154 memset(&desc->u.ss.DeviceRemovable,
155 (__force __u16) cpu_to_le16(port_removable),
156 sizeof(__u16));
157}
158
159static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
160 struct usb_hub_descriptor *desc)
161{
162
163 if (hcd->speed == HCD_USB3)
164 xhci_usb3_hub_descriptor(hcd, xhci, desc);
165 else
166 xhci_usb2_hub_descriptor(hcd, xhci, desc);
167
168}
169
170static unsigned int xhci_port_speed(unsigned int port_status)
171{
172 if (DEV_LOWSPEED(port_status))
173 return USB_PORT_STAT_LOW_SPEED;
174 if (DEV_HIGHSPEED(port_status))
175 return USB_PORT_STAT_HIGH_SPEED;
176 /*
177 * FIXME: Yes, we should check for full speed, but the core uses that as
178 * a default in portspeed() in usb/core/hub.c (which is the only place
179 * USB_PORT_STAT_*_SPEED is used).
180 */
181 return 0;
182}
183
184/*
185 * These bits are Read Only (RO) and should be saved and written to the
186 * registers: 0, 3, 10:13, 30
187 * connect status, over-current status, port speed, and device removable.
188 * connect status and port speed are also sticky - meaning they're in
189 * the AUX well and they aren't changed by a hot, warm, or cold reset.
190 */
191#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
192/*
193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
194 * bits 5:8, 9, 14:15, 25:27
195 * link state, port power, port indicator state, "wake on" enable state
196 */
197#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
198/*
199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
200 * bit 4 (port reset)
201 */
202#define XHCI_PORT_RW1S ((1<<4))
203/*
204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
205 * bits 1, 17, 18, 19, 20, 21, 22, 23
206 * port enable/disable, and
207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
208 * over-current, reset, link state, and L1 change
209 */
210#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
211/*
212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
213 * latched in
214 */
215#define XHCI_PORT_RW ((1<<16))
216/*
217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
218 * bits 2, 24, 28:31
219 */
220#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
221
222/*
223 * Given a port state, this function returns a value that would result in the
224 * port being in the same state, if the value was written to the port status
225 * control register.
226 * Save Read Only (RO) bits and save read/write bits where
227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
229 */
230u32 xhci_port_state_to_neutral(u32 state)
231{
232 /* Save read-only status and port state */
233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
234}
235
236/*
237 * find slot id based on port number.
238 * @port: The one-based port number from one of the two split roothubs.
239 */
240int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
241 u16 port)
242{
243 int slot_id;
244 int i;
245 enum usb_device_speed speed;
246
247 slot_id = 0;
248 for (i = 0; i < MAX_HC_SLOTS; i++) {
249 if (!xhci->devs[i])
250 continue;
251 speed = xhci->devs[i]->udev->speed;
252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
253 && xhci->devs[i]->fake_port == port) {
254 slot_id = i;
255 break;
256 }
257 }
258
259 return slot_id;
260}
261
262/*
263 * Stop device
264 * It issues stop endpoint command for EP 0 to 30. And wait the last command
265 * to complete.
266 * suspend will set to 1, if suspend bit need to set in command.
267 */
268static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
269{
270 struct xhci_virt_device *virt_dev;
271 struct xhci_command *cmd;
272 unsigned long flags;
273 int timeleft;
274 int ret;
275 int i;
276
277 ret = 0;
278 virt_dev = xhci->devs[slot_id];
279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
280 if (!cmd) {
281 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
282 return -ENOMEM;
283 }
284
285 spin_lock_irqsave(&xhci->lock, flags);
286 for (i = LAST_EP_INDEX; i > 0; i--) {
287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
289 }
290 cmd->command_trb = xhci->cmd_ring->enqueue;
291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
293 xhci_ring_cmd_db(xhci);
294 spin_unlock_irqrestore(&xhci->lock, flags);
295
296 /* Wait for last stop endpoint command to finish */
297 timeleft = wait_for_completion_interruptible_timeout(
298 cmd->completion,
299 USB_CTRL_SET_TIMEOUT);
300 if (timeleft <= 0) {
301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
302 timeleft == 0 ? "Timeout" : "Signal");
303 spin_lock_irqsave(&xhci->lock, flags);
304 /* The timeout might have raced with the event ring handler, so
305 * only delete from the list if the item isn't poisoned.
306 */
307 if (cmd->cmd_list.next != LIST_POISON1)
308 list_del(&cmd->cmd_list);
309 spin_unlock_irqrestore(&xhci->lock, flags);
310 ret = -ETIME;
311 goto command_cleanup;
312 }
313
314command_cleanup:
315 xhci_free_command(xhci, cmd);
316 return ret;
317}
318
319/*
320 * Ring device, it rings the all doorbells unconditionally.
321 */
322void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
323{
324 int i;
325
326 for (i = 0; i < LAST_EP_INDEX + 1; i++)
327 if (xhci->devs[slot_id]->eps[i].ring &&
328 xhci->devs[slot_id]->eps[i].ring->dequeue)
329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
330
331 return;
332}
333
334static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
335 u16 wIndex, __le32 __iomem *addr, u32 port_status)
336{
337 /* Don't allow the USB core to disable SuperSpeed ports. */
338 if (hcd->speed == HCD_USB3) {
339 xhci_dbg(xhci, "Ignoring request to disable "
340 "SuperSpeed port.\n");
341 return;
342 }
343
344 /* Write 1 to disable the port */
345 xhci_writel(xhci, port_status | PORT_PE, addr);
346 port_status = xhci_readl(xhci, addr);
347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
348 wIndex, port_status);
349}
350
351static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
352 u16 wIndex, __le32 __iomem *addr, u32 port_status)
353{
354 char *port_change_bit;
355 u32 status;
356
357 switch (wValue) {
358 case USB_PORT_FEAT_C_RESET:
359 status = PORT_RC;
360 port_change_bit = "reset";
361 break;
362 case USB_PORT_FEAT_C_BH_PORT_RESET:
363 status = PORT_WRC;
364 port_change_bit = "warm(BH) reset";
365 break;
366 case USB_PORT_FEAT_C_CONNECTION:
367 status = PORT_CSC;
368 port_change_bit = "connect";
369 break;
370 case USB_PORT_FEAT_C_OVER_CURRENT:
371 status = PORT_OCC;
372 port_change_bit = "over-current";
373 break;
374 case USB_PORT_FEAT_C_ENABLE:
375 status = PORT_PEC;
376 port_change_bit = "enable/disable";
377 break;
378 case USB_PORT_FEAT_C_SUSPEND:
379 status = PORT_PLC;
380 port_change_bit = "suspend/resume";
381 break;
382 case USB_PORT_FEAT_C_PORT_LINK_STATE:
383 status = PORT_PLC;
384 port_change_bit = "link state";
385 break;
386 default:
387 /* Should never happen */
388 return;
389 }
390 /* Change bits are all write 1 to clear */
391 xhci_writel(xhci, port_status | status, addr);
392 port_status = xhci_readl(xhci, addr);
393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
394 port_change_bit, wIndex, port_status);
395}
396
397static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
398{
399 int max_ports;
400 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
401
402 if (hcd->speed == HCD_USB3) {
403 max_ports = xhci->num_usb3_ports;
404 *port_array = xhci->usb3_ports;
405 } else {
406 max_ports = xhci->num_usb2_ports;
407 *port_array = xhci->usb2_ports;
408 }
409
410 return max_ports;
411}
412
413void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
414 int port_id, u32 link_state)
415{
416 u32 temp;
417
418 temp = xhci_readl(xhci, port_array[port_id]);
419 temp = xhci_port_state_to_neutral(temp);
420 temp &= ~PORT_PLS_MASK;
421 temp |= PORT_LINK_STROBE | link_state;
422 xhci_writel(xhci, temp, port_array[port_id]);
423}
424
425void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
426 __le32 __iomem **port_array, int port_id, u16 wake_mask)
427{
428 u32 temp;
429
430 temp = xhci_readl(xhci, port_array[port_id]);
431 temp = xhci_port_state_to_neutral(temp);
432
433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
434 temp |= PORT_WKCONN_E;
435 else
436 temp &= ~PORT_WKCONN_E;
437
438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
439 temp |= PORT_WKDISC_E;
440 else
441 temp &= ~PORT_WKDISC_E;
442
443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
444 temp |= PORT_WKOC_E;
445 else
446 temp &= ~PORT_WKOC_E;
447
448 xhci_writel(xhci, temp, port_array[port_id]);
449}
450
451/* Test and clear port RWC bit */
452void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
453 int port_id, u32 port_bit)
454{
455 u32 temp;
456
457 temp = xhci_readl(xhci, port_array[port_id]);
458 if (temp & port_bit) {
459 temp = xhci_port_state_to_neutral(temp);
460 temp |= port_bit;
461 xhci_writel(xhci, temp, port_array[port_id]);
462 }
463}
464
465/* Updates Link Status for super Speed port */
466static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
467{
468 u32 pls = status_reg & PORT_PLS_MASK;
469
470 /* resume state is a xHCI internal state.
471 * Do not report it to usb core.
472 */
473 if (pls == XDEV_RESUME)
474 return;
475
476 /* When the CAS bit is set then warm reset
477 * should be performed on port
478 */
479 if (status_reg & PORT_CAS) {
480 /* The CAS bit can be set while the port is
481 * in any link state.
482 * Only roothubs have CAS bit, so we
483 * pretend to be in compliance mode
484 * unless we're already in compliance
485 * or the inactive state.
486 */
487 if (pls != USB_SS_PORT_LS_COMP_MOD &&
488 pls != USB_SS_PORT_LS_SS_INACTIVE) {
489 pls = USB_SS_PORT_LS_COMP_MOD;
490 }
491 /* Return also connection bit -
492 * hub state machine resets port
493 * when this bit is set.
494 */
495 pls |= USB_PORT_STAT_CONNECTION;
496 } else {
497 /*
498 * If CAS bit isn't set but the Port is already at
499 * Compliance Mode, fake a connection so the USB core
500 * notices the Compliance state and resets the port.
501 * This resolves an issue generated by the SN65LVPE502CP
502 * in which sometimes the port enters compliance mode
503 * caused by a delay on the host-device negotiation.
504 */
505 if (pls == USB_SS_PORT_LS_COMP_MOD)
506 pls |= USB_PORT_STAT_CONNECTION;
507 }
508
509 /* update status field */
510 *status |= pls;
511}
512
513/*
514 * Function for Compliance Mode Quirk.
515 *
516 * This Function verifies if all xhc USB3 ports have entered U0, if so,
517 * the compliance mode timer is deleted. A port won't enter
518 * compliance mode if it has previously entered U0.
519 */
520void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
521{
522 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
523 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
524
525 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
526 return;
527
528 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
529 xhci->port_status_u0 |= 1 << wIndex;
530 if (xhci->port_status_u0 == all_ports_seen_u0) {
531 del_timer_sync(&xhci->comp_mode_recovery_timer);
532 xhci_dbg(xhci, "All USB3 ports have entered U0 already!\n");
533 xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted.\n");
534 }
535 }
536}
537
538int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
539 u16 wIndex, char *buf, u16 wLength)
540{
541 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
542 int max_ports;
543 unsigned long flags;
544 u32 temp, status;
545 int retval = 0;
546 __le32 __iomem **port_array;
547 int slot_id;
548 struct xhci_bus_state *bus_state;
549 u16 link_state = 0;
550 u16 wake_mask = 0;
551 u16 timeout = 0;
552
553 max_ports = xhci_get_ports(hcd, &port_array);
554 bus_state = &xhci->bus_state[hcd_index(hcd)];
555
556 spin_lock_irqsave(&xhci->lock, flags);
557 switch (typeReq) {
558 case GetHubStatus:
559 /* No power source, over-current reported per port */
560 memset(buf, 0, 4);
561 break;
562 case GetHubDescriptor:
563 /* Check to make sure userspace is asking for the USB 3.0 hub
564 * descriptor for the USB 3.0 roothub. If not, we stall the
565 * endpoint, like external hubs do.
566 */
567 if (hcd->speed == HCD_USB3 &&
568 (wLength < USB_DT_SS_HUB_SIZE ||
569 wValue != (USB_DT_SS_HUB << 8))) {
570 xhci_dbg(xhci, "Wrong hub descriptor type for "
571 "USB 3.0 roothub.\n");
572 goto error;
573 }
574 xhci_hub_descriptor(hcd, xhci,
575 (struct usb_hub_descriptor *) buf);
576 break;
577 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
578 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
579 goto error;
580
581 if (hcd->speed != HCD_USB3)
582 goto error;
583
584 memcpy(buf, &usb_bos_descriptor,
585 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
586 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
587 buf[12] = HCS_U1_LATENCY(temp);
588 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
589
590 spin_unlock_irqrestore(&xhci->lock, flags);
591 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
592 case GetPortStatus:
593 if (!wIndex || wIndex > max_ports)
594 goto error;
595 wIndex--;
596 status = 0;
597 temp = xhci_readl(xhci, port_array[wIndex]);
598 if (temp == 0xffffffff) {
599 retval = -ENODEV;
600 break;
601 }
602 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
603
604 /* wPortChange bits */
605 if (temp & PORT_CSC)
606 status |= USB_PORT_STAT_C_CONNECTION << 16;
607 if (temp & PORT_PEC)
608 status |= USB_PORT_STAT_C_ENABLE << 16;
609 if ((temp & PORT_OCC))
610 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
611 if ((temp & PORT_RC))
612 status |= USB_PORT_STAT_C_RESET << 16;
613 /* USB3.0 only */
614 if (hcd->speed == HCD_USB3) {
615 if ((temp & PORT_PLC))
616 status |= USB_PORT_STAT_C_LINK_STATE << 16;
617 if ((temp & PORT_WRC))
618 status |= USB_PORT_STAT_C_BH_RESET << 16;
619 }
620
621 if (hcd->speed != HCD_USB3) {
622 if ((temp & PORT_PLS_MASK) == XDEV_U3
623 && (temp & PORT_POWER))
624 status |= USB_PORT_STAT_SUSPEND;
625 }
626 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
627 !DEV_SUPERSPEED(temp)) {
628 if ((temp & PORT_RESET) || !(temp & PORT_PE))
629 goto error;
630 if (time_after_eq(jiffies,
631 bus_state->resume_done[wIndex])) {
632 xhci_dbg(xhci, "Resume USB2 port %d\n",
633 wIndex + 1);
634 bus_state->resume_done[wIndex] = 0;
635 clear_bit(wIndex, &bus_state->resuming_ports);
636 xhci_set_link_state(xhci, port_array, wIndex,
637 XDEV_U0);
638 xhci_dbg(xhci, "set port %d resume\n",
639 wIndex + 1);
640 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
641 wIndex + 1);
642 if (!slot_id) {
643 xhci_dbg(xhci, "slot_id is zero\n");
644 goto error;
645 }
646 xhci_ring_device(xhci, slot_id);
647 bus_state->port_c_suspend |= 1 << wIndex;
648 bus_state->suspended_ports &= ~(1 << wIndex);
649 } else {
650 /*
651 * The resume has been signaling for less than
652 * 20ms. Report the port status as SUSPEND,
653 * let the usbcore check port status again
654 * and clear resume signaling later.
655 */
656 status |= USB_PORT_STAT_SUSPEND;
657 }
658 }
659 if ((temp & PORT_PLS_MASK) == XDEV_U0
660 && (temp & PORT_POWER)
661 && (bus_state->suspended_ports & (1 << wIndex))) {
662 bus_state->suspended_ports &= ~(1 << wIndex);
663 if (hcd->speed != HCD_USB3)
664 bus_state->port_c_suspend |= 1 << wIndex;
665 }
666 if (temp & PORT_CONNECT) {
667 status |= USB_PORT_STAT_CONNECTION;
668 status |= xhci_port_speed(temp);
669 }
670 if (temp & PORT_PE)
671 status |= USB_PORT_STAT_ENABLE;
672 if (temp & PORT_OC)
673 status |= USB_PORT_STAT_OVERCURRENT;
674 if (temp & PORT_RESET)
675 status |= USB_PORT_STAT_RESET;
676 if (temp & PORT_POWER) {
677 if (hcd->speed == HCD_USB3)
678 status |= USB_SS_PORT_STAT_POWER;
679 else
680 status |= USB_PORT_STAT_POWER;
681 }
682 /* Update Port Link State for super speed ports*/
683 if (hcd->speed == HCD_USB3) {
684 xhci_hub_report_link_state(&status, temp);
685 /*
686 * Verify if all USB3 Ports Have entered U0 already.
687 * Delete Compliance Mode Timer if so.
688 */
689 xhci_del_comp_mod_timer(xhci, temp, wIndex);
690 }
691 if (bus_state->port_c_suspend & (1 << wIndex))
692 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
693 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
694 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
695 break;
696 case SetPortFeature:
697 if (wValue == USB_PORT_FEAT_LINK_STATE)
698 link_state = (wIndex & 0xff00) >> 3;
699 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
700 wake_mask = wIndex & 0xff00;
701 /* The MSB of wIndex is the U1/U2 timeout */
702 timeout = (wIndex & 0xff00) >> 8;
703 wIndex &= 0xff;
704 if (!wIndex || wIndex > max_ports)
705 goto error;
706 wIndex--;
707 temp = xhci_readl(xhci, port_array[wIndex]);
708 if (temp == 0xffffffff) {
709 retval = -ENODEV;
710 break;
711 }
712 temp = xhci_port_state_to_neutral(temp);
713 /* FIXME: What new port features do we need to support? */
714 switch (wValue) {
715 case USB_PORT_FEAT_SUSPEND:
716 temp = xhci_readl(xhci, port_array[wIndex]);
717 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
718 /* Resume the port to U0 first */
719 xhci_set_link_state(xhci, port_array, wIndex,
720 XDEV_U0);
721 spin_unlock_irqrestore(&xhci->lock, flags);
722 msleep(10);
723 spin_lock_irqsave(&xhci->lock, flags);
724 }
725 /* In spec software should not attempt to suspend
726 * a port unless the port reports that it is in the
727 * enabled (PED = ‘1’,PLS < ‘3’) state.
728 */
729 temp = xhci_readl(xhci, port_array[wIndex]);
730 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
731 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
732 xhci_warn(xhci, "USB core suspending device "
733 "not in U0/U1/U2.\n");
734 goto error;
735 }
736
737 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
738 wIndex + 1);
739 if (!slot_id) {
740 xhci_warn(xhci, "slot_id is zero\n");
741 goto error;
742 }
743 /* unlock to execute stop endpoint commands */
744 spin_unlock_irqrestore(&xhci->lock, flags);
745 xhci_stop_device(xhci, slot_id, 1);
746 spin_lock_irqsave(&xhci->lock, flags);
747
748 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
749
750 spin_unlock_irqrestore(&xhci->lock, flags);
751 msleep(10); /* wait device to enter */
752 spin_lock_irqsave(&xhci->lock, flags);
753
754 temp = xhci_readl(xhci, port_array[wIndex]);
755 bus_state->suspended_ports |= 1 << wIndex;
756 break;
757 case USB_PORT_FEAT_LINK_STATE:
758 temp = xhci_readl(xhci, port_array[wIndex]);
759 /* Software should not attempt to set
760 * port link state above '5' (Rx.Detect) and the port
761 * must be enabled.
762 */
763 if ((temp & PORT_PE) == 0 ||
764 (link_state > USB_SS_PORT_LS_RX_DETECT)) {
765 xhci_warn(xhci, "Cannot set link state.\n");
766 goto error;
767 }
768
769 if (link_state == USB_SS_PORT_LS_U3) {
770 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
771 wIndex + 1);
772 if (slot_id) {
773 /* unlock to execute stop endpoint
774 * commands */
775 spin_unlock_irqrestore(&xhci->lock,
776 flags);
777 xhci_stop_device(xhci, slot_id, 1);
778 spin_lock_irqsave(&xhci->lock, flags);
779 }
780 }
781
782 xhci_set_link_state(xhci, port_array, wIndex,
783 link_state);
784
785 spin_unlock_irqrestore(&xhci->lock, flags);
786 msleep(20); /* wait device to enter */
787 spin_lock_irqsave(&xhci->lock, flags);
788
789 temp = xhci_readl(xhci, port_array[wIndex]);
790 if (link_state == USB_SS_PORT_LS_U3)
791 bus_state->suspended_ports |= 1 << wIndex;
792 break;
793 case USB_PORT_FEAT_POWER:
794 /*
795 * Turn on ports, even if there isn't per-port switching.
796 * HC will report connect events even before this is set.
797 * However, khubd will ignore the roothub events until
798 * the roothub is registered.
799 */
800 xhci_writel(xhci, temp | PORT_POWER,
801 port_array[wIndex]);
802
803 temp = xhci_readl(xhci, port_array[wIndex]);
804 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
805 break;
806 case USB_PORT_FEAT_RESET:
807 temp = (temp | PORT_RESET);
808 xhci_writel(xhci, temp, port_array[wIndex]);
809
810 temp = xhci_readl(xhci, port_array[wIndex]);
811 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
812 break;
813 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
814 xhci_set_remote_wake_mask(xhci, port_array,
815 wIndex, wake_mask);
816 temp = xhci_readl(xhci, port_array[wIndex]);
817 xhci_dbg(xhci, "set port remote wake mask, "
818 "actual port %d status = 0x%x\n",
819 wIndex, temp);
820 break;
821 case USB_PORT_FEAT_BH_PORT_RESET:
822 temp |= PORT_WR;
823 xhci_writel(xhci, temp, port_array[wIndex]);
824
825 temp = xhci_readl(xhci, port_array[wIndex]);
826 break;
827 case USB_PORT_FEAT_U1_TIMEOUT:
828 if (hcd->speed != HCD_USB3)
829 goto error;
830 temp = xhci_readl(xhci, port_array[wIndex] + 1);
831 temp &= ~PORT_U1_TIMEOUT_MASK;
832 temp |= PORT_U1_TIMEOUT(timeout);
833 xhci_writel(xhci, temp, port_array[wIndex] + 1);
834 break;
835 case USB_PORT_FEAT_U2_TIMEOUT:
836 if (hcd->speed != HCD_USB3)
837 goto error;
838 temp = xhci_readl(xhci, port_array[wIndex] + 1);
839 temp &= ~PORT_U2_TIMEOUT_MASK;
840 temp |= PORT_U2_TIMEOUT(timeout);
841 xhci_writel(xhci, temp, port_array[wIndex] + 1);
842 break;
843 default:
844 goto error;
845 }
846 /* unblock any posted writes */
847 temp = xhci_readl(xhci, port_array[wIndex]);
848 break;
849 case ClearPortFeature:
850 if (!wIndex || wIndex > max_ports)
851 goto error;
852 wIndex--;
853 temp = xhci_readl(xhci, port_array[wIndex]);
854 if (temp == 0xffffffff) {
855 retval = -ENODEV;
856 break;
857 }
858 /* FIXME: What new port features do we need to support? */
859 temp = xhci_port_state_to_neutral(temp);
860 switch (wValue) {
861 case USB_PORT_FEAT_SUSPEND:
862 temp = xhci_readl(xhci, port_array[wIndex]);
863 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
864 xhci_dbg(xhci, "PORTSC %04x\n", temp);
865 if (temp & PORT_RESET)
866 goto error;
867 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
868 if ((temp & PORT_PE) == 0)
869 goto error;
870
871 xhci_set_link_state(xhci, port_array, wIndex,
872 XDEV_RESUME);
873 spin_unlock_irqrestore(&xhci->lock, flags);
874 msleep(20);
875 spin_lock_irqsave(&xhci->lock, flags);
876 xhci_set_link_state(xhci, port_array, wIndex,
877 XDEV_U0);
878 }
879 bus_state->port_c_suspend |= 1 << wIndex;
880
881 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
882 wIndex + 1);
883 if (!slot_id) {
884 xhci_dbg(xhci, "slot_id is zero\n");
885 goto error;
886 }
887 xhci_ring_device(xhci, slot_id);
888 break;
889 case USB_PORT_FEAT_C_SUSPEND:
890 bus_state->port_c_suspend &= ~(1 << wIndex);
891 case USB_PORT_FEAT_C_RESET:
892 case USB_PORT_FEAT_C_BH_PORT_RESET:
893 case USB_PORT_FEAT_C_CONNECTION:
894 case USB_PORT_FEAT_C_OVER_CURRENT:
895 case USB_PORT_FEAT_C_ENABLE:
896 case USB_PORT_FEAT_C_PORT_LINK_STATE:
897 xhci_clear_port_change_bit(xhci, wValue, wIndex,
898 port_array[wIndex], temp);
899 break;
900 case USB_PORT_FEAT_ENABLE:
901 xhci_disable_port(hcd, xhci, wIndex,
902 port_array[wIndex], temp);
903 break;
904 default:
905 goto error;
906 }
907 break;
908 default:
909error:
910 /* "stall" on error */
911 retval = -EPIPE;
912 }
913 spin_unlock_irqrestore(&xhci->lock, flags);
914 return retval;
915}
916
917/*
918 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
919 * Ports are 0-indexed from the HCD point of view,
920 * and 1-indexed from the USB core pointer of view.
921 *
922 * Note that the status change bits will be cleared as soon as a port status
923 * change event is generated, so we use the saved status from that event.
924 */
925int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
926{
927 unsigned long flags;
928 u32 temp, status;
929 u32 mask;
930 int i, retval;
931 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
932 int max_ports;
933 __le32 __iomem **port_array;
934 struct xhci_bus_state *bus_state;
935
936 max_ports = xhci_get_ports(hcd, &port_array);
937 bus_state = &xhci->bus_state[hcd_index(hcd)];
938
939 /* Initial status is no changes */
940 retval = (max_ports + 8) / 8;
941 memset(buf, 0, retval);
942
943 /*
944 * Inform the usbcore about resume-in-progress by returning
945 * a non-zero value even if there are no status changes.
946 */
947 status = bus_state->resuming_ports;
948
949 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
950
951 spin_lock_irqsave(&xhci->lock, flags);
952 /* For each port, did anything change? If so, set that bit in buf. */
953 for (i = 0; i < max_ports; i++) {
954 temp = xhci_readl(xhci, port_array[i]);
955 if (temp == 0xffffffff) {
956 retval = -ENODEV;
957 break;
958 }
959 if ((temp & mask) != 0 ||
960 (bus_state->port_c_suspend & 1 << i) ||
961 (bus_state->resume_done[i] && time_after_eq(
962 jiffies, bus_state->resume_done[i]))) {
963 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
964 status = 1;
965 }
966 }
967 spin_unlock_irqrestore(&xhci->lock, flags);
968 return status ? retval : 0;
969}
970
971#ifdef CONFIG_PM
972
973int xhci_bus_suspend(struct usb_hcd *hcd)
974{
975 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
976 int max_ports, port_index;
977 __le32 __iomem **port_array;
978 struct xhci_bus_state *bus_state;
979 unsigned long flags;
980
981 max_ports = xhci_get_ports(hcd, &port_array);
982 bus_state = &xhci->bus_state[hcd_index(hcd)];
983
984 spin_lock_irqsave(&xhci->lock, flags);
985
986 if (hcd->self.root_hub->do_remote_wakeup) {
987 if (bus_state->resuming_ports) {
988 spin_unlock_irqrestore(&xhci->lock, flags);
989 xhci_dbg(xhci, "suspend failed because "
990 "a port is resuming\n");
991 return -EBUSY;
992 }
993 }
994
995 port_index = max_ports;
996 bus_state->bus_suspended = 0;
997 while (port_index--) {
998 /* suspend the port if the port is not suspended */
999 u32 t1, t2;
1000 int slot_id;
1001
1002 t1 = xhci_readl(xhci, port_array[port_index]);
1003 t2 = xhci_port_state_to_neutral(t1);
1004
1005 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1006 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1007 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1008 port_index + 1);
1009 if (slot_id) {
1010 spin_unlock_irqrestore(&xhci->lock, flags);
1011 xhci_stop_device(xhci, slot_id, 1);
1012 spin_lock_irqsave(&xhci->lock, flags);
1013 }
1014 t2 &= ~PORT_PLS_MASK;
1015 t2 |= PORT_LINK_STROBE | XDEV_U3;
1016 set_bit(port_index, &bus_state->bus_suspended);
1017 }
1018 /* USB core sets remote wake mask for USB 3.0 hubs,
1019 * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND
1020 * is enabled, so also enable remote wake here.
1021 */
1022 if (hcd->self.root_hub->do_remote_wakeup) {
1023 if (t1 & PORT_CONNECT) {
1024 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1025 t2 &= ~PORT_WKCONN_E;
1026 } else {
1027 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1028 t2 &= ~PORT_WKDISC_E;
1029 }
1030 } else
1031 t2 &= ~PORT_WAKE_BITS;
1032
1033 t1 = xhci_port_state_to_neutral(t1);
1034 if (t1 != t2)
1035 xhci_writel(xhci, t2, port_array[port_index]);
1036
1037 if (hcd->speed != HCD_USB3) {
1038 /* enable remote wake up for USB 2.0 */
1039 __le32 __iomem *addr;
1040 u32 tmp;
1041
1042 /* Add one to the port status register address to get
1043 * the port power control register address.
1044 */
1045 addr = port_array[port_index] + 1;
1046 tmp = xhci_readl(xhci, addr);
1047 tmp |= PORT_RWE;
1048 xhci_writel(xhci, tmp, addr);
1049 }
1050 }
1051 hcd->state = HC_STATE_SUSPENDED;
1052 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1053 spin_unlock_irqrestore(&xhci->lock, flags);
1054 return 0;
1055}
1056
1057int xhci_bus_resume(struct usb_hcd *hcd)
1058{
1059 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1060 int max_ports, port_index;
1061 __le32 __iomem **port_array;
1062 struct xhci_bus_state *bus_state;
1063 u32 temp;
1064 unsigned long flags;
1065
1066 max_ports = xhci_get_ports(hcd, &port_array);
1067 bus_state = &xhci->bus_state[hcd_index(hcd)];
1068
1069 if (time_before(jiffies, bus_state->next_statechange))
1070 msleep(5);
1071
1072 spin_lock_irqsave(&xhci->lock, flags);
1073 if (!HCD_HW_ACCESSIBLE(hcd)) {
1074 spin_unlock_irqrestore(&xhci->lock, flags);
1075 return -ESHUTDOWN;
1076 }
1077
1078 /* delay the irqs */
1079 temp = xhci_readl(xhci, &xhci->op_regs->command);
1080 temp &= ~CMD_EIE;
1081 xhci_writel(xhci, temp, &xhci->op_regs->command);
1082
1083 port_index = max_ports;
1084 while (port_index--) {
1085 /* Check whether need resume ports. If needed
1086 resume port and disable remote wakeup */
1087 u32 temp;
1088 int slot_id;
1089
1090 temp = xhci_readl(xhci, port_array[port_index]);
1091 if (DEV_SUPERSPEED(temp))
1092 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1093 else
1094 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1095 if (test_bit(port_index, &bus_state->bus_suspended) &&
1096 (temp & PORT_PLS_MASK)) {
1097 if (DEV_SUPERSPEED(temp)) {
1098 xhci_set_link_state(xhci, port_array,
1099 port_index, XDEV_U0);
1100 } else {
1101 xhci_set_link_state(xhci, port_array,
1102 port_index, XDEV_RESUME);
1103
1104 spin_unlock_irqrestore(&xhci->lock, flags);
1105 msleep(20);
1106 spin_lock_irqsave(&xhci->lock, flags);
1107
1108 xhci_set_link_state(xhci, port_array,
1109 port_index, XDEV_U0);
1110 }
1111 /* wait for the port to enter U0 and report port link
1112 * state change.
1113 */
1114 spin_unlock_irqrestore(&xhci->lock, flags);
1115 msleep(20);
1116 spin_lock_irqsave(&xhci->lock, flags);
1117
1118 /* Clear PLC */
1119 xhci_test_and_clear_bit(xhci, port_array, port_index,
1120 PORT_PLC);
1121
1122 slot_id = xhci_find_slot_id_by_port(hcd,
1123 xhci, port_index + 1);
1124 if (slot_id)
1125 xhci_ring_device(xhci, slot_id);
1126 } else
1127 xhci_writel(xhci, temp, port_array[port_index]);
1128
1129 if (hcd->speed != HCD_USB3) {
1130 /* disable remote wake up for USB 2.0 */
1131 __le32 __iomem *addr;
1132 u32 tmp;
1133
1134 /* Add one to the port status register address to get
1135 * the port power control register address.
1136 */
1137 addr = port_array[port_index] + 1;
1138 tmp = xhci_readl(xhci, addr);
1139 tmp &= ~PORT_RWE;
1140 xhci_writel(xhci, tmp, addr);
1141 }
1142 }
1143
1144 (void) xhci_readl(xhci, &xhci->op_regs->command);
1145
1146 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1147 /* re-enable irqs */
1148 temp = xhci_readl(xhci, &xhci->op_regs->command);
1149 temp |= CMD_EIE;
1150 xhci_writel(xhci, temp, &xhci->op_regs->command);
1151 temp = xhci_readl(xhci, &xhci->op_regs->command);
1152
1153 spin_unlock_irqrestore(&xhci->lock, flags);
1154 return 0;
1155}
1156
1157#endif /* CONFIG_PM */