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1/*
2 * Universal Host Controller Interface driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu
13 */
14
15static const __u8 root_hub_hub_des[] =
16{
17 0x09, /* __u8 bLength; */
18 USB_DT_HUB, /* __u8 bDescriptorType; Hub-descriptor */
19 0x02, /* __u8 bNbrPorts; */
20 HUB_CHAR_NO_LPSM | /* __u16 wHubCharacteristics; */
21 HUB_CHAR_INDV_PORT_OCPM, /* (per-port OC, no power switching) */
22 0x00,
23 0x01, /* __u8 bPwrOn2pwrGood; 2ms */
24 0x00, /* __u8 bHubContrCurrent; 0 mA */
25 0x00, /* __u8 DeviceRemovable; *** 7 Ports max */
26 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max */
27};
28
29#define UHCI_RH_MAXCHILD 7
30
31/* must write as zeroes */
32#define WZ_BITS (USBPORTSC_RES2 | USBPORTSC_RES3 | USBPORTSC_RES4)
33
34/* status change bits: nonzero writes will clear */
35#define RWC_BITS (USBPORTSC_OCC | USBPORTSC_PEC | USBPORTSC_CSC)
36
37/* suspend/resume bits: port suspended or port resuming */
38#define SUSPEND_BITS (USBPORTSC_SUSP | USBPORTSC_RD)
39
40/* A port that either is connected or has a changed-bit set will prevent
41 * us from AUTO_STOPPING.
42 */
43static int any_ports_active(struct uhci_hcd *uhci)
44{
45 int port;
46
47 for (port = 0; port < uhci->rh_numports; ++port) {
48 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) &
49 (USBPORTSC_CCS | RWC_BITS)) ||
50 test_bit(port, &uhci->port_c_suspend))
51 return 1;
52 }
53 return 0;
54}
55
56static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf)
57{
58 int port;
59 int mask = RWC_BITS;
60
61 /* Some boards (both VIA and Intel apparently) report bogus
62 * overcurrent indications, causing massive log spam unless
63 * we completely ignore them. This doesn't seem to be a problem
64 * with the chipset so much as with the way it is connected on
65 * the motherboard; if the overcurrent input is left to float
66 * then it may constantly register false positives. */
67 if (ignore_oc)
68 mask &= ~USBPORTSC_OCC;
69
70 *buf = 0;
71 for (port = 0; port < uhci->rh_numports; ++port) {
72 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) ||
73 test_bit(port, &uhci->port_c_suspend))
74 *buf |= (1 << (port + 1));
75 }
76 return !!*buf;
77}
78
79#define CLR_RH_PORTSTAT(x) \
80 status = uhci_readw(uhci, port_addr); \
81 status &= ~(RWC_BITS|WZ_BITS); \
82 status &= ~(x); \
83 status |= RWC_BITS & (x); \
84 uhci_writew(uhci, status, port_addr)
85
86#define SET_RH_PORTSTAT(x) \
87 status = uhci_readw(uhci, port_addr); \
88 status |= (x); \
89 status &= ~(RWC_BITS|WZ_BITS); \
90 uhci_writew(uhci, status, port_addr)
91
92/* UHCI controllers don't automatically stop resume signalling after 20 msec,
93 * so we have to poll and check timeouts in order to take care of it.
94 */
95static void uhci_finish_suspend(struct uhci_hcd *uhci, int port,
96 unsigned long port_addr)
97{
98 int status;
99 int i;
100
101 if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) {
102 CLR_RH_PORTSTAT(SUSPEND_BITS);
103 if (test_bit(port, &uhci->resuming_ports))
104 set_bit(port, &uhci->port_c_suspend);
105
106 /* The controller won't actually turn off the RD bit until
107 * it has had a chance to send a low-speed EOP sequence,
108 * which is supposed to take 3 bit times (= 2 microseconds).
109 * Experiments show that some controllers take longer, so
110 * we'll poll for completion. */
111 for (i = 0; i < 10; ++i) {
112 if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS))
113 break;
114 udelay(1);
115 }
116 }
117 clear_bit(port, &uhci->resuming_ports);
118 usb_hcd_end_port_resume(&uhci_to_hcd(uhci)->self, port);
119}
120
121/* Wait for the UHCI controller in HP's iLO2 server management chip.
122 * It can take up to 250 us to finish a reset and set the CSC bit.
123 */
124static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr)
125{
126 int i;
127
128 for (i = 10; i < 250; i += 10) {
129 if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC)
130 return;
131 udelay(10);
132 }
133 /* Log a warning? */
134}
135
136static void uhci_check_ports(struct uhci_hcd *uhci)
137{
138 unsigned int port;
139 unsigned long port_addr;
140 int status;
141
142 for (port = 0; port < uhci->rh_numports; ++port) {
143 port_addr = USBPORTSC1 + 2 * port;
144 status = uhci_readw(uhci, port_addr);
145 if (unlikely(status & USBPORTSC_PR)) {
146 if (time_after_eq(jiffies, uhci->ports_timeout)) {
147 CLR_RH_PORTSTAT(USBPORTSC_PR);
148 udelay(10);
149
150 /* HP's server management chip requires
151 * a longer delay. */
152 if (uhci->wait_for_hp)
153 wait_for_HP(uhci, port_addr);
154
155 /* If the port was enabled before, turning
156 * reset on caused a port enable change.
157 * Turning reset off causes a port connect
158 * status change. Clear these changes. */
159 CLR_RH_PORTSTAT(USBPORTSC_CSC | USBPORTSC_PEC);
160 SET_RH_PORTSTAT(USBPORTSC_PE);
161 }
162 }
163 if (unlikely(status & USBPORTSC_RD)) {
164 if (!test_bit(port, &uhci->resuming_ports)) {
165
166 /* Port received a wakeup request */
167 set_bit(port, &uhci->resuming_ports);
168 uhci->ports_timeout = jiffies +
169 msecs_to_jiffies(USB_RESUME_TIMEOUT);
170 usb_hcd_start_port_resume(
171 &uhci_to_hcd(uhci)->self, port);
172
173 /* Make sure we see the port again
174 * after the resuming period is over. */
175 mod_timer(&uhci_to_hcd(uhci)->rh_timer,
176 uhci->ports_timeout);
177 } else if (time_after_eq(jiffies,
178 uhci->ports_timeout)) {
179 uhci_finish_suspend(uhci, port, port_addr);
180 }
181 }
182 }
183}
184
185static int uhci_hub_status_data(struct usb_hcd *hcd, char *buf)
186{
187 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
188 unsigned long flags;
189 int status = 0;
190
191 spin_lock_irqsave(&uhci->lock, flags);
192
193 uhci_scan_schedule(uhci);
194 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
195 goto done;
196 uhci_check_ports(uhci);
197
198 status = get_hub_status_data(uhci, buf);
199
200 switch (uhci->rh_state) {
201 case UHCI_RH_SUSPENDED:
202 /* if port change, ask to be resumed */
203 if (status || uhci->resuming_ports) {
204 status = 1;
205 usb_hcd_resume_root_hub(hcd);
206 }
207 break;
208
209 case UHCI_RH_AUTO_STOPPED:
210 /* if port change, auto start */
211 if (status)
212 wakeup_rh(uhci);
213 break;
214
215 case UHCI_RH_RUNNING:
216 /* are any devices attached? */
217 if (!any_ports_active(uhci)) {
218 uhci->rh_state = UHCI_RH_RUNNING_NODEVS;
219 uhci->auto_stop_time = jiffies + HZ;
220 }
221 break;
222
223 case UHCI_RH_RUNNING_NODEVS:
224 /* auto-stop if nothing connected for 1 second */
225 if (any_ports_active(uhci))
226 uhci->rh_state = UHCI_RH_RUNNING;
227 else if (time_after_eq(jiffies, uhci->auto_stop_time) &&
228 !uhci->wait_for_hp)
229 suspend_rh(uhci, UHCI_RH_AUTO_STOPPED);
230 break;
231
232 default:
233 break;
234 }
235
236done:
237 spin_unlock_irqrestore(&uhci->lock, flags);
238 return status;
239}
240
241/* size of returned buffer is part of USB spec */
242static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
243 u16 wIndex, char *buf, u16 wLength)
244{
245 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
246 int status, lstatus, retval = 0;
247 unsigned int port = wIndex - 1;
248 unsigned long port_addr = USBPORTSC1 + 2 * port;
249 u16 wPortChange, wPortStatus;
250 unsigned long flags;
251
252 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
253 return -ETIMEDOUT;
254
255 spin_lock_irqsave(&uhci->lock, flags);
256 switch (typeReq) {
257
258 case GetHubStatus:
259 *(__le32 *)buf = cpu_to_le32(0);
260 retval = 4; /* hub power */
261 break;
262 case GetPortStatus:
263 if (port >= uhci->rh_numports)
264 goto err;
265
266 uhci_check_ports(uhci);
267 status = uhci_readw(uhci, port_addr);
268
269 /* Intel controllers report the OverCurrent bit active on.
270 * VIA controllers report it active off, so we'll adjust the
271 * bit value. (It's not standardized in the UHCI spec.)
272 */
273 if (uhci->oc_low)
274 status ^= USBPORTSC_OC;
275
276 /* UHCI doesn't support C_RESET (always false) */
277 wPortChange = lstatus = 0;
278 if (status & USBPORTSC_CSC)
279 wPortChange |= USB_PORT_STAT_C_CONNECTION;
280 if (status & USBPORTSC_PEC)
281 wPortChange |= USB_PORT_STAT_C_ENABLE;
282 if ((status & USBPORTSC_OCC) && !ignore_oc)
283 wPortChange |= USB_PORT_STAT_C_OVERCURRENT;
284
285 if (test_bit(port, &uhci->port_c_suspend)) {
286 wPortChange |= USB_PORT_STAT_C_SUSPEND;
287 lstatus |= 1;
288 }
289 if (test_bit(port, &uhci->resuming_ports))
290 lstatus |= 4;
291
292 /* UHCI has no power switching (always on) */
293 wPortStatus = USB_PORT_STAT_POWER;
294 if (status & USBPORTSC_CCS)
295 wPortStatus |= USB_PORT_STAT_CONNECTION;
296 if (status & USBPORTSC_PE) {
297 wPortStatus |= USB_PORT_STAT_ENABLE;
298 if (status & SUSPEND_BITS)
299 wPortStatus |= USB_PORT_STAT_SUSPEND;
300 }
301 if (status & USBPORTSC_OC)
302 wPortStatus |= USB_PORT_STAT_OVERCURRENT;
303 if (status & USBPORTSC_PR)
304 wPortStatus |= USB_PORT_STAT_RESET;
305 if (status & USBPORTSC_LSDA)
306 wPortStatus |= USB_PORT_STAT_LOW_SPEED;
307
308 if (wPortChange)
309 dev_dbg(uhci_dev(uhci), "port %d portsc %04x,%02x\n",
310 wIndex, status, lstatus);
311
312 *(__le16 *)buf = cpu_to_le16(wPortStatus);
313 *(__le16 *)(buf + 2) = cpu_to_le16(wPortChange);
314 retval = 4;
315 break;
316 case SetHubFeature: /* We don't implement these */
317 case ClearHubFeature:
318 switch (wValue) {
319 case C_HUB_OVER_CURRENT:
320 case C_HUB_LOCAL_POWER:
321 break;
322 default:
323 goto err;
324 }
325 break;
326 case SetPortFeature:
327 if (port >= uhci->rh_numports)
328 goto err;
329
330 switch (wValue) {
331 case USB_PORT_FEAT_SUSPEND:
332 SET_RH_PORTSTAT(USBPORTSC_SUSP);
333 break;
334 case USB_PORT_FEAT_RESET:
335 SET_RH_PORTSTAT(USBPORTSC_PR);
336
337 /* Reset terminates Resume signalling */
338 uhci_finish_suspend(uhci, port, port_addr);
339
340 /* USB v2.0 7.1.7.5 */
341 uhci->ports_timeout = jiffies +
342 msecs_to_jiffies(USB_RESUME_TIMEOUT);
343 break;
344 case USB_PORT_FEAT_POWER:
345 /* UHCI has no power switching */
346 break;
347 default:
348 goto err;
349 }
350 break;
351 case ClearPortFeature:
352 if (port >= uhci->rh_numports)
353 goto err;
354
355 switch (wValue) {
356 case USB_PORT_FEAT_ENABLE:
357 CLR_RH_PORTSTAT(USBPORTSC_PE);
358
359 /* Disable terminates Resume signalling */
360 uhci_finish_suspend(uhci, port, port_addr);
361 break;
362 case USB_PORT_FEAT_C_ENABLE:
363 CLR_RH_PORTSTAT(USBPORTSC_PEC);
364 break;
365 case USB_PORT_FEAT_SUSPEND:
366 if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) {
367
368 /* Make certain the port isn't suspended */
369 uhci_finish_suspend(uhci, port, port_addr);
370 } else if (!test_and_set_bit(port,
371 &uhci->resuming_ports)) {
372 SET_RH_PORTSTAT(USBPORTSC_RD);
373
374 /* The controller won't allow RD to be set
375 * if the port is disabled. When this happens
376 * just skip the Resume signalling.
377 */
378 if (!(uhci_readw(uhci, port_addr) &
379 USBPORTSC_RD))
380 uhci_finish_suspend(uhci, port,
381 port_addr);
382 else
383 /* USB v2.0 7.1.7.7 */
384 uhci->ports_timeout = jiffies +
385 msecs_to_jiffies(20);
386 }
387 break;
388 case USB_PORT_FEAT_C_SUSPEND:
389 clear_bit(port, &uhci->port_c_suspend);
390 break;
391 case USB_PORT_FEAT_POWER:
392 /* UHCI has no power switching */
393 goto err;
394 case USB_PORT_FEAT_C_CONNECTION:
395 CLR_RH_PORTSTAT(USBPORTSC_CSC);
396 break;
397 case USB_PORT_FEAT_C_OVER_CURRENT:
398 CLR_RH_PORTSTAT(USBPORTSC_OCC);
399 break;
400 case USB_PORT_FEAT_C_RESET:
401 /* this driver won't report these */
402 break;
403 default:
404 goto err;
405 }
406 break;
407 case GetHubDescriptor:
408 retval = min_t(unsigned int, sizeof(root_hub_hub_des), wLength);
409 memcpy(buf, root_hub_hub_des, retval);
410 if (retval > 2)
411 buf[2] = uhci->rh_numports;
412 break;
413 default:
414err:
415 retval = -EPIPE;
416 }
417 spin_unlock_irqrestore(&uhci->lock, flags);
418
419 return retval;
420}
1/*
2 * Universal Host Controller Interface driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu
13 */
14
15static const __u8 root_hub_hub_des[] =
16{
17 0x09, /* __u8 bLength; */
18 0x29, /* __u8 bDescriptorType; Hub-descriptor */
19 0x02, /* __u8 bNbrPorts; */
20 0x0a, /* __u16 wHubCharacteristics; */
21 0x00, /* (per-port OC, no power switching) */
22 0x01, /* __u8 bPwrOn2pwrGood; 2ms */
23 0x00, /* __u8 bHubContrCurrent; 0 mA */
24 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */
25 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */
26};
27
28#define UHCI_RH_MAXCHILD 7
29
30/* must write as zeroes */
31#define WZ_BITS (USBPORTSC_RES2 | USBPORTSC_RES3 | USBPORTSC_RES4)
32
33/* status change bits: nonzero writes will clear */
34#define RWC_BITS (USBPORTSC_OCC | USBPORTSC_PEC | USBPORTSC_CSC)
35
36/* suspend/resume bits: port suspended or port resuming */
37#define SUSPEND_BITS (USBPORTSC_SUSP | USBPORTSC_RD)
38
39/* A port that either is connected or has a changed-bit set will prevent
40 * us from AUTO_STOPPING.
41 */
42static int any_ports_active(struct uhci_hcd *uhci)
43{
44 int port;
45
46 for (port = 0; port < uhci->rh_numports; ++port) {
47 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) &
48 (USBPORTSC_CCS | RWC_BITS)) ||
49 test_bit(port, &uhci->port_c_suspend))
50 return 1;
51 }
52 return 0;
53}
54
55static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf)
56{
57 int port;
58 int mask = RWC_BITS;
59
60 /* Some boards (both VIA and Intel apparently) report bogus
61 * overcurrent indications, causing massive log spam unless
62 * we completely ignore them. This doesn't seem to be a problem
63 * with the chipset so much as with the way it is connected on
64 * the motherboard; if the overcurrent input is left to float
65 * then it may constantly register false positives. */
66 if (ignore_oc)
67 mask &= ~USBPORTSC_OCC;
68
69 *buf = 0;
70 for (port = 0; port < uhci->rh_numports; ++port) {
71 if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) ||
72 test_bit(port, &uhci->port_c_suspend))
73 *buf |= (1 << (port + 1));
74 }
75 return !!*buf;
76}
77
78#define OK(x) len = (x); break
79
80#define CLR_RH_PORTSTAT(x) \
81 status = uhci_readw(uhci, port_addr); \
82 status &= ~(RWC_BITS|WZ_BITS); \
83 status &= ~(x); \
84 status |= RWC_BITS & (x); \
85 uhci_writew(uhci, status, port_addr)
86
87#define SET_RH_PORTSTAT(x) \
88 status = uhci_readw(uhci, port_addr); \
89 status |= (x); \
90 status &= ~(RWC_BITS|WZ_BITS); \
91 uhci_writew(uhci, status, port_addr)
92
93/* UHCI controllers don't automatically stop resume signalling after 20 msec,
94 * so we have to poll and check timeouts in order to take care of it.
95 */
96static void uhci_finish_suspend(struct uhci_hcd *uhci, int port,
97 unsigned long port_addr)
98{
99 int status;
100 int i;
101
102 if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) {
103 CLR_RH_PORTSTAT(SUSPEND_BITS);
104 if (test_bit(port, &uhci->resuming_ports))
105 set_bit(port, &uhci->port_c_suspend);
106
107 /* The controller won't actually turn off the RD bit until
108 * it has had a chance to send a low-speed EOP sequence,
109 * which is supposed to take 3 bit times (= 2 microseconds).
110 * Experiments show that some controllers take longer, so
111 * we'll poll for completion. */
112 for (i = 0; i < 10; ++i) {
113 if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS))
114 break;
115 udelay(1);
116 }
117 }
118 clear_bit(port, &uhci->resuming_ports);
119}
120
121/* Wait for the UHCI controller in HP's iLO2 server management chip.
122 * It can take up to 250 us to finish a reset and set the CSC bit.
123 */
124static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr)
125{
126 int i;
127
128 for (i = 10; i < 250; i += 10) {
129 if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC)
130 return;
131 udelay(10);
132 }
133 /* Log a warning? */
134}
135
136static void uhci_check_ports(struct uhci_hcd *uhci)
137{
138 unsigned int port;
139 unsigned long port_addr;
140 int status;
141
142 for (port = 0; port < uhci->rh_numports; ++port) {
143 port_addr = USBPORTSC1 + 2 * port;
144 status = uhci_readw(uhci, port_addr);
145 if (unlikely(status & USBPORTSC_PR)) {
146 if (time_after_eq(jiffies, uhci->ports_timeout)) {
147 CLR_RH_PORTSTAT(USBPORTSC_PR);
148 udelay(10);
149
150 /* HP's server management chip requires
151 * a longer delay. */
152 if (uhci->wait_for_hp)
153 wait_for_HP(uhci, port_addr);
154
155 /* If the port was enabled before, turning
156 * reset on caused a port enable change.
157 * Turning reset off causes a port connect
158 * status change. Clear these changes. */
159 CLR_RH_PORTSTAT(USBPORTSC_CSC | USBPORTSC_PEC);
160 SET_RH_PORTSTAT(USBPORTSC_PE);
161 }
162 }
163 if (unlikely(status & USBPORTSC_RD)) {
164 if (!test_bit(port, &uhci->resuming_ports)) {
165
166 /* Port received a wakeup request */
167 set_bit(port, &uhci->resuming_ports);
168 uhci->ports_timeout = jiffies +
169 msecs_to_jiffies(25);
170
171 /* Make sure we see the port again
172 * after the resuming period is over. */
173 mod_timer(&uhci_to_hcd(uhci)->rh_timer,
174 uhci->ports_timeout);
175 } else if (time_after_eq(jiffies,
176 uhci->ports_timeout)) {
177 uhci_finish_suspend(uhci, port, port_addr);
178 }
179 }
180 }
181}
182
183static int uhci_hub_status_data(struct usb_hcd *hcd, char *buf)
184{
185 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
186 unsigned long flags;
187 int status = 0;
188
189 spin_lock_irqsave(&uhci->lock, flags);
190
191 uhci_scan_schedule(uhci);
192 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
193 goto done;
194 uhci_check_ports(uhci);
195
196 status = get_hub_status_data(uhci, buf);
197
198 switch (uhci->rh_state) {
199 case UHCI_RH_SUSPENDED:
200 /* if port change, ask to be resumed */
201 if (status || uhci->resuming_ports) {
202 status = 1;
203 usb_hcd_resume_root_hub(hcd);
204 }
205 break;
206
207 case UHCI_RH_AUTO_STOPPED:
208 /* if port change, auto start */
209 if (status)
210 wakeup_rh(uhci);
211 break;
212
213 case UHCI_RH_RUNNING:
214 /* are any devices attached? */
215 if (!any_ports_active(uhci)) {
216 uhci->rh_state = UHCI_RH_RUNNING_NODEVS;
217 uhci->auto_stop_time = jiffies + HZ;
218 }
219 break;
220
221 case UHCI_RH_RUNNING_NODEVS:
222 /* auto-stop if nothing connected for 1 second */
223 if (any_ports_active(uhci))
224 uhci->rh_state = UHCI_RH_RUNNING;
225 else if (time_after_eq(jiffies, uhci->auto_stop_time))
226 suspend_rh(uhci, UHCI_RH_AUTO_STOPPED);
227 break;
228
229 default:
230 break;
231 }
232
233done:
234 spin_unlock_irqrestore(&uhci->lock, flags);
235 return status;
236}
237
238/* size of returned buffer is part of USB spec */
239static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
240 u16 wIndex, char *buf, u16 wLength)
241{
242 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
243 int status, lstatus, retval = 0, len = 0;
244 unsigned int port = wIndex - 1;
245 unsigned long port_addr = USBPORTSC1 + 2 * port;
246 u16 wPortChange, wPortStatus;
247 unsigned long flags;
248
249 if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
250 return -ETIMEDOUT;
251
252 spin_lock_irqsave(&uhci->lock, flags);
253 switch (typeReq) {
254
255 case GetHubStatus:
256 *(__le32 *)buf = cpu_to_le32(0);
257 OK(4); /* hub power */
258 case GetPortStatus:
259 if (port >= uhci->rh_numports)
260 goto err;
261
262 uhci_check_ports(uhci);
263 status = uhci_readw(uhci, port_addr);
264
265 /* Intel controllers report the OverCurrent bit active on.
266 * VIA controllers report it active off, so we'll adjust the
267 * bit value. (It's not standardized in the UHCI spec.)
268 */
269 if (uhci->oc_low)
270 status ^= USBPORTSC_OC;
271
272 /* UHCI doesn't support C_RESET (always false) */
273 wPortChange = lstatus = 0;
274 if (status & USBPORTSC_CSC)
275 wPortChange |= USB_PORT_STAT_C_CONNECTION;
276 if (status & USBPORTSC_PEC)
277 wPortChange |= USB_PORT_STAT_C_ENABLE;
278 if ((status & USBPORTSC_OCC) && !ignore_oc)
279 wPortChange |= USB_PORT_STAT_C_OVERCURRENT;
280
281 if (test_bit(port, &uhci->port_c_suspend)) {
282 wPortChange |= USB_PORT_STAT_C_SUSPEND;
283 lstatus |= 1;
284 }
285 if (test_bit(port, &uhci->resuming_ports))
286 lstatus |= 4;
287
288 /* UHCI has no power switching (always on) */
289 wPortStatus = USB_PORT_STAT_POWER;
290 if (status & USBPORTSC_CCS)
291 wPortStatus |= USB_PORT_STAT_CONNECTION;
292 if (status & USBPORTSC_PE) {
293 wPortStatus |= USB_PORT_STAT_ENABLE;
294 if (status & SUSPEND_BITS)
295 wPortStatus |= USB_PORT_STAT_SUSPEND;
296 }
297 if (status & USBPORTSC_OC)
298 wPortStatus |= USB_PORT_STAT_OVERCURRENT;
299 if (status & USBPORTSC_PR)
300 wPortStatus |= USB_PORT_STAT_RESET;
301 if (status & USBPORTSC_LSDA)
302 wPortStatus |= USB_PORT_STAT_LOW_SPEED;
303
304 if (wPortChange)
305 dev_dbg(uhci_dev(uhci), "port %d portsc %04x,%02x\n",
306 wIndex, status, lstatus);
307
308 *(__le16 *)buf = cpu_to_le16(wPortStatus);
309 *(__le16 *)(buf + 2) = cpu_to_le16(wPortChange);
310 OK(4);
311 case SetHubFeature: /* We don't implement these */
312 case ClearHubFeature:
313 switch (wValue) {
314 case C_HUB_OVER_CURRENT:
315 case C_HUB_LOCAL_POWER:
316 OK(0);
317 default:
318 goto err;
319 }
320 break;
321 case SetPortFeature:
322 if (port >= uhci->rh_numports)
323 goto err;
324
325 switch (wValue) {
326 case USB_PORT_FEAT_SUSPEND:
327 SET_RH_PORTSTAT(USBPORTSC_SUSP);
328 OK(0);
329 case USB_PORT_FEAT_RESET:
330 SET_RH_PORTSTAT(USBPORTSC_PR);
331
332 /* Reset terminates Resume signalling */
333 uhci_finish_suspend(uhci, port, port_addr);
334
335 /* USB v2.0 7.1.7.5 */
336 uhci->ports_timeout = jiffies + msecs_to_jiffies(50);
337 OK(0);
338 case USB_PORT_FEAT_POWER:
339 /* UHCI has no power switching */
340 OK(0);
341 default:
342 goto err;
343 }
344 break;
345 case ClearPortFeature:
346 if (port >= uhci->rh_numports)
347 goto err;
348
349 switch (wValue) {
350 case USB_PORT_FEAT_ENABLE:
351 CLR_RH_PORTSTAT(USBPORTSC_PE);
352
353 /* Disable terminates Resume signalling */
354 uhci_finish_suspend(uhci, port, port_addr);
355 OK(0);
356 case USB_PORT_FEAT_C_ENABLE:
357 CLR_RH_PORTSTAT(USBPORTSC_PEC);
358 OK(0);
359 case USB_PORT_FEAT_SUSPEND:
360 if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) {
361
362 /* Make certain the port isn't suspended */
363 uhci_finish_suspend(uhci, port, port_addr);
364 } else if (!test_and_set_bit(port,
365 &uhci->resuming_ports)) {
366 SET_RH_PORTSTAT(USBPORTSC_RD);
367
368 /* The controller won't allow RD to be set
369 * if the port is disabled. When this happens
370 * just skip the Resume signalling.
371 */
372 if (!(uhci_readw(uhci, port_addr) &
373 USBPORTSC_RD))
374 uhci_finish_suspend(uhci, port,
375 port_addr);
376 else
377 /* USB v2.0 7.1.7.7 */
378 uhci->ports_timeout = jiffies +
379 msecs_to_jiffies(20);
380 }
381 OK(0);
382 case USB_PORT_FEAT_C_SUSPEND:
383 clear_bit(port, &uhci->port_c_suspend);
384 OK(0);
385 case USB_PORT_FEAT_POWER:
386 /* UHCI has no power switching */
387 goto err;
388 case USB_PORT_FEAT_C_CONNECTION:
389 CLR_RH_PORTSTAT(USBPORTSC_CSC);
390 OK(0);
391 case USB_PORT_FEAT_C_OVER_CURRENT:
392 CLR_RH_PORTSTAT(USBPORTSC_OCC);
393 OK(0);
394 case USB_PORT_FEAT_C_RESET:
395 /* this driver won't report these */
396 OK(0);
397 default:
398 goto err;
399 }
400 break;
401 case GetHubDescriptor:
402 len = min_t(unsigned int, sizeof(root_hub_hub_des), wLength);
403 memcpy(buf, root_hub_hub_des, len);
404 if (len > 2)
405 buf[2] = uhci->rh_numports;
406 OK(len);
407 default:
408err:
409 retval = -EPIPE;
410 }
411 spin_unlock_irqrestore(&uhci->lock, flags);
412
413 return retval;
414}