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1/*
2 * linux/drivers/mmc/host/pxa.c - PXA MMCI driver
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This hardware is really sick:
11 * - No way to clear interrupts.
12 * - Have to turn off the clock whenever we touch the device.
13 * - Doesn't tell you how many data blocks were transferred.
14 * Yuck!
15 *
16 * 1 and 3 byte data transfers not supported
17 * max block length up to 1023
18 */
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/platform_device.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
27#include <linux/dma/pxa-dma.h>
28#include <linux/clk.h>
29#include <linux/err.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/slot-gpio.h>
32#include <linux/io.h>
33#include <linux/regulator/consumer.h>
34#include <linux/gpio.h>
35#include <linux/gfp.h>
36#include <linux/of.h>
37#include <linux/of_gpio.h>
38#include <linux/of_device.h>
39
40#include <asm/sizes.h>
41
42#include <mach/hardware.h>
43#include <linux/platform_data/mmc-pxamci.h>
44
45#include "pxamci.h"
46
47#define DRIVER_NAME "pxa2xx-mci"
48
49#define NR_SG 1
50#define CLKRT_OFF (~0)
51
52#define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \
53 || cpu_is_pxa935())
54
55struct pxamci_host {
56 struct mmc_host *mmc;
57 spinlock_t lock;
58 struct resource *res;
59 void __iomem *base;
60 struct clk *clk;
61 unsigned long clkrate;
62 int irq;
63 unsigned int clkrt;
64 unsigned int cmdat;
65 unsigned int imask;
66 unsigned int power_mode;
67 struct pxamci_platform_data *pdata;
68
69 struct mmc_request *mrq;
70 struct mmc_command *cmd;
71 struct mmc_data *data;
72
73 struct dma_chan *dma_chan_rx;
74 struct dma_chan *dma_chan_tx;
75 dma_cookie_t dma_cookie;
76 dma_addr_t sg_dma;
77 unsigned int dma_len;
78
79 unsigned int dma_dir;
80 unsigned int dma_drcmrrx;
81 unsigned int dma_drcmrtx;
82
83 struct regulator *vcc;
84};
85
86static inline void pxamci_init_ocr(struct pxamci_host *host)
87{
88#ifdef CONFIG_REGULATOR
89 host->vcc = devm_regulator_get_optional(mmc_dev(host->mmc), "vmmc");
90
91 if (IS_ERR(host->vcc))
92 host->vcc = NULL;
93 else {
94 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
95 if (host->pdata && host->pdata->ocr_mask)
96 dev_warn(mmc_dev(host->mmc),
97 "ocr_mask/setpower will not be used\n");
98 }
99#endif
100 if (host->vcc == NULL) {
101 /* fall-back to platform data */
102 host->mmc->ocr_avail = host->pdata ?
103 host->pdata->ocr_mask :
104 MMC_VDD_32_33 | MMC_VDD_33_34;
105 }
106}
107
108static inline int pxamci_set_power(struct pxamci_host *host,
109 unsigned char power_mode,
110 unsigned int vdd)
111{
112 int on;
113
114 if (host->vcc) {
115 int ret;
116
117 if (power_mode == MMC_POWER_UP) {
118 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
119 if (ret)
120 return ret;
121 } else if (power_mode == MMC_POWER_OFF) {
122 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
123 if (ret)
124 return ret;
125 }
126 }
127 if (!host->vcc && host->pdata &&
128 gpio_is_valid(host->pdata->gpio_power)) {
129 on = ((1 << vdd) & host->pdata->ocr_mask);
130 gpio_set_value(host->pdata->gpio_power,
131 !!on ^ host->pdata->gpio_power_invert);
132 }
133 if (!host->vcc && host->pdata && host->pdata->setpower)
134 return host->pdata->setpower(mmc_dev(host->mmc), vdd);
135
136 return 0;
137}
138
139static void pxamci_stop_clock(struct pxamci_host *host)
140{
141 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
142 unsigned long timeout = 10000;
143 unsigned int v;
144
145 writel(STOP_CLOCK, host->base + MMC_STRPCL);
146
147 do {
148 v = readl(host->base + MMC_STAT);
149 if (!(v & STAT_CLK_EN))
150 break;
151 udelay(1);
152 } while (timeout--);
153
154 if (v & STAT_CLK_EN)
155 dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
156 }
157}
158
159static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
160{
161 unsigned long flags;
162
163 spin_lock_irqsave(&host->lock, flags);
164 host->imask &= ~mask;
165 writel(host->imask, host->base + MMC_I_MASK);
166 spin_unlock_irqrestore(&host->lock, flags);
167}
168
169static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
170{
171 unsigned long flags;
172
173 spin_lock_irqsave(&host->lock, flags);
174 host->imask |= mask;
175 writel(host->imask, host->base + MMC_I_MASK);
176 spin_unlock_irqrestore(&host->lock, flags);
177}
178
179static void pxamci_dma_irq(void *param);
180
181static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
182{
183 struct dma_async_tx_descriptor *tx;
184 enum dma_data_direction direction;
185 struct dma_slave_config config;
186 struct dma_chan *chan;
187 unsigned int nob = data->blocks;
188 unsigned long long clks;
189 unsigned int timeout;
190 int ret;
191
192 host->data = data;
193
194 writel(nob, host->base + MMC_NOB);
195 writel(data->blksz, host->base + MMC_BLKLEN);
196
197 clks = (unsigned long long)data->timeout_ns * host->clkrate;
198 do_div(clks, 1000000000UL);
199 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
200 writel((timeout + 255) / 256, host->base + MMC_RDTO);
201
202 memset(&config, 0, sizeof(config));
203 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
204 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
205 config.src_addr = host->res->start + MMC_RXFIFO;
206 config.dst_addr = host->res->start + MMC_TXFIFO;
207 config.src_maxburst = 32;
208 config.dst_maxburst = 32;
209
210 if (data->flags & MMC_DATA_READ) {
211 host->dma_dir = DMA_FROM_DEVICE;
212 direction = DMA_DEV_TO_MEM;
213 chan = host->dma_chan_rx;
214 } else {
215 host->dma_dir = DMA_TO_DEVICE;
216 direction = DMA_MEM_TO_DEV;
217 chan = host->dma_chan_tx;
218 }
219
220 config.direction = direction;
221
222 ret = dmaengine_slave_config(chan, &config);
223 if (ret < 0) {
224 dev_err(mmc_dev(host->mmc), "dma slave config failed\n");
225 return;
226 }
227
228 host->dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
229 host->dma_dir);
230
231 tx = dmaengine_prep_slave_sg(chan, data->sg, host->dma_len, direction,
232 DMA_PREP_INTERRUPT);
233 if (!tx) {
234 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
235 return;
236 }
237
238 if (!(data->flags & MMC_DATA_READ)) {
239 tx->callback = pxamci_dma_irq;
240 tx->callback_param = host;
241 }
242
243 host->dma_cookie = dmaengine_submit(tx);
244
245 /*
246 * workaround for erratum #91:
247 * only start DMA now if we are doing a read,
248 * otherwise we wait until CMD/RESP has finished
249 * before starting DMA.
250 */
251 if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
252 dma_async_issue_pending(chan);
253}
254
255static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
256{
257 WARN_ON(host->cmd != NULL);
258 host->cmd = cmd;
259
260 if (cmd->flags & MMC_RSP_BUSY)
261 cmdat |= CMDAT_BUSY;
262
263#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
264 switch (RSP_TYPE(mmc_resp_type(cmd))) {
265 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
266 cmdat |= CMDAT_RESP_SHORT;
267 break;
268 case RSP_TYPE(MMC_RSP_R3):
269 cmdat |= CMDAT_RESP_R3;
270 break;
271 case RSP_TYPE(MMC_RSP_R2):
272 cmdat |= CMDAT_RESP_R2;
273 break;
274 default:
275 break;
276 }
277
278 writel(cmd->opcode, host->base + MMC_CMD);
279 writel(cmd->arg >> 16, host->base + MMC_ARGH);
280 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
281 writel(cmdat, host->base + MMC_CMDAT);
282 writel(host->clkrt, host->base + MMC_CLKRT);
283
284 writel(START_CLOCK, host->base + MMC_STRPCL);
285
286 pxamci_enable_irq(host, END_CMD_RES);
287}
288
289static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
290{
291 host->mrq = NULL;
292 host->cmd = NULL;
293 host->data = NULL;
294 mmc_request_done(host->mmc, mrq);
295}
296
297static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
298{
299 struct mmc_command *cmd = host->cmd;
300 int i;
301 u32 v;
302
303 if (!cmd)
304 return 0;
305
306 host->cmd = NULL;
307
308 /*
309 * Did I mention this is Sick. We always need to
310 * discard the upper 8 bits of the first 16-bit word.
311 */
312 v = readl(host->base + MMC_RES) & 0xffff;
313 for (i = 0; i < 4; i++) {
314 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
315 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
316 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
317 v = w2;
318 }
319
320 if (stat & STAT_TIME_OUT_RESPONSE) {
321 cmd->error = -ETIMEDOUT;
322 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
323 /*
324 * workaround for erratum #42:
325 * Intel PXA27x Family Processor Specification Update Rev 001
326 * A bogus CRC error can appear if the msb of a 136 bit
327 * response is a one.
328 */
329 if (cpu_is_pxa27x() &&
330 (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000))
331 pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
332 else
333 cmd->error = -EILSEQ;
334 }
335
336 pxamci_disable_irq(host, END_CMD_RES);
337 if (host->data && !cmd->error) {
338 pxamci_enable_irq(host, DATA_TRAN_DONE);
339 /*
340 * workaround for erratum #91, if doing write
341 * enable DMA late
342 */
343 if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
344 dma_async_issue_pending(host->dma_chan_tx);
345 } else {
346 pxamci_finish_request(host, host->mrq);
347 }
348
349 return 1;
350}
351
352static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
353{
354 struct mmc_data *data = host->data;
355 struct dma_chan *chan;
356
357 if (!data)
358 return 0;
359
360 if (data->flags & MMC_DATA_READ)
361 chan = host->dma_chan_rx;
362 else
363 chan = host->dma_chan_tx;
364 dma_unmap_sg(chan->device->dev,
365 data->sg, data->sg_len, host->dma_dir);
366
367 if (stat & STAT_READ_TIME_OUT)
368 data->error = -ETIMEDOUT;
369 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
370 data->error = -EILSEQ;
371
372 /*
373 * There appears to be a hardware design bug here. There seems to
374 * be no way to find out how much data was transferred to the card.
375 * This means that if there was an error on any block, we mark all
376 * data blocks as being in error.
377 */
378 if (!data->error)
379 data->bytes_xfered = data->blocks * data->blksz;
380 else
381 data->bytes_xfered = 0;
382
383 pxamci_disable_irq(host, DATA_TRAN_DONE);
384
385 host->data = NULL;
386 if (host->mrq->stop) {
387 pxamci_stop_clock(host);
388 pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
389 } else {
390 pxamci_finish_request(host, host->mrq);
391 }
392
393 return 1;
394}
395
396static irqreturn_t pxamci_irq(int irq, void *devid)
397{
398 struct pxamci_host *host = devid;
399 unsigned int ireg;
400 int handled = 0;
401
402 ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
403
404 if (ireg) {
405 unsigned stat = readl(host->base + MMC_STAT);
406
407 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
408
409 if (ireg & END_CMD_RES)
410 handled |= pxamci_cmd_done(host, stat);
411 if (ireg & DATA_TRAN_DONE)
412 handled |= pxamci_data_done(host, stat);
413 if (ireg & SDIO_INT) {
414 mmc_signal_sdio_irq(host->mmc);
415 handled = 1;
416 }
417 }
418
419 return IRQ_RETVAL(handled);
420}
421
422static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
423{
424 struct pxamci_host *host = mmc_priv(mmc);
425 unsigned int cmdat;
426
427 WARN_ON(host->mrq != NULL);
428
429 host->mrq = mrq;
430
431 pxamci_stop_clock(host);
432
433 cmdat = host->cmdat;
434 host->cmdat &= ~CMDAT_INIT;
435
436 if (mrq->data) {
437 pxamci_setup_data(host, mrq->data);
438
439 cmdat &= ~CMDAT_BUSY;
440 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
441 if (mrq->data->flags & MMC_DATA_WRITE)
442 cmdat |= CMDAT_WRITE;
443 }
444
445 pxamci_start_cmd(host, mrq->cmd, cmdat);
446}
447
448static int pxamci_get_ro(struct mmc_host *mmc)
449{
450 struct pxamci_host *host = mmc_priv(mmc);
451
452 if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro))
453 return mmc_gpio_get_ro(mmc);
454 if (host->pdata && host->pdata->get_ro)
455 return !!host->pdata->get_ro(mmc_dev(mmc));
456 /*
457 * Board doesn't support read only detection; let the mmc core
458 * decide what to do.
459 */
460 return -ENOSYS;
461}
462
463static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
464{
465 struct pxamci_host *host = mmc_priv(mmc);
466
467 if (ios->clock) {
468 unsigned long rate = host->clkrate;
469 unsigned int clk = rate / ios->clock;
470
471 if (host->clkrt == CLKRT_OFF)
472 clk_prepare_enable(host->clk);
473
474 if (ios->clock == 26000000) {
475 /* to support 26MHz */
476 host->clkrt = 7;
477 } else {
478 /* to handle (19.5MHz, 26MHz) */
479 if (!clk)
480 clk = 1;
481
482 /*
483 * clk might result in a lower divisor than we
484 * desire. check for that condition and adjust
485 * as appropriate.
486 */
487 if (rate / clk > ios->clock)
488 clk <<= 1;
489 host->clkrt = fls(clk) - 1;
490 }
491
492 /*
493 * we write clkrt on the next command
494 */
495 } else {
496 pxamci_stop_clock(host);
497 if (host->clkrt != CLKRT_OFF) {
498 host->clkrt = CLKRT_OFF;
499 clk_disable_unprepare(host->clk);
500 }
501 }
502
503 if (host->power_mode != ios->power_mode) {
504 int ret;
505
506 host->power_mode = ios->power_mode;
507
508 ret = pxamci_set_power(host, ios->power_mode, ios->vdd);
509 if (ret) {
510 dev_err(mmc_dev(mmc), "unable to set power\n");
511 /*
512 * The .set_ios() function in the mmc_host_ops
513 * struct return void, and failing to set the
514 * power should be rare so we print an error and
515 * return here.
516 */
517 return;
518 }
519
520 if (ios->power_mode == MMC_POWER_ON)
521 host->cmdat |= CMDAT_INIT;
522 }
523
524 if (ios->bus_width == MMC_BUS_WIDTH_4)
525 host->cmdat |= CMDAT_SD_4DAT;
526 else
527 host->cmdat &= ~CMDAT_SD_4DAT;
528
529 dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n",
530 host->clkrt, host->cmdat);
531}
532
533static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
534{
535 struct pxamci_host *pxa_host = mmc_priv(host);
536
537 if (enable)
538 pxamci_enable_irq(pxa_host, SDIO_INT);
539 else
540 pxamci_disable_irq(pxa_host, SDIO_INT);
541}
542
543static const struct mmc_host_ops pxamci_ops = {
544 .request = pxamci_request,
545 .get_cd = mmc_gpio_get_cd,
546 .get_ro = pxamci_get_ro,
547 .set_ios = pxamci_set_ios,
548 .enable_sdio_irq = pxamci_enable_sdio_irq,
549};
550
551static void pxamci_dma_irq(void *param)
552{
553 struct pxamci_host *host = param;
554 struct dma_tx_state state;
555 enum dma_status status;
556 struct dma_chan *chan;
557 unsigned long flags;
558
559 spin_lock_irqsave(&host->lock, flags);
560
561 if (!host->data)
562 goto out_unlock;
563
564 if (host->data->flags & MMC_DATA_READ)
565 chan = host->dma_chan_rx;
566 else
567 chan = host->dma_chan_tx;
568
569 status = dmaengine_tx_status(chan, host->dma_cookie, &state);
570
571 if (likely(status == DMA_COMPLETE)) {
572 writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
573 } else {
574 pr_err("%s: DMA error on %s channel\n", mmc_hostname(host->mmc),
575 host->data->flags & MMC_DATA_READ ? "rx" : "tx");
576 host->data->error = -EIO;
577 pxamci_data_done(host, 0);
578 }
579
580out_unlock:
581 spin_unlock_irqrestore(&host->lock, flags);
582}
583
584static irqreturn_t pxamci_detect_irq(int irq, void *devid)
585{
586 struct pxamci_host *host = mmc_priv(devid);
587
588 mmc_detect_change(devid, msecs_to_jiffies(host->pdata->detect_delay_ms));
589 return IRQ_HANDLED;
590}
591
592#ifdef CONFIG_OF
593static const struct of_device_id pxa_mmc_dt_ids[] = {
594 { .compatible = "marvell,pxa-mmc" },
595 { }
596};
597
598MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids);
599
600static int pxamci_of_init(struct platform_device *pdev)
601{
602 struct device_node *np = pdev->dev.of_node;
603 struct pxamci_platform_data *pdata;
604 u32 tmp;
605
606 if (!np)
607 return 0;
608
609 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
610 if (!pdata)
611 return -ENOMEM;
612
613 pdata->gpio_card_detect =
614 of_get_named_gpio(np, "cd-gpios", 0);
615 pdata->gpio_card_ro =
616 of_get_named_gpio(np, "wp-gpios", 0);
617
618 /* pxa-mmc specific */
619 pdata->gpio_power =
620 of_get_named_gpio(np, "pxa-mmc,gpio-power", 0);
621
622 if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0)
623 pdata->detect_delay_ms = tmp;
624
625 pdev->dev.platform_data = pdata;
626
627 return 0;
628}
629#else
630static int pxamci_of_init(struct platform_device *pdev)
631{
632 return 0;
633}
634#endif
635
636static int pxamci_probe(struct platform_device *pdev)
637{
638 struct mmc_host *mmc;
639 struct pxamci_host *host = NULL;
640 struct resource *r, *dmarx, *dmatx;
641 struct pxad_param param_rx, param_tx;
642 int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1;
643 dma_cap_mask_t mask;
644
645 ret = pxamci_of_init(pdev);
646 if (ret)
647 return ret;
648
649 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
650 irq = platform_get_irq(pdev, 0);
651 if (irq < 0)
652 return irq;
653
654 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
655 if (!mmc) {
656 ret = -ENOMEM;
657 goto out;
658 }
659
660 mmc->ops = &pxamci_ops;
661
662 /*
663 * We can do SG-DMA, but we don't because we never know how much
664 * data we successfully wrote to the card.
665 */
666 mmc->max_segs = NR_SG;
667
668 /*
669 * Our hardware DMA can handle a maximum of one page per SG entry.
670 */
671 mmc->max_seg_size = PAGE_SIZE;
672
673 /*
674 * Block length register is only 10 bits before PXA27x.
675 */
676 mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048;
677
678 /*
679 * Block count register is 16 bits.
680 */
681 mmc->max_blk_count = 65535;
682
683 host = mmc_priv(mmc);
684 host->mmc = mmc;
685 host->pdata = pdev->dev.platform_data;
686 host->clkrt = CLKRT_OFF;
687
688 host->clk = devm_clk_get(&pdev->dev, NULL);
689 if (IS_ERR(host->clk)) {
690 ret = PTR_ERR(host->clk);
691 host->clk = NULL;
692 goto out;
693 }
694
695 host->clkrate = clk_get_rate(host->clk);
696
697 /*
698 * Calculate minimum clock rate, rounding up.
699 */
700 mmc->f_min = (host->clkrate + 63) / 64;
701 mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
702
703 pxamci_init_ocr(host);
704
705 mmc->caps = 0;
706 host->cmdat = 0;
707 if (!cpu_is_pxa25x()) {
708 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
709 host->cmdat |= CMDAT_SDIO_INT_EN;
710 if (mmc_has_26MHz())
711 mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
712 MMC_CAP_SD_HIGHSPEED;
713 }
714
715 spin_lock_init(&host->lock);
716 host->res = r;
717 host->irq = irq;
718 host->imask = MMC_I_MASK_ALL;
719
720 host->base = devm_ioremap_resource(&pdev->dev, r);
721 if (IS_ERR(host->base)) {
722 ret = PTR_ERR(host->base);
723 goto out;
724 }
725
726 /*
727 * Ensure that the host controller is shut down, and setup
728 * with our defaults.
729 */
730 pxamci_stop_clock(host);
731 writel(0, host->base + MMC_SPI);
732 writel(64, host->base + MMC_RESTO);
733 writel(host->imask, host->base + MMC_I_MASK);
734
735 ret = devm_request_irq(&pdev->dev, host->irq, pxamci_irq, 0,
736 DRIVER_NAME, host);
737 if (ret)
738 goto out;
739
740 platform_set_drvdata(pdev, mmc);
741
742 if (!pdev->dev.of_node) {
743 dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0);
744 dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1);
745 if (!dmarx || !dmatx) {
746 ret = -ENXIO;
747 goto out;
748 }
749 param_rx.prio = PXAD_PRIO_LOWEST;
750 param_rx.drcmr = dmarx->start;
751 param_tx.prio = PXAD_PRIO_LOWEST;
752 param_tx.drcmr = dmatx->start;
753 }
754
755 dma_cap_zero(mask);
756 dma_cap_set(DMA_SLAVE, mask);
757
758 host->dma_chan_rx =
759 dma_request_slave_channel_compat(mask, pxad_filter_fn,
760 ¶m_rx, &pdev->dev, "rx");
761 if (host->dma_chan_rx == NULL) {
762 dev_err(&pdev->dev, "unable to request rx dma channel\n");
763 ret = -ENODEV;
764 goto out;
765 }
766
767 host->dma_chan_tx =
768 dma_request_slave_channel_compat(mask, pxad_filter_fn,
769 ¶m_tx, &pdev->dev, "tx");
770 if (host->dma_chan_tx == NULL) {
771 dev_err(&pdev->dev, "unable to request tx dma channel\n");
772 ret = -ENODEV;
773 goto out;
774 }
775
776 if (host->pdata) {
777 gpio_cd = host->pdata->gpio_card_detect;
778 gpio_ro = host->pdata->gpio_card_ro;
779 gpio_power = host->pdata->gpio_power;
780 }
781 if (gpio_is_valid(gpio_power)) {
782 ret = devm_gpio_request(&pdev->dev, gpio_power,
783 "mmc card power");
784 if (ret) {
785 dev_err(&pdev->dev, "Failed requesting gpio_power %d\n",
786 gpio_power);
787 goto out;
788 }
789 gpio_direction_output(gpio_power,
790 host->pdata->gpio_power_invert);
791 }
792 if (gpio_is_valid(gpio_ro))
793 ret = mmc_gpio_request_ro(mmc, gpio_ro);
794 if (ret) {
795 dev_err(&pdev->dev, "Failed requesting gpio_ro %d\n", gpio_ro);
796 goto out;
797 } else {
798 mmc->caps2 |= host->pdata->gpio_card_ro_invert ?
799 0 : MMC_CAP2_RO_ACTIVE_HIGH;
800 }
801
802 if (gpio_is_valid(gpio_cd))
803 ret = mmc_gpio_request_cd(mmc, gpio_cd, 0);
804 if (ret) {
805 dev_err(&pdev->dev, "Failed requesting gpio_cd %d\n", gpio_cd);
806 goto out;
807 }
808
809 if (host->pdata && host->pdata->init)
810 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
811
812 if (gpio_is_valid(gpio_power) && host->pdata->setpower)
813 dev_warn(&pdev->dev, "gpio_power and setpower() both defined\n");
814 if (gpio_is_valid(gpio_ro) && host->pdata->get_ro)
815 dev_warn(&pdev->dev, "gpio_ro and get_ro() both defined\n");
816
817 mmc_add_host(mmc);
818
819 return 0;
820
821out:
822 if (host) {
823 if (host->dma_chan_rx)
824 dma_release_channel(host->dma_chan_rx);
825 if (host->dma_chan_tx)
826 dma_release_channel(host->dma_chan_tx);
827 }
828 if (mmc)
829 mmc_free_host(mmc);
830 return ret;
831}
832
833static int pxamci_remove(struct platform_device *pdev)
834{
835 struct mmc_host *mmc = platform_get_drvdata(pdev);
836 int gpio_cd = -1, gpio_ro = -1, gpio_power = -1;
837
838 if (mmc) {
839 struct pxamci_host *host = mmc_priv(mmc);
840
841 mmc_remove_host(mmc);
842
843 if (host->pdata) {
844 gpio_cd = host->pdata->gpio_card_detect;
845 gpio_ro = host->pdata->gpio_card_ro;
846 gpio_power = host->pdata->gpio_power;
847 }
848 if (host->pdata && host->pdata->exit)
849 host->pdata->exit(&pdev->dev, mmc);
850
851 pxamci_stop_clock(host);
852 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
853 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
854 host->base + MMC_I_MASK);
855
856 dmaengine_terminate_all(host->dma_chan_rx);
857 dmaengine_terminate_all(host->dma_chan_tx);
858 dma_release_channel(host->dma_chan_rx);
859 dma_release_channel(host->dma_chan_tx);
860
861 mmc_free_host(mmc);
862 }
863 return 0;
864}
865
866static struct platform_driver pxamci_driver = {
867 .probe = pxamci_probe,
868 .remove = pxamci_remove,
869 .driver = {
870 .name = DRIVER_NAME,
871 .of_match_table = of_match_ptr(pxa_mmc_dt_ids),
872 },
873};
874
875module_platform_driver(pxamci_driver);
876
877MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
878MODULE_LICENSE("GPL");
879MODULE_ALIAS("platform:pxa2xx-mci");
1/*
2 * linux/drivers/mmc/host/pxa.c - PXA MMCI driver
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This hardware is really sick:
11 * - No way to clear interrupts.
12 * - Have to turn off the clock whenever we touch the device.
13 * - Doesn't tell you how many data blocks were transferred.
14 * Yuck!
15 *
16 * 1 and 3 byte data transfers not supported
17 * max block length up to 1023
18 */
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/platform_device.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <linux/mmc/host.h>
29#include <linux/io.h>
30#include <linux/regulator/consumer.h>
31#include <linux/gpio.h>
32#include <linux/gfp.h>
33
34#include <asm/sizes.h>
35
36#include <mach/hardware.h>
37#include <mach/dma.h>
38#include <mach/mmc.h>
39
40#include "pxamci.h"
41
42#define DRIVER_NAME "pxa2xx-mci"
43
44#define NR_SG 1
45#define CLKRT_OFF (~0)
46
47#define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \
48 || cpu_is_pxa935())
49
50struct pxamci_host {
51 struct mmc_host *mmc;
52 spinlock_t lock;
53 struct resource *res;
54 void __iomem *base;
55 struct clk *clk;
56 unsigned long clkrate;
57 int irq;
58 int dma;
59 unsigned int clkrt;
60 unsigned int cmdat;
61 unsigned int imask;
62 unsigned int power_mode;
63 struct pxamci_platform_data *pdata;
64
65 struct mmc_request *mrq;
66 struct mmc_command *cmd;
67 struct mmc_data *data;
68
69 dma_addr_t sg_dma;
70 struct pxa_dma_desc *sg_cpu;
71 unsigned int dma_len;
72
73 unsigned int dma_dir;
74 unsigned int dma_drcmrrx;
75 unsigned int dma_drcmrtx;
76
77 struct regulator *vcc;
78};
79
80static inline void pxamci_init_ocr(struct pxamci_host *host)
81{
82#ifdef CONFIG_REGULATOR
83 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
84
85 if (IS_ERR(host->vcc))
86 host->vcc = NULL;
87 else {
88 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
89 if (host->pdata && host->pdata->ocr_mask)
90 dev_warn(mmc_dev(host->mmc),
91 "ocr_mask/setpower will not be used\n");
92 }
93#endif
94 if (host->vcc == NULL) {
95 /* fall-back to platform data */
96 host->mmc->ocr_avail = host->pdata ?
97 host->pdata->ocr_mask :
98 MMC_VDD_32_33 | MMC_VDD_33_34;
99 }
100}
101
102static inline int pxamci_set_power(struct pxamci_host *host,
103 unsigned char power_mode,
104 unsigned int vdd)
105{
106 int on;
107
108 if (host->vcc) {
109 int ret;
110
111 if (power_mode == MMC_POWER_UP) {
112 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
113 if (ret)
114 return ret;
115 } else if (power_mode == MMC_POWER_OFF) {
116 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
117 if (ret)
118 return ret;
119 }
120 }
121 if (!host->vcc && host->pdata &&
122 gpio_is_valid(host->pdata->gpio_power)) {
123 on = ((1 << vdd) & host->pdata->ocr_mask);
124 gpio_set_value(host->pdata->gpio_power,
125 !!on ^ host->pdata->gpio_power_invert);
126 }
127 if (!host->vcc && host->pdata && host->pdata->setpower)
128 host->pdata->setpower(mmc_dev(host->mmc), vdd);
129
130 return 0;
131}
132
133static void pxamci_stop_clock(struct pxamci_host *host)
134{
135 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
136 unsigned long timeout = 10000;
137 unsigned int v;
138
139 writel(STOP_CLOCK, host->base + MMC_STRPCL);
140
141 do {
142 v = readl(host->base + MMC_STAT);
143 if (!(v & STAT_CLK_EN))
144 break;
145 udelay(1);
146 } while (timeout--);
147
148 if (v & STAT_CLK_EN)
149 dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
150 }
151}
152
153static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
154{
155 unsigned long flags;
156
157 spin_lock_irqsave(&host->lock, flags);
158 host->imask &= ~mask;
159 writel(host->imask, host->base + MMC_I_MASK);
160 spin_unlock_irqrestore(&host->lock, flags);
161}
162
163static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&host->lock, flags);
168 host->imask |= mask;
169 writel(host->imask, host->base + MMC_I_MASK);
170 spin_unlock_irqrestore(&host->lock, flags);
171}
172
173static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
174{
175 unsigned int nob = data->blocks;
176 unsigned long long clks;
177 unsigned int timeout;
178 bool dalgn = 0;
179 u32 dcmd;
180 int i;
181
182 host->data = data;
183
184 if (data->flags & MMC_DATA_STREAM)
185 nob = 0xffff;
186
187 writel(nob, host->base + MMC_NOB);
188 writel(data->blksz, host->base + MMC_BLKLEN);
189
190 clks = (unsigned long long)data->timeout_ns * host->clkrate;
191 do_div(clks, 1000000000UL);
192 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
193 writel((timeout + 255) / 256, host->base + MMC_RDTO);
194
195 if (data->flags & MMC_DATA_READ) {
196 host->dma_dir = DMA_FROM_DEVICE;
197 dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC;
198 DRCMR(host->dma_drcmrtx) = 0;
199 DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD;
200 } else {
201 host->dma_dir = DMA_TO_DEVICE;
202 dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
203 DRCMR(host->dma_drcmrrx) = 0;
204 DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD;
205 }
206
207 dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
208
209 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
210 host->dma_dir);
211
212 for (i = 0; i < host->dma_len; i++) {
213 unsigned int length = sg_dma_len(&data->sg[i]);
214 host->sg_cpu[i].dcmd = dcmd | length;
215 if (length & 31 && !(data->flags & MMC_DATA_READ))
216 host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN;
217 /* Not aligned to 8-byte boundary? */
218 if (sg_dma_address(&data->sg[i]) & 0x7)
219 dalgn = 1;
220 if (data->flags & MMC_DATA_READ) {
221 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
222 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
223 } else {
224 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
225 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
226 }
227 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
228 sizeof(struct pxa_dma_desc);
229 }
230 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
231 wmb();
232
233 /*
234 * The PXA27x DMA controller encounters overhead when working with
235 * unaligned (to 8-byte boundaries) data, so switch on byte alignment
236 * mode only if we have unaligned data.
237 */
238 if (dalgn)
239 DALGN |= (1 << host->dma);
240 else
241 DALGN &= ~(1 << host->dma);
242 DDADR(host->dma) = host->sg_dma;
243
244 /*
245 * workaround for erratum #91:
246 * only start DMA now if we are doing a read,
247 * otherwise we wait until CMD/RESP has finished
248 * before starting DMA.
249 */
250 if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
251 DCSR(host->dma) = DCSR_RUN;
252}
253
254static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
255{
256 WARN_ON(host->cmd != NULL);
257 host->cmd = cmd;
258
259 if (cmd->flags & MMC_RSP_BUSY)
260 cmdat |= CMDAT_BUSY;
261
262#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
263 switch (RSP_TYPE(mmc_resp_type(cmd))) {
264 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
265 cmdat |= CMDAT_RESP_SHORT;
266 break;
267 case RSP_TYPE(MMC_RSP_R3):
268 cmdat |= CMDAT_RESP_R3;
269 break;
270 case RSP_TYPE(MMC_RSP_R2):
271 cmdat |= CMDAT_RESP_R2;
272 break;
273 default:
274 break;
275 }
276
277 writel(cmd->opcode, host->base + MMC_CMD);
278 writel(cmd->arg >> 16, host->base + MMC_ARGH);
279 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
280 writel(cmdat, host->base + MMC_CMDAT);
281 writel(host->clkrt, host->base + MMC_CLKRT);
282
283 writel(START_CLOCK, host->base + MMC_STRPCL);
284
285 pxamci_enable_irq(host, END_CMD_RES);
286}
287
288static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
289{
290 host->mrq = NULL;
291 host->cmd = NULL;
292 host->data = NULL;
293 mmc_request_done(host->mmc, mrq);
294}
295
296static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
297{
298 struct mmc_command *cmd = host->cmd;
299 int i;
300 u32 v;
301
302 if (!cmd)
303 return 0;
304
305 host->cmd = NULL;
306
307 /*
308 * Did I mention this is Sick. We always need to
309 * discard the upper 8 bits of the first 16-bit word.
310 */
311 v = readl(host->base + MMC_RES) & 0xffff;
312 for (i = 0; i < 4; i++) {
313 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
314 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
315 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
316 v = w2;
317 }
318
319 if (stat & STAT_TIME_OUT_RESPONSE) {
320 cmd->error = -ETIMEDOUT;
321 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
322 /*
323 * workaround for erratum #42:
324 * Intel PXA27x Family Processor Specification Update Rev 001
325 * A bogus CRC error can appear if the msb of a 136 bit
326 * response is a one.
327 */
328 if (cpu_is_pxa27x() &&
329 (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000))
330 pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
331 else
332 cmd->error = -EILSEQ;
333 }
334
335 pxamci_disable_irq(host, END_CMD_RES);
336 if (host->data && !cmd->error) {
337 pxamci_enable_irq(host, DATA_TRAN_DONE);
338 /*
339 * workaround for erratum #91, if doing write
340 * enable DMA late
341 */
342 if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
343 DCSR(host->dma) = DCSR_RUN;
344 } else {
345 pxamci_finish_request(host, host->mrq);
346 }
347
348 return 1;
349}
350
351static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
352{
353 struct mmc_data *data = host->data;
354
355 if (!data)
356 return 0;
357
358 DCSR(host->dma) = 0;
359 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
360 host->dma_dir);
361
362 if (stat & STAT_READ_TIME_OUT)
363 data->error = -ETIMEDOUT;
364 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
365 data->error = -EILSEQ;
366
367 /*
368 * There appears to be a hardware design bug here. There seems to
369 * be no way to find out how much data was transferred to the card.
370 * This means that if there was an error on any block, we mark all
371 * data blocks as being in error.
372 */
373 if (!data->error)
374 data->bytes_xfered = data->blocks * data->blksz;
375 else
376 data->bytes_xfered = 0;
377
378 pxamci_disable_irq(host, DATA_TRAN_DONE);
379
380 host->data = NULL;
381 if (host->mrq->stop) {
382 pxamci_stop_clock(host);
383 pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
384 } else {
385 pxamci_finish_request(host, host->mrq);
386 }
387
388 return 1;
389}
390
391static irqreturn_t pxamci_irq(int irq, void *devid)
392{
393 struct pxamci_host *host = devid;
394 unsigned int ireg;
395 int handled = 0;
396
397 ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
398
399 if (ireg) {
400 unsigned stat = readl(host->base + MMC_STAT);
401
402 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
403
404 if (ireg & END_CMD_RES)
405 handled |= pxamci_cmd_done(host, stat);
406 if (ireg & DATA_TRAN_DONE)
407 handled |= pxamci_data_done(host, stat);
408 if (ireg & SDIO_INT) {
409 mmc_signal_sdio_irq(host->mmc);
410 handled = 1;
411 }
412 }
413
414 return IRQ_RETVAL(handled);
415}
416
417static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
418{
419 struct pxamci_host *host = mmc_priv(mmc);
420 unsigned int cmdat;
421
422 WARN_ON(host->mrq != NULL);
423
424 host->mrq = mrq;
425
426 pxamci_stop_clock(host);
427
428 cmdat = host->cmdat;
429 host->cmdat &= ~CMDAT_INIT;
430
431 if (mrq->data) {
432 pxamci_setup_data(host, mrq->data);
433
434 cmdat &= ~CMDAT_BUSY;
435 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
436 if (mrq->data->flags & MMC_DATA_WRITE)
437 cmdat |= CMDAT_WRITE;
438
439 if (mrq->data->flags & MMC_DATA_STREAM)
440 cmdat |= CMDAT_STREAM;
441 }
442
443 pxamci_start_cmd(host, mrq->cmd, cmdat);
444}
445
446static int pxamci_get_ro(struct mmc_host *mmc)
447{
448 struct pxamci_host *host = mmc_priv(mmc);
449
450 if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro)) {
451 if (host->pdata->gpio_card_ro_invert)
452 return !gpio_get_value(host->pdata->gpio_card_ro);
453 else
454 return gpio_get_value(host->pdata->gpio_card_ro);
455 }
456 if (host->pdata && host->pdata->get_ro)
457 return !!host->pdata->get_ro(mmc_dev(mmc));
458 /*
459 * Board doesn't support read only detection; let the mmc core
460 * decide what to do.
461 */
462 return -ENOSYS;
463}
464
465static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
466{
467 struct pxamci_host *host = mmc_priv(mmc);
468
469 if (ios->clock) {
470 unsigned long rate = host->clkrate;
471 unsigned int clk = rate / ios->clock;
472
473 if (host->clkrt == CLKRT_OFF)
474 clk_enable(host->clk);
475
476 if (ios->clock == 26000000) {
477 /* to support 26MHz */
478 host->clkrt = 7;
479 } else {
480 /* to handle (19.5MHz, 26MHz) */
481 if (!clk)
482 clk = 1;
483
484 /*
485 * clk might result in a lower divisor than we
486 * desire. check for that condition and adjust
487 * as appropriate.
488 */
489 if (rate / clk > ios->clock)
490 clk <<= 1;
491 host->clkrt = fls(clk) - 1;
492 }
493
494 /*
495 * we write clkrt on the next command
496 */
497 } else {
498 pxamci_stop_clock(host);
499 if (host->clkrt != CLKRT_OFF) {
500 host->clkrt = CLKRT_OFF;
501 clk_disable(host->clk);
502 }
503 }
504
505 if (host->power_mode != ios->power_mode) {
506 int ret;
507
508 host->power_mode = ios->power_mode;
509
510 ret = pxamci_set_power(host, ios->power_mode, ios->vdd);
511 if (ret) {
512 dev_err(mmc_dev(mmc), "unable to set power\n");
513 /*
514 * The .set_ios() function in the mmc_host_ops
515 * struct return void, and failing to set the
516 * power should be rare so we print an error and
517 * return here.
518 */
519 return;
520 }
521
522 if (ios->power_mode == MMC_POWER_ON)
523 host->cmdat |= CMDAT_INIT;
524 }
525
526 if (ios->bus_width == MMC_BUS_WIDTH_4)
527 host->cmdat |= CMDAT_SD_4DAT;
528 else
529 host->cmdat &= ~CMDAT_SD_4DAT;
530
531 dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n",
532 host->clkrt, host->cmdat);
533}
534
535static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
536{
537 struct pxamci_host *pxa_host = mmc_priv(host);
538
539 if (enable)
540 pxamci_enable_irq(pxa_host, SDIO_INT);
541 else
542 pxamci_disable_irq(pxa_host, SDIO_INT);
543}
544
545static const struct mmc_host_ops pxamci_ops = {
546 .request = pxamci_request,
547 .get_ro = pxamci_get_ro,
548 .set_ios = pxamci_set_ios,
549 .enable_sdio_irq = pxamci_enable_sdio_irq,
550};
551
552static void pxamci_dma_irq(int dma, void *devid)
553{
554 struct pxamci_host *host = devid;
555 int dcsr = DCSR(dma);
556 DCSR(dma) = dcsr & ~DCSR_STOPIRQEN;
557
558 if (dcsr & DCSR_ENDINTR) {
559 writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
560 } else {
561 pr_err("%s: DMA error on channel %d (DCSR=%#x)\n",
562 mmc_hostname(host->mmc), dma, dcsr);
563 host->data->error = -EIO;
564 pxamci_data_done(host, 0);
565 }
566}
567
568static irqreturn_t pxamci_detect_irq(int irq, void *devid)
569{
570 struct pxamci_host *host = mmc_priv(devid);
571
572 mmc_detect_change(devid, msecs_to_jiffies(host->pdata->detect_delay_ms));
573 return IRQ_HANDLED;
574}
575
576static int pxamci_probe(struct platform_device *pdev)
577{
578 struct mmc_host *mmc;
579 struct pxamci_host *host = NULL;
580 struct resource *r, *dmarx, *dmatx;
581 int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1;
582
583 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
584 irq = platform_get_irq(pdev, 0);
585 if (!r || irq < 0)
586 return -ENXIO;
587
588 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
589 if (!r)
590 return -EBUSY;
591
592 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
593 if (!mmc) {
594 ret = -ENOMEM;
595 goto out;
596 }
597
598 mmc->ops = &pxamci_ops;
599
600 /*
601 * We can do SG-DMA, but we don't because we never know how much
602 * data we successfully wrote to the card.
603 */
604 mmc->max_segs = NR_SG;
605
606 /*
607 * Our hardware DMA can handle a maximum of one page per SG entry.
608 */
609 mmc->max_seg_size = PAGE_SIZE;
610
611 /*
612 * Block length register is only 10 bits before PXA27x.
613 */
614 mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048;
615
616 /*
617 * Block count register is 16 bits.
618 */
619 mmc->max_blk_count = 65535;
620
621 host = mmc_priv(mmc);
622 host->mmc = mmc;
623 host->dma = -1;
624 host->pdata = pdev->dev.platform_data;
625 host->clkrt = CLKRT_OFF;
626
627 host->clk = clk_get(&pdev->dev, NULL);
628 if (IS_ERR(host->clk)) {
629 ret = PTR_ERR(host->clk);
630 host->clk = NULL;
631 goto out;
632 }
633
634 host->clkrate = clk_get_rate(host->clk);
635
636 /*
637 * Calculate minimum clock rate, rounding up.
638 */
639 mmc->f_min = (host->clkrate + 63) / 64;
640 mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
641
642 pxamci_init_ocr(host);
643
644 mmc->caps = 0;
645 host->cmdat = 0;
646 if (!cpu_is_pxa25x()) {
647 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
648 host->cmdat |= CMDAT_SDIO_INT_EN;
649 if (mmc_has_26MHz())
650 mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
651 MMC_CAP_SD_HIGHSPEED;
652 }
653
654 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
655 if (!host->sg_cpu) {
656 ret = -ENOMEM;
657 goto out;
658 }
659
660 spin_lock_init(&host->lock);
661 host->res = r;
662 host->irq = irq;
663 host->imask = MMC_I_MASK_ALL;
664
665 host->base = ioremap(r->start, SZ_4K);
666 if (!host->base) {
667 ret = -ENOMEM;
668 goto out;
669 }
670
671 /*
672 * Ensure that the host controller is shut down, and setup
673 * with our defaults.
674 */
675 pxamci_stop_clock(host);
676 writel(0, host->base + MMC_SPI);
677 writel(64, host->base + MMC_RESTO);
678 writel(host->imask, host->base + MMC_I_MASK);
679
680 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
681 pxamci_dma_irq, host);
682 if (host->dma < 0) {
683 ret = -EBUSY;
684 goto out;
685 }
686
687 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
688 if (ret)
689 goto out;
690
691 platform_set_drvdata(pdev, mmc);
692
693 dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0);
694 if (!dmarx) {
695 ret = -ENXIO;
696 goto out;
697 }
698 host->dma_drcmrrx = dmarx->start;
699
700 dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1);
701 if (!dmatx) {
702 ret = -ENXIO;
703 goto out;
704 }
705 host->dma_drcmrtx = dmatx->start;
706
707 if (host->pdata) {
708 gpio_cd = host->pdata->gpio_card_detect;
709 gpio_ro = host->pdata->gpio_card_ro;
710 gpio_power = host->pdata->gpio_power;
711 }
712 if (gpio_is_valid(gpio_power)) {
713 ret = gpio_request(gpio_power, "mmc card power");
714 if (ret) {
715 dev_err(&pdev->dev, "Failed requesting gpio_power %d\n", gpio_power);
716 goto out;
717 }
718 gpio_direction_output(gpio_power,
719 host->pdata->gpio_power_invert);
720 }
721 if (gpio_is_valid(gpio_ro)) {
722 ret = gpio_request(gpio_ro, "mmc card read only");
723 if (ret) {
724 dev_err(&pdev->dev, "Failed requesting gpio_ro %d\n", gpio_ro);
725 goto err_gpio_ro;
726 }
727 gpio_direction_input(gpio_ro);
728 }
729 if (gpio_is_valid(gpio_cd)) {
730 ret = gpio_request(gpio_cd, "mmc card detect");
731 if (ret) {
732 dev_err(&pdev->dev, "Failed requesting gpio_cd %d\n", gpio_cd);
733 goto err_gpio_cd;
734 }
735 gpio_direction_input(gpio_cd);
736
737 ret = request_irq(gpio_to_irq(gpio_cd), pxamci_detect_irq,
738 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
739 "mmc card detect", mmc);
740 if (ret) {
741 dev_err(&pdev->dev, "failed to request card detect IRQ\n");
742 goto err_request_irq;
743 }
744 }
745
746 if (host->pdata && host->pdata->init)
747 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
748
749 if (gpio_is_valid(gpio_power) && host->pdata->setpower)
750 dev_warn(&pdev->dev, "gpio_power and setpower() both defined\n");
751 if (gpio_is_valid(gpio_ro) && host->pdata->get_ro)
752 dev_warn(&pdev->dev, "gpio_ro and get_ro() both defined\n");
753
754 mmc_add_host(mmc);
755
756 return 0;
757
758err_request_irq:
759 gpio_free(gpio_cd);
760err_gpio_cd:
761 gpio_free(gpio_ro);
762err_gpio_ro:
763 gpio_free(gpio_power);
764 out:
765 if (host) {
766 if (host->dma >= 0)
767 pxa_free_dma(host->dma);
768 if (host->base)
769 iounmap(host->base);
770 if (host->sg_cpu)
771 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
772 if (host->clk)
773 clk_put(host->clk);
774 }
775 if (mmc)
776 mmc_free_host(mmc);
777 release_resource(r);
778 return ret;
779}
780
781static int pxamci_remove(struct platform_device *pdev)
782{
783 struct mmc_host *mmc = platform_get_drvdata(pdev);
784 int gpio_cd = -1, gpio_ro = -1, gpio_power = -1;
785
786 platform_set_drvdata(pdev, NULL);
787
788 if (mmc) {
789 struct pxamci_host *host = mmc_priv(mmc);
790
791 mmc_remove_host(mmc);
792
793 if (host->pdata) {
794 gpio_cd = host->pdata->gpio_card_detect;
795 gpio_ro = host->pdata->gpio_card_ro;
796 gpio_power = host->pdata->gpio_power;
797 }
798 if (gpio_is_valid(gpio_cd)) {
799 free_irq(gpio_to_irq(gpio_cd), mmc);
800 gpio_free(gpio_cd);
801 }
802 if (gpio_is_valid(gpio_ro))
803 gpio_free(gpio_ro);
804 if (gpio_is_valid(gpio_power))
805 gpio_free(gpio_power);
806 if (host->vcc)
807 regulator_put(host->vcc);
808
809 if (host->pdata && host->pdata->exit)
810 host->pdata->exit(&pdev->dev, mmc);
811
812 pxamci_stop_clock(host);
813 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
814 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
815 host->base + MMC_I_MASK);
816
817 DRCMR(host->dma_drcmrrx) = 0;
818 DRCMR(host->dma_drcmrtx) = 0;
819
820 free_irq(host->irq, host);
821 pxa_free_dma(host->dma);
822 iounmap(host->base);
823 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
824
825 clk_put(host->clk);
826
827 release_resource(host->res);
828
829 mmc_free_host(mmc);
830 }
831 return 0;
832}
833
834#ifdef CONFIG_PM
835static int pxamci_suspend(struct device *dev)
836{
837 struct mmc_host *mmc = dev_get_drvdata(dev);
838 int ret = 0;
839
840 if (mmc)
841 ret = mmc_suspend_host(mmc);
842
843 return ret;
844}
845
846static int pxamci_resume(struct device *dev)
847{
848 struct mmc_host *mmc = dev_get_drvdata(dev);
849 int ret = 0;
850
851 if (mmc)
852 ret = mmc_resume_host(mmc);
853
854 return ret;
855}
856
857static const struct dev_pm_ops pxamci_pm_ops = {
858 .suspend = pxamci_suspend,
859 .resume = pxamci_resume,
860};
861#endif
862
863static struct platform_driver pxamci_driver = {
864 .probe = pxamci_probe,
865 .remove = pxamci_remove,
866 .driver = {
867 .name = DRIVER_NAME,
868 .owner = THIS_MODULE,
869#ifdef CONFIG_PM
870 .pm = &pxamci_pm_ops,
871#endif
872 },
873};
874
875module_platform_driver(pxamci_driver);
876
877MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
878MODULE_LICENSE("GPL");
879MODULE_ALIAS("platform:pxa2xx-mci");