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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H
11
12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h>
15
16/*
17 * SMP assumption: Options of CPU 0 are a superset of all processors.
18 * This is true for all known MIPS systems.
19 */
20#ifndef cpu_has_tlb
21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
22#endif
23#ifndef cpu_has_ftlb
24#define cpu_has_ftlb (cpu_data[0].options & MIPS_CPU_FTLB)
25#endif
26#ifndef cpu_has_tlbinv
27#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
28#endif
29#ifndef cpu_has_segments
30#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
31#endif
32#ifndef cpu_has_eva
33#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
34#endif
35#ifndef cpu_has_htw
36#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
37#endif
38#ifndef cpu_has_rixiex
39#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
40#endif
41#ifndef cpu_has_maar
42#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
43#endif
44#ifndef cpu_has_rw_llb
45#define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
46#endif
47
48/*
49 * For the moment we don't consider R6000 and R8000 so we can assume that
50 * anything that doesn't support R4000-style exceptions and interrupts is
51 * R3000-like. Users should still treat these two macro definitions as
52 * opaque.
53 */
54#ifndef cpu_has_3kex
55#define cpu_has_3kex (!cpu_has_4kex)
56#endif
57#ifndef cpu_has_4kex
58#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
59#endif
60#ifndef cpu_has_3k_cache
61#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
62#endif
63#define cpu_has_6k_cache 0
64#define cpu_has_8k_cache 0
65#ifndef cpu_has_4k_cache
66#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
67#endif
68#ifndef cpu_has_tx39_cache
69#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
70#endif
71#ifndef cpu_has_octeon_cache
72#define cpu_has_octeon_cache 0
73#endif
74/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
75#ifndef cpu_has_fpu
76#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
77#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
78#else
79#define raw_cpu_has_fpu cpu_has_fpu
80#endif
81#ifndef cpu_has_32fpr
82#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
83#endif
84#ifndef cpu_has_counter
85#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
86#endif
87#ifndef cpu_has_watch
88#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
89#endif
90#ifndef cpu_has_divec
91#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
92#endif
93#ifndef cpu_has_vce
94#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
95#endif
96#ifndef cpu_has_cache_cdex_p
97#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
98#endif
99#ifndef cpu_has_cache_cdex_s
100#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
101#endif
102#ifndef cpu_has_prefetch
103#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
104#endif
105#ifndef cpu_has_mcheck
106#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
107#endif
108#ifndef cpu_has_ejtag
109#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
110#endif
111#ifndef cpu_has_llsc
112#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
113#endif
114#ifndef cpu_has_bp_ghist
115#define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST)
116#endif
117#ifndef kernel_uses_llsc
118#define kernel_uses_llsc cpu_has_llsc
119#endif
120#ifndef cpu_has_mips16
121#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
122#endif
123#ifndef cpu_has_mdmx
124#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
125#endif
126#ifndef cpu_has_mips3d
127#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
128#endif
129#ifndef cpu_has_smartmips
130#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
131#endif
132
133#ifndef cpu_has_rixi
134#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
135#endif
136
137#ifndef cpu_has_mmips
138# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
139# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
140# else
141# define cpu_has_mmips 0
142# endif
143#endif
144
145#ifndef cpu_has_xpa
146#define cpu_has_xpa (cpu_data[0].options & MIPS_CPU_XPA)
147#endif
148#ifndef cpu_has_vtag_icache
149#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
150#endif
151#ifndef cpu_has_dc_aliases
152#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
153#endif
154#ifndef cpu_has_ic_fills_f_dc
155#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
156#endif
157#ifndef cpu_has_pindexed_dcache
158#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
159#endif
160#ifndef cpu_has_local_ebase
161#define cpu_has_local_ebase 1
162#endif
163
164/*
165 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
166 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
167 * don't. For maintaining I-cache coherency this means we need to flush the
168 * D-cache all the way back to whever the I-cache does refills from, so the
169 * I-cache has a chance to see the new data at all. Then we have to flush the
170 * I-cache also.
171 * Note we may have been rescheduled and may no longer be running on the CPU
172 * that did the store so we can't optimize this into only doing the flush on
173 * the local CPU.
174 */
175#ifndef cpu_icache_snoops_remote_store
176#ifdef CONFIG_SMP
177#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
178#else
179#define cpu_icache_snoops_remote_store 1
180#endif
181#endif
182
183#ifndef cpu_has_mips_1
184# define cpu_has_mips_1 (!cpu_has_mips_r6)
185#endif
186#ifndef cpu_has_mips_2
187# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
188#endif
189#ifndef cpu_has_mips_3
190# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
191#endif
192#ifndef cpu_has_mips_4
193# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
194#endif
195#ifndef cpu_has_mips_5
196# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
197#endif
198#ifndef cpu_has_mips32r1
199# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
200#endif
201#ifndef cpu_has_mips32r2
202# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
203#endif
204#ifndef cpu_has_mips32r6
205# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
206#endif
207#ifndef cpu_has_mips64r1
208# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
209#endif
210#ifndef cpu_has_mips64r2
211# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
212#endif
213#ifndef cpu_has_mips64r6
214# define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
215#endif
216
217/*
218 * Shortcuts ...
219 */
220#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
221#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
222#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
223
224#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
225#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
226#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
227#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
228
229#define cpu_has_mips_3_4_5_64_r2_r6 \
230 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
231#define cpu_has_mips_4_5_64_r2_r6 \
232 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \
233 cpu_has_mips_r2 | cpu_has_mips_r6)
234
235#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
236#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
237#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
238#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
239#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
240#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
241 cpu_has_mips32r6 | cpu_has_mips64r1 | \
242 cpu_has_mips64r2 | cpu_has_mips64r6)
243
244/* MIPSR2 and MIPSR6 have a lot of similarities */
245#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
246
247/*
248 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
249 *
250 * Returns non-zero value if the current processor implementation requires
251 * an IHB instruction to deal with an instruction hazard as per MIPS R2
252 * architecture specification, zero otherwise.
253 */
254#ifndef cpu_has_mips_r2_exec_hazard
255#define cpu_has_mips_r2_exec_hazard \
256({ \
257 int __res; \
258 \
259 switch (current_cpu_type()) { \
260 case CPU_M14KC: \
261 case CPU_74K: \
262 case CPU_1074K: \
263 case CPU_PROAPTIV: \
264 case CPU_P5600: \
265 case CPU_M5150: \
266 case CPU_QEMU_GENERIC: \
267 case CPU_CAVIUM_OCTEON: \
268 case CPU_CAVIUM_OCTEON_PLUS: \
269 case CPU_CAVIUM_OCTEON2: \
270 case CPU_CAVIUM_OCTEON3: \
271 __res = 0; \
272 break; \
273 \
274 default: \
275 __res = 1; \
276 } \
277 \
278 __res; \
279})
280#endif
281
282/*
283 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
284 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
285 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
286 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
287 */
288#ifndef cpu_has_clo_clz
289#define cpu_has_clo_clz cpu_has_mips_r
290#endif
291
292/*
293 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
294 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
295 * This indicates the availability of WSBH and in case of 64 bit CPUs also
296 * DSBH and DSHD.
297 */
298#ifndef cpu_has_wsbh
299#define cpu_has_wsbh cpu_has_mips_r2
300#endif
301
302#ifndef cpu_has_dsp
303#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
304#endif
305
306#ifndef cpu_has_dsp2
307#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
308#endif
309
310#ifndef cpu_has_mipsmt
311#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
312#endif
313
314#ifndef cpu_has_userlocal
315#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
316#endif
317
318#ifdef CONFIG_32BIT
319# ifndef cpu_has_nofpuex
320# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
321# endif
322# ifndef cpu_has_64bits
323# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
324# endif
325# ifndef cpu_has_64bit_zero_reg
326# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
327# endif
328# ifndef cpu_has_64bit_gp_regs
329# define cpu_has_64bit_gp_regs 0
330# endif
331# ifndef cpu_has_64bit_addresses
332# define cpu_has_64bit_addresses 0
333# endif
334# ifndef cpu_vmbits
335# define cpu_vmbits 31
336# endif
337#endif
338
339#ifdef CONFIG_64BIT
340# ifndef cpu_has_nofpuex
341# define cpu_has_nofpuex 0
342# endif
343# ifndef cpu_has_64bits
344# define cpu_has_64bits 1
345# endif
346# ifndef cpu_has_64bit_zero_reg
347# define cpu_has_64bit_zero_reg 1
348# endif
349# ifndef cpu_has_64bit_gp_regs
350# define cpu_has_64bit_gp_regs 1
351# endif
352# ifndef cpu_has_64bit_addresses
353# define cpu_has_64bit_addresses 1
354# endif
355# ifndef cpu_vmbits
356# define cpu_vmbits cpu_data[0].vmbits
357# define __NEED_VMBITS_PROBE
358# endif
359#endif
360
361#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
362# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
363#elif !defined(cpu_has_vint)
364# define cpu_has_vint 0
365#endif
366
367#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
368# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
369#elif !defined(cpu_has_veic)
370# define cpu_has_veic 0
371#endif
372
373#ifndef cpu_has_inclusive_pcaches
374#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
375#endif
376
377#ifndef cpu_dcache_line_size
378#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
379#endif
380#ifndef cpu_icache_line_size
381#define cpu_icache_line_size() cpu_data[0].icache.linesz
382#endif
383#ifndef cpu_scache_line_size
384#define cpu_scache_line_size() cpu_data[0].scache.linesz
385#endif
386
387#ifndef cpu_hwrena_impl_bits
388#define cpu_hwrena_impl_bits 0
389#endif
390
391#ifndef cpu_has_perf_cntr_intr_bit
392#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
393#endif
394
395#ifndef cpu_has_vz
396#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
397#endif
398
399#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
400# define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
401#elif !defined(cpu_has_msa)
402# define cpu_has_msa 0
403#endif
404
405#ifndef cpu_has_fre
406# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
407#endif
408
409#ifndef cpu_has_cdmm
410# define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)
411#endif
412
413#ifndef cpu_has_small_pages
414# define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP)
415#endif
416
417#ifndef cpu_has_nan_legacy
418#define cpu_has_nan_legacy (cpu_data[0].options & MIPS_CPU_NAN_LEGACY)
419#endif
420#ifndef cpu_has_nan_2008
421#define cpu_has_nan_2008 (cpu_data[0].options & MIPS_CPU_NAN_2008)
422#endif
423
424#endif /* __ASM_CPU_FEATURES_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H
11
12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h>
15
16#ifndef current_cpu_type
17#define current_cpu_type() current_cpu_data.cputype
18#endif
19
20/*
21 * SMP assumption: Options of CPU 0 are a superset of all processors.
22 * This is true for all known MIPS systems.
23 */
24#ifndef cpu_has_tlb
25#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
26#endif
27#ifndef cpu_has_4kex
28#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
29#endif
30#ifndef cpu_has_3k_cache
31#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
32#endif
33#define cpu_has_6k_cache 0
34#define cpu_has_8k_cache 0
35#ifndef cpu_has_4k_cache
36#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
37#endif
38#ifndef cpu_has_tx39_cache
39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
40#endif
41#ifndef cpu_has_octeon_cache
42#define cpu_has_octeon_cache 0
43#endif
44#ifndef cpu_has_fpu
45#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
46#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
47#else
48#define raw_cpu_has_fpu cpu_has_fpu
49#endif
50#ifndef cpu_has_32fpr
51#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
52#endif
53#ifndef cpu_has_counter
54#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
55#endif
56#ifndef cpu_has_watch
57#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
58#endif
59#ifndef cpu_has_divec
60#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
61#endif
62#ifndef cpu_has_vce
63#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
64#endif
65#ifndef cpu_has_cache_cdex_p
66#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
67#endif
68#ifndef cpu_has_cache_cdex_s
69#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
70#endif
71#ifndef cpu_has_prefetch
72#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
73#endif
74#ifndef cpu_has_mcheck
75#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
76#endif
77#ifndef cpu_has_ejtag
78#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
79#endif
80#ifndef cpu_has_llsc
81#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
82#endif
83#ifndef kernel_uses_llsc
84#define kernel_uses_llsc cpu_has_llsc
85#endif
86#ifndef cpu_has_mips16
87#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
88#endif
89#ifndef cpu_has_mdmx
90#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
91#endif
92#ifndef cpu_has_mips3d
93#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
94#endif
95#ifndef cpu_has_smartmips
96#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
97#endif
98#ifndef kernel_uses_smartmips_rixi
99#define kernel_uses_smartmips_rixi 0
100#endif
101#ifndef cpu_has_vtag_icache
102#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
103#endif
104#ifndef cpu_has_dc_aliases
105#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
106#endif
107#ifndef cpu_has_ic_fills_f_dc
108#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
109#endif
110#ifndef cpu_has_pindexed_dcache
111#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
112#endif
113
114/*
115 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
116 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
117 * don't. For maintaining I-cache coherency this means we need to flush the
118 * D-cache all the way back to whever the I-cache does refills from, so the
119 * I-cache has a chance to see the new data at all. Then we have to flush the
120 * I-cache also.
121 * Note we may have been rescheduled and may no longer be running on the CPU
122 * that did the store so we can't optimize this into only doing the flush on
123 * the local CPU.
124 */
125#ifndef cpu_icache_snoops_remote_store
126#ifdef CONFIG_SMP
127#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
128#else
129#define cpu_icache_snoops_remote_store 1
130#endif
131#endif
132
133# ifndef cpu_has_mips32r1
134# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
135# endif
136# ifndef cpu_has_mips32r2
137# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
138# endif
139# ifndef cpu_has_mips64r1
140# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
141# endif
142# ifndef cpu_has_mips64r2
143# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
144# endif
145
146/*
147 * Shortcuts ...
148 */
149#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
150#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
151#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
152#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
153#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
154 cpu_has_mips64r1 | cpu_has_mips64r2)
155
156#ifndef cpu_has_mips_r2_exec_hazard
157#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
158#endif
159
160/*
161 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
162 * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
163 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
164 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
165 */
166# ifndef cpu_has_clo_clz
167# define cpu_has_clo_clz cpu_has_mips_r
168# endif
169
170#ifndef cpu_has_dsp
171#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
172#endif
173
174#ifndef cpu_has_mipsmt
175#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
176#endif
177
178#ifndef cpu_has_userlocal
179#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
180#endif
181
182#ifdef CONFIG_32BIT
183# ifndef cpu_has_nofpuex
184# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
185# endif
186# ifndef cpu_has_64bits
187# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
188# endif
189# ifndef cpu_has_64bit_zero_reg
190# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
191# endif
192# ifndef cpu_has_64bit_gp_regs
193# define cpu_has_64bit_gp_regs 0
194# endif
195# ifndef cpu_has_64bit_addresses
196# define cpu_has_64bit_addresses 0
197# endif
198# ifndef cpu_vmbits
199# define cpu_vmbits 31
200# endif
201#endif
202
203#ifdef CONFIG_64BIT
204# ifndef cpu_has_nofpuex
205# define cpu_has_nofpuex 0
206# endif
207# ifndef cpu_has_64bits
208# define cpu_has_64bits 1
209# endif
210# ifndef cpu_has_64bit_zero_reg
211# define cpu_has_64bit_zero_reg 1
212# endif
213# ifndef cpu_has_64bit_gp_regs
214# define cpu_has_64bit_gp_regs 1
215# endif
216# ifndef cpu_has_64bit_addresses
217# define cpu_has_64bit_addresses 1
218# endif
219# ifndef cpu_vmbits
220# define cpu_vmbits cpu_data[0].vmbits
221# define __NEED_VMBITS_PROBE
222# endif
223#endif
224
225#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
226# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
227#elif !defined(cpu_has_vint)
228# define cpu_has_vint 0
229#endif
230
231#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
232# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
233#elif !defined(cpu_has_veic)
234# define cpu_has_veic 0
235#endif
236
237#ifndef cpu_has_inclusive_pcaches
238#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
239#endif
240
241#ifndef cpu_dcache_line_size
242#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
243#endif
244#ifndef cpu_icache_line_size
245#define cpu_icache_line_size() cpu_data[0].icache.linesz
246#endif
247#ifndef cpu_scache_line_size
248#define cpu_scache_line_size() cpu_data[0].scache.linesz
249#endif
250
251#ifndef cpu_hwrena_impl_bits
252#define cpu_hwrena_impl_bits 0
253#endif
254
255#endif /* __ASM_CPU_FEATURES_H */