1/*
   2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
   3 *
   4 * Multi-channel Audio Serial Port Driver
   5 *
   6 * Author: Nirmal Pandey <n-pandey@ti.com>,
   7 *         Suresh Rajashekara <suresh.r@ti.com>
   8 *         Steve Chen <schen@.mvista.com>
   9 *
  10 * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
  11 * Copyright:   (C) 2009  Texas Instruments, India
  12 *
  13 * This program is free software; you can redistribute it and/or modify
  14 * it under the terms of the GNU General Public License version 2 as
  15 * published by the Free Software Foundation.
  16 */
  17
  18#include <linux/init.h>
  19#include <linux/module.h>
  20#include <linux/device.h>
  21#include <linux/slab.h>
  22#include <linux/delay.h>
  23#include <linux/io.h>
  24#include <linux/clk.h>
  25#include <linux/pm_runtime.h>
  26#include <linux/of.h>
  27#include <linux/of_platform.h>
  28#include <linux/of_device.h>
  29#include <linux/platform_data/davinci_asp.h>
  30#include <linux/math64.h>
  31
  32#include <sound/asoundef.h>
  33#include <sound/core.h>
  34#include <sound/pcm.h>
  35#include <sound/pcm_params.h>
  36#include <sound/initval.h>
  37#include <sound/soc.h>
  38#include <sound/dmaengine_pcm.h>
  39#include <sound/omap-pcm.h>
  40
  41#include "edma-pcm.h"
  42#include "davinci-mcasp.h"
  43
  44#define MCASP_MAX_AFIFO_DEPTH	64
  45
  46static u32 context_regs[] = {
  47	DAVINCI_MCASP_TXFMCTL_REG,
  48	DAVINCI_MCASP_RXFMCTL_REG,
  49	DAVINCI_MCASP_TXFMT_REG,
  50	DAVINCI_MCASP_RXFMT_REG,
  51	DAVINCI_MCASP_ACLKXCTL_REG,
  52	DAVINCI_MCASP_ACLKRCTL_REG,
  53	DAVINCI_MCASP_AHCLKXCTL_REG,
  54	DAVINCI_MCASP_AHCLKRCTL_REG,
  55	DAVINCI_MCASP_PDIR_REG,
  56	DAVINCI_MCASP_RXMASK_REG,
  57	DAVINCI_MCASP_TXMASK_REG,
  58	DAVINCI_MCASP_RXTDM_REG,
  59	DAVINCI_MCASP_TXTDM_REG,
  60};
  61
  62struct davinci_mcasp_context {
  63	u32	config_regs[ARRAY_SIZE(context_regs)];
  64	u32	afifo_regs[2]; /* for read/write fifo control registers */
  65	u32	*xrsr_regs; /* for serializer configuration */
  66	bool	pm_state;
  67};
  68
  69struct davinci_mcasp_ruledata {
  70	struct davinci_mcasp *mcasp;
  71	int serializers;
  72};
  73
  74struct davinci_mcasp {
 
  75	struct snd_dmaengine_dai_dma_data dma_data[2];
  76	void __iomem *base;
  77	u32 fifo_base;
  78	struct device *dev;
  79	struct snd_pcm_substream *substreams[2];
  80	unsigned int dai_fmt;
  81
  82	/* McASP specific data */
  83	int	tdm_slots;
  84	u32	tdm_mask[2];
  85	int	slot_width;
  86	u8	op_mode;
  87	u8	num_serializer;
  88	u8	*serial_dir;
  89	u8	version;
  90	u8	bclk_div;
  91	int	streams;
  92	u32	irq_request[2];
  93	int	dma_request[2];
  94
  95	int	sysclk_freq;
  96	bool	bclk_master;
  97
  98	/* McASP FIFO related */
  99	u8	txnumevt;
 100	u8	rxnumevt;
 101
 102	bool	dat_port;
 103
 104	/* Used for comstraint setting on the second stream */
 105	u32	channels;
 106
 107#ifdef CONFIG_PM_SLEEP
 108	struct davinci_mcasp_context context;
 109#endif
 110
 111	struct davinci_mcasp_ruledata ruledata[2];
 112	struct snd_pcm_hw_constraint_list chconstr[2];
 113};
 114
 115static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
 116				  u32 val)
 117{
 118	void __iomem *reg = mcasp->base + offset;
 119	__raw_writel(__raw_readl(reg) | val, reg);
 120}
 121
 122static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
 123				  u32 val)
 124{
 125	void __iomem *reg = mcasp->base + offset;
 126	__raw_writel((__raw_readl(reg) & ~(val)), reg);
 127}
 128
 129static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
 130				  u32 val, u32 mask)
 131{
 132	void __iomem *reg = mcasp->base + offset;
 133	__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
 134}
 135
 136static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
 137				 u32 val)
 138{
 139	__raw_writel(val, mcasp->base + offset);
 140}
 141
 142static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
 143{
 144	return (u32)__raw_readl(mcasp->base + offset);
 145}
 146
 147static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
 148{
 149	int i = 0;
 150
 151	mcasp_set_bits(mcasp, ctl_reg, val);
 152
 153	/* programming GBLCTL needs to read back from GBLCTL and verfiy */
 154	/* loop count is to avoid the lock-up */
 155	for (i = 0; i < 1000; i++) {
 156		if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
 157			break;
 158	}
 159
 160	if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
 161		printk(KERN_ERR "GBLCTL write error\n");
 162}
 163
 164static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
 165{
 166	u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
 167	u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
 168
 169	return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
 170}
 171
 172static void mcasp_start_rx(struct davinci_mcasp *mcasp)
 173{
 174	if (mcasp->rxnumevt) {	/* enable FIFO */
 175		u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
 176
 177		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
 178		mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
 179	}
 180
 181	/* Start clocks */
 182	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
 183	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
 
 184	/*
 185	 * When ASYNC == 0 the transmit and receive sections operate
 186	 * synchronously from the transmit clock and frame sync. We need to make
 187	 * sure that the TX signlas are enabled when starting reception.
 188	 */
 189	if (mcasp_is_synchronous(mcasp)) {
 190		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
 191		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
 192	}
 193
 194	/* Activate serializer(s) */
 195	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
 196	/* Release RX state machine */
 
 197	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
 198	/* Release Frame Sync generator */
 199	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
 
 
 
 
 
 200	if (mcasp_is_synchronous(mcasp))
 201		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
 202
 203	/* enable receive IRQs */
 204	mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
 205		       mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
 206}
 207
 208static void mcasp_start_tx(struct davinci_mcasp *mcasp)
 209{
 
 210	u32 cnt;
 211
 212	if (mcasp->txnumevt) {	/* enable FIFO */
 213		u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
 214
 215		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
 216		mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
 217	}
 218
 219	/* Start clocks */
 220	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
 221	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
 222	/* Activate serializer(s) */
 223	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
 
 224
 225	/* wait for XDATA to be cleared */
 226	cnt = 0;
 227	while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
 228	       (cnt < 100000))
 229		cnt++;
 230
 231	/* Release TX state machine */
 232	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
 233	/* Release Frame Sync generator */
 234	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
 
 
 
 
 
 
 
 
 
 
 
 
 
 235
 236	/* enable transmit IRQs */
 237	mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
 238		       mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
 239}
 240
 241static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
 242{
 
 
 243	mcasp->streams++;
 244
 245	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 
 
 
 
 
 246		mcasp_start_tx(mcasp);
 247	else
 
 
 
 
 
 248		mcasp_start_rx(mcasp);
 
 249}
 250
 251static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
 252{
 253	/* disable IRQ sources */
 254	mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
 255		       mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
 256
 257	/*
 258	 * In synchronous mode stop the TX clocks if no other stream is
 259	 * running
 260	 */
 261	if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
 262		mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
 263
 264	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
 265	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
 266
 267	if (mcasp->rxnumevt) {	/* disable FIFO */
 268		u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
 269
 270		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
 271	}
 272}
 273
 274static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
 275{
 276	u32 val = 0;
 277
 278	/* disable IRQ sources */
 279	mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
 280		       mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
 281
 282	/*
 283	 * In synchronous mode keep TX clocks running if the capture stream is
 284	 * still running.
 285	 */
 286	if (mcasp_is_synchronous(mcasp) && mcasp->streams)
 287		val =  TXHCLKRST | TXCLKRST | TXFSRST;
 288
 289	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
 290	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
 291
 292	if (mcasp->txnumevt) {	/* disable FIFO */
 293		u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
 294
 295		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
 296	}
 297}
 298
 299static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
 300{
 301	mcasp->streams--;
 302
 303	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 304		mcasp_stop_tx(mcasp);
 305	else
 306		mcasp_stop_rx(mcasp);
 307}
 308
 309static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
 310{
 311	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
 312	struct snd_pcm_substream *substream;
 313	u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
 314	u32 handled_mask = 0;
 315	u32 stat;
 316
 317	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
 318	if (stat & XUNDRN & irq_mask) {
 319		dev_warn(mcasp->dev, "Transmit buffer underflow\n");
 320		handled_mask |= XUNDRN;
 321
 322		substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
 323		if (substream) {
 324			snd_pcm_stream_lock_irq(substream);
 325			if (snd_pcm_running(substream))
 326				snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
 327			snd_pcm_stream_unlock_irq(substream);
 328		}
 329	}
 330
 331	if (!handled_mask)
 332		dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
 333			 stat);
 334
 335	if (stat & XRERR)
 336		handled_mask |= XRERR;
 337
 338	/* Ack the handled event only */
 339	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
 340
 341	return IRQ_RETVAL(handled_mask);
 342}
 343
 344static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
 345{
 346	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
 347	struct snd_pcm_substream *substream;
 348	u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
 349	u32 handled_mask = 0;
 350	u32 stat;
 351
 352	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
 353	if (stat & ROVRN & irq_mask) {
 354		dev_warn(mcasp->dev, "Receive buffer overflow\n");
 355		handled_mask |= ROVRN;
 356
 357		substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
 358		if (substream) {
 359			snd_pcm_stream_lock_irq(substream);
 360			if (snd_pcm_running(substream))
 361				snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
 362			snd_pcm_stream_unlock_irq(substream);
 363		}
 
 364	}
 365
 366	if (!handled_mask)
 367		dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
 368			 stat);
 369
 370	if (stat & XRERR)
 371		handled_mask |= XRERR;
 372
 373	/* Ack the handled event only */
 374	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
 375
 376	return IRQ_RETVAL(handled_mask);
 377}
 378
 379static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
 380{
 381	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
 382	irqreturn_t ret = IRQ_NONE;
 383
 384	if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
 385		ret = davinci_mcasp_tx_irq_handler(irq, data);
 386
 387	if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
 388		ret |= davinci_mcasp_rx_irq_handler(irq, data);
 389
 390	return ret;
 391}
 392
 393static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 394					 unsigned int fmt)
 395{
 396	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
 397	int ret = 0;
 398	u32 data_delay;
 399	bool fs_pol_rising;
 400	bool inv_fs = false;
 401
 402	if (!fmt)
 403		return 0;
 404
 405	pm_runtime_get_sync(mcasp->dev);
 406	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 407	case SND_SOC_DAIFMT_DSP_A:
 408		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
 409		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
 410		/* 1st data bit occur one ACLK cycle after the frame sync */
 411		data_delay = 1;
 412		break;
 413	case SND_SOC_DAIFMT_DSP_B:
 414	case SND_SOC_DAIFMT_AC97:
 415		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
 416		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
 417		/* No delay after FS */
 418		data_delay = 0;
 419		break;
 420	case SND_SOC_DAIFMT_I2S:
 421		/* configure a full-word SYNC pulse (LRCLK) */
 422		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
 423		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
 424		/* 1st data bit occur one ACLK cycle after the frame sync */
 425		data_delay = 1;
 426		/* FS need to be inverted */
 427		inv_fs = true;
 428		break;
 429	case SND_SOC_DAIFMT_LEFT_J:
 430		/* configure a full-word SYNC pulse (LRCLK) */
 431		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
 432		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
 433		/* No delay after FS */
 434		data_delay = 0;
 
 
 435		break;
 436	default:
 437		ret = -EINVAL;
 438		goto out;
 439	}
 440
 441	mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
 442		       FSXDLY(3));
 443	mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
 444		       FSRDLY(3));
 445
 446	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 447	case SND_SOC_DAIFMT_CBS_CFS:
 448		/* codec is clock and frame slave */
 449		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
 450		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
 451
 452		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
 453		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
 454
 455		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
 456		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
 457		mcasp->bclk_master = 1;
 458		break;
 459	case SND_SOC_DAIFMT_CBS_CFM:
 460		/* codec is clock slave and frame master */
 461		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
 462		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
 463
 464		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
 465		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
 466
 467		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
 468		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
 469		mcasp->bclk_master = 1;
 470		break;
 471	case SND_SOC_DAIFMT_CBM_CFS:
 472		/* codec is clock master and frame slave */
 473		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
 474		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
 475
 476		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
 477		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
 478
 479		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
 480		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
 481		mcasp->bclk_master = 0;
 482		break;
 483	case SND_SOC_DAIFMT_CBM_CFM:
 484		/* codec is clock and frame master */
 485		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
 486		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
 487
 488		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
 489		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
 490
 491		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
 492			       ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
 493		mcasp->bclk_master = 0;
 494		break;
 
 495	default:
 496		ret = -EINVAL;
 497		goto out;
 498	}
 499
 500	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 501	case SND_SOC_DAIFMT_IB_NF:
 502		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
 
 
 503		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
 504		fs_pol_rising = true;
 505		break;
 
 506	case SND_SOC_DAIFMT_NB_IF:
 507		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
 
 
 508		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
 509		fs_pol_rising = false;
 510		break;
 
 511	case SND_SOC_DAIFMT_IB_IF:
 512		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
 
 
 513		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
 514		fs_pol_rising = false;
 515		break;
 
 516	case SND_SOC_DAIFMT_NB_NF:
 517		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
 
 
 518		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
 519		fs_pol_rising = true;
 520		break;
 
 521	default:
 522		ret = -EINVAL;
 523		goto out;
 524	}
 525
 526	if (inv_fs)
 527		fs_pol_rising = !fs_pol_rising;
 528
 529	if (fs_pol_rising) {
 530		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
 531		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
 532	} else {
 533		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
 534		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
 535	}
 536
 537	mcasp->dai_fmt = fmt;
 538out:
 539	pm_runtime_put(mcasp->dev);
 540	return ret;
 541}
 542
 543static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
 544				      int div, bool explicit)
 545{
 546	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
 547
 548	pm_runtime_get_sync(mcasp->dev);
 549	switch (div_id) {
 550	case 0:		/* MCLK divider */
 551		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
 552			       AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
 553		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
 554			       AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
 555		break;
 556
 557	case 1:		/* BCLK divider */
 558		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
 559			       ACLKXDIV(div - 1), ACLKXDIV_MASK);
 560		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
 561			       ACLKRDIV(div - 1), ACLKRDIV_MASK);
 562		if (explicit)
 563			mcasp->bclk_div = div;
 564		break;
 565
 566	case 2:	/*
 567		 * BCLK/LRCLK ratio descries how many bit-clock cycles
 568		 * fit into one frame. The clock ratio is given for a
 569		 * full period of data (for I2S format both left and
 570		 * right channels), so it has to be divided by number
 571		 * of tdm-slots (for I2S - divided by 2).
 572		 * Instead of storing this ratio, we calculate a new
 573		 * tdm_slot width by dividing the the ratio by the
 574		 * number of configured tdm slots.
 575		 */
 576		mcasp->slot_width = div / mcasp->tdm_slots;
 577		if (div % mcasp->tdm_slots)
 578			dev_warn(mcasp->dev,
 579				 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
 580				 __func__, div, mcasp->tdm_slots);
 581		break;
 582
 583	default:
 584		return -EINVAL;
 585	}
 586
 587	pm_runtime_put(mcasp->dev);
 588	return 0;
 589}
 590
 591static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
 592				    int div)
 593{
 594	return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
 595}
 596
 597static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 598				    unsigned int freq, int dir)
 599{
 600	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
 601
 602	pm_runtime_get_sync(mcasp->dev);
 603	if (dir == SND_SOC_CLOCK_OUT) {
 604		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
 605		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
 606		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
 607	} else {
 608		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
 609		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
 610		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
 611	}
 612
 613	mcasp->sysclk_freq = freq;
 614
 615	pm_runtime_put(mcasp->dev);
 616	return 0;
 617}
 618
 619/* All serializers must have equal number of channels */
 620static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
 621				       int serializers)
 622{
 623	struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
 624	unsigned int *list = (unsigned int *) cl->list;
 625	int slots = mcasp->tdm_slots;
 626	int i, count = 0;
 627
 628	if (mcasp->tdm_mask[stream])
 629		slots = hweight32(mcasp->tdm_mask[stream]);
 630
 631	for (i = 2; i <= slots; i++)
 632		list[count++] = i;
 633
 634	for (i = 2; i <= serializers; i++)
 635		list[count++] = i*slots;
 636
 637	cl->count = count;
 638
 639	return 0;
 640}
 641
 642static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
 643{
 644	int rx_serializers = 0, tx_serializers = 0, ret, i;
 645
 646	for (i = 0; i < mcasp->num_serializer; i++)
 647		if (mcasp->serial_dir[i] == TX_MODE)
 648			tx_serializers++;
 649		else if (mcasp->serial_dir[i] == RX_MODE)
 650			rx_serializers++;
 651
 652	ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
 653					  tx_serializers);
 654	if (ret)
 655		return ret;
 656
 657	ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
 658					  rx_serializers);
 659
 660	return ret;
 661}
 662
 663
 664static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
 665				      unsigned int tx_mask,
 666				      unsigned int rx_mask,
 667				      int slots, int slot_width)
 668{
 669	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
 670
 671	dev_dbg(mcasp->dev,
 672		 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
 673		 __func__, tx_mask, rx_mask, slots, slot_width);
 674
 675	if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
 676		dev_err(mcasp->dev,
 677			"Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
 678			tx_mask, rx_mask, slots);
 679		return -EINVAL;
 680	}
 681
 682	if (slot_width &&
 683	    (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
 684		dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
 685			__func__, slot_width);
 686		return -EINVAL;
 687	}
 688
 689	mcasp->tdm_slots = slots;
 690	mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
 691	mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
 692	mcasp->slot_width = slot_width;
 693
 694	return davinci_mcasp_set_ch_constraints(mcasp);
 695}
 696
 697static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
 698				       int sample_width)
 699{
 700	u32 fmt;
 701	u32 tx_rotate = (sample_width / 4) & 0x7;
 702	u32 mask = (1ULL << sample_width) - 1;
 703	u32 slot_width = sample_width;
 704
 705	/*
 706	 * For captured data we should not rotate, inversion and masking is
 707	 * enoguh to get the data to the right position:
 708	 * Format	  data from bus		after reverse (XRBUF)
 709	 * S16_LE:	|LSB|MSB|xxx|xxx|	|xxx|xxx|MSB|LSB|
 710	 * S24_3LE:	|LSB|DAT|MSB|xxx|	|xxx|MSB|DAT|LSB|
 711	 * S24_LE:	|LSB|DAT|MSB|xxx|	|xxx|MSB|DAT|LSB|
 712	 * S32_LE:	|LSB|DAT|DAT|MSB|	|MSB|DAT|DAT|LSB|
 713	 */
 714	u32 rx_rotate = 0;
 715
 716	/*
 717	 * Setting the tdm slot width either with set_clkdiv() or
 718	 * set_tdm_slot() allows us to for example send 32 bits per
 719	 * channel to the codec, while only 16 of them carry audio
 720	 * payload.
 
 
 
 721	 */
 722	if (mcasp->slot_width) {
 723		/*
 724		 * When we have more bclk then it is needed for the
 725		 * data, we need to use the rotation to move the
 726		 * received samples to have correct alignment.
 727		 */
 728		slot_width = mcasp->slot_width;
 729		rx_rotate = (slot_width - sample_width) / 4;
 730	}
 731
 732	/* mapping of the XSSZ bit-field as described in the datasheet */
 733	fmt = (slot_width >> 1) - 1;
 734
 735	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
 736		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
 737			       RXSSZ(0x0F));
 738		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
 739			       TXSSZ(0x0F));
 740		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
 741			       TXROT(7));
 742		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
 743			       RXROT(7));
 744		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
 745	}
 746
 747	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
 748
 749	return 0;
 750}
 751
 752static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
 753				 int period_words, int channels)
 754{
 755	struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
 756	int i;
 757	u8 tx_ser = 0;
 758	u8 rx_ser = 0;
 
 759	u8 slots = mcasp->tdm_slots;
 760	u8 max_active_serializers = (channels + slots - 1) / slots;
 761	int active_serializers, numevt;
 762	u32 reg;
 763	/* Default configuration */
 764	if (mcasp->version < MCASP_VERSION_3)
 765		mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
 766
 767	/* All PINS as McASP */
 768	mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
 769
 770	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 771		mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
 772		mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
 773	} else {
 774		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
 775		mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
 776	}
 777
 778	for (i = 0; i < mcasp->num_serializer; i++) {
 779		mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
 780			       mcasp->serial_dir[i]);
 781		if (mcasp->serial_dir[i] == TX_MODE &&
 782					tx_ser < max_active_serializers) {
 783			mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
 784			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
 785				       DISMOD_LOW, DISMOD_MASK);
 786			tx_ser++;
 787		} else if (mcasp->serial_dir[i] == RX_MODE &&
 788					rx_ser < max_active_serializers) {
 789			mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
 790			rx_ser++;
 791		} else {
 792			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
 793				       SRMOD_INACTIVE, SRMOD_MASK);
 794		}
 795	}
 796
 797	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 798		active_serializers = tx_ser;
 799		numevt = mcasp->txnumevt;
 800		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
 801	} else {
 802		active_serializers = rx_ser;
 803		numevt = mcasp->rxnumevt;
 804		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
 805	}
 806
 807	if (active_serializers < max_active_serializers) {
 808		dev_warn(mcasp->dev, "stream has more channels (%d) than are "
 809			 "enabled in mcasp (%d)\n", channels,
 810			 active_serializers * slots);
 811		return -EINVAL;
 812	}
 813
 814	/* AFIFO is not in use */
 815	if (!numevt) {
 816		/* Configure the burst size for platform drivers */
 817		if (active_serializers > 1) {
 818			/*
 819			 * If more than one serializers are in use we have one
 820			 * DMA request to provide data for all serializers.
 821			 * For example if three serializers are enabled the DMA
 822			 * need to transfer three words per DMA request.
 823			 */
 824			dma_data->maxburst = active_serializers;
 825		} else {
 826			dma_data->maxburst = 0;
 827		}
 828		return 0;
 829	}
 830
 831	if (period_words % active_serializers) {
 832		dev_err(mcasp->dev, "Invalid combination of period words and "
 833			"active serializers: %d, %d\n", period_words,
 834			active_serializers);
 835		return -EINVAL;
 836	}
 837
 838	/*
 839	 * Calculate the optimal AFIFO depth for platform side:
 840	 * The number of words for numevt need to be in steps of active
 841	 * serializers.
 842	 */
 843	numevt = (numevt / active_serializers) * active_serializers;
 844
 845	while (period_words % numevt && numevt > 0)
 846		numevt -= active_serializers;
 847	if (numevt <= 0)
 848		numevt = active_serializers;
 849
 850	mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
 851	mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
 852
 853	/* Configure the burst size for platform drivers */
 854	if (numevt == 1)
 855		numevt = 0;
 856	dma_data->maxburst = numevt;
 857
 858	return 0;
 859}
 860
 861static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
 862			      int channels)
 863{
 864	int i, active_slots;
 865	int total_slots;
 866	int active_serializers;
 867	u32 mask = 0;
 868	u32 busel = 0;
 869
 870	total_slots = mcasp->tdm_slots;
 
 
 
 
 871
 872	/*
 873	 * If more than one serializer is needed, then use them with
 874	 * all the specified tdm_slots. Otherwise, one serializer can
 875	 * cope with the transaction using just as many slots as there
 876	 * are channels in the stream.
 877	 */
 878	if (mcasp->tdm_mask[stream]) {
 879		active_slots = hweight32(mcasp->tdm_mask[stream]);
 880		active_serializers = (channels + active_slots - 1) /
 881			active_slots;
 882		if (active_serializers == 1) {
 883			active_slots = channels;
 884			for (i = 0; i < total_slots; i++) {
 885				if ((1 << i) & mcasp->tdm_mask[stream]) {
 886					mask |= (1 << i);
 887					if (--active_slots <= 0)
 888						break;
 889				}
 890			}
 891		}
 892	} else {
 893		active_serializers = (channels + total_slots - 1) / total_slots;
 894		if (active_serializers == 1)
 895			active_slots = channels;
 896		else
 897			active_slots = total_slots;
 898
 899		for (i = 0; i < active_slots; i++)
 900			mask |= (1 << i);
 901	}
 902	mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
 903
 904	if (!mcasp->dat_port)
 905		busel = TXSEL;
 906
 907	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 908		mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
 909		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
 910		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
 911			       FSXMOD(total_slots), FSXMOD(0x1FF));
 912	} else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
 913		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
 914		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
 915		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
 916			       FSRMOD(total_slots), FSRMOD(0x1FF));
 917		/*
 918		 * If McASP is set to be TX/RX synchronous and the playback is
 919		 * not running already we need to configure the TX slots in
 920		 * order to have correct FSX on the bus
 921		 */
 922		if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
 923			mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
 924				       FSXMOD(total_slots), FSXMOD(0x1FF));
 925	}
 926
 927	return 0;
 928}
 929
 930/* S/PDIF */
 931static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
 932			      unsigned int rate)
 933{
 934	u32 cs_value = 0;
 935	u8 *cs_bytes = (u8*) &cs_value;
 936
 937	/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
 938	   and LSB first */
 939	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
 940
 941	/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
 942	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
 943
 944	/* Set the TX tdm : for all the slots */
 945	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
 946
 947	/* Set the TX clock controls : div = 1 and internal */
 948	mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
 949
 950	mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
 951
 952	/* Only 44100 and 48000 are valid, both have the same setting */
 953	mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
 954
 955	/* Enable the DIT */
 956	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
 957
 958	/* Set S/PDIF channel status bits */
 959	cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
 960	cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
 961
 962	switch (rate) {
 963	case 22050:
 964		cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
 965		break;
 966	case 24000:
 967		cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
 968		break;
 969	case 32000:
 970		cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
 971		break;
 972	case 44100:
 973		cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
 974		break;
 975	case 48000:
 976		cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
 977		break;
 978	case 88200:
 979		cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
 980		break;
 981	case 96000:
 982		cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
 983		break;
 984	case 176400:
 985		cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
 986		break;
 987	case 192000:
 988		cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
 989		break;
 990	default:
 991		printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
 992		return -EINVAL;
 993	}
 994
 995	mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
 996	mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
 997
 998	return 0;
 999}
1000
1001static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1002				      unsigned int bclk_freq,
1003				      int *error_ppm)
1004{
1005	int div = mcasp->sysclk_freq / bclk_freq;
1006	int rem = mcasp->sysclk_freq % bclk_freq;
1007
1008	if (rem != 0) {
1009		if (div == 0 ||
1010		    ((mcasp->sysclk_freq / div) - bclk_freq) >
1011		    (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
1012			div++;
1013			rem = rem - bclk_freq;
1014		}
1015	}
1016	if (error_ppm)
1017		*error_ppm =
1018			(div*1000000 + (int)div64_long(1000000LL*rem,
1019						       (int)bclk_freq))
1020			/div - 1000000;
1021
1022	return div;
1023}
1024
1025static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1026					struct snd_pcm_hw_params *params,
1027					struct snd_soc_dai *cpu_dai)
1028{
1029	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
 
 
 
 
1030	int word_length;
 
 
 
1031	int channels = params_channels(params);
1032	int period_size = params_period_size(params);
1033	int ret;
1034
1035	ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1036	if (ret)
1037		return ret;
1038
1039	/*
1040	 * If mcasp is BCLK master, and a BCLK divider was not provided by
1041	 * the machine driver, we need to calculate the ratio.
1042	 */
1043	if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1044		int slots = mcasp->tdm_slots;
1045		int rate = params_rate(params);
1046		int sbits = params_width(params);
1047		int ppm, div;
1048
1049		if (mcasp->slot_width)
1050			sbits = mcasp->slot_width;
1051
1052		div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
1053						 &ppm);
1054		if (ppm)
1055			dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1056				 ppm);
1057
1058		__davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
1059	}
1060
1061	ret = mcasp_common_hw_param(mcasp, substream->stream,
1062				    period_size * channels, channels);
1063	if (ret)
1064		return ret;
1065
1066	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1067		ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1068	else
1069		ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1070					 channels);
1071
1072	if (ret)
1073		return ret;
1074
1075	switch (params_format(params)) {
1076	case SNDRV_PCM_FORMAT_U8:
1077	case SNDRV_PCM_FORMAT_S8:
 
1078		word_length = 8;
1079		break;
1080
1081	case SNDRV_PCM_FORMAT_U16_LE:
1082	case SNDRV_PCM_FORMAT_S16_LE:
 
1083		word_length = 16;
1084		break;
1085
1086	case SNDRV_PCM_FORMAT_U24_3LE:
1087	case SNDRV_PCM_FORMAT_S24_3LE:
 
1088		word_length = 24;
1089		break;
1090
1091	case SNDRV_PCM_FORMAT_U24_LE:
1092	case SNDRV_PCM_FORMAT_S24_LE:
1093		word_length = 24;
1094		break;
1095
1096	case SNDRV_PCM_FORMAT_U32_LE:
1097	case SNDRV_PCM_FORMAT_S32_LE:
 
1098		word_length = 32;
1099		break;
1100
1101	default:
1102		printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1103		return -EINVAL;
1104	}
1105
1106	davinci_config_channel_size(mcasp, word_length);
 
 
 
 
 
 
 
 
 
 
 
 
 
1107
1108	if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1109		mcasp->channels = channels;
1110
1111	return 0;
1112}
1113
1114static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1115				     int cmd, struct snd_soc_dai *cpu_dai)
1116{
1117	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1118	int ret = 0;
1119
1120	switch (cmd) {
1121	case SNDRV_PCM_TRIGGER_RESUME:
1122	case SNDRV_PCM_TRIGGER_START:
1123	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1124		davinci_mcasp_start(mcasp, substream->stream);
1125		break;
1126	case SNDRV_PCM_TRIGGER_SUSPEND:
1127	case SNDRV_PCM_TRIGGER_STOP:
1128	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1129		davinci_mcasp_stop(mcasp, substream->stream);
1130		break;
1131
1132	default:
1133		ret = -EINVAL;
1134	}
1135
1136	return ret;
1137}
1138
1139static const unsigned int davinci_mcasp_dai_rates[] = {
1140	8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1141	88200, 96000, 176400, 192000,
1142};
1143
1144#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1145
1146static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1147				      struct snd_pcm_hw_rule *rule)
1148{
1149	struct davinci_mcasp_ruledata *rd = rule->private;
1150	struct snd_interval *ri =
1151		hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1152	int sbits = params_width(params);
1153	int slots = rd->mcasp->tdm_slots;
1154	struct snd_interval range;
1155	int i;
1156
1157	if (rd->mcasp->slot_width)
1158		sbits = rd->mcasp->slot_width;
1159
1160	snd_interval_any(&range);
1161	range.empty = 1;
1162
1163	for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1164		if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1165			uint bclk_freq = sbits*slots*
1166				davinci_mcasp_dai_rates[i];
1167			int ppm;
1168
1169			davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1170			if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1171				if (range.empty) {
1172					range.min = davinci_mcasp_dai_rates[i];
1173					range.empty = 0;
1174				}
1175				range.max = davinci_mcasp_dai_rates[i];
1176			}
1177		}
1178	}
1179
1180	dev_dbg(rd->mcasp->dev,
1181		"Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1182		ri->min, ri->max, range.min, range.max, sbits, slots);
1183
1184	return snd_interval_refine(hw_param_interval(params, rule->var),
1185				   &range);
1186}
1187
1188static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1189					struct snd_pcm_hw_rule *rule)
1190{
1191	struct davinci_mcasp_ruledata *rd = rule->private;
1192	struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1193	struct snd_mask nfmt;
1194	int rate = params_rate(params);
1195	int slots = rd->mcasp->tdm_slots;
1196	int i, count = 0;
1197
1198	snd_mask_none(&nfmt);
1199
1200	for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1201		if (snd_mask_test(fmt, i)) {
1202			uint sbits = snd_pcm_format_width(i);
1203			int ppm;
1204
1205			if (rd->mcasp->slot_width)
1206				sbits = rd->mcasp->slot_width;
1207
1208			davinci_mcasp_calc_clk_div(rd->mcasp, sbits*slots*rate,
1209						   &ppm);
1210			if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1211				snd_mask_set(&nfmt, i);
1212				count++;
1213			}
1214		}
1215	}
1216	dev_dbg(rd->mcasp->dev,
1217		"%d possible sample format for %d Hz and %d tdm slots\n",
1218		count, rate, slots);
1219
1220	return snd_mask_refine(fmt, &nfmt);
1221}
1222
1223static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1224				 struct snd_soc_dai *cpu_dai)
1225{
1226	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1227	struct davinci_mcasp_ruledata *ruledata =
1228					&mcasp->ruledata[substream->stream];
1229	u32 max_channels = 0;
1230	int i, dir;
1231	int tdm_slots = mcasp->tdm_slots;
1232
1233	if (mcasp->tdm_mask[substream->stream])
1234		tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1235
1236	mcasp->substreams[substream->stream] = substream;
1237
1238	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1239		return 0;
1240
1241	/*
1242	 * Limit the maximum allowed channels for the first stream:
1243	 * number of serializers for the direction * tdm slots per serializer
1244	 */
1245	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1246		dir = TX_MODE;
1247	else
1248		dir = RX_MODE;
1249
1250	for (i = 0; i < mcasp->num_serializer; i++) {
1251		if (mcasp->serial_dir[i] == dir)
1252			max_channels++;
1253	}
1254	ruledata->serializers = max_channels;
1255	max_channels *= tdm_slots;
1256	/*
1257	 * If the already active stream has less channels than the calculated
1258	 * limnit based on the seirializers * tdm_slots, we need to use that as
1259	 * a constraint for the second stream.
1260	 * Otherwise (first stream or less allowed channels) we use the
1261	 * calculated constraint.
1262	 */
1263	if (mcasp->channels && mcasp->channels < max_channels)
1264		max_channels = mcasp->channels;
1265	/*
1266	 * But we can always allow channels upto the amount of
1267	 * the available tdm_slots.
1268	 */
1269	if (max_channels < tdm_slots)
1270		max_channels = tdm_slots;
1271
1272	snd_pcm_hw_constraint_minmax(substream->runtime,
1273				     SNDRV_PCM_HW_PARAM_CHANNELS,
1274				     2, max_channels);
1275
1276	snd_pcm_hw_constraint_list(substream->runtime,
1277				   0, SNDRV_PCM_HW_PARAM_CHANNELS,
1278				   &mcasp->chconstr[substream->stream]);
1279
1280	if (mcasp->slot_width)
1281		snd_pcm_hw_constraint_minmax(substream->runtime,
1282					     SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1283					     8, mcasp->slot_width);
1284
1285	/*
1286	 * If we rely on implicit BCLK divider setting we should
1287	 * set constraints based on what we can provide.
1288	 */
1289	if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1290		int ret;
1291
1292		ruledata->mcasp = mcasp;
1293
1294		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1295					  SNDRV_PCM_HW_PARAM_RATE,
1296					  davinci_mcasp_hw_rule_rate,
1297					  ruledata,
1298					  SNDRV_PCM_HW_PARAM_FORMAT, -1);
1299		if (ret)
1300			return ret;
1301		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1302					  SNDRV_PCM_HW_PARAM_FORMAT,
1303					  davinci_mcasp_hw_rule_format,
1304					  ruledata,
1305					  SNDRV_PCM_HW_PARAM_RATE, -1);
1306		if (ret)
1307			return ret;
1308	}
1309
1310	return 0;
1311}
1312
1313static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1314				   struct snd_soc_dai *cpu_dai)
1315{
1316	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1317
1318	mcasp->substreams[substream->stream] = NULL;
1319
1320	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1321		return;
1322
1323	if (!cpu_dai->active)
1324		mcasp->channels = 0;
1325}
1326
1327static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1328	.startup	= davinci_mcasp_startup,
1329	.shutdown	= davinci_mcasp_shutdown,
1330	.trigger	= davinci_mcasp_trigger,
1331	.hw_params	= davinci_mcasp_hw_params,
1332	.set_fmt	= davinci_mcasp_set_dai_fmt,
1333	.set_clkdiv	= davinci_mcasp_set_clkdiv,
1334	.set_sysclk	= davinci_mcasp_set_sysclk,
1335	.set_tdm_slot	= davinci_mcasp_set_tdm_slot,
1336};
1337
1338static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1339{
1340	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1341
1342	dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1343	dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1344
1345	return 0;
1346}
1347
1348#ifdef CONFIG_PM_SLEEP
1349static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1350{
1351	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1352	struct davinci_mcasp_context *context = &mcasp->context;
1353	u32 reg;
1354	int i;
1355
1356	context->pm_state = pm_runtime_active(mcasp->dev);
1357	if (!context->pm_state)
1358		pm_runtime_get_sync(mcasp->dev);
1359
1360	for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1361		context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1362
1363	if (mcasp->txnumevt) {
1364		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1365		context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1366	}
1367	if (mcasp->rxnumevt) {
1368		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1369		context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1370	}
1371
1372	for (i = 0; i < mcasp->num_serializer; i++)
1373		context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1374						DAVINCI_MCASP_XRSRCTL_REG(i));
1375
1376	pm_runtime_put_sync(mcasp->dev);
1377
1378	return 0;
1379}
1380
1381static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1382{
1383	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1384	struct davinci_mcasp_context *context = &mcasp->context;
1385	u32 reg;
1386	int i;
1387
1388	pm_runtime_get_sync(mcasp->dev);
1389
1390	for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1391		mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1392
1393	if (mcasp->txnumevt) {
1394		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1395		mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1396	}
1397	if (mcasp->rxnumevt) {
1398		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1399		mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1400	}
1401
1402	for (i = 0; i < mcasp->num_serializer; i++)
1403		mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1404			      context->xrsr_regs[i]);
1405
1406	if (!context->pm_state)
1407		pm_runtime_put_sync(mcasp->dev);
 
 
 
 
 
1408
1409	return 0;
1410}
1411#else
1412#define davinci_mcasp_suspend NULL
1413#define davinci_mcasp_resume NULL
1414#endif
1415
1416#define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_192000
1417
1418#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1419				SNDRV_PCM_FMTBIT_U8 | \
1420				SNDRV_PCM_FMTBIT_S16_LE | \
1421				SNDRV_PCM_FMTBIT_U16_LE | \
1422				SNDRV_PCM_FMTBIT_S24_LE | \
1423				SNDRV_PCM_FMTBIT_U24_LE | \
1424				SNDRV_PCM_FMTBIT_S24_3LE | \
1425				SNDRV_PCM_FMTBIT_U24_3LE | \
1426				SNDRV_PCM_FMTBIT_S32_LE | \
1427				SNDRV_PCM_FMTBIT_U32_LE)
1428
1429static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1430	{
1431		.name		= "davinci-mcasp.0",
1432		.probe		= davinci_mcasp_dai_probe,
1433		.suspend	= davinci_mcasp_suspend,
1434		.resume		= davinci_mcasp_resume,
1435		.playback	= {
1436			.channels_min	= 2,
1437			.channels_max	= 32 * 16,
1438			.rates 		= DAVINCI_MCASP_RATES,
1439			.formats	= DAVINCI_MCASP_PCM_FMTS,
1440		},
1441		.capture 	= {
1442			.channels_min 	= 2,
1443			.channels_max	= 32 * 16,
1444			.rates 		= DAVINCI_MCASP_RATES,
1445			.formats	= DAVINCI_MCASP_PCM_FMTS,
1446		},
1447		.ops 		= &davinci_mcasp_dai_ops,
1448
1449		.symmetric_samplebits	= 1,
1450		.symmetric_rates	= 1,
1451	},
1452	{
1453		.name		= "davinci-mcasp.1",
1454		.probe		= davinci_mcasp_dai_probe,
1455		.playback 	= {
1456			.channels_min	= 1,
1457			.channels_max	= 384,
1458			.rates		= DAVINCI_MCASP_RATES,
1459			.formats	= DAVINCI_MCASP_PCM_FMTS,
1460		},
1461		.ops 		= &davinci_mcasp_dai_ops,
1462	},
1463
1464};
1465
1466static const struct snd_soc_component_driver davinci_mcasp_component = {
1467	.name		= "davinci-mcasp",
1468};
1469
1470/* Some HW specific values and defaults. The rest is filled in from DT. */
1471static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1472	.tx_dma_offset = 0x400,
1473	.rx_dma_offset = 0x400,
 
1474	.version = MCASP_VERSION_1,
1475};
1476
1477static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1478	.tx_dma_offset = 0x2000,
1479	.rx_dma_offset = 0x2000,
 
1480	.version = MCASP_VERSION_2,
1481};
1482
1483static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1484	.tx_dma_offset = 0,
1485	.rx_dma_offset = 0,
 
1486	.version = MCASP_VERSION_3,
1487};
1488
1489static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1490	.tx_dma_offset = 0x200,
1491	.rx_dma_offset = 0x284,
 
1492	.version = MCASP_VERSION_4,
1493};
1494
1495static const struct of_device_id mcasp_dt_ids[] = {
1496	{
1497		.compatible = "ti,dm646x-mcasp-audio",
1498		.data = &dm646x_mcasp_pdata,
1499	},
1500	{
1501		.compatible = "ti,da830-mcasp-audio",
1502		.data = &da830_mcasp_pdata,
1503	},
1504	{
1505		.compatible = "ti,am33xx-mcasp-audio",
1506		.data = &am33xx_mcasp_pdata,
1507	},
1508	{
1509		.compatible = "ti,dra7-mcasp-audio",
1510		.data = &dra7_mcasp_pdata,
1511	},
1512	{ /* sentinel */ }
1513};
1514MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1515
1516static int mcasp_reparent_fck(struct platform_device *pdev)
1517{
1518	struct device_node *node = pdev->dev.of_node;
1519	struct clk *gfclk, *parent_clk;
1520	const char *parent_name;
1521	int ret;
1522
1523	if (!node)
1524		return 0;
1525
1526	parent_name = of_get_property(node, "fck_parent", NULL);
1527	if (!parent_name)
1528		return 0;
1529
1530	dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1531
1532	gfclk = clk_get(&pdev->dev, "fck");
1533	if (IS_ERR(gfclk)) {
1534		dev_err(&pdev->dev, "failed to get fck\n");
1535		return PTR_ERR(gfclk);
1536	}
1537
1538	parent_clk = clk_get(NULL, parent_name);
1539	if (IS_ERR(parent_clk)) {
1540		dev_err(&pdev->dev, "failed to get parent clock\n");
1541		ret = PTR_ERR(parent_clk);
1542		goto err1;
1543	}
1544
1545	ret = clk_set_parent(gfclk, parent_clk);
1546	if (ret) {
1547		dev_err(&pdev->dev, "failed to reparent fck\n");
1548		goto err2;
1549	}
1550
1551err2:
1552	clk_put(parent_clk);
1553err1:
1554	clk_put(gfclk);
1555	return ret;
1556}
1557
1558static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1559						struct platform_device *pdev)
1560{
1561	struct device_node *np = pdev->dev.of_node;
1562	struct davinci_mcasp_pdata *pdata = NULL;
1563	const struct of_device_id *match =
1564			of_match_device(mcasp_dt_ids, &pdev->dev);
1565	struct of_phandle_args dma_spec;
1566
1567	const u32 *of_serial_dir32;
1568	u32 val;
1569	int i, ret = 0;
1570
1571	if (pdev->dev.platform_data) {
1572		pdata = pdev->dev.platform_data;
1573		return pdata;
1574	} else if (match) {
1575		pdata = (struct davinci_mcasp_pdata*) match->data;
1576	} else {
1577		/* control shouldn't reach here. something is wrong */
1578		ret = -EINVAL;
1579		goto nodata;
1580	}
1581
1582	ret = of_property_read_u32(np, "op-mode", &val);
1583	if (ret >= 0)
1584		pdata->op_mode = val;
1585
1586	ret = of_property_read_u32(np, "tdm-slots", &val);
1587	if (ret >= 0) {
1588		if (val < 2 || val > 32) {
1589			dev_err(&pdev->dev,
1590				"tdm-slots must be in rage [2-32]\n");
1591			ret = -EINVAL;
1592			goto nodata;
1593		}
1594
1595		pdata->tdm_slots = val;
1596	}
1597
1598	of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1599	val /= sizeof(u32);
1600	if (of_serial_dir32) {
1601		u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1602						 (sizeof(*of_serial_dir) * val),
1603						 GFP_KERNEL);
1604		if (!of_serial_dir) {
1605			ret = -ENOMEM;
1606			goto nodata;
1607		}
1608
1609		for (i = 0; i < val; i++)
1610			of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1611
1612		pdata->num_serializer = val;
1613		pdata->serial_dir = of_serial_dir;
1614	}
1615
1616	ret = of_property_match_string(np, "dma-names", "tx");
1617	if (ret < 0)
1618		goto nodata;
1619
1620	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1621					 &dma_spec);
1622	if (ret < 0)
1623		goto nodata;
1624
1625	pdata->tx_dma_channel = dma_spec.args[0];
1626
1627	/* RX is not valid in DIT mode */
1628	if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1629		ret = of_property_match_string(np, "dma-names", "rx");
1630		if (ret < 0)
1631			goto nodata;
1632
1633		ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1634						 &dma_spec);
1635		if (ret < 0)
1636			goto nodata;
1637
1638		pdata->rx_dma_channel = dma_spec.args[0];
1639	}
1640
1641	ret = of_property_read_u32(np, "tx-num-evt", &val);
1642	if (ret >= 0)
1643		pdata->txnumevt = val;
1644
1645	ret = of_property_read_u32(np, "rx-num-evt", &val);
1646	if (ret >= 0)
1647		pdata->rxnumevt = val;
1648
1649	ret = of_property_read_u32(np, "sram-size-playback", &val);
1650	if (ret >= 0)
1651		pdata->sram_size_playback = val;
1652
1653	ret = of_property_read_u32(np, "sram-size-capture", &val);
1654	if (ret >= 0)
1655		pdata->sram_size_capture = val;
1656
1657	return  pdata;
1658
1659nodata:
1660	if (ret < 0) {
1661		dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1662			ret);
1663		pdata = NULL;
1664	}
1665	return  pdata;
1666}
1667
1668enum {
1669	PCM_EDMA,
1670	PCM_SDMA,
1671};
1672static const char *sdma_prefix = "ti,omap";
1673
1674static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1675{
1676	struct dma_chan *chan;
1677	const char *tmp;
1678	int ret = PCM_EDMA;
1679
1680	if (!mcasp->dev->of_node)
1681		return PCM_EDMA;
1682
1683	tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1684	chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1685	if (IS_ERR(chan)) {
1686		if (PTR_ERR(chan) != -EPROBE_DEFER)
1687			dev_err(mcasp->dev,
1688				"Can't verify DMA configuration (%ld)\n",
1689				PTR_ERR(chan));
1690		return PTR_ERR(chan);
1691	}
1692	BUG_ON(!chan->device || !chan->device->dev);
1693
1694	if (chan->device->dev->of_node)
1695		ret = of_property_read_string(chan->device->dev->of_node,
1696					      "compatible", &tmp);
1697	else
1698		dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1699
1700	dma_release_channel(chan);
1701	if (ret)
1702		return ret;
1703
1704	dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1705	if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1706		return PCM_SDMA;
1707
1708	return PCM_EDMA;
1709}
1710
1711static int davinci_mcasp_probe(struct platform_device *pdev)
1712{
 
1713	struct snd_dmaengine_dai_dma_data *dma_data;
1714	struct resource *mem, *res, *dat;
1715	struct davinci_mcasp_pdata *pdata;
1716	struct davinci_mcasp *mcasp;
1717	char *irq_name;
1718	int *dma;
1719	int irq;
1720	int ret;
1721
1722	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1723		dev_err(&pdev->dev, "No platform data supplied\n");
1724		return -EINVAL;
1725	}
1726
1727	mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1728			   GFP_KERNEL);
1729	if (!mcasp)
1730		return	-ENOMEM;
1731
1732	pdata = davinci_mcasp_set_pdata_from_of(pdev);
1733	if (!pdata) {
1734		dev_err(&pdev->dev, "no platform data\n");
1735		return -EINVAL;
1736	}
1737
1738	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1739	if (!mem) {
1740		dev_warn(mcasp->dev,
1741			 "\"mpu\" mem resource not found, using index 0\n");
1742		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1743		if (!mem) {
1744			dev_err(&pdev->dev, "no mem resource?\n");
1745			return -ENODEV;
1746		}
1747	}
1748
1749	mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1750	if (IS_ERR(mcasp->base))
1751		return PTR_ERR(mcasp->base);
 
 
 
1752
1753	pm_runtime_enable(&pdev->dev);
1754
1755	mcasp->op_mode = pdata->op_mode;
1756	/* sanity check for tdm slots parameter */
1757	if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1758		if (pdata->tdm_slots < 2) {
1759			dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1760				pdata->tdm_slots);
1761			mcasp->tdm_slots = 2;
1762		} else if (pdata->tdm_slots > 32) {
1763			dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1764				pdata->tdm_slots);
1765			mcasp->tdm_slots = 32;
1766		} else {
1767			mcasp->tdm_slots = pdata->tdm_slots;
1768		}
1769	}
1770
 
 
1771	mcasp->num_serializer = pdata->num_serializer;
1772#ifdef CONFIG_PM_SLEEP
1773	mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1774					sizeof(u32) * mcasp->num_serializer,
1775					GFP_KERNEL);
1776#endif
1777	mcasp->serial_dir = pdata->serial_dir;
1778	mcasp->version = pdata->version;
1779	mcasp->txnumevt = pdata->txnumevt;
1780	mcasp->rxnumevt = pdata->rxnumevt;
1781
1782	mcasp->dev = &pdev->dev;
1783
1784	irq = platform_get_irq_byname(pdev, "common");
1785	if (irq >= 0) {
1786		irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1787					  dev_name(&pdev->dev));
1788		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1789						davinci_mcasp_common_irq_handler,
1790						IRQF_ONESHOT | IRQF_SHARED,
1791						irq_name, mcasp);
1792		if (ret) {
1793			dev_err(&pdev->dev, "common IRQ request failed\n");
1794			goto err;
1795		}
1796
1797		mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1798		mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1799	}
1800
1801	irq = platform_get_irq_byname(pdev, "rx");
1802	if (irq >= 0) {
1803		irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1804					  dev_name(&pdev->dev));
1805		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1806						davinci_mcasp_rx_irq_handler,
1807						IRQF_ONESHOT, irq_name, mcasp);
1808		if (ret) {
1809			dev_err(&pdev->dev, "RX IRQ request failed\n");
1810			goto err;
1811		}
1812
1813		mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1814	}
1815
1816	irq = platform_get_irq_byname(pdev, "tx");
1817	if (irq >= 0) {
1818		irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1819					  dev_name(&pdev->dev));
1820		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1821						davinci_mcasp_tx_irq_handler,
1822						IRQF_ONESHOT, irq_name, mcasp);
1823		if (ret) {
1824			dev_err(&pdev->dev, "TX IRQ request failed\n");
1825			goto err;
1826		}
1827
1828		mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1829	}
1830
1831	dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1832	if (dat)
1833		mcasp->dat_port = true;
1834
 
1835	dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
 
 
 
 
1836	if (dat)
1837		dma_data->addr = dat->start;
1838	else
1839		dma_data->addr = mem->start + pdata->tx_dma_offset;
 
 
 
1840
1841	dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1842	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1843	if (res)
1844		*dma = res->start;
1845	else
1846		*dma = pdata->tx_dma_channel;
1847
1848	/* dmaengine filter data for DT and non-DT boot */
1849	if (pdev->dev.of_node)
1850		dma_data->filter_data = "tx";
1851	else
1852		dma_data->filter_data = dma;
1853
1854	/* RX is not valid in DIT mode */
1855	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1856		dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1857		if (dat)
1858			dma_data->addr = dat->start;
1859		else
1860			dma_data->addr = mem->start + pdata->rx_dma_offset;
1861
1862		dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1863		res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1864		if (res)
1865			*dma = res->start;
1866		else
1867			*dma = pdata->rx_dma_channel;
1868
1869		/* dmaengine filter data for DT and non-DT boot */
1870		if (pdev->dev.of_node)
1871			dma_data->filter_data = "rx";
1872		else
1873			dma_data->filter_data = dma;
1874	}
1875
1876	if (mcasp->version < MCASP_VERSION_3) {
1877		mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1878		/* dma_params->dma_addr is pointing to the data port address */
1879		mcasp->dat_port = true;
1880	} else {
1881		mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1882	}
1883
1884	/* Allocate memory for long enough list for all possible
1885	 * scenarios. Maximum number tdm slots is 32 and there cannot
1886	 * be more serializers than given in the configuration.  The
1887	 * serializer directions could be taken into account, but it
1888	 * would make code much more complex and save only couple of
1889	 * bytes.
1890	 */
1891	mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
1892		devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1893			     (32 + mcasp->num_serializer - 2),
1894			     GFP_KERNEL);
1895
1896	mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
1897		devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1898			     (32 + mcasp->num_serializer - 2),
1899			     GFP_KERNEL);
1900
1901	if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
1902	    !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list)
1903		return -ENOMEM;
1904
1905	ret = davinci_mcasp_set_ch_constraints(mcasp);
1906	if (ret)
1907		goto err;
 
 
1908
1909	dev_set_drvdata(&pdev->dev, mcasp);
1910
1911	mcasp_reparent_fck(pdev);
1912
1913	ret = devm_snd_soc_register_component(&pdev->dev,
1914					&davinci_mcasp_component,
1915					&davinci_mcasp_dai[pdata->op_mode], 1);
1916
1917	if (ret != 0)
1918		goto err;
1919
1920	ret = davinci_mcasp_get_dma_type(mcasp);
1921	switch (ret) {
1922	case PCM_EDMA:
1923#if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1924	(IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1925	 IS_MODULE(CONFIG_SND_EDMA_SOC))
1926		ret = edma_pcm_platform_register(&pdev->dev);
1927#else
1928		dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
1929		ret = -EINVAL;
1930		goto err;
1931#endif
1932		break;
1933	case PCM_SDMA:
1934#if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1935	(IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1936	 IS_MODULE(CONFIG_SND_OMAP_SOC))
1937		ret = omap_pcm_platform_register(&pdev->dev);
1938#else
1939		dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
1940		ret = -EINVAL;
1941		goto err;
1942#endif
1943		break;
1944	default:
1945		dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
1946	case -EPROBE_DEFER:
1947		goto err;
1948		break;
1949	}
1950
1951	if (ret) {
1952		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1953		goto err;
 
 
 
1954	}
1955
1956	return 0;
1957
1958err:
 
 
 
1959	pm_runtime_disable(&pdev->dev);
1960	return ret;
1961}
1962
1963static int davinci_mcasp_remove(struct platform_device *pdev)
1964{
 
 
 
 
 
 
 
1965	pm_runtime_disable(&pdev->dev);
1966
1967	return 0;
1968}
1969
1970static struct platform_driver davinci_mcasp_driver = {
1971	.probe		= davinci_mcasp_probe,
1972	.remove		= davinci_mcasp_remove,
1973	.driver		= {
1974		.name	= "davinci-mcasp",
 
1975		.of_match_table = mcasp_dt_ids,
1976	},
1977};
1978
1979module_platform_driver(davinci_mcasp_driver);
1980
1981MODULE_AUTHOR("Steve Chen");
1982MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1983MODULE_LICENSE("GPL");