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1/*
2 * rtc-twl.c -- TWL Real Time Clock interface
3 *
4 * Copyright (C) 2007 MontaVista Software, Inc
5 * Author: Alexandre Rusev <source@mvista.com>
6 *
7 * Based on original TI driver twl4030-rtc.c
8 * Copyright (C) 2006 Texas Instruments, Inc.
9 *
10 * Based on rtc-omap.c
11 * Copyright (C) 2003 MontaVista Software, Inc.
12 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
13 * Copyright (C) 2006 David Brownell
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/rtc.h>
29#include <linux/bcd.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/of.h>
33
34#include <linux/i2c/twl.h>
35
36
37/*
38 * RTC block register offsets (use TWL_MODULE_RTC)
39 */
40enum {
41 REG_SECONDS_REG = 0,
42 REG_MINUTES_REG,
43 REG_HOURS_REG,
44 REG_DAYS_REG,
45 REG_MONTHS_REG,
46 REG_YEARS_REG,
47 REG_WEEKS_REG,
48
49 REG_ALARM_SECONDS_REG,
50 REG_ALARM_MINUTES_REG,
51 REG_ALARM_HOURS_REG,
52 REG_ALARM_DAYS_REG,
53 REG_ALARM_MONTHS_REG,
54 REG_ALARM_YEARS_REG,
55
56 REG_RTC_CTRL_REG,
57 REG_RTC_STATUS_REG,
58 REG_RTC_INTERRUPTS_REG,
59
60 REG_RTC_COMP_LSB_REG,
61 REG_RTC_COMP_MSB_REG,
62};
63static const u8 twl4030_rtc_reg_map[] = {
64 [REG_SECONDS_REG] = 0x00,
65 [REG_MINUTES_REG] = 0x01,
66 [REG_HOURS_REG] = 0x02,
67 [REG_DAYS_REG] = 0x03,
68 [REG_MONTHS_REG] = 0x04,
69 [REG_YEARS_REG] = 0x05,
70 [REG_WEEKS_REG] = 0x06,
71
72 [REG_ALARM_SECONDS_REG] = 0x07,
73 [REG_ALARM_MINUTES_REG] = 0x08,
74 [REG_ALARM_HOURS_REG] = 0x09,
75 [REG_ALARM_DAYS_REG] = 0x0A,
76 [REG_ALARM_MONTHS_REG] = 0x0B,
77 [REG_ALARM_YEARS_REG] = 0x0C,
78
79 [REG_RTC_CTRL_REG] = 0x0D,
80 [REG_RTC_STATUS_REG] = 0x0E,
81 [REG_RTC_INTERRUPTS_REG] = 0x0F,
82
83 [REG_RTC_COMP_LSB_REG] = 0x10,
84 [REG_RTC_COMP_MSB_REG] = 0x11,
85};
86static const u8 twl6030_rtc_reg_map[] = {
87 [REG_SECONDS_REG] = 0x00,
88 [REG_MINUTES_REG] = 0x01,
89 [REG_HOURS_REG] = 0x02,
90 [REG_DAYS_REG] = 0x03,
91 [REG_MONTHS_REG] = 0x04,
92 [REG_YEARS_REG] = 0x05,
93 [REG_WEEKS_REG] = 0x06,
94
95 [REG_ALARM_SECONDS_REG] = 0x08,
96 [REG_ALARM_MINUTES_REG] = 0x09,
97 [REG_ALARM_HOURS_REG] = 0x0A,
98 [REG_ALARM_DAYS_REG] = 0x0B,
99 [REG_ALARM_MONTHS_REG] = 0x0C,
100 [REG_ALARM_YEARS_REG] = 0x0D,
101
102 [REG_RTC_CTRL_REG] = 0x10,
103 [REG_RTC_STATUS_REG] = 0x11,
104 [REG_RTC_INTERRUPTS_REG] = 0x12,
105
106 [REG_RTC_COMP_LSB_REG] = 0x13,
107 [REG_RTC_COMP_MSB_REG] = 0x14,
108};
109
110/* RTC_CTRL_REG bitfields */
111#define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
112#define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
113#define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
114#define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
115#define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
116#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
117#define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
118#define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
119
120/* RTC_STATUS_REG bitfields */
121#define BIT_RTC_STATUS_REG_RUN_M 0x02
122#define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
123#define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
124#define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
125#define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
126#define BIT_RTC_STATUS_REG_ALARM_M 0x40
127#define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
128
129/* RTC_INTERRUPTS_REG bitfields */
130#define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
131#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
132#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
133
134
135/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
136#define ALL_TIME_REGS 6
137
138/*----------------------------------------------------------------------*/
139static u8 *rtc_reg_map;
140
141/*
142 * Supports 1 byte read from TWL RTC register.
143 */
144static int twl_rtc_read_u8(u8 *data, u8 reg)
145{
146 int ret;
147
148 ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
149 if (ret < 0)
150 pr_err("Could not read TWL register %X - error %d\n", reg, ret);
151 return ret;
152}
153
154/*
155 * Supports 1 byte write to TWL RTC registers.
156 */
157static int twl_rtc_write_u8(u8 data, u8 reg)
158{
159 int ret;
160
161 ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
162 if (ret < 0)
163 pr_err("Could not write TWL register %X - error %d\n",
164 reg, ret);
165 return ret;
166}
167
168/*
169 * Cache the value for timer/alarm interrupts register; this is
170 * only changed by callers holding rtc ops lock (or resume).
171 */
172static unsigned char rtc_irq_bits;
173
174/*
175 * Enable 1/second update and/or alarm interrupts.
176 */
177static int set_rtc_irq_bit(unsigned char bit)
178{
179 unsigned char val;
180 int ret;
181
182 /* if the bit is set, return from here */
183 if (rtc_irq_bits & bit)
184 return 0;
185
186 val = rtc_irq_bits | bit;
187 val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
188 ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
189 if (ret == 0)
190 rtc_irq_bits = val;
191
192 return ret;
193}
194
195/*
196 * Disable update and/or alarm interrupts.
197 */
198static int mask_rtc_irq_bit(unsigned char bit)
199{
200 unsigned char val;
201 int ret;
202
203 /* if the bit is clear, return from here */
204 if (!(rtc_irq_bits & bit))
205 return 0;
206
207 val = rtc_irq_bits & ~bit;
208 ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
209 if (ret == 0)
210 rtc_irq_bits = val;
211
212 return ret;
213}
214
215static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
216{
217 struct platform_device *pdev = to_platform_device(dev);
218 int irq = platform_get_irq(pdev, 0);
219 static bool twl_rtc_wake_enabled;
220 int ret;
221
222 if (enabled) {
223 ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
224 if (device_can_wakeup(dev) && !twl_rtc_wake_enabled) {
225 enable_irq_wake(irq);
226 twl_rtc_wake_enabled = true;
227 }
228 } else {
229 ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
230 if (twl_rtc_wake_enabled) {
231 disable_irq_wake(irq);
232 twl_rtc_wake_enabled = false;
233 }
234 }
235
236 return ret;
237}
238
239/*
240 * Gets current TWL RTC time and date parameters.
241 *
242 * The RTC's time/alarm representation is not what gmtime(3) requires
243 * Linux to use:
244 *
245 * - Months are 1..12 vs Linux 0-11
246 * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
247 */
248static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
249{
250 unsigned char rtc_data[ALL_TIME_REGS];
251 int ret;
252 u8 save_control;
253 u8 rtc_control;
254
255 ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
256 if (ret < 0) {
257 dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
258 return ret;
259 }
260 /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
261 if (twl_class_is_6030()) {
262 if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
263 save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
264 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
265 if (ret < 0) {
266 dev_err(dev, "%s clr GET_TIME, error %d\n",
267 __func__, ret);
268 return ret;
269 }
270 }
271 }
272
273 /* Copy RTC counting registers to static registers or latches */
274 rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;
275
276 /* for twl6030/32 enable read access to static shadowed registers */
277 if (twl_class_is_6030())
278 rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;
279
280 ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
281 if (ret < 0) {
282 dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
283 return ret;
284 }
285
286 ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
287 (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
288
289 if (ret < 0) {
290 dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
291 return ret;
292 }
293
294 /* for twl6030 restore original state of rtc control register */
295 if (twl_class_is_6030()) {
296 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
297 if (ret < 0) {
298 dev_err(dev, "%s: restore CTRL_REG, error %d\n",
299 __func__, ret);
300 return ret;
301 }
302 }
303
304 tm->tm_sec = bcd2bin(rtc_data[0]);
305 tm->tm_min = bcd2bin(rtc_data[1]);
306 tm->tm_hour = bcd2bin(rtc_data[2]);
307 tm->tm_mday = bcd2bin(rtc_data[3]);
308 tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
309 tm->tm_year = bcd2bin(rtc_data[5]) + 100;
310
311 return ret;
312}
313
314static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
315{
316 unsigned char save_control;
317 unsigned char rtc_data[ALL_TIME_REGS];
318 int ret;
319
320 rtc_data[0] = bin2bcd(tm->tm_sec);
321 rtc_data[1] = bin2bcd(tm->tm_min);
322 rtc_data[2] = bin2bcd(tm->tm_hour);
323 rtc_data[3] = bin2bcd(tm->tm_mday);
324 rtc_data[4] = bin2bcd(tm->tm_mon + 1);
325 rtc_data[5] = bin2bcd(tm->tm_year - 100);
326
327 /* Stop RTC while updating the TC registers */
328 ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
329 if (ret < 0)
330 goto out;
331
332 save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
333 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
334 if (ret < 0)
335 goto out;
336
337 /* update all the time registers in one shot */
338 ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
339 (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
340 if (ret < 0) {
341 dev_err(dev, "rtc_set_time error %d\n", ret);
342 goto out;
343 }
344
345 /* Start back RTC */
346 save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
347 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
348
349out:
350 return ret;
351}
352
353/*
354 * Gets current TWL RTC alarm time.
355 */
356static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
357{
358 unsigned char rtc_data[ALL_TIME_REGS];
359 int ret;
360
361 ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
362 (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
363 if (ret < 0) {
364 dev_err(dev, "rtc_read_alarm error %d\n", ret);
365 return ret;
366 }
367
368 /* some of these fields may be wildcard/"match all" */
369 alm->time.tm_sec = bcd2bin(rtc_data[0]);
370 alm->time.tm_min = bcd2bin(rtc_data[1]);
371 alm->time.tm_hour = bcd2bin(rtc_data[2]);
372 alm->time.tm_mday = bcd2bin(rtc_data[3]);
373 alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
374 alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
375
376 /* report cached alarm enable state */
377 if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
378 alm->enabled = 1;
379
380 return ret;
381}
382
383static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
384{
385 unsigned char alarm_data[ALL_TIME_REGS];
386 int ret;
387
388 ret = twl_rtc_alarm_irq_enable(dev, 0);
389 if (ret)
390 goto out;
391
392 alarm_data[0] = bin2bcd(alm->time.tm_sec);
393 alarm_data[1] = bin2bcd(alm->time.tm_min);
394 alarm_data[2] = bin2bcd(alm->time.tm_hour);
395 alarm_data[3] = bin2bcd(alm->time.tm_mday);
396 alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
397 alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
398
399 /* update all the alarm registers in one shot */
400 ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
401 (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
402 if (ret) {
403 dev_err(dev, "rtc_set_alarm error %d\n", ret);
404 goto out;
405 }
406
407 if (alm->enabled)
408 ret = twl_rtc_alarm_irq_enable(dev, 1);
409out:
410 return ret;
411}
412
413static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
414{
415 unsigned long events;
416 int ret = IRQ_NONE;
417 int res;
418 u8 rd_reg;
419
420 res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
421 if (res)
422 goto out;
423 /*
424 * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
425 * only one (ALARM or RTC) interrupt source may be enabled
426 * at time, we also could check our results
427 * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
428 */
429 if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
430 events = RTC_IRQF | RTC_AF;
431 else
432 events = RTC_IRQF | RTC_PF;
433
434 res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
435 REG_RTC_STATUS_REG);
436 if (res)
437 goto out;
438
439 if (twl_class_is_4030()) {
440 /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
441 * needs 2 reads to clear the interrupt. One read is done in
442 * do_twl_pwrirq(). Doing the second read, to clear
443 * the bit.
444 *
445 * FIXME the reason PWR_ISR1 needs an extra read is that
446 * RTC_IF retriggered until we cleared REG_ALARM_M above.
447 * But re-reading like this is a bad hack; by doing so we
448 * risk wrongly clearing status for some other IRQ (losing
449 * the interrupt). Be smarter about handling RTC_UF ...
450 */
451 res = twl_i2c_read_u8(TWL4030_MODULE_INT,
452 &rd_reg, TWL4030_INT_PWR_ISR1);
453 if (res)
454 goto out;
455 }
456
457 /* Notify RTC core on event */
458 rtc_update_irq(rtc, 1, events);
459
460 ret = IRQ_HANDLED;
461out:
462 return ret;
463}
464
465static struct rtc_class_ops twl_rtc_ops = {
466 .read_time = twl_rtc_read_time,
467 .set_time = twl_rtc_set_time,
468 .read_alarm = twl_rtc_read_alarm,
469 .set_alarm = twl_rtc_set_alarm,
470 .alarm_irq_enable = twl_rtc_alarm_irq_enable,
471};
472
473/*----------------------------------------------------------------------*/
474
475static int twl_rtc_probe(struct platform_device *pdev)
476{
477 struct rtc_device *rtc;
478 int ret = -EINVAL;
479 int irq = platform_get_irq(pdev, 0);
480 u8 rd_reg;
481
482 if (irq <= 0)
483 return ret;
484
485 /* Initialize the register map */
486 if (twl_class_is_4030())
487 rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
488 else
489 rtc_reg_map = (u8 *)twl6030_rtc_reg_map;
490
491 ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
492 if (ret < 0)
493 return ret;
494
495 if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
496 dev_warn(&pdev->dev, "Power up reset detected.\n");
497
498 if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
499 dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
500
501 /* Clear RTC Power up reset and pending alarm interrupts */
502 ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
503 if (ret < 0)
504 return ret;
505
506 if (twl_class_is_6030()) {
507 twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
508 REG_INT_MSK_LINE_A);
509 twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
510 REG_INT_MSK_STS_A);
511 }
512
513 dev_info(&pdev->dev, "Enabling TWL-RTC\n");
514 ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
515 if (ret < 0)
516 return ret;
517
518 /* ensure interrupts are disabled, bootloaders can be strange */
519 ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
520 if (ret < 0)
521 dev_warn(&pdev->dev, "unable to disable interrupt\n");
522
523 /* init cached IRQ enable bits */
524 ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
525 if (ret < 0)
526 return ret;
527
528 device_init_wakeup(&pdev->dev, 1);
529
530 rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
531 &twl_rtc_ops, THIS_MODULE);
532 if (IS_ERR(rtc)) {
533 dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
534 PTR_ERR(rtc));
535 return PTR_ERR(rtc);
536 }
537
538 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
539 twl_rtc_interrupt,
540 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
541 dev_name(&rtc->dev), rtc);
542 if (ret < 0) {
543 dev_err(&pdev->dev, "IRQ is not free.\n");
544 return ret;
545 }
546
547 platform_set_drvdata(pdev, rtc);
548 return 0;
549}
550
551/*
552 * Disable all TWL RTC module interrupts.
553 * Sets status flag to free.
554 */
555static int twl_rtc_remove(struct platform_device *pdev)
556{
557 /* leave rtc running, but disable irqs */
558 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
559 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
560 if (twl_class_is_6030()) {
561 twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
562 REG_INT_MSK_LINE_A);
563 twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
564 REG_INT_MSK_STS_A);
565 }
566
567 return 0;
568}
569
570static void twl_rtc_shutdown(struct platform_device *pdev)
571{
572 /* mask timer interrupts, but leave alarm interrupts on to enable
573 power-on when alarm is triggered */
574 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
575}
576
577#ifdef CONFIG_PM_SLEEP
578static unsigned char irqstat;
579
580static int twl_rtc_suspend(struct device *dev)
581{
582 irqstat = rtc_irq_bits;
583
584 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
585 return 0;
586}
587
588static int twl_rtc_resume(struct device *dev)
589{
590 set_rtc_irq_bit(irqstat);
591 return 0;
592}
593#endif
594
595static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
596
597#ifdef CONFIG_OF
598static const struct of_device_id twl_rtc_of_match[] = {
599 {.compatible = "ti,twl4030-rtc", },
600 { },
601};
602MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
603#endif
604
605MODULE_ALIAS("platform:twl_rtc");
606
607static struct platform_driver twl4030rtc_driver = {
608 .probe = twl_rtc_probe,
609 .remove = twl_rtc_remove,
610 .shutdown = twl_rtc_shutdown,
611 .driver = {
612 .name = "twl_rtc",
613 .pm = &twl_rtc_pm_ops,
614 .of_match_table = of_match_ptr(twl_rtc_of_match),
615 },
616};
617
618module_platform_driver(twl4030rtc_driver);
619
620MODULE_AUTHOR("Texas Instruments, MontaVista Software");
621MODULE_LICENSE("GPL");
1/*
2 * rtc-twl.c -- TWL Real Time Clock interface
3 *
4 * Copyright (C) 2007 MontaVista Software, Inc
5 * Author: Alexandre Rusev <source@mvista.com>
6 *
7 * Based on original TI driver twl4030-rtc.c
8 * Copyright (C) 2006 Texas Instruments, Inc.
9 *
10 * Based on rtc-omap.c
11 * Copyright (C) 2003 MontaVista Software, Inc.
12 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
13 * Copyright (C) 2006 David Brownell
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/types.h>
26#include <linux/rtc.h>
27#include <linux/bcd.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/of.h>
31
32#include <linux/i2c/twl.h>
33
34
35/*
36 * RTC block register offsets (use TWL_MODULE_RTC)
37 */
38enum {
39 REG_SECONDS_REG = 0,
40 REG_MINUTES_REG,
41 REG_HOURS_REG,
42 REG_DAYS_REG,
43 REG_MONTHS_REG,
44 REG_YEARS_REG,
45 REG_WEEKS_REG,
46
47 REG_ALARM_SECONDS_REG,
48 REG_ALARM_MINUTES_REG,
49 REG_ALARM_HOURS_REG,
50 REG_ALARM_DAYS_REG,
51 REG_ALARM_MONTHS_REG,
52 REG_ALARM_YEARS_REG,
53
54 REG_RTC_CTRL_REG,
55 REG_RTC_STATUS_REG,
56 REG_RTC_INTERRUPTS_REG,
57
58 REG_RTC_COMP_LSB_REG,
59 REG_RTC_COMP_MSB_REG,
60};
61static const u8 twl4030_rtc_reg_map[] = {
62 [REG_SECONDS_REG] = 0x00,
63 [REG_MINUTES_REG] = 0x01,
64 [REG_HOURS_REG] = 0x02,
65 [REG_DAYS_REG] = 0x03,
66 [REG_MONTHS_REG] = 0x04,
67 [REG_YEARS_REG] = 0x05,
68 [REG_WEEKS_REG] = 0x06,
69
70 [REG_ALARM_SECONDS_REG] = 0x07,
71 [REG_ALARM_MINUTES_REG] = 0x08,
72 [REG_ALARM_HOURS_REG] = 0x09,
73 [REG_ALARM_DAYS_REG] = 0x0A,
74 [REG_ALARM_MONTHS_REG] = 0x0B,
75 [REG_ALARM_YEARS_REG] = 0x0C,
76
77 [REG_RTC_CTRL_REG] = 0x0D,
78 [REG_RTC_STATUS_REG] = 0x0E,
79 [REG_RTC_INTERRUPTS_REG] = 0x0F,
80
81 [REG_RTC_COMP_LSB_REG] = 0x10,
82 [REG_RTC_COMP_MSB_REG] = 0x11,
83};
84static const u8 twl6030_rtc_reg_map[] = {
85 [REG_SECONDS_REG] = 0x00,
86 [REG_MINUTES_REG] = 0x01,
87 [REG_HOURS_REG] = 0x02,
88 [REG_DAYS_REG] = 0x03,
89 [REG_MONTHS_REG] = 0x04,
90 [REG_YEARS_REG] = 0x05,
91 [REG_WEEKS_REG] = 0x06,
92
93 [REG_ALARM_SECONDS_REG] = 0x08,
94 [REG_ALARM_MINUTES_REG] = 0x09,
95 [REG_ALARM_HOURS_REG] = 0x0A,
96 [REG_ALARM_DAYS_REG] = 0x0B,
97 [REG_ALARM_MONTHS_REG] = 0x0C,
98 [REG_ALARM_YEARS_REG] = 0x0D,
99
100 [REG_RTC_CTRL_REG] = 0x10,
101 [REG_RTC_STATUS_REG] = 0x11,
102 [REG_RTC_INTERRUPTS_REG] = 0x12,
103
104 [REG_RTC_COMP_LSB_REG] = 0x13,
105 [REG_RTC_COMP_MSB_REG] = 0x14,
106};
107
108/* RTC_CTRL_REG bitfields */
109#define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
110#define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
111#define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
112#define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
113#define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
114#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
115#define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
116#define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
117
118/* RTC_STATUS_REG bitfields */
119#define BIT_RTC_STATUS_REG_RUN_M 0x02
120#define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
121#define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
122#define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
123#define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
124#define BIT_RTC_STATUS_REG_ALARM_M 0x40
125#define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
126
127/* RTC_INTERRUPTS_REG bitfields */
128#define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
129#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
130#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
131
132
133/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
134#define ALL_TIME_REGS 6
135
136/*----------------------------------------------------------------------*/
137static u8 *rtc_reg_map;
138
139/*
140 * Supports 1 byte read from TWL RTC register.
141 */
142static int twl_rtc_read_u8(u8 *data, u8 reg)
143{
144 int ret;
145
146 ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
147 if (ret < 0)
148 pr_err("twl_rtc: Could not read TWL"
149 "register %X - error %d\n", reg, ret);
150 return ret;
151}
152
153/*
154 * Supports 1 byte write to TWL RTC registers.
155 */
156static int twl_rtc_write_u8(u8 data, u8 reg)
157{
158 int ret;
159
160 ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
161 if (ret < 0)
162 pr_err("twl_rtc: Could not write TWL"
163 "register %X - error %d\n", reg, ret);
164 return ret;
165}
166
167/*
168 * Cache the value for timer/alarm interrupts register; this is
169 * only changed by callers holding rtc ops lock (or resume).
170 */
171static unsigned char rtc_irq_bits;
172
173/*
174 * Enable 1/second update and/or alarm interrupts.
175 */
176static int set_rtc_irq_bit(unsigned char bit)
177{
178 unsigned char val;
179 int ret;
180
181 /* if the bit is set, return from here */
182 if (rtc_irq_bits & bit)
183 return 0;
184
185 val = rtc_irq_bits | bit;
186 val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
187 ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
188 if (ret == 0)
189 rtc_irq_bits = val;
190
191 return ret;
192}
193
194/*
195 * Disable update and/or alarm interrupts.
196 */
197static int mask_rtc_irq_bit(unsigned char bit)
198{
199 unsigned char val;
200 int ret;
201
202 /* if the bit is clear, return from here */
203 if (!(rtc_irq_bits & bit))
204 return 0;
205
206 val = rtc_irq_bits & ~bit;
207 ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
208 if (ret == 0)
209 rtc_irq_bits = val;
210
211 return ret;
212}
213
214static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
215{
216 struct platform_device *pdev = to_platform_device(dev);
217 int irq = platform_get_irq(pdev, 0);
218 static bool twl_rtc_wake_enabled;
219 int ret;
220
221 if (enabled) {
222 ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
223 if (device_can_wakeup(dev) && !twl_rtc_wake_enabled) {
224 enable_irq_wake(irq);
225 twl_rtc_wake_enabled = true;
226 }
227 } else {
228 ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
229 if (twl_rtc_wake_enabled) {
230 disable_irq_wake(irq);
231 twl_rtc_wake_enabled = false;
232 }
233 }
234
235 return ret;
236}
237
238/*
239 * Gets current TWL RTC time and date parameters.
240 *
241 * The RTC's time/alarm representation is not what gmtime(3) requires
242 * Linux to use:
243 *
244 * - Months are 1..12 vs Linux 0-11
245 * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
246 */
247static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
248{
249 unsigned char rtc_data[ALL_TIME_REGS];
250 int ret;
251 u8 save_control;
252 u8 rtc_control;
253
254 ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
255 if (ret < 0) {
256 dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
257 return ret;
258 }
259 /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
260 if (twl_class_is_6030()) {
261 if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
262 save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
263 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
264 if (ret < 0) {
265 dev_err(dev, "%s clr GET_TIME, error %d\n",
266 __func__, ret);
267 return ret;
268 }
269 }
270 }
271
272 /* Copy RTC counting registers to static registers or latches */
273 rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;
274
275 /* for twl6030/32 enable read access to static shadowed registers */
276 if (twl_class_is_6030())
277 rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;
278
279 ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
280 if (ret < 0) {
281 dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
282 return ret;
283 }
284
285 ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
286 (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
287
288 if (ret < 0) {
289 dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
290 return ret;
291 }
292
293 /* for twl6030 restore original state of rtc control register */
294 if (twl_class_is_6030()) {
295 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
296 if (ret < 0) {
297 dev_err(dev, "%s: restore CTRL_REG, error %d\n",
298 __func__, ret);
299 return ret;
300 }
301 }
302
303 tm->tm_sec = bcd2bin(rtc_data[0]);
304 tm->tm_min = bcd2bin(rtc_data[1]);
305 tm->tm_hour = bcd2bin(rtc_data[2]);
306 tm->tm_mday = bcd2bin(rtc_data[3]);
307 tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
308 tm->tm_year = bcd2bin(rtc_data[5]) + 100;
309
310 return ret;
311}
312
313static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
314{
315 unsigned char save_control;
316 unsigned char rtc_data[ALL_TIME_REGS];
317 int ret;
318
319 rtc_data[0] = bin2bcd(tm->tm_sec);
320 rtc_data[1] = bin2bcd(tm->tm_min);
321 rtc_data[2] = bin2bcd(tm->tm_hour);
322 rtc_data[3] = bin2bcd(tm->tm_mday);
323 rtc_data[4] = bin2bcd(tm->tm_mon + 1);
324 rtc_data[5] = bin2bcd(tm->tm_year - 100);
325
326 /* Stop RTC while updating the TC registers */
327 ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
328 if (ret < 0)
329 goto out;
330
331 save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
332 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
333 if (ret < 0)
334 goto out;
335
336 /* update all the time registers in one shot */
337 ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
338 (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
339 if (ret < 0) {
340 dev_err(dev, "rtc_set_time error %d\n", ret);
341 goto out;
342 }
343
344 /* Start back RTC */
345 save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
346 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
347
348out:
349 return ret;
350}
351
352/*
353 * Gets current TWL RTC alarm time.
354 */
355static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
356{
357 unsigned char rtc_data[ALL_TIME_REGS];
358 int ret;
359
360 ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
361 (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
362 if (ret < 0) {
363 dev_err(dev, "rtc_read_alarm error %d\n", ret);
364 return ret;
365 }
366
367 /* some of these fields may be wildcard/"match all" */
368 alm->time.tm_sec = bcd2bin(rtc_data[0]);
369 alm->time.tm_min = bcd2bin(rtc_data[1]);
370 alm->time.tm_hour = bcd2bin(rtc_data[2]);
371 alm->time.tm_mday = bcd2bin(rtc_data[3]);
372 alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
373 alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
374
375 /* report cached alarm enable state */
376 if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
377 alm->enabled = 1;
378
379 return ret;
380}
381
382static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
383{
384 unsigned char alarm_data[ALL_TIME_REGS];
385 int ret;
386
387 ret = twl_rtc_alarm_irq_enable(dev, 0);
388 if (ret)
389 goto out;
390
391 alarm_data[0] = bin2bcd(alm->time.tm_sec);
392 alarm_data[1] = bin2bcd(alm->time.tm_min);
393 alarm_data[2] = bin2bcd(alm->time.tm_hour);
394 alarm_data[3] = bin2bcd(alm->time.tm_mday);
395 alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
396 alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
397
398 /* update all the alarm registers in one shot */
399 ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
400 (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
401 if (ret) {
402 dev_err(dev, "rtc_set_alarm error %d\n", ret);
403 goto out;
404 }
405
406 if (alm->enabled)
407 ret = twl_rtc_alarm_irq_enable(dev, 1);
408out:
409 return ret;
410}
411
412static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
413{
414 unsigned long events;
415 int ret = IRQ_NONE;
416 int res;
417 u8 rd_reg;
418
419 res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
420 if (res)
421 goto out;
422 /*
423 * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
424 * only one (ALARM or RTC) interrupt source may be enabled
425 * at time, we also could check our results
426 * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
427 */
428 if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
429 events = RTC_IRQF | RTC_AF;
430 else
431 events = RTC_IRQF | RTC_PF;
432
433 res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
434 REG_RTC_STATUS_REG);
435 if (res)
436 goto out;
437
438 if (twl_class_is_4030()) {
439 /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
440 * needs 2 reads to clear the interrupt. One read is done in
441 * do_twl_pwrirq(). Doing the second read, to clear
442 * the bit.
443 *
444 * FIXME the reason PWR_ISR1 needs an extra read is that
445 * RTC_IF retriggered until we cleared REG_ALARM_M above.
446 * But re-reading like this is a bad hack; by doing so we
447 * risk wrongly clearing status for some other IRQ (losing
448 * the interrupt). Be smarter about handling RTC_UF ...
449 */
450 res = twl_i2c_read_u8(TWL4030_MODULE_INT,
451 &rd_reg, TWL4030_INT_PWR_ISR1);
452 if (res)
453 goto out;
454 }
455
456 /* Notify RTC core on event */
457 rtc_update_irq(rtc, 1, events);
458
459 ret = IRQ_HANDLED;
460out:
461 return ret;
462}
463
464static struct rtc_class_ops twl_rtc_ops = {
465 .read_time = twl_rtc_read_time,
466 .set_time = twl_rtc_set_time,
467 .read_alarm = twl_rtc_read_alarm,
468 .set_alarm = twl_rtc_set_alarm,
469 .alarm_irq_enable = twl_rtc_alarm_irq_enable,
470};
471
472/*----------------------------------------------------------------------*/
473
474static int twl_rtc_probe(struct platform_device *pdev)
475{
476 struct rtc_device *rtc;
477 int ret = -EINVAL;
478 int irq = platform_get_irq(pdev, 0);
479 u8 rd_reg;
480
481 if (irq <= 0)
482 return ret;
483
484 /* Initialize the register map */
485 if (twl_class_is_4030())
486 rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
487 else
488 rtc_reg_map = (u8 *)twl6030_rtc_reg_map;
489
490 ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
491 if (ret < 0)
492 return ret;
493
494 if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
495 dev_warn(&pdev->dev, "Power up reset detected.\n");
496
497 if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
498 dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
499
500 /* Clear RTC Power up reset and pending alarm interrupts */
501 ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
502 if (ret < 0)
503 return ret;
504
505 if (twl_class_is_6030()) {
506 twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
507 REG_INT_MSK_LINE_A);
508 twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
509 REG_INT_MSK_STS_A);
510 }
511
512 dev_info(&pdev->dev, "Enabling TWL-RTC\n");
513 ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
514 if (ret < 0)
515 return ret;
516
517 /* ensure interrupts are disabled, bootloaders can be strange */
518 ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
519 if (ret < 0)
520 dev_warn(&pdev->dev, "unable to disable interrupt\n");
521
522 /* init cached IRQ enable bits */
523 ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
524 if (ret < 0)
525 return ret;
526
527 device_init_wakeup(&pdev->dev, 1);
528
529 rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
530 &twl_rtc_ops, THIS_MODULE);
531 if (IS_ERR(rtc)) {
532 dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
533 PTR_ERR(rtc));
534 return PTR_ERR(rtc);
535 }
536
537 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
538 twl_rtc_interrupt,
539 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
540 dev_name(&rtc->dev), rtc);
541 if (ret < 0) {
542 dev_err(&pdev->dev, "IRQ is not free.\n");
543 return ret;
544 }
545
546 platform_set_drvdata(pdev, rtc);
547 return 0;
548}
549
550/*
551 * Disable all TWL RTC module interrupts.
552 * Sets status flag to free.
553 */
554static int twl_rtc_remove(struct platform_device *pdev)
555{
556 /* leave rtc running, but disable irqs */
557 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
558 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
559 if (twl_class_is_6030()) {
560 twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
561 REG_INT_MSK_LINE_A);
562 twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
563 REG_INT_MSK_STS_A);
564 }
565
566 return 0;
567}
568
569static void twl_rtc_shutdown(struct platform_device *pdev)
570{
571 /* mask timer interrupts, but leave alarm interrupts on to enable
572 power-on when alarm is triggered */
573 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
574}
575
576#ifdef CONFIG_PM_SLEEP
577static unsigned char irqstat;
578
579static int twl_rtc_suspend(struct device *dev)
580{
581 irqstat = rtc_irq_bits;
582
583 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
584 return 0;
585}
586
587static int twl_rtc_resume(struct device *dev)
588{
589 set_rtc_irq_bit(irqstat);
590 return 0;
591}
592#endif
593
594static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
595
596#ifdef CONFIG_OF
597static const struct of_device_id twl_rtc_of_match[] = {
598 {.compatible = "ti,twl4030-rtc", },
599 { },
600};
601MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
602#endif
603
604MODULE_ALIAS("platform:twl_rtc");
605
606static struct platform_driver twl4030rtc_driver = {
607 .probe = twl_rtc_probe,
608 .remove = twl_rtc_remove,
609 .shutdown = twl_rtc_shutdown,
610 .driver = {
611 .owner = THIS_MODULE,
612 .name = "twl_rtc",
613 .pm = &twl_rtc_pm_ops,
614 .of_match_table = of_match_ptr(twl_rtc_of_match),
615 },
616};
617
618module_platform_driver(twl4030rtc_driver);
619
620MODULE_AUTHOR("Texas Instruments, MontaVista Software");
621MODULE_LICENSE("GPL");