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1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#include <linux/of.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/rtc.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21
22/* RTC Register offsets from RTC CTRL REG */
23#define PM8XXX_ALARM_CTRL_OFFSET 0x01
24#define PM8XXX_RTC_WRITE_OFFSET 0x02
25#define PM8XXX_RTC_READ_OFFSET 0x06
26#define PM8XXX_ALARM_RW_OFFSET 0x0A
27
28/* RTC_CTRL register bit fields */
29#define PM8xxx_RTC_ENABLE BIT(7)
30#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
31
32#define NUM_8_BIT_RTC_REGS 0x4
33
34/**
35 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
36 * @ctrl: base address of control register
37 * @write: base address of write register
38 * @read: base address of read register
39 * @alarm_ctrl: base address of alarm control register
40 * @alarm_ctrl2: base address of alarm control2 register
41 * @alarm_rw: base address of alarm read-write register
42 * @alarm_en: alarm enable mask
43 */
44struct pm8xxx_rtc_regs {
45 unsigned int ctrl;
46 unsigned int write;
47 unsigned int read;
48 unsigned int alarm_ctrl;
49 unsigned int alarm_ctrl2;
50 unsigned int alarm_rw;
51 unsigned int alarm_en;
52};
53
54/**
55 * struct pm8xxx_rtc - rtc driver internal structure
56 * @rtc: rtc device for this driver.
57 * @regmap: regmap used to access RTC registers
58 * @allow_set_time: indicates whether writing to the RTC is allowed
59 * @rtc_alarm_irq: rtc alarm irq number.
60 * @ctrl_reg: rtc control register.
61 * @rtc_dev: device structure.
62 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
63 */
64struct pm8xxx_rtc {
65 struct rtc_device *rtc;
66 struct regmap *regmap;
67 bool allow_set_time;
68 int rtc_alarm_irq;
69 const struct pm8xxx_rtc_regs *regs;
70 struct device *rtc_dev;
71 spinlock_t ctrl_reg_lock;
72};
73
74/*
75 * Steps to write the RTC registers.
76 * 1. Disable alarm if enabled.
77 * 2. Write 0x00 to LSB.
78 * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
79 * 4. Enable alarm if disabled in step 1.
80 */
81static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
82{
83 int rc, i;
84 unsigned long secs, irq_flags;
85 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0;
86 unsigned int ctrl_reg;
87 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
88 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
89
90 if (!rtc_dd->allow_set_time)
91 return -EACCES;
92
93 rtc_tm_to_time(tm, &secs);
94
95 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
96 value[i] = secs & 0xFF;
97 secs >>= 8;
98 }
99
100 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
101
102 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
103
104 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
105 if (rc)
106 goto rtc_rw_fail;
107
108 if (ctrl_reg & regs->alarm_en) {
109 alarm_enabled = 1;
110 ctrl_reg &= ~regs->alarm_en;
111 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
112 if (rc) {
113 dev_err(dev, "Write to RTC control register failed\n");
114 goto rtc_rw_fail;
115 }
116 }
117
118 /* Write 0 to Byte[0] */
119 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
120 if (rc) {
121 dev_err(dev, "Write to RTC write data register failed\n");
122 goto rtc_rw_fail;
123 }
124
125 /* Write Byte[1], Byte[2], Byte[3] */
126 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
127 &value[1], sizeof(value) - 1);
128 if (rc) {
129 dev_err(dev, "Write to RTC write data register failed\n");
130 goto rtc_rw_fail;
131 }
132
133 /* Write Byte[0] */
134 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
135 if (rc) {
136 dev_err(dev, "Write to RTC write data register failed\n");
137 goto rtc_rw_fail;
138 }
139
140 if (alarm_enabled) {
141 ctrl_reg |= regs->alarm_en;
142 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
143 if (rc) {
144 dev_err(dev, "Write to RTC control register failed\n");
145 goto rtc_rw_fail;
146 }
147 }
148
149rtc_rw_fail:
150 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
151
152 return rc;
153}
154
155static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
156{
157 int rc;
158 u8 value[NUM_8_BIT_RTC_REGS];
159 unsigned long secs;
160 unsigned int reg;
161 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
162 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
163
164 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
165 if (rc) {
166 dev_err(dev, "RTC read data register failed\n");
167 return rc;
168 }
169
170 /*
171 * Read the LSB again and check if there has been a carry over.
172 * If there is, redo the read operation.
173 */
174 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
175 if (rc < 0) {
176 dev_err(dev, "RTC read data register failed\n");
177 return rc;
178 }
179
180 if (unlikely(reg < value[0])) {
181 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
182 value, sizeof(value));
183 if (rc) {
184 dev_err(dev, "RTC read data register failed\n");
185 return rc;
186 }
187 }
188
189 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
190
191 rtc_time_to_tm(secs, tm);
192
193 rc = rtc_valid_tm(tm);
194 if (rc < 0) {
195 dev_err(dev, "Invalid time read from RTC\n");
196 return rc;
197 }
198
199 dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
200 secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
201 tm->tm_mday, tm->tm_mon, tm->tm_year);
202
203 return 0;
204}
205
206static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
207{
208 int rc, i;
209 u8 value[NUM_8_BIT_RTC_REGS];
210 unsigned int ctrl_reg;
211 unsigned long secs, irq_flags;
212 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
213 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
214
215 rtc_tm_to_time(&alarm->time, &secs);
216
217 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
218 value[i] = secs & 0xFF;
219 secs >>= 8;
220 }
221
222 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
223
224 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
225 sizeof(value));
226 if (rc) {
227 dev_err(dev, "Write to RTC ALARM register failed\n");
228 goto rtc_rw_fail;
229 }
230
231 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
232 if (rc)
233 goto rtc_rw_fail;
234
235 if (alarm->enabled)
236 ctrl_reg |= regs->alarm_en;
237 else
238 ctrl_reg &= ~regs->alarm_en;
239
240 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
241 if (rc) {
242 dev_err(dev, "Write to RTC alarm control register failed\n");
243 goto rtc_rw_fail;
244 }
245
246 dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
247 alarm->time.tm_hour, alarm->time.tm_min,
248 alarm->time.tm_sec, alarm->time.tm_mday,
249 alarm->time.tm_mon, alarm->time.tm_year);
250rtc_rw_fail:
251 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
252 return rc;
253}
254
255static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
256{
257 int rc;
258 u8 value[NUM_8_BIT_RTC_REGS];
259 unsigned long secs;
260 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
261 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
262
263 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
264 sizeof(value));
265 if (rc) {
266 dev_err(dev, "RTC alarm time read failed\n");
267 return rc;
268 }
269
270 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
271
272 rtc_time_to_tm(secs, &alarm->time);
273
274 rc = rtc_valid_tm(&alarm->time);
275 if (rc < 0) {
276 dev_err(dev, "Invalid alarm time read from RTC\n");
277 return rc;
278 }
279
280 dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
281 alarm->time.tm_hour, alarm->time.tm_min,
282 alarm->time.tm_sec, alarm->time.tm_mday,
283 alarm->time.tm_mon, alarm->time.tm_year);
284
285 return 0;
286}
287
288static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
289{
290 int rc;
291 unsigned long irq_flags;
292 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
293 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
294 unsigned int ctrl_reg;
295
296 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
297
298 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
299 if (rc)
300 goto rtc_rw_fail;
301
302 if (enable)
303 ctrl_reg |= regs->alarm_en;
304 else
305 ctrl_reg &= ~regs->alarm_en;
306
307 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
308 if (rc) {
309 dev_err(dev, "Write to RTC control register failed\n");
310 goto rtc_rw_fail;
311 }
312
313rtc_rw_fail:
314 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
315 return rc;
316}
317
318static const struct rtc_class_ops pm8xxx_rtc_ops = {
319 .read_time = pm8xxx_rtc_read_time,
320 .set_time = pm8xxx_rtc_set_time,
321 .set_alarm = pm8xxx_rtc_set_alarm,
322 .read_alarm = pm8xxx_rtc_read_alarm,
323 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
324};
325
326static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
327{
328 struct pm8xxx_rtc *rtc_dd = dev_id;
329 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
330 unsigned int ctrl_reg;
331 int rc;
332 unsigned long irq_flags;
333
334 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
335
336 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
337
338 /* Clear the alarm enable bit */
339 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
340 if (rc) {
341 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
342 goto rtc_alarm_handled;
343 }
344
345 ctrl_reg &= ~regs->alarm_en;
346
347 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
348 if (rc) {
349 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
350 dev_err(rtc_dd->rtc_dev,
351 "Write to alarm control register failed\n");
352 goto rtc_alarm_handled;
353 }
354
355 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
356
357 /* Clear RTC alarm register */
358 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
359 if (rc) {
360 dev_err(rtc_dd->rtc_dev,
361 "RTC Alarm control2 register read failed\n");
362 goto rtc_alarm_handled;
363 }
364
365 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
366 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
367 if (rc)
368 dev_err(rtc_dd->rtc_dev,
369 "Write to RTC Alarm control2 register failed\n");
370
371rtc_alarm_handled:
372 return IRQ_HANDLED;
373}
374
375static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
376{
377 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
378 unsigned int ctrl_reg;
379 int rc;
380
381 /* Check if the RTC is on, else turn it on */
382 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
383 if (rc)
384 return rc;
385
386 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
387 ctrl_reg |= PM8xxx_RTC_ENABLE;
388 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
389 if (rc)
390 return rc;
391 }
392
393 return 0;
394}
395
396static const struct pm8xxx_rtc_regs pm8921_regs = {
397 .ctrl = 0x11d,
398 .write = 0x11f,
399 .read = 0x123,
400 .alarm_rw = 0x127,
401 .alarm_ctrl = 0x11d,
402 .alarm_ctrl2 = 0x11e,
403 .alarm_en = BIT(1),
404};
405
406static const struct pm8xxx_rtc_regs pm8058_regs = {
407 .ctrl = 0x1e8,
408 .write = 0x1ea,
409 .read = 0x1ee,
410 .alarm_rw = 0x1f2,
411 .alarm_ctrl = 0x1e8,
412 .alarm_ctrl2 = 0x1e9,
413 .alarm_en = BIT(1),
414};
415
416static const struct pm8xxx_rtc_regs pm8941_regs = {
417 .ctrl = 0x6046,
418 .write = 0x6040,
419 .read = 0x6048,
420 .alarm_rw = 0x6140,
421 .alarm_ctrl = 0x6146,
422 .alarm_ctrl2 = 0x6148,
423 .alarm_en = BIT(7),
424};
425
426/*
427 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
428 */
429static const struct of_device_id pm8xxx_id_table[] = {
430 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
431 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
432 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
433 { },
434};
435MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
436
437static int pm8xxx_rtc_probe(struct platform_device *pdev)
438{
439 int rc;
440 struct pm8xxx_rtc *rtc_dd;
441 const struct of_device_id *match;
442
443 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
444 if (!match)
445 return -ENXIO;
446
447 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
448 if (rtc_dd == NULL)
449 return -ENOMEM;
450
451 /* Initialise spinlock to protect RTC control register */
452 spin_lock_init(&rtc_dd->ctrl_reg_lock);
453
454 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
455 if (!rtc_dd->regmap) {
456 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
457 return -ENXIO;
458 }
459
460 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
461 if (rtc_dd->rtc_alarm_irq < 0) {
462 dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
463 return -ENXIO;
464 }
465
466 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
467 "allow-set-time");
468
469 rtc_dd->regs = match->data;
470 rtc_dd->rtc_dev = &pdev->dev;
471
472 rc = pm8xxx_rtc_enable(rtc_dd);
473 if (rc)
474 return rc;
475
476 platform_set_drvdata(pdev, rtc_dd);
477
478 device_init_wakeup(&pdev->dev, 1);
479
480 /* Register the RTC device */
481 rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
482 &pm8xxx_rtc_ops, THIS_MODULE);
483 if (IS_ERR(rtc_dd->rtc)) {
484 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
485 __func__, PTR_ERR(rtc_dd->rtc));
486 return PTR_ERR(rtc_dd->rtc);
487 }
488
489 /* Request the alarm IRQ */
490 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
491 pm8xxx_alarm_trigger,
492 IRQF_TRIGGER_RISING,
493 "pm8xxx_rtc_alarm", rtc_dd);
494 if (rc < 0) {
495 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
496 return rc;
497 }
498
499 dev_dbg(&pdev->dev, "Probe success !!\n");
500
501 return 0;
502}
503
504#ifdef CONFIG_PM_SLEEP
505static int pm8xxx_rtc_resume(struct device *dev)
506{
507 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
508
509 if (device_may_wakeup(dev))
510 disable_irq_wake(rtc_dd->rtc_alarm_irq);
511
512 return 0;
513}
514
515static int pm8xxx_rtc_suspend(struct device *dev)
516{
517 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
518
519 if (device_may_wakeup(dev))
520 enable_irq_wake(rtc_dd->rtc_alarm_irq);
521
522 return 0;
523}
524#endif
525
526static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
527 pm8xxx_rtc_suspend,
528 pm8xxx_rtc_resume);
529
530static struct platform_driver pm8xxx_rtc_driver = {
531 .probe = pm8xxx_rtc_probe,
532 .driver = {
533 .name = "rtc-pm8xxx",
534 .pm = &pm8xxx_rtc_pm_ops,
535 .of_match_table = pm8xxx_id_table,
536 },
537};
538
539module_platform_driver(pm8xxx_rtc_driver);
540
541MODULE_ALIAS("platform:rtc-pm8xxx");
542MODULE_DESCRIPTION("PMIC8xxx RTC driver");
543MODULE_LICENSE("GPL v2");
544MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#include <linux/of.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/rtc.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21
22/* RTC Register offsets from RTC CTRL REG */
23#define PM8XXX_ALARM_CTRL_OFFSET 0x01
24#define PM8XXX_RTC_WRITE_OFFSET 0x02
25#define PM8XXX_RTC_READ_OFFSET 0x06
26#define PM8XXX_ALARM_RW_OFFSET 0x0A
27
28/* RTC_CTRL register bit fields */
29#define PM8xxx_RTC_ENABLE BIT(7)
30#define PM8xxx_RTC_ALARM_ENABLE BIT(1)
31#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
32
33#define NUM_8_BIT_RTC_REGS 0x4
34
35/**
36 * struct pm8xxx_rtc - rtc driver internal structure
37 * @rtc: rtc device for this driver.
38 * @regmap: regmap used to access RTC registers
39 * @allow_set_time: indicates whether writing to the RTC is allowed
40 * @rtc_alarm_irq: rtc alarm irq number.
41 * @rtc_base: address of rtc control register.
42 * @rtc_read_base: base address of read registers.
43 * @rtc_write_base: base address of write registers.
44 * @alarm_rw_base: base address of alarm registers.
45 * @ctrl_reg: rtc control register.
46 * @rtc_dev: device structure.
47 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
48 */
49struct pm8xxx_rtc {
50 struct rtc_device *rtc;
51 struct regmap *regmap;
52 bool allow_set_time;
53 int rtc_alarm_irq;
54 int rtc_base;
55 int rtc_read_base;
56 int rtc_write_base;
57 int alarm_rw_base;
58 u8 ctrl_reg;
59 struct device *rtc_dev;
60 spinlock_t ctrl_reg_lock;
61};
62
63/*
64 * Steps to write the RTC registers.
65 * 1. Disable alarm if enabled.
66 * 2. Write 0x00 to LSB.
67 * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
68 * 4. Enable alarm if disabled in step 1.
69 */
70static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
71{
72 int rc, i;
73 unsigned long secs, irq_flags;
74 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, ctrl_reg;
75 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
76
77 if (!rtc_dd->allow_set_time)
78 return -EACCES;
79
80 rtc_tm_to_time(tm, &secs);
81
82 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
83 value[i] = secs & 0xFF;
84 secs >>= 8;
85 }
86
87 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
88
89 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
90 ctrl_reg = rtc_dd->ctrl_reg;
91
92 if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) {
93 alarm_enabled = 1;
94 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
95 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
96 if (rc) {
97 dev_err(dev, "Write to RTC control register failed\n");
98 goto rtc_rw_fail;
99 }
100 rtc_dd->ctrl_reg = ctrl_reg;
101 } else {
102 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
103 }
104
105 /* Write 0 to Byte[0] */
106 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, 0);
107 if (rc) {
108 dev_err(dev, "Write to RTC write data register failed\n");
109 goto rtc_rw_fail;
110 }
111
112 /* Write Byte[1], Byte[2], Byte[3] */
113 rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->rtc_write_base + 1,
114 &value[1], sizeof(value) - 1);
115 if (rc) {
116 dev_err(dev, "Write to RTC write data register failed\n");
117 goto rtc_rw_fail;
118 }
119
120 /* Write Byte[0] */
121 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, value[0]);
122 if (rc) {
123 dev_err(dev, "Write to RTC write data register failed\n");
124 goto rtc_rw_fail;
125 }
126
127 if (alarm_enabled) {
128 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
129 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
130 if (rc) {
131 dev_err(dev, "Write to RTC control register failed\n");
132 goto rtc_rw_fail;
133 }
134 rtc_dd->ctrl_reg = ctrl_reg;
135 }
136
137rtc_rw_fail:
138 if (alarm_enabled)
139 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
140
141 return rc;
142}
143
144static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
145{
146 int rc;
147 u8 value[NUM_8_BIT_RTC_REGS];
148 unsigned long secs;
149 unsigned int reg;
150 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
151
152 rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base,
153 value, sizeof(value));
154 if (rc) {
155 dev_err(dev, "RTC read data register failed\n");
156 return rc;
157 }
158
159 /*
160 * Read the LSB again and check if there has been a carry over.
161 * If there is, redo the read operation.
162 */
163 rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_read_base, ®);
164 if (rc < 0) {
165 dev_err(dev, "RTC read data register failed\n");
166 return rc;
167 }
168
169 if (unlikely(reg < value[0])) {
170 rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base,
171 value, sizeof(value));
172 if (rc) {
173 dev_err(dev, "RTC read data register failed\n");
174 return rc;
175 }
176 }
177
178 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
179
180 rtc_time_to_tm(secs, tm);
181
182 rc = rtc_valid_tm(tm);
183 if (rc < 0) {
184 dev_err(dev, "Invalid time read from RTC\n");
185 return rc;
186 }
187
188 dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
189 secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
190 tm->tm_mday, tm->tm_mon, tm->tm_year);
191
192 return 0;
193}
194
195static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
196{
197 int rc, i;
198 u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg;
199 unsigned long secs, irq_flags;
200 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
201
202 rtc_tm_to_time(&alarm->time, &secs);
203
204 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
205 value[i] = secs & 0xFF;
206 secs >>= 8;
207 }
208
209 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
210
211 rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->alarm_rw_base, value,
212 sizeof(value));
213 if (rc) {
214 dev_err(dev, "Write to RTC ALARM register failed\n");
215 goto rtc_rw_fail;
216 }
217
218 ctrl_reg = rtc_dd->ctrl_reg;
219
220 if (alarm->enabled)
221 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
222 else
223 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
224
225 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
226 if (rc) {
227 dev_err(dev, "Write to RTC control register failed\n");
228 goto rtc_rw_fail;
229 }
230
231 rtc_dd->ctrl_reg = ctrl_reg;
232
233 dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
234 alarm->time.tm_hour, alarm->time.tm_min,
235 alarm->time.tm_sec, alarm->time.tm_mday,
236 alarm->time.tm_mon, alarm->time.tm_year);
237rtc_rw_fail:
238 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
239 return rc;
240}
241
242static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
243{
244 int rc;
245 u8 value[NUM_8_BIT_RTC_REGS];
246 unsigned long secs;
247 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
248
249 rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->alarm_rw_base, value,
250 sizeof(value));
251 if (rc) {
252 dev_err(dev, "RTC alarm time read failed\n");
253 return rc;
254 }
255
256 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
257
258 rtc_time_to_tm(secs, &alarm->time);
259
260 rc = rtc_valid_tm(&alarm->time);
261 if (rc < 0) {
262 dev_err(dev, "Invalid alarm time read from RTC\n");
263 return rc;
264 }
265
266 dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
267 alarm->time.tm_hour, alarm->time.tm_min,
268 alarm->time.tm_sec, alarm->time.tm_mday,
269 alarm->time.tm_mon, alarm->time.tm_year);
270
271 return 0;
272}
273
274static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
275{
276 int rc;
277 unsigned long irq_flags;
278 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
279 u8 ctrl_reg;
280
281 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
282
283 ctrl_reg = rtc_dd->ctrl_reg;
284
285 if (enable)
286 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
287 else
288 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
289
290 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
291 if (rc) {
292 dev_err(dev, "Write to RTC control register failed\n");
293 goto rtc_rw_fail;
294 }
295
296 rtc_dd->ctrl_reg = ctrl_reg;
297
298rtc_rw_fail:
299 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
300 return rc;
301}
302
303static const struct rtc_class_ops pm8xxx_rtc_ops = {
304 .read_time = pm8xxx_rtc_read_time,
305 .set_time = pm8xxx_rtc_set_time,
306 .set_alarm = pm8xxx_rtc_set_alarm,
307 .read_alarm = pm8xxx_rtc_read_alarm,
308 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
309};
310
311static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
312{
313 struct pm8xxx_rtc *rtc_dd = dev_id;
314 unsigned int ctrl_reg;
315 int rc;
316 unsigned long irq_flags;
317
318 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
319
320 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
321
322 /* Clear the alarm enable bit */
323 ctrl_reg = rtc_dd->ctrl_reg;
324 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
325
326 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
327 if (rc) {
328 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
329 dev_err(rtc_dd->rtc_dev,
330 "Write to RTC control register failed\n");
331 goto rtc_alarm_handled;
332 }
333
334 rtc_dd->ctrl_reg = ctrl_reg;
335 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
336
337 /* Clear RTC alarm register */
338 rc = regmap_read(rtc_dd->regmap,
339 rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
340 &ctrl_reg);
341 if (rc) {
342 dev_err(rtc_dd->rtc_dev,
343 "RTC Alarm control register read failed\n");
344 goto rtc_alarm_handled;
345 }
346
347 ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR;
348 rc = regmap_write(rtc_dd->regmap,
349 rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
350 ctrl_reg);
351 if (rc)
352 dev_err(rtc_dd->rtc_dev,
353 "Write to RTC Alarm control register failed\n");
354
355rtc_alarm_handled:
356 return IRQ_HANDLED;
357}
358
359/*
360 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
361 */
362static const struct of_device_id pm8xxx_id_table[] = {
363 { .compatible = "qcom,pm8921-rtc", .data = (void *) 0x11D },
364 { .compatible = "qcom,pm8058-rtc", .data = (void *) 0x1E8 },
365 { },
366};
367MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
368
369static int pm8xxx_rtc_probe(struct platform_device *pdev)
370{
371 int rc;
372 unsigned int ctrl_reg;
373 struct pm8xxx_rtc *rtc_dd;
374 const struct of_device_id *match;
375
376 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
377 if (!match)
378 return -ENXIO;
379
380 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
381 if (rtc_dd == NULL)
382 return -ENOMEM;
383
384 /* Initialise spinlock to protect RTC control register */
385 spin_lock_init(&rtc_dd->ctrl_reg_lock);
386
387 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
388 if (!rtc_dd->regmap) {
389 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
390 return -ENXIO;
391 }
392
393 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
394 if (rtc_dd->rtc_alarm_irq < 0) {
395 dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
396 return -ENXIO;
397 }
398
399 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
400 "allow-set-time");
401
402 rtc_dd->rtc_base = (long) match->data;
403
404 /* Setup RTC register addresses */
405 rtc_dd->rtc_write_base = rtc_dd->rtc_base + PM8XXX_RTC_WRITE_OFFSET;
406 rtc_dd->rtc_read_base = rtc_dd->rtc_base + PM8XXX_RTC_READ_OFFSET;
407 rtc_dd->alarm_rw_base = rtc_dd->rtc_base + PM8XXX_ALARM_RW_OFFSET;
408
409 rtc_dd->rtc_dev = &pdev->dev;
410
411 /* Check if the RTC is on, else turn it on */
412 rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_base, &ctrl_reg);
413 if (rc) {
414 dev_err(&pdev->dev, "RTC control register read failed!\n");
415 return rc;
416 }
417
418 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
419 ctrl_reg |= PM8xxx_RTC_ENABLE;
420 rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
421 if (rc) {
422 dev_err(&pdev->dev,
423 "Write to RTC control register failed\n");
424 return rc;
425 }
426 }
427
428 rtc_dd->ctrl_reg = ctrl_reg;
429
430 platform_set_drvdata(pdev, rtc_dd);
431
432 device_init_wakeup(&pdev->dev, 1);
433
434 /* Register the RTC device */
435 rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
436 &pm8xxx_rtc_ops, THIS_MODULE);
437 if (IS_ERR(rtc_dd->rtc)) {
438 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
439 __func__, PTR_ERR(rtc_dd->rtc));
440 return PTR_ERR(rtc_dd->rtc);
441 }
442
443 /* Request the alarm IRQ */
444 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
445 pm8xxx_alarm_trigger,
446 IRQF_TRIGGER_RISING,
447 "pm8xxx_rtc_alarm", rtc_dd);
448 if (rc < 0) {
449 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
450 return rc;
451 }
452
453 dev_dbg(&pdev->dev, "Probe success !!\n");
454
455 return 0;
456}
457
458#ifdef CONFIG_PM_SLEEP
459static int pm8xxx_rtc_resume(struct device *dev)
460{
461 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
462
463 if (device_may_wakeup(dev))
464 disable_irq_wake(rtc_dd->rtc_alarm_irq);
465
466 return 0;
467}
468
469static int pm8xxx_rtc_suspend(struct device *dev)
470{
471 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
472
473 if (device_may_wakeup(dev))
474 enable_irq_wake(rtc_dd->rtc_alarm_irq);
475
476 return 0;
477}
478#endif
479
480static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
481 pm8xxx_rtc_suspend,
482 pm8xxx_rtc_resume);
483
484static struct platform_driver pm8xxx_rtc_driver = {
485 .probe = pm8xxx_rtc_probe,
486 .driver = {
487 .name = "rtc-pm8xxx",
488 .owner = THIS_MODULE,
489 .pm = &pm8xxx_rtc_pm_ops,
490 .of_match_table = pm8xxx_id_table,
491 },
492};
493
494module_platform_driver(pm8xxx_rtc_driver);
495
496MODULE_ALIAS("platform:rtc-pm8xxx");
497MODULE_DESCRIPTION("PMIC8xxx RTC driver");
498MODULE_LICENSE("GPL v2");
499MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");