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1/*
2 * Driver for Atmel Pulse Width Modulation Controller
3 *
4 * Copyright (C) 2013 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21
22/* The following is global registers for PWM controller */
23#define PWM_ENA 0x04
24#define PWM_DIS 0x08
25#define PWM_SR 0x0C
26#define PWM_ISR 0x1C
27/* Bit field in SR */
28#define PWM_SR_ALL_CH_ON 0x0F
29
30/* The following register is PWM channel related registers */
31#define PWM_CH_REG_OFFSET 0x200
32#define PWM_CH_REG_SIZE 0x20
33
34#define PWM_CMR 0x0
35/* Bit field in CMR */
36#define PWM_CMR_CPOL (1 << 9)
37#define PWM_CMR_UPD_CDTY (1 << 10)
38#define PWM_CMR_CPRE_MSK 0xF
39
40/* The following registers for PWM v1 */
41#define PWMV1_CDTY 0x04
42#define PWMV1_CPRD 0x08
43#define PWMV1_CUPD 0x10
44
45/* The following registers for PWM v2 */
46#define PWMV2_CDTY 0x04
47#define PWMV2_CDTYUPD 0x08
48#define PWMV2_CPRD 0x0C
49#define PWMV2_CPRDUPD 0x10
50
51/*
52 * Max value for duty and period
53 *
54 * Although the duty and period register is 32 bit,
55 * however only the LSB 16 bits are significant.
56 */
57#define PWM_MAX_DTY 0xFFFF
58#define PWM_MAX_PRD 0xFFFF
59#define PRD_MAX_PRES 10
60
61struct atmel_pwm_chip {
62 struct pwm_chip chip;
63 struct clk *clk;
64 void __iomem *base;
65
66 unsigned int updated_pwms;
67 struct mutex isr_lock; /* ISR is cleared when read, ensure only one thread does that */
68
69 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
70 unsigned long dty, unsigned long prd);
71};
72
73static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
74{
75 return container_of(chip, struct atmel_pwm_chip, chip);
76}
77
78static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
79 unsigned long offset)
80{
81 return readl_relaxed(chip->base + offset);
82}
83
84static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
85 unsigned long offset, unsigned long val)
86{
87 writel_relaxed(val, chip->base + offset);
88}
89
90static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
91 unsigned int ch, unsigned long offset)
92{
93 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
94
95 return readl_relaxed(chip->base + base + offset);
96}
97
98static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
99 unsigned int ch, unsigned long offset,
100 unsigned long val)
101{
102 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
103
104 writel_relaxed(val, chip->base + base + offset);
105}
106
107static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
108 int duty_ns, int period_ns)
109{
110 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
111 unsigned long prd, dty;
112 unsigned long long div;
113 unsigned int pres = 0;
114 u32 val;
115 int ret;
116
117 if (pwm_is_enabled(pwm) && (period_ns != pwm_get_period(pwm))) {
118 dev_err(chip->dev, "cannot change PWM period while enabled\n");
119 return -EBUSY;
120 }
121
122 /* Calculate the period cycles and prescale value */
123 div = (unsigned long long)clk_get_rate(atmel_pwm->clk) * period_ns;
124 do_div(div, NSEC_PER_SEC);
125
126 while (div > PWM_MAX_PRD) {
127 div >>= 1;
128 pres++;
129 }
130
131 if (pres > PRD_MAX_PRES) {
132 dev_err(chip->dev, "pres exceeds the maximum value\n");
133 return -EINVAL;
134 }
135
136 /* Calculate the duty cycles */
137 prd = div;
138 div *= duty_ns;
139 do_div(div, period_ns);
140 dty = prd - div;
141
142 ret = clk_enable(atmel_pwm->clk);
143 if (ret) {
144 dev_err(chip->dev, "failed to enable PWM clock\n");
145 return ret;
146 }
147
148 /* It is necessary to preserve CPOL, inside CMR */
149 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
150 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
151 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
152 atmel_pwm->config(chip, pwm, dty, prd);
153 mutex_lock(&atmel_pwm->isr_lock);
154 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
155 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
156 mutex_unlock(&atmel_pwm->isr_lock);
157
158 clk_disable(atmel_pwm->clk);
159 return ret;
160}
161
162static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
163 unsigned long dty, unsigned long prd)
164{
165 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
166 unsigned int val;
167
168
169 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
170
171 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
172 val &= ~PWM_CMR_UPD_CDTY;
173 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
174
175 /*
176 * If the PWM channel is enabled, only update CDTY by using the update
177 * register, it needs to set bit 10 of CMR to 0
178 */
179 if (pwm_is_enabled(pwm))
180 return;
181 /*
182 * If the PWM channel is disabled, write value to duty and period
183 * registers directly.
184 */
185 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
186 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
187}
188
189static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
190 unsigned long dty, unsigned long prd)
191{
192 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
193
194 if (pwm_is_enabled(pwm)) {
195 /*
196 * If the PWM channel is enabled, using the duty update register
197 * to update the value.
198 */
199 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTYUPD, dty);
200 } else {
201 /*
202 * If the PWM channel is disabled, write value to duty and
203 * period registers directly.
204 */
205 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTY, dty);
206 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CPRD, prd);
207 }
208}
209
210static int atmel_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
211 enum pwm_polarity polarity)
212{
213 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
214 u32 val;
215 int ret;
216
217 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
218
219 if (polarity == PWM_POLARITY_NORMAL)
220 val &= ~PWM_CMR_CPOL;
221 else
222 val |= PWM_CMR_CPOL;
223
224 ret = clk_enable(atmel_pwm->clk);
225 if (ret) {
226 dev_err(chip->dev, "failed to enable PWM clock\n");
227 return ret;
228 }
229
230 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
231
232 clk_disable(atmel_pwm->clk);
233
234 return 0;
235}
236
237static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
238{
239 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
240 int ret;
241
242 ret = clk_enable(atmel_pwm->clk);
243 if (ret) {
244 dev_err(chip->dev, "failed to enable PWM clock\n");
245 return ret;
246 }
247
248 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
249
250 return 0;
251}
252
253static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
254{
255 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
256 unsigned long timeout = jiffies + 2 * HZ;
257
258 /*
259 * Wait for at least a complete period to have passed before disabling a
260 * channel to be sure that CDTY has been updated
261 */
262 mutex_lock(&atmel_pwm->isr_lock);
263 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
264
265 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
266 time_before(jiffies, timeout)) {
267 usleep_range(10, 100);
268 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
269 }
270
271 mutex_unlock(&atmel_pwm->isr_lock);
272 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
273
274 clk_disable(atmel_pwm->clk);
275}
276
277static const struct pwm_ops atmel_pwm_ops = {
278 .config = atmel_pwm_config,
279 .set_polarity = atmel_pwm_set_polarity,
280 .enable = atmel_pwm_enable,
281 .disable = atmel_pwm_disable,
282 .owner = THIS_MODULE,
283};
284
285struct atmel_pwm_data {
286 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
287 unsigned long dty, unsigned long prd);
288};
289
290static const struct atmel_pwm_data atmel_pwm_data_v1 = {
291 .config = atmel_pwm_config_v1,
292};
293
294static const struct atmel_pwm_data atmel_pwm_data_v2 = {
295 .config = atmel_pwm_config_v2,
296};
297
298static const struct platform_device_id atmel_pwm_devtypes[] = {
299 {
300 .name = "at91sam9rl-pwm",
301 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v1,
302 }, {
303 .name = "sama5d3-pwm",
304 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v2,
305 }, {
306 /* sentinel */
307 },
308};
309MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
310
311static const struct of_device_id atmel_pwm_dt_ids[] = {
312 {
313 .compatible = "atmel,at91sam9rl-pwm",
314 .data = &atmel_pwm_data_v1,
315 }, {
316 .compatible = "atmel,sama5d3-pwm",
317 .data = &atmel_pwm_data_v2,
318 }, {
319 /* sentinel */
320 },
321};
322MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
323
324static inline const struct atmel_pwm_data *
325atmel_pwm_get_driver_data(struct platform_device *pdev)
326{
327 if (pdev->dev.of_node) {
328 const struct of_device_id *match;
329
330 match = of_match_device(atmel_pwm_dt_ids, &pdev->dev);
331 if (!match)
332 return NULL;
333
334 return match->data;
335 } else {
336 const struct platform_device_id *id;
337
338 id = platform_get_device_id(pdev);
339
340 return (struct atmel_pwm_data *)id->driver_data;
341 }
342}
343
344static int atmel_pwm_probe(struct platform_device *pdev)
345{
346 const struct atmel_pwm_data *data;
347 struct atmel_pwm_chip *atmel_pwm;
348 struct resource *res;
349 int ret;
350
351 data = atmel_pwm_get_driver_data(pdev);
352 if (!data)
353 return -ENODEV;
354
355 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
356 if (!atmel_pwm)
357 return -ENOMEM;
358
359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
361 if (IS_ERR(atmel_pwm->base))
362 return PTR_ERR(atmel_pwm->base);
363
364 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
365 if (IS_ERR(atmel_pwm->clk))
366 return PTR_ERR(atmel_pwm->clk);
367
368 ret = clk_prepare(atmel_pwm->clk);
369 if (ret) {
370 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
371 return ret;
372 }
373
374 atmel_pwm->chip.dev = &pdev->dev;
375 atmel_pwm->chip.ops = &atmel_pwm_ops;
376
377 if (pdev->dev.of_node) {
378 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
379 atmel_pwm->chip.of_pwm_n_cells = 3;
380 }
381
382 atmel_pwm->chip.base = -1;
383 atmel_pwm->chip.npwm = 4;
384 atmel_pwm->chip.can_sleep = true;
385 atmel_pwm->config = data->config;
386 atmel_pwm->updated_pwms = 0;
387 mutex_init(&atmel_pwm->isr_lock);
388
389 ret = pwmchip_add(&atmel_pwm->chip);
390 if (ret < 0) {
391 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
392 goto unprepare_clk;
393 }
394
395 platform_set_drvdata(pdev, atmel_pwm);
396
397 return ret;
398
399unprepare_clk:
400 clk_unprepare(atmel_pwm->clk);
401 return ret;
402}
403
404static int atmel_pwm_remove(struct platform_device *pdev)
405{
406 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
407
408 clk_unprepare(atmel_pwm->clk);
409 mutex_destroy(&atmel_pwm->isr_lock);
410
411 return pwmchip_remove(&atmel_pwm->chip);
412}
413
414static struct platform_driver atmel_pwm_driver = {
415 .driver = {
416 .name = "atmel-pwm",
417 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
418 },
419 .id_table = atmel_pwm_devtypes,
420 .probe = atmel_pwm_probe,
421 .remove = atmel_pwm_remove,
422};
423module_platform_driver(atmel_pwm_driver);
424
425MODULE_ALIAS("platform:atmel-pwm");
426MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
427MODULE_DESCRIPTION("Atmel PWM driver");
428MODULE_LICENSE("GPL v2");
1/*
2 * Driver for Atmel Pulse Width Modulation Controller
3 *
4 * Copyright (C) 2013 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/pwm.h>
18#include <linux/slab.h>
19
20/* The following is global registers for PWM controller */
21#define PWM_ENA 0x04
22#define PWM_DIS 0x08
23#define PWM_SR 0x0C
24/* Bit field in SR */
25#define PWM_SR_ALL_CH_ON 0x0F
26
27/* The following register is PWM channel related registers */
28#define PWM_CH_REG_OFFSET 0x200
29#define PWM_CH_REG_SIZE 0x20
30
31#define PWM_CMR 0x0
32/* Bit field in CMR */
33#define PWM_CMR_CPOL (1 << 9)
34#define PWM_CMR_UPD_CDTY (1 << 10)
35#define PWM_CMR_CPRE_MSK 0xF
36
37/* The following registers for PWM v1 */
38#define PWMV1_CDTY 0x04
39#define PWMV1_CPRD 0x08
40#define PWMV1_CUPD 0x10
41
42/* The following registers for PWM v2 */
43#define PWMV2_CDTY 0x04
44#define PWMV2_CDTYUPD 0x08
45#define PWMV2_CPRD 0x0C
46#define PWMV2_CPRDUPD 0x10
47
48/*
49 * Max value for duty and period
50 *
51 * Although the duty and period register is 32 bit,
52 * however only the LSB 16 bits are significant.
53 */
54#define PWM_MAX_DTY 0xFFFF
55#define PWM_MAX_PRD 0xFFFF
56#define PRD_MAX_PRES 10
57
58struct atmel_pwm_chip {
59 struct pwm_chip chip;
60 struct clk *clk;
61 void __iomem *base;
62
63 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
64 unsigned long dty, unsigned long prd);
65};
66
67static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
68{
69 return container_of(chip, struct atmel_pwm_chip, chip);
70}
71
72static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
73 unsigned long offset)
74{
75 return readl_relaxed(chip->base + offset);
76}
77
78static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
79 unsigned long offset, unsigned long val)
80{
81 writel_relaxed(val, chip->base + offset);
82}
83
84static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
85 unsigned int ch, unsigned long offset)
86{
87 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
88
89 return readl_relaxed(chip->base + base + offset);
90}
91
92static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
93 unsigned int ch, unsigned long offset,
94 unsigned long val)
95{
96 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
97
98 writel_relaxed(val, chip->base + base + offset);
99}
100
101static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
102 int duty_ns, int period_ns)
103{
104 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
105 unsigned long clk_rate, prd, dty;
106 unsigned long long div;
107 unsigned int pres = 0;
108 u32 val;
109 int ret;
110
111 if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) {
112 dev_err(chip->dev, "cannot change PWM period while enabled\n");
113 return -EBUSY;
114 }
115
116 clk_rate = clk_get_rate(atmel_pwm->clk);
117 div = clk_rate;
118
119 /* Calculate the period cycles */
120 while (div > PWM_MAX_PRD) {
121 div = clk_rate / (1 << pres);
122 div = div * period_ns;
123 /* 1/Hz = 100000000 ns */
124 do_div(div, 1000000000);
125
126 if (pres++ > PRD_MAX_PRES) {
127 dev_err(chip->dev, "pres exceeds the maximum value\n");
128 return -EINVAL;
129 }
130 }
131
132 /* Calculate the duty cycles */
133 prd = div;
134 div *= duty_ns;
135 do_div(div, period_ns);
136 dty = prd - div;
137
138 ret = clk_enable(atmel_pwm->clk);
139 if (ret) {
140 dev_err(chip->dev, "failed to enable PWM clock\n");
141 return ret;
142 }
143
144 /* It is necessary to preserve CPOL, inside CMR */
145 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
146 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
147 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
148 atmel_pwm->config(chip, pwm, dty, prd);
149
150 clk_disable(atmel_pwm->clk);
151 return ret;
152}
153
154static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
155 unsigned long dty, unsigned long prd)
156{
157 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
158 unsigned int val;
159
160 if (test_bit(PWMF_ENABLED, &pwm->flags)) {
161 /*
162 * If the PWM channel is enabled, using the update register,
163 * it needs to set bit 10 of CMR to 0
164 */
165 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
166
167 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
168 val &= ~PWM_CMR_UPD_CDTY;
169 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
170 } else {
171 /*
172 * If the PWM channel is disabled, write value to duty and
173 * period registers directly.
174 */
175 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
176 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
177 }
178}
179
180static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
181 unsigned long dty, unsigned long prd)
182{
183 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
184
185 if (test_bit(PWMF_ENABLED, &pwm->flags)) {
186 /*
187 * If the PWM channel is enabled, using the duty update register
188 * to update the value.
189 */
190 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTYUPD, dty);
191 } else {
192 /*
193 * If the PWM channel is disabled, write value to duty and
194 * period registers directly.
195 */
196 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTY, dty);
197 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CPRD, prd);
198 }
199}
200
201static int atmel_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
202 enum pwm_polarity polarity)
203{
204 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
205 u32 val;
206 int ret;
207
208 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
209
210 if (polarity == PWM_POLARITY_NORMAL)
211 val &= ~PWM_CMR_CPOL;
212 else
213 val |= PWM_CMR_CPOL;
214
215 ret = clk_enable(atmel_pwm->clk);
216 if (ret) {
217 dev_err(chip->dev, "failed to enable PWM clock\n");
218 return ret;
219 }
220
221 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
222
223 clk_disable(atmel_pwm->clk);
224
225 return 0;
226}
227
228static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
229{
230 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
231 int ret;
232
233 ret = clk_enable(atmel_pwm->clk);
234 if (ret) {
235 dev_err(chip->dev, "failed to enable PWM clock\n");
236 return ret;
237 }
238
239 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
240
241 return 0;
242}
243
244static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
245{
246 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
247
248 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
249
250 clk_disable(atmel_pwm->clk);
251}
252
253static const struct pwm_ops atmel_pwm_ops = {
254 .config = atmel_pwm_config,
255 .set_polarity = atmel_pwm_set_polarity,
256 .enable = atmel_pwm_enable,
257 .disable = atmel_pwm_disable,
258 .owner = THIS_MODULE,
259};
260
261struct atmel_pwm_data {
262 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
263 unsigned long dty, unsigned long prd);
264};
265
266static const struct atmel_pwm_data atmel_pwm_data_v1 = {
267 .config = atmel_pwm_config_v1,
268};
269
270static const struct atmel_pwm_data atmel_pwm_data_v2 = {
271 .config = atmel_pwm_config_v2,
272};
273
274static const struct platform_device_id atmel_pwm_devtypes[] = {
275 {
276 .name = "at91sam9rl-pwm",
277 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v1,
278 }, {
279 .name = "sama5d3-pwm",
280 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v2,
281 }, {
282 /* sentinel */
283 },
284};
285MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
286
287static const struct of_device_id atmel_pwm_dt_ids[] = {
288 {
289 .compatible = "atmel,at91sam9rl-pwm",
290 .data = &atmel_pwm_data_v1,
291 }, {
292 .compatible = "atmel,sama5d3-pwm",
293 .data = &atmel_pwm_data_v2,
294 }, {
295 /* sentinel */
296 },
297};
298MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
299
300static inline const struct atmel_pwm_data *
301atmel_pwm_get_driver_data(struct platform_device *pdev)
302{
303 if (pdev->dev.of_node) {
304 const struct of_device_id *match;
305
306 match = of_match_device(atmel_pwm_dt_ids, &pdev->dev);
307 if (!match)
308 return NULL;
309
310 return match->data;
311 } else {
312 const struct platform_device_id *id;
313
314 id = platform_get_device_id(pdev);
315
316 return (struct atmel_pwm_data *)id->driver_data;
317 }
318}
319
320static int atmel_pwm_probe(struct platform_device *pdev)
321{
322 const struct atmel_pwm_data *data;
323 struct atmel_pwm_chip *atmel_pwm;
324 struct resource *res;
325 int ret;
326
327 data = atmel_pwm_get_driver_data(pdev);
328 if (!data)
329 return -ENODEV;
330
331 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
332 if (!atmel_pwm)
333 return -ENOMEM;
334
335 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
336 atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
337 if (IS_ERR(atmel_pwm->base))
338 return PTR_ERR(atmel_pwm->base);
339
340 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
341 if (IS_ERR(atmel_pwm->clk))
342 return PTR_ERR(atmel_pwm->clk);
343
344 ret = clk_prepare(atmel_pwm->clk);
345 if (ret) {
346 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
347 return ret;
348 }
349
350 atmel_pwm->chip.dev = &pdev->dev;
351 atmel_pwm->chip.ops = &atmel_pwm_ops;
352
353 if (pdev->dev.of_node) {
354 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
355 atmel_pwm->chip.of_pwm_n_cells = 3;
356 }
357
358 atmel_pwm->chip.base = -1;
359 atmel_pwm->chip.npwm = 4;
360 atmel_pwm->config = data->config;
361
362 ret = pwmchip_add(&atmel_pwm->chip);
363 if (ret < 0) {
364 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
365 goto unprepare_clk;
366 }
367
368 platform_set_drvdata(pdev, atmel_pwm);
369
370 return ret;
371
372unprepare_clk:
373 clk_unprepare(atmel_pwm->clk);
374 return ret;
375}
376
377static int atmel_pwm_remove(struct platform_device *pdev)
378{
379 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
380
381 clk_unprepare(atmel_pwm->clk);
382
383 return pwmchip_remove(&atmel_pwm->chip);
384}
385
386static struct platform_driver atmel_pwm_driver = {
387 .driver = {
388 .name = "atmel-pwm",
389 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
390 },
391 .id_table = atmel_pwm_devtypes,
392 .probe = atmel_pwm_probe,
393 .remove = atmel_pwm_remove,
394};
395module_platform_driver(atmel_pwm_driver);
396
397MODULE_ALIAS("platform:atmel-pwm");
398MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
399MODULE_DESCRIPTION("Atmel PWM driver");
400MODULE_LICENSE("GPL v2");