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1/*
2 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
3 *
4 * Copyright (C) 2006 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/sched.h>
18
19#include <linux/nvmem-provider.h>
20#include <linux/regmap.h>
21#include <linux/spi/spi.h>
22#include <linux/spi/eeprom.h>
23#include <linux/property.h>
24
25/*
26 * NOTE: this is an *EEPROM* driver. The vagaries of product naming
27 * mean that some AT25 products are EEPROMs, and others are FLASH.
28 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
29 * not this one!
30 */
31
32struct at25_data {
33 struct spi_device *spi;
34 struct mutex lock;
35 struct spi_eeprom chip;
36 unsigned addrlen;
37 struct regmap_config regmap_config;
38 struct nvmem_config nvmem_config;
39 struct nvmem_device *nvmem;
40};
41
42#define AT25_WREN 0x06 /* latch the write enable */
43#define AT25_WRDI 0x04 /* reset the write enable */
44#define AT25_RDSR 0x05 /* read status register */
45#define AT25_WRSR 0x01 /* write status register */
46#define AT25_READ 0x03 /* read byte(s) */
47#define AT25_WRITE 0x02 /* write byte(s)/sector */
48
49#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
50#define AT25_SR_WEN 0x02 /* write enable (latched) */
51#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
52#define AT25_SR_BP1 0x08
53#define AT25_SR_WPEN 0x80 /* writeprotect enable */
54
55#define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */
56
57#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
58
59/* Specs often allow 5 msec for a page write, sometimes 20 msec;
60 * it's important to recover from write timeouts.
61 */
62#define EE_TIMEOUT 25
63
64/*-------------------------------------------------------------------------*/
65
66#define io_limit PAGE_SIZE /* bytes */
67
68static ssize_t
69at25_ee_read(
70 struct at25_data *at25,
71 char *buf,
72 unsigned offset,
73 size_t count
74)
75{
76 u8 command[EE_MAXADDRLEN + 1];
77 u8 *cp;
78 ssize_t status;
79 struct spi_transfer t[2];
80 struct spi_message m;
81 u8 instr;
82
83 if (unlikely(offset >= at25->chip.byte_len))
84 return 0;
85 if ((offset + count) > at25->chip.byte_len)
86 count = at25->chip.byte_len - offset;
87 if (unlikely(!count))
88 return count;
89
90 cp = command;
91
92 instr = AT25_READ;
93 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
94 if (offset >= (1U << (at25->addrlen * 8)))
95 instr |= AT25_INSTR_BIT3;
96 *cp++ = instr;
97
98 /* 8/16/24-bit address is written MSB first */
99 switch (at25->addrlen) {
100 default: /* case 3 */
101 *cp++ = offset >> 16;
102 case 2:
103 *cp++ = offset >> 8;
104 case 1:
105 case 0: /* can't happen: for better codegen */
106 *cp++ = offset >> 0;
107 }
108
109 spi_message_init(&m);
110 memset(t, 0, sizeof t);
111
112 t[0].tx_buf = command;
113 t[0].len = at25->addrlen + 1;
114 spi_message_add_tail(&t[0], &m);
115
116 t[1].rx_buf = buf;
117 t[1].len = count;
118 spi_message_add_tail(&t[1], &m);
119
120 mutex_lock(&at25->lock);
121
122 /* Read it all at once.
123 *
124 * REVISIT that's potentially a problem with large chips, if
125 * other devices on the bus need to be accessed regularly or
126 * this chip is clocked very slowly
127 */
128 status = spi_sync(at25->spi, &m);
129 dev_dbg(&at25->spi->dev,
130 "read %Zd bytes at %d --> %d\n",
131 count, offset, (int) status);
132
133 mutex_unlock(&at25->lock);
134 return status ? status : count;
135}
136
137static int at25_regmap_read(void *context, const void *reg, size_t reg_size,
138 void *val, size_t val_size)
139{
140 struct at25_data *at25 = context;
141 off_t offset = *(u32 *)reg;
142 int err;
143
144 err = at25_ee_read(at25, val, offset, val_size);
145 if (err)
146 return err;
147 return 0;
148}
149
150static ssize_t
151at25_ee_write(struct at25_data *at25, const char *buf, loff_t off,
152 size_t count)
153{
154 ssize_t status = 0;
155 unsigned written = 0;
156 unsigned buf_size;
157 u8 *bounce;
158
159 if (unlikely(off >= at25->chip.byte_len))
160 return -EFBIG;
161 if ((off + count) > at25->chip.byte_len)
162 count = at25->chip.byte_len - off;
163 if (unlikely(!count))
164 return count;
165
166 /* Temp buffer starts with command and address */
167 buf_size = at25->chip.page_size;
168 if (buf_size > io_limit)
169 buf_size = io_limit;
170 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
171 if (!bounce)
172 return -ENOMEM;
173
174 /* For write, rollover is within the page ... so we write at
175 * most one page, then manually roll over to the next page.
176 */
177 mutex_lock(&at25->lock);
178 do {
179 unsigned long timeout, retries;
180 unsigned segment;
181 unsigned offset = (unsigned) off;
182 u8 *cp = bounce;
183 int sr;
184 u8 instr;
185
186 *cp = AT25_WREN;
187 status = spi_write(at25->spi, cp, 1);
188 if (status < 0) {
189 dev_dbg(&at25->spi->dev, "WREN --> %d\n",
190 (int) status);
191 break;
192 }
193
194 instr = AT25_WRITE;
195 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
196 if (offset >= (1U << (at25->addrlen * 8)))
197 instr |= AT25_INSTR_BIT3;
198 *cp++ = instr;
199
200 /* 8/16/24-bit address is written MSB first */
201 switch (at25->addrlen) {
202 default: /* case 3 */
203 *cp++ = offset >> 16;
204 case 2:
205 *cp++ = offset >> 8;
206 case 1:
207 case 0: /* can't happen: for better codegen */
208 *cp++ = offset >> 0;
209 }
210
211 /* Write as much of a page as we can */
212 segment = buf_size - (offset % buf_size);
213 if (segment > count)
214 segment = count;
215 memcpy(cp, buf, segment);
216 status = spi_write(at25->spi, bounce,
217 segment + at25->addrlen + 1);
218 dev_dbg(&at25->spi->dev,
219 "write %u bytes at %u --> %d\n",
220 segment, offset, (int) status);
221 if (status < 0)
222 break;
223
224 /* REVISIT this should detect (or prevent) failed writes
225 * to readonly sections of the EEPROM...
226 */
227
228 /* Wait for non-busy status */
229 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
230 retries = 0;
231 do {
232
233 sr = spi_w8r8(at25->spi, AT25_RDSR);
234 if (sr < 0 || (sr & AT25_SR_nRDY)) {
235 dev_dbg(&at25->spi->dev,
236 "rdsr --> %d (%02x)\n", sr, sr);
237 /* at HZ=100, this is sloooow */
238 msleep(1);
239 continue;
240 }
241 if (!(sr & AT25_SR_nRDY))
242 break;
243 } while (retries++ < 3 || time_before_eq(jiffies, timeout));
244
245 if ((sr < 0) || (sr & AT25_SR_nRDY)) {
246 dev_err(&at25->spi->dev,
247 "write %d bytes offset %d, "
248 "timeout after %u msecs\n",
249 segment, offset,
250 jiffies_to_msecs(jiffies -
251 (timeout - EE_TIMEOUT)));
252 status = -ETIMEDOUT;
253 break;
254 }
255
256 off += segment;
257 buf += segment;
258 count -= segment;
259 written += segment;
260
261 } while (count > 0);
262
263 mutex_unlock(&at25->lock);
264
265 kfree(bounce);
266 return written ? written : status;
267}
268
269static int at25_regmap_write(void *context, const void *data, size_t count)
270{
271 struct at25_data *at25 = context;
272 const char *buf;
273 u32 offset;
274 size_t len;
275 int err;
276
277 memcpy(&offset, data, sizeof(offset));
278 buf = (const char *)data + sizeof(offset);
279 len = count - sizeof(offset);
280
281 err = at25_ee_write(at25, buf, offset, len);
282 if (err)
283 return err;
284 return 0;
285}
286
287static const struct regmap_bus at25_regmap_bus = {
288 .read = at25_regmap_read,
289 .write = at25_regmap_write,
290 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
291};
292
293/*-------------------------------------------------------------------------*/
294
295static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
296{
297 u32 val;
298
299 memset(chip, 0, sizeof(*chip));
300 strncpy(chip->name, "at25", sizeof(chip->name));
301
302 if (device_property_read_u32(dev, "size", &val) == 0 ||
303 device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
304 chip->byte_len = val;
305 } else {
306 dev_err(dev, "Error: missing \"size\" property\n");
307 return -ENODEV;
308 }
309
310 if (device_property_read_u32(dev, "pagesize", &val) == 0 ||
311 device_property_read_u32(dev, "at25,page-size", &val) == 0) {
312 chip->page_size = (u16)val;
313 } else {
314 dev_err(dev, "Error: missing \"pagesize\" property\n");
315 return -ENODEV;
316 }
317
318 if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
319 chip->flags = (u16)val;
320 } else {
321 if (device_property_read_u32(dev, "address-width", &val)) {
322 dev_err(dev,
323 "Error: missing \"address-width\" property\n");
324 return -ENODEV;
325 }
326 switch (val) {
327 case 8:
328 chip->flags |= EE_ADDR1;
329 break;
330 case 16:
331 chip->flags |= EE_ADDR2;
332 break;
333 case 24:
334 chip->flags |= EE_ADDR3;
335 break;
336 default:
337 dev_err(dev,
338 "Error: bad \"address-width\" property: %u\n",
339 val);
340 return -ENODEV;
341 }
342 if (device_property_present(dev, "read-only"))
343 chip->flags |= EE_READONLY;
344 }
345 return 0;
346}
347
348static int at25_probe(struct spi_device *spi)
349{
350 struct at25_data *at25 = NULL;
351 struct spi_eeprom chip;
352 struct regmap *regmap;
353 int err;
354 int sr;
355 int addrlen;
356
357 /* Chip description */
358 if (!spi->dev.platform_data) {
359 err = at25_fw_to_chip(&spi->dev, &chip);
360 if (err)
361 return err;
362 } else
363 chip = *(struct spi_eeprom *)spi->dev.platform_data;
364
365 /* For now we only support 8/16/24 bit addressing */
366 if (chip.flags & EE_ADDR1)
367 addrlen = 1;
368 else if (chip.flags & EE_ADDR2)
369 addrlen = 2;
370 else if (chip.flags & EE_ADDR3)
371 addrlen = 3;
372 else {
373 dev_dbg(&spi->dev, "unsupported address type\n");
374 return -EINVAL;
375 }
376
377 /* Ping the chip ... the status register is pretty portable,
378 * unlike probing manufacturer IDs. We do expect that system
379 * firmware didn't write it in the past few milliseconds!
380 */
381 sr = spi_w8r8(spi, AT25_RDSR);
382 if (sr < 0 || sr & AT25_SR_nRDY) {
383 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
384 return -ENXIO;
385 }
386
387 at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
388 if (!at25)
389 return -ENOMEM;
390
391 mutex_init(&at25->lock);
392 at25->chip = chip;
393 at25->spi = spi_dev_get(spi);
394 spi_set_drvdata(spi, at25);
395 at25->addrlen = addrlen;
396
397 at25->regmap_config.reg_bits = 32;
398 at25->regmap_config.val_bits = 8;
399 at25->regmap_config.reg_stride = 1;
400 at25->regmap_config.max_register = chip.byte_len - 1;
401
402 regmap = devm_regmap_init(&spi->dev, &at25_regmap_bus, at25,
403 &at25->regmap_config);
404 if (IS_ERR(regmap)) {
405 dev_err(&spi->dev, "regmap init failed\n");
406 return PTR_ERR(regmap);
407 }
408
409 at25->nvmem_config.name = dev_name(&spi->dev);
410 at25->nvmem_config.dev = &spi->dev;
411 at25->nvmem_config.read_only = chip.flags & EE_READONLY;
412 at25->nvmem_config.root_only = true;
413 at25->nvmem_config.owner = THIS_MODULE;
414 at25->nvmem_config.compat = true;
415 at25->nvmem_config.base_dev = &spi->dev;
416
417 at25->nvmem = nvmem_register(&at25->nvmem_config);
418 if (IS_ERR(at25->nvmem))
419 return PTR_ERR(at25->nvmem);
420
421 dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
422 (chip.byte_len < 1024)
423 ? chip.byte_len
424 : (chip.byte_len / 1024),
425 (chip.byte_len < 1024) ? "Byte" : "KByte",
426 at25->chip.name,
427 (chip.flags & EE_READONLY) ? " (readonly)" : "",
428 at25->chip.page_size);
429 return 0;
430}
431
432static int at25_remove(struct spi_device *spi)
433{
434 struct at25_data *at25;
435
436 at25 = spi_get_drvdata(spi);
437 nvmem_unregister(at25->nvmem);
438
439 return 0;
440}
441
442/*-------------------------------------------------------------------------*/
443
444static const struct of_device_id at25_of_match[] = {
445 { .compatible = "atmel,at25", },
446 { }
447};
448MODULE_DEVICE_TABLE(of, at25_of_match);
449
450static struct spi_driver at25_driver = {
451 .driver = {
452 .name = "at25",
453 .of_match_table = at25_of_match,
454 },
455 .probe = at25_probe,
456 .remove = at25_remove,
457};
458
459module_spi_driver(at25_driver);
460
461MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
462MODULE_AUTHOR("David Brownell");
463MODULE_LICENSE("GPL");
464MODULE_ALIAS("spi:at25");
1/*
2 * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
3 *
4 * Copyright (C) 2006 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/sched.h>
18
19#include <linux/spi/spi.h>
20#include <linux/spi/eeprom.h>
21#include <linux/of.h>
22
23/*
24 * NOTE: this is an *EEPROM* driver. The vagaries of product naming
25 * mean that some AT25 products are EEPROMs, and others are FLASH.
26 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
27 * not this one!
28 */
29
30struct at25_data {
31 struct spi_device *spi;
32 struct memory_accessor mem;
33 struct mutex lock;
34 struct spi_eeprom chip;
35 struct bin_attribute bin;
36 unsigned addrlen;
37};
38
39#define AT25_WREN 0x06 /* latch the write enable */
40#define AT25_WRDI 0x04 /* reset the write enable */
41#define AT25_RDSR 0x05 /* read status register */
42#define AT25_WRSR 0x01 /* write status register */
43#define AT25_READ 0x03 /* read byte(s) */
44#define AT25_WRITE 0x02 /* write byte(s)/sector */
45
46#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
47#define AT25_SR_WEN 0x02 /* write enable (latched) */
48#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
49#define AT25_SR_BP1 0x08
50#define AT25_SR_WPEN 0x80 /* writeprotect enable */
51
52#define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */
53
54#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
55
56/* Specs often allow 5 msec for a page write, sometimes 20 msec;
57 * it's important to recover from write timeouts.
58 */
59#define EE_TIMEOUT 25
60
61/*-------------------------------------------------------------------------*/
62
63#define io_limit PAGE_SIZE /* bytes */
64
65static ssize_t
66at25_ee_read(
67 struct at25_data *at25,
68 char *buf,
69 unsigned offset,
70 size_t count
71)
72{
73 u8 command[EE_MAXADDRLEN + 1];
74 u8 *cp;
75 ssize_t status;
76 struct spi_transfer t[2];
77 struct spi_message m;
78 u8 instr;
79
80 if (unlikely(offset >= at25->bin.size))
81 return 0;
82 if ((offset + count) > at25->bin.size)
83 count = at25->bin.size - offset;
84 if (unlikely(!count))
85 return count;
86
87 cp = command;
88
89 instr = AT25_READ;
90 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
91 if (offset >= (1U << (at25->addrlen * 8)))
92 instr |= AT25_INSTR_BIT3;
93 *cp++ = instr;
94
95 /* 8/16/24-bit address is written MSB first */
96 switch (at25->addrlen) {
97 default: /* case 3 */
98 *cp++ = offset >> 16;
99 case 2:
100 *cp++ = offset >> 8;
101 case 1:
102 case 0: /* can't happen: for better codegen */
103 *cp++ = offset >> 0;
104 }
105
106 spi_message_init(&m);
107 memset(t, 0, sizeof t);
108
109 t[0].tx_buf = command;
110 t[0].len = at25->addrlen + 1;
111 spi_message_add_tail(&t[0], &m);
112
113 t[1].rx_buf = buf;
114 t[1].len = count;
115 spi_message_add_tail(&t[1], &m);
116
117 mutex_lock(&at25->lock);
118
119 /* Read it all at once.
120 *
121 * REVISIT that's potentially a problem with large chips, if
122 * other devices on the bus need to be accessed regularly or
123 * this chip is clocked very slowly
124 */
125 status = spi_sync(at25->spi, &m);
126 dev_dbg(&at25->spi->dev,
127 "read %Zd bytes at %d --> %d\n",
128 count, offset, (int) status);
129
130 mutex_unlock(&at25->lock);
131 return status ? status : count;
132}
133
134static ssize_t
135at25_bin_read(struct file *filp, struct kobject *kobj,
136 struct bin_attribute *bin_attr,
137 char *buf, loff_t off, size_t count)
138{
139 struct device *dev;
140 struct at25_data *at25;
141
142 dev = container_of(kobj, struct device, kobj);
143 at25 = dev_get_drvdata(dev);
144
145 return at25_ee_read(at25, buf, off, count);
146}
147
148
149static ssize_t
150at25_ee_write(struct at25_data *at25, const char *buf, loff_t off,
151 size_t count)
152{
153 ssize_t status = 0;
154 unsigned written = 0;
155 unsigned buf_size;
156 u8 *bounce;
157
158 if (unlikely(off >= at25->bin.size))
159 return -EFBIG;
160 if ((off + count) > at25->bin.size)
161 count = at25->bin.size - off;
162 if (unlikely(!count))
163 return count;
164
165 /* Temp buffer starts with command and address */
166 buf_size = at25->chip.page_size;
167 if (buf_size > io_limit)
168 buf_size = io_limit;
169 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
170 if (!bounce)
171 return -ENOMEM;
172
173 /* For write, rollover is within the page ... so we write at
174 * most one page, then manually roll over to the next page.
175 */
176 mutex_lock(&at25->lock);
177 do {
178 unsigned long timeout, retries;
179 unsigned segment;
180 unsigned offset = (unsigned) off;
181 u8 *cp = bounce;
182 int sr;
183 u8 instr;
184
185 *cp = AT25_WREN;
186 status = spi_write(at25->spi, cp, 1);
187 if (status < 0) {
188 dev_dbg(&at25->spi->dev, "WREN --> %d\n",
189 (int) status);
190 break;
191 }
192
193 instr = AT25_WRITE;
194 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
195 if (offset >= (1U << (at25->addrlen * 8)))
196 instr |= AT25_INSTR_BIT3;
197 *cp++ = instr;
198
199 /* 8/16/24-bit address is written MSB first */
200 switch (at25->addrlen) {
201 default: /* case 3 */
202 *cp++ = offset >> 16;
203 case 2:
204 *cp++ = offset >> 8;
205 case 1:
206 case 0: /* can't happen: for better codegen */
207 *cp++ = offset >> 0;
208 }
209
210 /* Write as much of a page as we can */
211 segment = buf_size - (offset % buf_size);
212 if (segment > count)
213 segment = count;
214 memcpy(cp, buf, segment);
215 status = spi_write(at25->spi, bounce,
216 segment + at25->addrlen + 1);
217 dev_dbg(&at25->spi->dev,
218 "write %u bytes at %u --> %d\n",
219 segment, offset, (int) status);
220 if (status < 0)
221 break;
222
223 /* REVISIT this should detect (or prevent) failed writes
224 * to readonly sections of the EEPROM...
225 */
226
227 /* Wait for non-busy status */
228 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
229 retries = 0;
230 do {
231
232 sr = spi_w8r8(at25->spi, AT25_RDSR);
233 if (sr < 0 || (sr & AT25_SR_nRDY)) {
234 dev_dbg(&at25->spi->dev,
235 "rdsr --> %d (%02x)\n", sr, sr);
236 /* at HZ=100, this is sloooow */
237 msleep(1);
238 continue;
239 }
240 if (!(sr & AT25_SR_nRDY))
241 break;
242 } while (retries++ < 3 || time_before_eq(jiffies, timeout));
243
244 if ((sr < 0) || (sr & AT25_SR_nRDY)) {
245 dev_err(&at25->spi->dev,
246 "write %d bytes offset %d, "
247 "timeout after %u msecs\n",
248 segment, offset,
249 jiffies_to_msecs(jiffies -
250 (timeout - EE_TIMEOUT)));
251 status = -ETIMEDOUT;
252 break;
253 }
254
255 off += segment;
256 buf += segment;
257 count -= segment;
258 written += segment;
259
260 } while (count > 0);
261
262 mutex_unlock(&at25->lock);
263
264 kfree(bounce);
265 return written ? written : status;
266}
267
268static ssize_t
269at25_bin_write(struct file *filp, struct kobject *kobj,
270 struct bin_attribute *bin_attr,
271 char *buf, loff_t off, size_t count)
272{
273 struct device *dev;
274 struct at25_data *at25;
275
276 dev = container_of(kobj, struct device, kobj);
277 at25 = dev_get_drvdata(dev);
278
279 return at25_ee_write(at25, buf, off, count);
280}
281
282/*-------------------------------------------------------------------------*/
283
284/* Let in-kernel code access the eeprom data. */
285
286static ssize_t at25_mem_read(struct memory_accessor *mem, char *buf,
287 off_t offset, size_t count)
288{
289 struct at25_data *at25 = container_of(mem, struct at25_data, mem);
290
291 return at25_ee_read(at25, buf, offset, count);
292}
293
294static ssize_t at25_mem_write(struct memory_accessor *mem, const char *buf,
295 off_t offset, size_t count)
296{
297 struct at25_data *at25 = container_of(mem, struct at25_data, mem);
298
299 return at25_ee_write(at25, buf, offset, count);
300}
301
302/*-------------------------------------------------------------------------*/
303
304static int at25_np_to_chip(struct device *dev,
305 struct device_node *np,
306 struct spi_eeprom *chip)
307{
308 u32 val;
309
310 memset(chip, 0, sizeof(*chip));
311 strncpy(chip->name, np->name, sizeof(chip->name));
312
313 if (of_property_read_u32(np, "size", &val) == 0 ||
314 of_property_read_u32(np, "at25,byte-len", &val) == 0) {
315 chip->byte_len = val;
316 } else {
317 dev_err(dev, "Error: missing \"size\" property\n");
318 return -ENODEV;
319 }
320
321 if (of_property_read_u32(np, "pagesize", &val) == 0 ||
322 of_property_read_u32(np, "at25,page-size", &val) == 0) {
323 chip->page_size = (u16)val;
324 } else {
325 dev_err(dev, "Error: missing \"pagesize\" property\n");
326 return -ENODEV;
327 }
328
329 if (of_property_read_u32(np, "at25,addr-mode", &val) == 0) {
330 chip->flags = (u16)val;
331 } else {
332 if (of_property_read_u32(np, "address-width", &val)) {
333 dev_err(dev,
334 "Error: missing \"address-width\" property\n");
335 return -ENODEV;
336 }
337 switch (val) {
338 case 8:
339 chip->flags |= EE_ADDR1;
340 break;
341 case 16:
342 chip->flags |= EE_ADDR2;
343 break;
344 case 24:
345 chip->flags |= EE_ADDR3;
346 break;
347 default:
348 dev_err(dev,
349 "Error: bad \"address-width\" property: %u\n",
350 val);
351 return -ENODEV;
352 }
353 if (of_find_property(np, "read-only", NULL))
354 chip->flags |= EE_READONLY;
355 }
356 return 0;
357}
358
359static int at25_probe(struct spi_device *spi)
360{
361 struct at25_data *at25 = NULL;
362 struct spi_eeprom chip;
363 struct device_node *np = spi->dev.of_node;
364 int err;
365 int sr;
366 int addrlen;
367
368 /* Chip description */
369 if (!spi->dev.platform_data) {
370 if (np) {
371 err = at25_np_to_chip(&spi->dev, np, &chip);
372 if (err)
373 return err;
374 } else {
375 dev_err(&spi->dev, "Error: no chip description\n");
376 return -ENODEV;
377 }
378 } else
379 chip = *(struct spi_eeprom *)spi->dev.platform_data;
380
381 /* For now we only support 8/16/24 bit addressing */
382 if (chip.flags & EE_ADDR1)
383 addrlen = 1;
384 else if (chip.flags & EE_ADDR2)
385 addrlen = 2;
386 else if (chip.flags & EE_ADDR3)
387 addrlen = 3;
388 else {
389 dev_dbg(&spi->dev, "unsupported address type\n");
390 return -EINVAL;
391 }
392
393 /* Ping the chip ... the status register is pretty portable,
394 * unlike probing manufacturer IDs. We do expect that system
395 * firmware didn't write it in the past few milliseconds!
396 */
397 sr = spi_w8r8(spi, AT25_RDSR);
398 if (sr < 0 || sr & AT25_SR_nRDY) {
399 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
400 return -ENXIO;
401 }
402
403 at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
404 if (!at25)
405 return -ENOMEM;
406
407 mutex_init(&at25->lock);
408 at25->chip = chip;
409 at25->spi = spi_dev_get(spi);
410 spi_set_drvdata(spi, at25);
411 at25->addrlen = addrlen;
412
413 /* Export the EEPROM bytes through sysfs, since that's convenient.
414 * And maybe to other kernel code; it might hold a board's Ethernet
415 * address, or board-specific calibration data generated on the
416 * manufacturing floor.
417 *
418 * Default to root-only access to the data; EEPROMs often hold data
419 * that's sensitive for read and/or write, like ethernet addresses,
420 * security codes, board-specific manufacturing calibrations, etc.
421 */
422 sysfs_bin_attr_init(&at25->bin);
423 at25->bin.attr.name = "eeprom";
424 at25->bin.attr.mode = S_IRUSR;
425 at25->bin.read = at25_bin_read;
426 at25->mem.read = at25_mem_read;
427
428 at25->bin.size = at25->chip.byte_len;
429 if (!(chip.flags & EE_READONLY)) {
430 at25->bin.write = at25_bin_write;
431 at25->bin.attr.mode |= S_IWUSR;
432 at25->mem.write = at25_mem_write;
433 }
434
435 err = sysfs_create_bin_file(&spi->dev.kobj, &at25->bin);
436 if (err)
437 return err;
438
439 if (chip.setup)
440 chip.setup(&at25->mem, chip.context);
441
442 dev_info(&spi->dev, "%Zd %s %s eeprom%s, pagesize %u\n",
443 (at25->bin.size < 1024)
444 ? at25->bin.size
445 : (at25->bin.size / 1024),
446 (at25->bin.size < 1024) ? "Byte" : "KByte",
447 at25->chip.name,
448 (chip.flags & EE_READONLY) ? " (readonly)" : "",
449 at25->chip.page_size);
450 return 0;
451}
452
453static int at25_remove(struct spi_device *spi)
454{
455 struct at25_data *at25;
456
457 at25 = spi_get_drvdata(spi);
458 sysfs_remove_bin_file(&spi->dev.kobj, &at25->bin);
459 return 0;
460}
461
462/*-------------------------------------------------------------------------*/
463
464static const struct of_device_id at25_of_match[] = {
465 { .compatible = "atmel,at25", },
466 { }
467};
468MODULE_DEVICE_TABLE(of, at25_of_match);
469
470static struct spi_driver at25_driver = {
471 .driver = {
472 .name = "at25",
473 .owner = THIS_MODULE,
474 .of_match_table = at25_of_match,
475 },
476 .probe = at25_probe,
477 .remove = at25_remove,
478};
479
480module_spi_driver(at25_driver);
481
482MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
483MODULE_AUTHOR("David Brownell");
484MODULE_LICENSE("GPL");
485MODULE_ALIAS("spi:at25");