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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <linux/slab.h>
34#include <drm/drmP.h>
35#include <drm/radeon_drm.h>
36#include <drm/drm_cache.h>
37#include "radeon.h"
38#include "radeon_trace.h"
39
40
41int radeon_ttm_init(struct radeon_device *rdev);
42void radeon_ttm_fini(struct radeon_device *rdev);
43static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
44
45/*
46 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
47 * function are calling it.
48 */
49
50static void radeon_update_memory_usage(struct radeon_bo *bo,
51 unsigned mem_type, int sign)
52{
53 struct radeon_device *rdev = bo->rdev;
54 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
55
56 switch (mem_type) {
57 case TTM_PL_TT:
58 if (sign > 0)
59 atomic64_add(size, &rdev->gtt_usage);
60 else
61 atomic64_sub(size, &rdev->gtt_usage);
62 break;
63 case TTM_PL_VRAM:
64 if (sign > 0)
65 atomic64_add(size, &rdev->vram_usage);
66 else
67 atomic64_sub(size, &rdev->vram_usage);
68 break;
69 }
70}
71
72static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
73{
74 struct radeon_bo *bo;
75
76 bo = container_of(tbo, struct radeon_bo, tbo);
77
78 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
79
80 mutex_lock(&bo->rdev->gem.mutex);
81 list_del_init(&bo->list);
82 mutex_unlock(&bo->rdev->gem.mutex);
83 radeon_bo_clear_surface_reg(bo);
84 WARN_ON(!list_empty(&bo->va));
85 drm_gem_object_release(&bo->gem_base);
86 kfree(bo);
87}
88
89bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
90{
91 if (bo->destroy == &radeon_ttm_bo_destroy)
92 return true;
93 return false;
94}
95
96void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
97{
98 u32 c = 0, i;
99
100 rbo->placement.placement = rbo->placements;
101 rbo->placement.busy_placement = rbo->placements;
102 if (domain & RADEON_GEM_DOMAIN_VRAM) {
103 /* Try placing BOs which don't need CPU access outside of the
104 * CPU accessible part of VRAM
105 */
106 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
107 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
108 rbo->placements[c].fpfn =
109 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
110 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
111 TTM_PL_FLAG_UNCACHED |
112 TTM_PL_FLAG_VRAM;
113 }
114
115 rbo->placements[c].fpfn = 0;
116 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
117 TTM_PL_FLAG_UNCACHED |
118 TTM_PL_FLAG_VRAM;
119 }
120
121 if (domain & RADEON_GEM_DOMAIN_GTT) {
122 if (rbo->flags & RADEON_GEM_GTT_UC) {
123 rbo->placements[c].fpfn = 0;
124 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
125 TTM_PL_FLAG_TT;
126
127 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
128 (rbo->rdev->flags & RADEON_IS_AGP)) {
129 rbo->placements[c].fpfn = 0;
130 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
131 TTM_PL_FLAG_UNCACHED |
132 TTM_PL_FLAG_TT;
133 } else {
134 rbo->placements[c].fpfn = 0;
135 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
136 TTM_PL_FLAG_TT;
137 }
138 }
139
140 if (domain & RADEON_GEM_DOMAIN_CPU) {
141 if (rbo->flags & RADEON_GEM_GTT_UC) {
142 rbo->placements[c].fpfn = 0;
143 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
144 TTM_PL_FLAG_SYSTEM;
145
146 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
147 rbo->rdev->flags & RADEON_IS_AGP) {
148 rbo->placements[c].fpfn = 0;
149 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
150 TTM_PL_FLAG_UNCACHED |
151 TTM_PL_FLAG_SYSTEM;
152 } else {
153 rbo->placements[c].fpfn = 0;
154 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
155 TTM_PL_FLAG_SYSTEM;
156 }
157 }
158 if (!c) {
159 rbo->placements[c].fpfn = 0;
160 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
161 TTM_PL_FLAG_SYSTEM;
162 }
163
164 rbo->placement.num_placement = c;
165 rbo->placement.num_busy_placement = c;
166
167 for (i = 0; i < c; ++i) {
168 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
169 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
170 !rbo->placements[i].fpfn)
171 rbo->placements[i].lpfn =
172 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
173 else
174 rbo->placements[i].lpfn = 0;
175 }
176}
177
178int radeon_bo_create(struct radeon_device *rdev,
179 unsigned long size, int byte_align, bool kernel,
180 u32 domain, u32 flags, struct sg_table *sg,
181 struct reservation_object *resv,
182 struct radeon_bo **bo_ptr)
183{
184 struct radeon_bo *bo;
185 enum ttm_bo_type type;
186 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
187 size_t acc_size;
188 int r;
189
190 size = ALIGN(size, PAGE_SIZE);
191
192 if (kernel) {
193 type = ttm_bo_type_kernel;
194 } else if (sg) {
195 type = ttm_bo_type_sg;
196 } else {
197 type = ttm_bo_type_device;
198 }
199 *bo_ptr = NULL;
200
201 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
202 sizeof(struct radeon_bo));
203
204 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
205 if (bo == NULL)
206 return -ENOMEM;
207 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
208 if (unlikely(r)) {
209 kfree(bo);
210 return r;
211 }
212 bo->rdev = rdev;
213 bo->surface_reg = -1;
214 INIT_LIST_HEAD(&bo->list);
215 INIT_LIST_HEAD(&bo->va);
216 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
217 RADEON_GEM_DOMAIN_GTT |
218 RADEON_GEM_DOMAIN_CPU);
219
220 bo->flags = flags;
221 /* PCI GART is always snooped */
222 if (!(rdev->flags & RADEON_IS_PCIE))
223 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
224
225 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
226 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
227 */
228 if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
229 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
230
231#ifdef CONFIG_X86_32
232 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
233 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
234 */
235 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
236#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
237 /* Don't try to enable write-combining when it can't work, or things
238 * may be slow
239 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
240 */
241
242#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
243 thanks to write-combining
244
245 if (bo->flags & RADEON_GEM_GTT_WC)
246 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
247 "better performance thanks to write-combining\n");
248 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
249#else
250 /* For architectures that don't support WC memory,
251 * mask out the WC flag from the BO
252 */
253 if (!drm_arch_can_wc_memory())
254 bo->flags &= ~RADEON_GEM_GTT_WC;
255#endif
256
257 radeon_ttm_placement_from_domain(bo, domain);
258 /* Kernel allocation are uninterruptible */
259 down_read(&rdev->pm.mclk_lock);
260 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
261 &bo->placement, page_align, !kernel, NULL,
262 acc_size, sg, resv, &radeon_ttm_bo_destroy);
263 up_read(&rdev->pm.mclk_lock);
264 if (unlikely(r != 0)) {
265 return r;
266 }
267 *bo_ptr = bo;
268
269 trace_radeon_bo_create(bo);
270
271 return 0;
272}
273
274int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
275{
276 bool is_iomem;
277 int r;
278
279 if (bo->kptr) {
280 if (ptr) {
281 *ptr = bo->kptr;
282 }
283 return 0;
284 }
285 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
286 if (r) {
287 return r;
288 }
289 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
290 if (ptr) {
291 *ptr = bo->kptr;
292 }
293 radeon_bo_check_tiling(bo, 0, 0);
294 return 0;
295}
296
297void radeon_bo_kunmap(struct radeon_bo *bo)
298{
299 if (bo->kptr == NULL)
300 return;
301 bo->kptr = NULL;
302 radeon_bo_check_tiling(bo, 0, 0);
303 ttm_bo_kunmap(&bo->kmap);
304}
305
306struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
307{
308 if (bo == NULL)
309 return NULL;
310
311 ttm_bo_reference(&bo->tbo);
312 return bo;
313}
314
315void radeon_bo_unref(struct radeon_bo **bo)
316{
317 struct ttm_buffer_object *tbo;
318 struct radeon_device *rdev;
319
320 if ((*bo) == NULL)
321 return;
322 rdev = (*bo)->rdev;
323 tbo = &((*bo)->tbo);
324 ttm_bo_unref(&tbo);
325 if (tbo == NULL)
326 *bo = NULL;
327}
328
329int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
330 u64 *gpu_addr)
331{
332 int r, i;
333
334 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
335 return -EPERM;
336
337 if (bo->pin_count) {
338 bo->pin_count++;
339 if (gpu_addr)
340 *gpu_addr = radeon_bo_gpu_offset(bo);
341
342 if (max_offset != 0) {
343 u64 domain_start;
344
345 if (domain == RADEON_GEM_DOMAIN_VRAM)
346 domain_start = bo->rdev->mc.vram_start;
347 else
348 domain_start = bo->rdev->mc.gtt_start;
349 WARN_ON_ONCE(max_offset <
350 (radeon_bo_gpu_offset(bo) - domain_start));
351 }
352
353 return 0;
354 }
355 radeon_ttm_placement_from_domain(bo, domain);
356 for (i = 0; i < bo->placement.num_placement; i++) {
357 /* force to pin into visible video ram */
358 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
359 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
360 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
361 bo->placements[i].lpfn =
362 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
363 else
364 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
365
366 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
367 }
368
369 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
370 if (likely(r == 0)) {
371 bo->pin_count = 1;
372 if (gpu_addr != NULL)
373 *gpu_addr = radeon_bo_gpu_offset(bo);
374 if (domain == RADEON_GEM_DOMAIN_VRAM)
375 bo->rdev->vram_pin_size += radeon_bo_size(bo);
376 else
377 bo->rdev->gart_pin_size += radeon_bo_size(bo);
378 } else {
379 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
380 }
381 return r;
382}
383
384int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
385{
386 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
387}
388
389int radeon_bo_unpin(struct radeon_bo *bo)
390{
391 int r, i;
392
393 if (!bo->pin_count) {
394 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
395 return 0;
396 }
397 bo->pin_count--;
398 if (bo->pin_count)
399 return 0;
400 for (i = 0; i < bo->placement.num_placement; i++) {
401 bo->placements[i].lpfn = 0;
402 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
403 }
404 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
405 if (likely(r == 0)) {
406 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
407 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
408 else
409 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
410 } else {
411 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
412 }
413 return r;
414}
415
416int radeon_bo_evict_vram(struct radeon_device *rdev)
417{
418 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
419 if (0 && (rdev->flags & RADEON_IS_IGP)) {
420 if (rdev->mc.igp_sideport_enabled == false)
421 /* Useless to evict on IGP chips */
422 return 0;
423 }
424 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
425}
426
427void radeon_bo_force_delete(struct radeon_device *rdev)
428{
429 struct radeon_bo *bo, *n;
430
431 if (list_empty(&rdev->gem.objects)) {
432 return;
433 }
434 dev_err(rdev->dev, "Userspace still has active objects !\n");
435 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
436 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
437 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
438 *((unsigned long *)&bo->gem_base.refcount));
439 mutex_lock(&bo->rdev->gem.mutex);
440 list_del_init(&bo->list);
441 mutex_unlock(&bo->rdev->gem.mutex);
442 /* this should unref the ttm bo */
443 drm_gem_object_unreference_unlocked(&bo->gem_base);
444 }
445}
446
447int radeon_bo_init(struct radeon_device *rdev)
448{
449 /* Add an MTRR for the VRAM */
450 if (!rdev->fastfb_working) {
451 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
452 rdev->mc.aper_size);
453 }
454 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
455 rdev->mc.mc_vram_size >> 20,
456 (unsigned long long)rdev->mc.aper_size >> 20);
457 DRM_INFO("RAM width %dbits %cDR\n",
458 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
459 return radeon_ttm_init(rdev);
460}
461
462void radeon_bo_fini(struct radeon_device *rdev)
463{
464 radeon_ttm_fini(rdev);
465 arch_phys_wc_del(rdev->mc.vram_mtrr);
466}
467
468/* Returns how many bytes TTM can move per IB.
469 */
470static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
471{
472 u64 real_vram_size = rdev->mc.real_vram_size;
473 u64 vram_usage = atomic64_read(&rdev->vram_usage);
474
475 /* This function is based on the current VRAM usage.
476 *
477 * - If all of VRAM is free, allow relocating the number of bytes that
478 * is equal to 1/4 of the size of VRAM for this IB.
479
480 * - If more than one half of VRAM is occupied, only allow relocating
481 * 1 MB of data for this IB.
482 *
483 * - From 0 to one half of used VRAM, the threshold decreases
484 * linearly.
485 * __________________
486 * 1/4 of -|\ |
487 * VRAM | \ |
488 * | \ |
489 * | \ |
490 * | \ |
491 * | \ |
492 * | \ |
493 * | \________|1 MB
494 * |----------------|
495 * VRAM 0 % 100 %
496 * used used
497 *
498 * Note: It's a threshold, not a limit. The threshold must be crossed
499 * for buffer relocations to stop, so any buffer of an arbitrary size
500 * can be moved as long as the threshold isn't crossed before
501 * the relocation takes place. We don't want to disable buffer
502 * relocations completely.
503 *
504 * The idea is that buffers should be placed in VRAM at creation time
505 * and TTM should only do a minimum number of relocations during
506 * command submission. In practice, you need to submit at least
507 * a dozen IBs to move all buffers to VRAM if they are in GTT.
508 *
509 * Also, things can get pretty crazy under memory pressure and actual
510 * VRAM usage can change a lot, so playing safe even at 50% does
511 * consistently increase performance.
512 */
513
514 u64 half_vram = real_vram_size >> 1;
515 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
516 u64 bytes_moved_threshold = half_free_vram >> 1;
517 return max(bytes_moved_threshold, 1024*1024ull);
518}
519
520int radeon_bo_list_validate(struct radeon_device *rdev,
521 struct ww_acquire_ctx *ticket,
522 struct list_head *head, int ring)
523{
524 struct radeon_bo_list *lobj;
525 struct list_head duplicates;
526 int r;
527 u64 bytes_moved = 0, initial_bytes_moved;
528 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
529
530 INIT_LIST_HEAD(&duplicates);
531 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
532 if (unlikely(r != 0)) {
533 return r;
534 }
535
536 list_for_each_entry(lobj, head, tv.head) {
537 struct radeon_bo *bo = lobj->robj;
538 if (!bo->pin_count) {
539 u32 domain = lobj->prefered_domains;
540 u32 allowed = lobj->allowed_domains;
541 u32 current_domain =
542 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
543
544 /* Check if this buffer will be moved and don't move it
545 * if we have moved too many buffers for this IB already.
546 *
547 * Note that this allows moving at least one buffer of
548 * any size, because it doesn't take the current "bo"
549 * into account. We don't want to disallow buffer moves
550 * completely.
551 */
552 if ((allowed & current_domain) != 0 &&
553 (domain & current_domain) == 0 && /* will be moved */
554 bytes_moved > bytes_moved_threshold) {
555 /* don't move it */
556 domain = current_domain;
557 }
558
559 retry:
560 radeon_ttm_placement_from_domain(bo, domain);
561 if (ring == R600_RING_TYPE_UVD_INDEX)
562 radeon_uvd_force_into_uvd_segment(bo, allowed);
563
564 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
565 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
566 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
567 initial_bytes_moved;
568
569 if (unlikely(r)) {
570 if (r != -ERESTARTSYS &&
571 domain != lobj->allowed_domains) {
572 domain = lobj->allowed_domains;
573 goto retry;
574 }
575 ttm_eu_backoff_reservation(ticket, head);
576 return r;
577 }
578 }
579 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
580 lobj->tiling_flags = bo->tiling_flags;
581 }
582
583 list_for_each_entry(lobj, &duplicates, tv.head) {
584 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
585 lobj->tiling_flags = lobj->robj->tiling_flags;
586 }
587
588 return 0;
589}
590
591int radeon_bo_get_surface_reg(struct radeon_bo *bo)
592{
593 struct radeon_device *rdev = bo->rdev;
594 struct radeon_surface_reg *reg;
595 struct radeon_bo *old_object;
596 int steal;
597 int i;
598
599 lockdep_assert_held(&bo->tbo.resv->lock.base);
600
601 if (!bo->tiling_flags)
602 return 0;
603
604 if (bo->surface_reg >= 0) {
605 reg = &rdev->surface_regs[bo->surface_reg];
606 i = bo->surface_reg;
607 goto out;
608 }
609
610 steal = -1;
611 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
612
613 reg = &rdev->surface_regs[i];
614 if (!reg->bo)
615 break;
616
617 old_object = reg->bo;
618 if (old_object->pin_count == 0)
619 steal = i;
620 }
621
622 /* if we are all out */
623 if (i == RADEON_GEM_MAX_SURFACES) {
624 if (steal == -1)
625 return -ENOMEM;
626 /* find someone with a surface reg and nuke their BO */
627 reg = &rdev->surface_regs[steal];
628 old_object = reg->bo;
629 /* blow away the mapping */
630 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
631 ttm_bo_unmap_virtual(&old_object->tbo);
632 old_object->surface_reg = -1;
633 i = steal;
634 }
635
636 bo->surface_reg = i;
637 reg->bo = bo;
638
639out:
640 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
641 bo->tbo.mem.start << PAGE_SHIFT,
642 bo->tbo.num_pages << PAGE_SHIFT);
643 return 0;
644}
645
646static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
647{
648 struct radeon_device *rdev = bo->rdev;
649 struct radeon_surface_reg *reg;
650
651 if (bo->surface_reg == -1)
652 return;
653
654 reg = &rdev->surface_regs[bo->surface_reg];
655 radeon_clear_surface_reg(rdev, bo->surface_reg);
656
657 reg->bo = NULL;
658 bo->surface_reg = -1;
659}
660
661int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
662 uint32_t tiling_flags, uint32_t pitch)
663{
664 struct radeon_device *rdev = bo->rdev;
665 int r;
666
667 if (rdev->family >= CHIP_CEDAR) {
668 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
669
670 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
671 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
672 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
673 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
674 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
675 switch (bankw) {
676 case 0:
677 case 1:
678 case 2:
679 case 4:
680 case 8:
681 break;
682 default:
683 return -EINVAL;
684 }
685 switch (bankh) {
686 case 0:
687 case 1:
688 case 2:
689 case 4:
690 case 8:
691 break;
692 default:
693 return -EINVAL;
694 }
695 switch (mtaspect) {
696 case 0:
697 case 1:
698 case 2:
699 case 4:
700 case 8:
701 break;
702 default:
703 return -EINVAL;
704 }
705 if (tilesplit > 6) {
706 return -EINVAL;
707 }
708 if (stilesplit > 6) {
709 return -EINVAL;
710 }
711 }
712 r = radeon_bo_reserve(bo, false);
713 if (unlikely(r != 0))
714 return r;
715 bo->tiling_flags = tiling_flags;
716 bo->pitch = pitch;
717 radeon_bo_unreserve(bo);
718 return 0;
719}
720
721void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
722 uint32_t *tiling_flags,
723 uint32_t *pitch)
724{
725 lockdep_assert_held(&bo->tbo.resv->lock.base);
726
727 if (tiling_flags)
728 *tiling_flags = bo->tiling_flags;
729 if (pitch)
730 *pitch = bo->pitch;
731}
732
733int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
734 bool force_drop)
735{
736 if (!force_drop)
737 lockdep_assert_held(&bo->tbo.resv->lock.base);
738
739 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
740 return 0;
741
742 if (force_drop) {
743 radeon_bo_clear_surface_reg(bo);
744 return 0;
745 }
746
747 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
748 if (!has_moved)
749 return 0;
750
751 if (bo->surface_reg >= 0)
752 radeon_bo_clear_surface_reg(bo);
753 return 0;
754 }
755
756 if ((bo->surface_reg >= 0) && !has_moved)
757 return 0;
758
759 return radeon_bo_get_surface_reg(bo);
760}
761
762void radeon_bo_move_notify(struct ttm_buffer_object *bo,
763 struct ttm_mem_reg *new_mem)
764{
765 struct radeon_bo *rbo;
766
767 if (!radeon_ttm_bo_is_radeon_bo(bo))
768 return;
769
770 rbo = container_of(bo, struct radeon_bo, tbo);
771 radeon_bo_check_tiling(rbo, 0, 1);
772 radeon_vm_bo_invalidate(rbo->rdev, rbo);
773
774 /* update statistics */
775 if (!new_mem)
776 return;
777
778 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
779 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
780}
781
782int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
783{
784 struct radeon_device *rdev;
785 struct radeon_bo *rbo;
786 unsigned long offset, size, lpfn;
787 int i, r;
788
789 if (!radeon_ttm_bo_is_radeon_bo(bo))
790 return 0;
791 rbo = container_of(bo, struct radeon_bo, tbo);
792 radeon_bo_check_tiling(rbo, 0, 0);
793 rdev = rbo->rdev;
794 if (bo->mem.mem_type != TTM_PL_VRAM)
795 return 0;
796
797 size = bo->mem.num_pages << PAGE_SHIFT;
798 offset = bo->mem.start << PAGE_SHIFT;
799 if ((offset + size) <= rdev->mc.visible_vram_size)
800 return 0;
801
802 /* Can't move a pinned BO to visible VRAM */
803 if (rbo->pin_count > 0)
804 return -EINVAL;
805
806 /* hurrah the memory is not visible ! */
807 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
808 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
809 for (i = 0; i < rbo->placement.num_placement; i++) {
810 /* Force into visible VRAM */
811 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
812 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
813 rbo->placements[i].lpfn = lpfn;
814 }
815 r = ttm_bo_validate(bo, &rbo->placement, false, false);
816 if (unlikely(r == -ENOMEM)) {
817 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
818 return ttm_bo_validate(bo, &rbo->placement, false, false);
819 } else if (unlikely(r != 0)) {
820 return r;
821 }
822
823 offset = bo->mem.start << PAGE_SHIFT;
824 /* this should never happen */
825 if ((offset + size) > rdev->mc.visible_vram_size)
826 return -EINVAL;
827
828 return 0;
829}
830
831int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
832{
833 int r;
834
835 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
836 if (unlikely(r != 0))
837 return r;
838 if (mem_type)
839 *mem_type = bo->tbo.mem.mem_type;
840
841 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
842 ttm_bo_unreserve(&bo->tbo);
843 return r;
844}
845
846/**
847 * radeon_bo_fence - add fence to buffer object
848 *
849 * @bo: buffer object in question
850 * @fence: fence to add
851 * @shared: true if fence should be added shared
852 *
853 */
854void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
855 bool shared)
856{
857 struct reservation_object *resv = bo->tbo.resv;
858
859 if (shared)
860 reservation_object_add_shared_fence(resv, &fence->base);
861 else
862 reservation_object_add_excl_fence(resv, &fence->base);
863}
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <linux/slab.h>
34#include <drm/drmP.h>
35#include <drm/radeon_drm.h>
36#include "radeon.h"
37#include "radeon_trace.h"
38
39
40int radeon_ttm_init(struct radeon_device *rdev);
41void radeon_ttm_fini(struct radeon_device *rdev);
42static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
43
44/*
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
47 */
48
49static void radeon_bo_clear_va(struct radeon_bo *bo)
50{
51 struct radeon_bo_va *bo_va, *tmp;
52
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */
55 radeon_vm_bo_rmv(bo->rdev, bo_va);
56 }
57}
58
59static void radeon_update_memory_usage(struct radeon_bo *bo,
60 unsigned mem_type, int sign)
61{
62 struct radeon_device *rdev = bo->rdev;
63 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
64
65 switch (mem_type) {
66 case TTM_PL_TT:
67 if (sign > 0)
68 atomic64_add(size, &rdev->gtt_usage);
69 else
70 atomic64_sub(size, &rdev->gtt_usage);
71 break;
72 case TTM_PL_VRAM:
73 if (sign > 0)
74 atomic64_add(size, &rdev->vram_usage);
75 else
76 atomic64_sub(size, &rdev->vram_usage);
77 break;
78 }
79}
80
81static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
82{
83 struct radeon_bo *bo;
84
85 bo = container_of(tbo, struct radeon_bo, tbo);
86
87 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
88
89 mutex_lock(&bo->rdev->gem.mutex);
90 list_del_init(&bo->list);
91 mutex_unlock(&bo->rdev->gem.mutex);
92 radeon_bo_clear_surface_reg(bo);
93 radeon_bo_clear_va(bo);
94 drm_gem_object_release(&bo->gem_base);
95 kfree(bo);
96}
97
98bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
99{
100 if (bo->destroy == &radeon_ttm_bo_destroy)
101 return true;
102 return false;
103}
104
105void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
106{
107 u32 c = 0, i;
108
109 rbo->placement.fpfn = 0;
110 rbo->placement.lpfn = 0;
111 rbo->placement.placement = rbo->placements;
112 rbo->placement.busy_placement = rbo->placements;
113 if (domain & RADEON_GEM_DOMAIN_VRAM)
114 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
115 TTM_PL_FLAG_VRAM;
116 if (domain & RADEON_GEM_DOMAIN_GTT) {
117 if (rbo->rdev->flags & RADEON_IS_AGP) {
118 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
119 } else {
120 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
121 }
122 }
123 if (domain & RADEON_GEM_DOMAIN_CPU) {
124 if (rbo->rdev->flags & RADEON_IS_AGP) {
125 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
126 } else {
127 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
128 }
129 }
130 if (!c)
131 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
132 rbo->placement.num_placement = c;
133 rbo->placement.num_busy_placement = c;
134
135 /*
136 * Use two-ended allocation depending on the buffer size to
137 * improve fragmentation quality.
138 * 512kb was measured as the most optimal number.
139 */
140 if (rbo->tbo.mem.size > 512 * 1024) {
141 for (i = 0; i < c; i++) {
142 rbo->placements[i] |= TTM_PL_FLAG_TOPDOWN;
143 }
144 }
145}
146
147int radeon_bo_create(struct radeon_device *rdev,
148 unsigned long size, int byte_align, bool kernel, u32 domain,
149 struct sg_table *sg, struct radeon_bo **bo_ptr)
150{
151 struct radeon_bo *bo;
152 enum ttm_bo_type type;
153 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
154 size_t acc_size;
155 int r;
156
157 size = ALIGN(size, PAGE_SIZE);
158
159 if (kernel) {
160 type = ttm_bo_type_kernel;
161 } else if (sg) {
162 type = ttm_bo_type_sg;
163 } else {
164 type = ttm_bo_type_device;
165 }
166 *bo_ptr = NULL;
167
168 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
169 sizeof(struct radeon_bo));
170
171 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
172 if (bo == NULL)
173 return -ENOMEM;
174 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
175 if (unlikely(r)) {
176 kfree(bo);
177 return r;
178 }
179 bo->rdev = rdev;
180 bo->surface_reg = -1;
181 INIT_LIST_HEAD(&bo->list);
182 INIT_LIST_HEAD(&bo->va);
183 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
184 RADEON_GEM_DOMAIN_GTT |
185 RADEON_GEM_DOMAIN_CPU);
186 radeon_ttm_placement_from_domain(bo, domain);
187 /* Kernel allocation are uninterruptible */
188 down_read(&rdev->pm.mclk_lock);
189 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
190 &bo->placement, page_align, !kernel, NULL,
191 acc_size, sg, &radeon_ttm_bo_destroy);
192 up_read(&rdev->pm.mclk_lock);
193 if (unlikely(r != 0)) {
194 return r;
195 }
196 *bo_ptr = bo;
197
198 trace_radeon_bo_create(bo);
199
200 return 0;
201}
202
203int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
204{
205 bool is_iomem;
206 int r;
207
208 if (bo->kptr) {
209 if (ptr) {
210 *ptr = bo->kptr;
211 }
212 return 0;
213 }
214 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
215 if (r) {
216 return r;
217 }
218 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
219 if (ptr) {
220 *ptr = bo->kptr;
221 }
222 radeon_bo_check_tiling(bo, 0, 0);
223 return 0;
224}
225
226void radeon_bo_kunmap(struct radeon_bo *bo)
227{
228 if (bo->kptr == NULL)
229 return;
230 bo->kptr = NULL;
231 radeon_bo_check_tiling(bo, 0, 0);
232 ttm_bo_kunmap(&bo->kmap);
233}
234
235void radeon_bo_unref(struct radeon_bo **bo)
236{
237 struct ttm_buffer_object *tbo;
238 struct radeon_device *rdev;
239
240 if ((*bo) == NULL)
241 return;
242 rdev = (*bo)->rdev;
243 tbo = &((*bo)->tbo);
244 down_read(&rdev->pm.mclk_lock);
245 ttm_bo_unref(&tbo);
246 up_read(&rdev->pm.mclk_lock);
247 if (tbo == NULL)
248 *bo = NULL;
249}
250
251int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
252 u64 *gpu_addr)
253{
254 int r, i;
255
256 if (bo->pin_count) {
257 bo->pin_count++;
258 if (gpu_addr)
259 *gpu_addr = radeon_bo_gpu_offset(bo);
260
261 if (max_offset != 0) {
262 u64 domain_start;
263
264 if (domain == RADEON_GEM_DOMAIN_VRAM)
265 domain_start = bo->rdev->mc.vram_start;
266 else
267 domain_start = bo->rdev->mc.gtt_start;
268 WARN_ON_ONCE(max_offset <
269 (radeon_bo_gpu_offset(bo) - domain_start));
270 }
271
272 return 0;
273 }
274 radeon_ttm_placement_from_domain(bo, domain);
275 if (domain == RADEON_GEM_DOMAIN_VRAM) {
276 /* force to pin into visible video ram */
277 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
278 }
279 if (max_offset) {
280 u64 lpfn = max_offset >> PAGE_SHIFT;
281
282 if (!bo->placement.lpfn)
283 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
284
285 if (lpfn < bo->placement.lpfn)
286 bo->placement.lpfn = lpfn;
287 }
288 for (i = 0; i < bo->placement.num_placement; i++)
289 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
290 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
291 if (likely(r == 0)) {
292 bo->pin_count = 1;
293 if (gpu_addr != NULL)
294 *gpu_addr = radeon_bo_gpu_offset(bo);
295 }
296 if (unlikely(r != 0))
297 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
298 return r;
299}
300
301int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
302{
303 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
304}
305
306int radeon_bo_unpin(struct radeon_bo *bo)
307{
308 int r, i;
309
310 if (!bo->pin_count) {
311 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
312 return 0;
313 }
314 bo->pin_count--;
315 if (bo->pin_count)
316 return 0;
317 for (i = 0; i < bo->placement.num_placement; i++)
318 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
319 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
320 if (unlikely(r != 0))
321 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
322 return r;
323}
324
325int radeon_bo_evict_vram(struct radeon_device *rdev)
326{
327 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
328 if (0 && (rdev->flags & RADEON_IS_IGP)) {
329 if (rdev->mc.igp_sideport_enabled == false)
330 /* Useless to evict on IGP chips */
331 return 0;
332 }
333 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
334}
335
336void radeon_bo_force_delete(struct radeon_device *rdev)
337{
338 struct radeon_bo *bo, *n;
339
340 if (list_empty(&rdev->gem.objects)) {
341 return;
342 }
343 dev_err(rdev->dev, "Userspace still has active objects !\n");
344 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
345 mutex_lock(&rdev->ddev->struct_mutex);
346 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
347 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
348 *((unsigned long *)&bo->gem_base.refcount));
349 mutex_lock(&bo->rdev->gem.mutex);
350 list_del_init(&bo->list);
351 mutex_unlock(&bo->rdev->gem.mutex);
352 /* this should unref the ttm bo */
353 drm_gem_object_unreference(&bo->gem_base);
354 mutex_unlock(&rdev->ddev->struct_mutex);
355 }
356}
357
358int radeon_bo_init(struct radeon_device *rdev)
359{
360 /* Add an MTRR for the VRAM */
361 if (!rdev->fastfb_working) {
362 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
363 rdev->mc.aper_size);
364 }
365 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
366 rdev->mc.mc_vram_size >> 20,
367 (unsigned long long)rdev->mc.aper_size >> 20);
368 DRM_INFO("RAM width %dbits %cDR\n",
369 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
370 return radeon_ttm_init(rdev);
371}
372
373void radeon_bo_fini(struct radeon_device *rdev)
374{
375 radeon_ttm_fini(rdev);
376 arch_phys_wc_del(rdev->mc.vram_mtrr);
377}
378
379/* Returns how many bytes TTM can move per IB.
380 */
381static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
382{
383 u64 real_vram_size = rdev->mc.real_vram_size;
384 u64 vram_usage = atomic64_read(&rdev->vram_usage);
385
386 /* This function is based on the current VRAM usage.
387 *
388 * - If all of VRAM is free, allow relocating the number of bytes that
389 * is equal to 1/4 of the size of VRAM for this IB.
390
391 * - If more than one half of VRAM is occupied, only allow relocating
392 * 1 MB of data for this IB.
393 *
394 * - From 0 to one half of used VRAM, the threshold decreases
395 * linearly.
396 * __________________
397 * 1/4 of -|\ |
398 * VRAM | \ |
399 * | \ |
400 * | \ |
401 * | \ |
402 * | \ |
403 * | \ |
404 * | \________|1 MB
405 * |----------------|
406 * VRAM 0 % 100 %
407 * used used
408 *
409 * Note: It's a threshold, not a limit. The threshold must be crossed
410 * for buffer relocations to stop, so any buffer of an arbitrary size
411 * can be moved as long as the threshold isn't crossed before
412 * the relocation takes place. We don't want to disable buffer
413 * relocations completely.
414 *
415 * The idea is that buffers should be placed in VRAM at creation time
416 * and TTM should only do a minimum number of relocations during
417 * command submission. In practice, you need to submit at least
418 * a dozen IBs to move all buffers to VRAM if they are in GTT.
419 *
420 * Also, things can get pretty crazy under memory pressure and actual
421 * VRAM usage can change a lot, so playing safe even at 50% does
422 * consistently increase performance.
423 */
424
425 u64 half_vram = real_vram_size >> 1;
426 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
427 u64 bytes_moved_threshold = half_free_vram >> 1;
428 return max(bytes_moved_threshold, 1024*1024ull);
429}
430
431int radeon_bo_list_validate(struct radeon_device *rdev,
432 struct ww_acquire_ctx *ticket,
433 struct list_head *head, int ring)
434{
435 struct radeon_cs_reloc *lobj;
436 struct radeon_bo *bo;
437 int r;
438 u64 bytes_moved = 0, initial_bytes_moved;
439 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
440
441 r = ttm_eu_reserve_buffers(ticket, head);
442 if (unlikely(r != 0)) {
443 return r;
444 }
445
446 list_for_each_entry(lobj, head, tv.head) {
447 bo = lobj->robj;
448 if (!bo->pin_count) {
449 u32 domain = lobj->domain;
450 u32 current_domain =
451 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
452
453 /* Check if this buffer will be moved and don't move it
454 * if we have moved too many buffers for this IB already.
455 *
456 * Note that this allows moving at least one buffer of
457 * any size, because it doesn't take the current "bo"
458 * into account. We don't want to disallow buffer moves
459 * completely.
460 */
461 if ((lobj->alt_domain & current_domain) != 0 &&
462 (domain & current_domain) == 0 && /* will be moved */
463 bytes_moved > bytes_moved_threshold) {
464 /* don't move it */
465 domain = current_domain;
466 }
467
468 retry:
469 radeon_ttm_placement_from_domain(bo, domain);
470 if (ring == R600_RING_TYPE_UVD_INDEX)
471 radeon_uvd_force_into_uvd_segment(bo);
472
473 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
474 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
475 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
476 initial_bytes_moved;
477
478 if (unlikely(r)) {
479 if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
480 domain = lobj->alt_domain;
481 goto retry;
482 }
483 ttm_eu_backoff_reservation(ticket, head);
484 return r;
485 }
486 }
487 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
488 lobj->tiling_flags = bo->tiling_flags;
489 }
490 return 0;
491}
492
493int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
494 struct vm_area_struct *vma)
495{
496 return ttm_fbdev_mmap(vma, &bo->tbo);
497}
498
499int radeon_bo_get_surface_reg(struct radeon_bo *bo)
500{
501 struct radeon_device *rdev = bo->rdev;
502 struct radeon_surface_reg *reg;
503 struct radeon_bo *old_object;
504 int steal;
505 int i;
506
507 lockdep_assert_held(&bo->tbo.resv->lock.base);
508
509 if (!bo->tiling_flags)
510 return 0;
511
512 if (bo->surface_reg >= 0) {
513 reg = &rdev->surface_regs[bo->surface_reg];
514 i = bo->surface_reg;
515 goto out;
516 }
517
518 steal = -1;
519 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
520
521 reg = &rdev->surface_regs[i];
522 if (!reg->bo)
523 break;
524
525 old_object = reg->bo;
526 if (old_object->pin_count == 0)
527 steal = i;
528 }
529
530 /* if we are all out */
531 if (i == RADEON_GEM_MAX_SURFACES) {
532 if (steal == -1)
533 return -ENOMEM;
534 /* find someone with a surface reg and nuke their BO */
535 reg = &rdev->surface_regs[steal];
536 old_object = reg->bo;
537 /* blow away the mapping */
538 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
539 ttm_bo_unmap_virtual(&old_object->tbo);
540 old_object->surface_reg = -1;
541 i = steal;
542 }
543
544 bo->surface_reg = i;
545 reg->bo = bo;
546
547out:
548 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
549 bo->tbo.mem.start << PAGE_SHIFT,
550 bo->tbo.num_pages << PAGE_SHIFT);
551 return 0;
552}
553
554static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
555{
556 struct radeon_device *rdev = bo->rdev;
557 struct radeon_surface_reg *reg;
558
559 if (bo->surface_reg == -1)
560 return;
561
562 reg = &rdev->surface_regs[bo->surface_reg];
563 radeon_clear_surface_reg(rdev, bo->surface_reg);
564
565 reg->bo = NULL;
566 bo->surface_reg = -1;
567}
568
569int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
570 uint32_t tiling_flags, uint32_t pitch)
571{
572 struct radeon_device *rdev = bo->rdev;
573 int r;
574
575 if (rdev->family >= CHIP_CEDAR) {
576 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
577
578 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
579 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
580 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
581 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
582 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
583 switch (bankw) {
584 case 0:
585 case 1:
586 case 2:
587 case 4:
588 case 8:
589 break;
590 default:
591 return -EINVAL;
592 }
593 switch (bankh) {
594 case 0:
595 case 1:
596 case 2:
597 case 4:
598 case 8:
599 break;
600 default:
601 return -EINVAL;
602 }
603 switch (mtaspect) {
604 case 0:
605 case 1:
606 case 2:
607 case 4:
608 case 8:
609 break;
610 default:
611 return -EINVAL;
612 }
613 if (tilesplit > 6) {
614 return -EINVAL;
615 }
616 if (stilesplit > 6) {
617 return -EINVAL;
618 }
619 }
620 r = radeon_bo_reserve(bo, false);
621 if (unlikely(r != 0))
622 return r;
623 bo->tiling_flags = tiling_flags;
624 bo->pitch = pitch;
625 radeon_bo_unreserve(bo);
626 return 0;
627}
628
629void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
630 uint32_t *tiling_flags,
631 uint32_t *pitch)
632{
633 lockdep_assert_held(&bo->tbo.resv->lock.base);
634
635 if (tiling_flags)
636 *tiling_flags = bo->tiling_flags;
637 if (pitch)
638 *pitch = bo->pitch;
639}
640
641int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
642 bool force_drop)
643{
644 if (!force_drop)
645 lockdep_assert_held(&bo->tbo.resv->lock.base);
646
647 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
648 return 0;
649
650 if (force_drop) {
651 radeon_bo_clear_surface_reg(bo);
652 return 0;
653 }
654
655 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
656 if (!has_moved)
657 return 0;
658
659 if (bo->surface_reg >= 0)
660 radeon_bo_clear_surface_reg(bo);
661 return 0;
662 }
663
664 if ((bo->surface_reg >= 0) && !has_moved)
665 return 0;
666
667 return radeon_bo_get_surface_reg(bo);
668}
669
670void radeon_bo_move_notify(struct ttm_buffer_object *bo,
671 struct ttm_mem_reg *new_mem)
672{
673 struct radeon_bo *rbo;
674
675 if (!radeon_ttm_bo_is_radeon_bo(bo))
676 return;
677
678 rbo = container_of(bo, struct radeon_bo, tbo);
679 radeon_bo_check_tiling(rbo, 0, 1);
680 radeon_vm_bo_invalidate(rbo->rdev, rbo);
681
682 /* update statistics */
683 if (!new_mem)
684 return;
685
686 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
687 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
688}
689
690int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
691{
692 struct radeon_device *rdev;
693 struct radeon_bo *rbo;
694 unsigned long offset, size;
695 int r;
696
697 if (!radeon_ttm_bo_is_radeon_bo(bo))
698 return 0;
699 rbo = container_of(bo, struct radeon_bo, tbo);
700 radeon_bo_check_tiling(rbo, 0, 0);
701 rdev = rbo->rdev;
702 if (bo->mem.mem_type != TTM_PL_VRAM)
703 return 0;
704
705 size = bo->mem.num_pages << PAGE_SHIFT;
706 offset = bo->mem.start << PAGE_SHIFT;
707 if ((offset + size) <= rdev->mc.visible_vram_size)
708 return 0;
709
710 /* hurrah the memory is not visible ! */
711 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
712 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
713 r = ttm_bo_validate(bo, &rbo->placement, false, false);
714 if (unlikely(r == -ENOMEM)) {
715 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
716 return ttm_bo_validate(bo, &rbo->placement, false, false);
717 } else if (unlikely(r != 0)) {
718 return r;
719 }
720
721 offset = bo->mem.start << PAGE_SHIFT;
722 /* this should never happen */
723 if ((offset + size) > rdev->mc.visible_vram_size)
724 return -EINVAL;
725
726 return 0;
727}
728
729int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
730{
731 int r;
732
733 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
734 if (unlikely(r != 0))
735 return r;
736 spin_lock(&bo->tbo.bdev->fence_lock);
737 if (mem_type)
738 *mem_type = bo->tbo.mem.mem_type;
739 if (bo->tbo.sync_obj)
740 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
741 spin_unlock(&bo->tbo.bdev->fence_lock);
742 ttm_bo_unreserve(&bo->tbo);
743 return r;
744}