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1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_dp_mst_helper.h>
37#include <drm/drm_fixed.h>
38#include <drm/drm_crtc_helper.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41
42struct radeon_bo;
43struct radeon_device;
44
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
50#define RADEON_MAX_HPD_PINS 7
51#define RADEON_MAX_CRTCS 6
52#define RADEON_MAX_AFMT_BLOCKS 7
53
54enum radeon_rmx_type {
55 RMX_OFF,
56 RMX_FULL,
57 RMX_CENTER,
58 RMX_ASPECT
59};
60
61enum radeon_tv_std {
62 TV_STD_NTSC,
63 TV_STD_PAL,
64 TV_STD_PAL_M,
65 TV_STD_PAL_60,
66 TV_STD_NTSC_J,
67 TV_STD_SCART_PAL,
68 TV_STD_SECAM,
69 TV_STD_PAL_CN,
70 TV_STD_PAL_N,
71};
72
73enum radeon_underscan_type {
74 UNDERSCAN_OFF,
75 UNDERSCAN_ON,
76 UNDERSCAN_AUTO,
77};
78
79enum radeon_hpd_id {
80 RADEON_HPD_1 = 0,
81 RADEON_HPD_2,
82 RADEON_HPD_3,
83 RADEON_HPD_4,
84 RADEON_HPD_5,
85 RADEON_HPD_6,
86 RADEON_HPD_NONE = 0xff,
87};
88
89enum radeon_output_csc {
90 RADEON_OUTPUT_CSC_BYPASS = 0,
91 RADEON_OUTPUT_CSC_TVRGB = 1,
92 RADEON_OUTPUT_CSC_YCBCR601 = 2,
93 RADEON_OUTPUT_CSC_YCBCR709 = 3,
94};
95
96#define RADEON_MAX_I2C_BUS 16
97
98/* radeon gpio-based i2c
99 * 1. "mask" reg and bits
100 * grabs the gpio pins for software use
101 * 0=not held 1=held
102 * 2. "a" reg and bits
103 * output pin value
104 * 0=low 1=high
105 * 3. "en" reg and bits
106 * sets the pin direction
107 * 0=input 1=output
108 * 4. "y" reg and bits
109 * input pin value
110 * 0=low 1=high
111 */
112struct radeon_i2c_bus_rec {
113 bool valid;
114 /* id used by atom */
115 uint8_t i2c_id;
116 /* id used by atom */
117 enum radeon_hpd_id hpd;
118 /* can be used with hw i2c engine */
119 bool hw_capable;
120 /* uses multi-media i2c engine */
121 bool mm_i2c;
122 /* regs and bits */
123 uint32_t mask_clk_reg;
124 uint32_t mask_data_reg;
125 uint32_t a_clk_reg;
126 uint32_t a_data_reg;
127 uint32_t en_clk_reg;
128 uint32_t en_data_reg;
129 uint32_t y_clk_reg;
130 uint32_t y_data_reg;
131 uint32_t mask_clk_mask;
132 uint32_t mask_data_mask;
133 uint32_t a_clk_mask;
134 uint32_t a_data_mask;
135 uint32_t en_clk_mask;
136 uint32_t en_data_mask;
137 uint32_t y_clk_mask;
138 uint32_t y_data_mask;
139};
140
141struct radeon_tmds_pll {
142 uint32_t freq;
143 uint32_t value;
144};
145
146#define RADEON_MAX_BIOS_CONNECTOR 16
147
148/* pll flags */
149#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
150#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
151#define RADEON_PLL_USE_REF_DIV (1 << 2)
152#define RADEON_PLL_LEGACY (1 << 3)
153#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
154#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
155#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
156#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
157#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
158#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
159#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
160#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
161#define RADEON_PLL_USE_POST_DIV (1 << 12)
162#define RADEON_PLL_IS_LCD (1 << 13)
163#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
164
165struct radeon_pll {
166 /* reference frequency */
167 uint32_t reference_freq;
168
169 /* fixed dividers */
170 uint32_t reference_div;
171 uint32_t post_div;
172
173 /* pll in/out limits */
174 uint32_t pll_in_min;
175 uint32_t pll_in_max;
176 uint32_t pll_out_min;
177 uint32_t pll_out_max;
178 uint32_t lcd_pll_out_min;
179 uint32_t lcd_pll_out_max;
180 uint32_t best_vco;
181
182 /* divider limits */
183 uint32_t min_ref_div;
184 uint32_t max_ref_div;
185 uint32_t min_post_div;
186 uint32_t max_post_div;
187 uint32_t min_feedback_div;
188 uint32_t max_feedback_div;
189 uint32_t min_frac_feedback_div;
190 uint32_t max_frac_feedback_div;
191
192 /* flags for the current clock */
193 uint32_t flags;
194
195 /* pll id */
196 uint32_t id;
197};
198
199struct radeon_i2c_chan {
200 struct i2c_adapter adapter;
201 struct drm_device *dev;
202 struct i2c_algo_bit_data bit;
203 struct radeon_i2c_bus_rec rec;
204 struct drm_dp_aux aux;
205 bool has_aux;
206 struct mutex mutex;
207};
208
209/* mostly for macs, but really any system without connector tables */
210enum radeon_connector_table {
211 CT_NONE = 0,
212 CT_GENERIC,
213 CT_IBOOK,
214 CT_POWERBOOK_EXTERNAL,
215 CT_POWERBOOK_INTERNAL,
216 CT_POWERBOOK_VGA,
217 CT_MINI_EXTERNAL,
218 CT_MINI_INTERNAL,
219 CT_IMAC_G5_ISIGHT,
220 CT_EMAC,
221 CT_RN50_POWER,
222 CT_MAC_X800,
223 CT_MAC_G5_9600,
224 CT_SAM440EP,
225 CT_MAC_G4_SILVER
226};
227
228enum radeon_dvo_chip {
229 DVO_SIL164,
230 DVO_SIL1178,
231};
232
233struct radeon_fbdev;
234
235struct radeon_afmt {
236 bool enabled;
237 int offset;
238 bool last_buffer_filled_status;
239 int id;
240};
241
242struct radeon_mode_info {
243 struct atom_context *atom_context;
244 struct card_info *atom_card_info;
245 enum radeon_connector_table connector_table;
246 bool mode_config_initialized;
247 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
248 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
249 /* DVI-I properties */
250 struct drm_property *coherent_mode_property;
251 /* DAC enable load detect */
252 struct drm_property *load_detect_property;
253 /* TV standard */
254 struct drm_property *tv_std_property;
255 /* legacy TMDS PLL detect */
256 struct drm_property *tmds_pll_property;
257 /* underscan */
258 struct drm_property *underscan_property;
259 struct drm_property *underscan_hborder_property;
260 struct drm_property *underscan_vborder_property;
261 /* audio */
262 struct drm_property *audio_property;
263 /* FMT dithering */
264 struct drm_property *dither_property;
265 /* Output CSC */
266 struct drm_property *output_csc_property;
267 /* hardcoded DFP edid from BIOS */
268 struct edid *bios_hardcoded_edid;
269 int bios_hardcoded_edid_size;
270
271 /* pointer to fbdev info structure */
272 struct radeon_fbdev *rfbdev;
273 /* firmware flags */
274 u16 firmware_flags;
275 /* pointer to backlight encoder */
276 struct radeon_encoder *bl_encoder;
277
278 /* bitmask for active encoder frontends */
279 uint32_t active_encoders;
280};
281
282#define RADEON_MAX_BL_LEVEL 0xFF
283
284#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
285
286struct radeon_backlight_privdata {
287 struct radeon_encoder *encoder;
288 uint8_t negative;
289};
290
291#endif
292
293#define MAX_H_CODE_TIMING_LEN 32
294#define MAX_V_CODE_TIMING_LEN 32
295
296/* need to store these as reading
297 back code tables is excessive */
298struct radeon_tv_regs {
299 uint32_t tv_uv_adr;
300 uint32_t timing_cntl;
301 uint32_t hrestart;
302 uint32_t vrestart;
303 uint32_t frestart;
304 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
305 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
306};
307
308struct radeon_atom_ss {
309 uint16_t percentage;
310 uint16_t percentage_divider;
311 uint8_t type;
312 uint16_t step;
313 uint8_t delay;
314 uint8_t range;
315 uint8_t refdiv;
316 /* asic_ss */
317 uint16_t rate;
318 uint16_t amount;
319};
320
321enum radeon_flip_status {
322 RADEON_FLIP_NONE,
323 RADEON_FLIP_PENDING,
324 RADEON_FLIP_SUBMITTED
325};
326
327struct radeon_crtc {
328 struct drm_crtc base;
329 int crtc_id;
330 u16 lut_r[256], lut_g[256], lut_b[256];
331 bool enabled;
332 bool can_tile;
333 uint32_t crtc_offset;
334 struct drm_gem_object *cursor_bo;
335 uint64_t cursor_addr;
336 int cursor_x;
337 int cursor_y;
338 int cursor_hot_x;
339 int cursor_hot_y;
340 int cursor_width;
341 int cursor_height;
342 int max_cursor_width;
343 int max_cursor_height;
344 uint32_t legacy_display_base_addr;
345 enum radeon_rmx_type rmx_type;
346 u8 h_border;
347 u8 v_border;
348 fixed20_12 vsc;
349 fixed20_12 hsc;
350 struct drm_display_mode native_mode;
351 int pll_id;
352 /* page flipping */
353 struct workqueue_struct *flip_queue;
354 struct radeon_flip_work *flip_work;
355 enum radeon_flip_status flip_status;
356 /* pll sharing */
357 struct radeon_atom_ss ss;
358 bool ss_enabled;
359 u32 adjusted_clock;
360 int bpc;
361 u32 pll_reference_div;
362 u32 pll_post_div;
363 u32 pll_flags;
364 struct drm_encoder *encoder;
365 struct drm_connector *connector;
366 /* for dpm */
367 u32 line_time;
368 u32 wm_low;
369 u32 wm_high;
370 u32 lb_vblank_lead_lines;
371 struct drm_display_mode hw_mode;
372 enum radeon_output_csc output_csc;
373};
374
375struct radeon_encoder_primary_dac {
376 /* legacy primary dac */
377 uint32_t ps2_pdac_adj;
378};
379
380struct radeon_encoder_lvds {
381 /* legacy lvds */
382 uint16_t panel_vcc_delay;
383 uint8_t panel_pwr_delay;
384 uint8_t panel_digon_delay;
385 uint8_t panel_blon_delay;
386 uint16_t panel_ref_divider;
387 uint8_t panel_post_divider;
388 uint16_t panel_fb_divider;
389 bool use_bios_dividers;
390 uint32_t lvds_gen_cntl;
391 /* panel mode */
392 struct drm_display_mode native_mode;
393 struct backlight_device *bl_dev;
394 int dpms_mode;
395 uint8_t backlight_level;
396};
397
398struct radeon_encoder_tv_dac {
399 /* legacy tv dac */
400 uint32_t ps2_tvdac_adj;
401 uint32_t ntsc_tvdac_adj;
402 uint32_t pal_tvdac_adj;
403
404 int h_pos;
405 int v_pos;
406 int h_size;
407 int supported_tv_stds;
408 bool tv_on;
409 enum radeon_tv_std tv_std;
410 struct radeon_tv_regs tv;
411};
412
413struct radeon_encoder_int_tmds {
414 /* legacy int tmds */
415 struct radeon_tmds_pll tmds_pll[4];
416};
417
418struct radeon_encoder_ext_tmds {
419 /* tmds over dvo */
420 struct radeon_i2c_chan *i2c_bus;
421 uint8_t slave_addr;
422 enum radeon_dvo_chip dvo_chip;
423};
424
425/* spread spectrum */
426struct radeon_encoder_atom_dig {
427 bool linkb;
428 /* atom dig */
429 bool coherent_mode;
430 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
431 /* atom lvds/edp */
432 uint32_t lcd_misc;
433 uint16_t panel_pwr_delay;
434 uint32_t lcd_ss_id;
435 /* panel mode */
436 struct drm_display_mode native_mode;
437 struct backlight_device *bl_dev;
438 int dpms_mode;
439 uint8_t backlight_level;
440 int panel_mode;
441 struct radeon_afmt *afmt;
442 struct r600_audio_pin *pin;
443 int active_mst_links;
444};
445
446struct radeon_encoder_atom_dac {
447 enum radeon_tv_std tv_std;
448};
449
450struct radeon_encoder_mst {
451 int crtc;
452 struct radeon_encoder *primary;
453 struct radeon_connector *connector;
454 struct drm_dp_mst_port *port;
455 int pbn;
456 int fe;
457 bool fe_from_be;
458 bool enc_active;
459};
460
461struct radeon_encoder {
462 struct drm_encoder base;
463 uint32_t encoder_enum;
464 uint32_t encoder_id;
465 uint32_t devices;
466 uint32_t active_device;
467 uint32_t flags;
468 uint32_t pixel_clock;
469 enum radeon_rmx_type rmx_type;
470 enum radeon_underscan_type underscan_type;
471 uint32_t underscan_hborder;
472 uint32_t underscan_vborder;
473 struct drm_display_mode native_mode;
474 void *enc_priv;
475 int audio_polling_active;
476 bool is_ext_encoder;
477 u16 caps;
478 struct radeon_audio_funcs *audio;
479 enum radeon_output_csc output_csc;
480 bool can_mst;
481 uint32_t offset;
482 bool is_mst_encoder;
483 /* front end for this mst encoder */
484};
485
486struct radeon_connector_atom_dig {
487 uint32_t igp_lane_info;
488 /* displayport */
489 u8 dpcd[DP_RECEIVER_CAP_SIZE];
490 u8 dp_sink_type;
491 int dp_clock;
492 int dp_lane_count;
493 bool edp_on;
494 bool is_mst;
495};
496
497struct radeon_gpio_rec {
498 bool valid;
499 u8 id;
500 u32 reg;
501 u32 mask;
502 u32 shift;
503};
504
505struct radeon_hpd {
506 enum radeon_hpd_id hpd;
507 u8 plugged_state;
508 struct radeon_gpio_rec gpio;
509};
510
511struct radeon_router {
512 u32 router_id;
513 struct radeon_i2c_bus_rec i2c_info;
514 u8 i2c_addr;
515 /* i2c mux */
516 bool ddc_valid;
517 u8 ddc_mux_type;
518 u8 ddc_mux_control_pin;
519 u8 ddc_mux_state;
520 /* clock/data mux */
521 bool cd_valid;
522 u8 cd_mux_type;
523 u8 cd_mux_control_pin;
524 u8 cd_mux_state;
525};
526
527enum radeon_connector_audio {
528 RADEON_AUDIO_DISABLE = 0,
529 RADEON_AUDIO_ENABLE = 1,
530 RADEON_AUDIO_AUTO = 2
531};
532
533enum radeon_connector_dither {
534 RADEON_FMT_DITHER_DISABLE = 0,
535 RADEON_FMT_DITHER_ENABLE = 1,
536};
537
538struct stream_attribs {
539 uint16_t fe;
540 uint16_t slots;
541};
542
543struct radeon_connector {
544 struct drm_connector base;
545 uint32_t connector_id;
546 uint32_t devices;
547 struct radeon_i2c_chan *ddc_bus;
548 /* some systems have an hdmi and vga port with a shared ddc line */
549 bool shared_ddc;
550 bool use_digital;
551 /* we need to mind the EDID between detect
552 and get modes due to analog/digital/tvencoder */
553 struct edid *edid;
554 void *con_priv;
555 bool dac_load_detect;
556 bool detected_by_load; /* if the connection status was determined by load */
557 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
558 uint16_t connector_object_id;
559 struct radeon_hpd hpd;
560 struct radeon_router router;
561 struct radeon_i2c_chan *router_bus;
562 enum radeon_connector_audio audio;
563 enum radeon_connector_dither dither;
564 int pixelclock_for_modeset;
565 bool is_mst_connector;
566 struct radeon_connector *mst_port;
567 struct drm_dp_mst_port *port;
568 struct drm_dp_mst_topology_mgr mst_mgr;
569
570 struct radeon_encoder *mst_encoder;
571 struct stream_attribs cur_stream_attribs[6];
572 int enabled_attribs;
573};
574
575struct radeon_framebuffer {
576 struct drm_framebuffer base;
577 struct drm_gem_object *obj;
578};
579
580#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
581 ((em) == ATOM_ENCODER_MODE_DP_MST))
582
583struct atom_clock_dividers {
584 u32 post_div;
585 union {
586 struct {
587#ifdef __BIG_ENDIAN
588 u32 reserved : 6;
589 u32 whole_fb_div : 12;
590 u32 frac_fb_div : 14;
591#else
592 u32 frac_fb_div : 14;
593 u32 whole_fb_div : 12;
594 u32 reserved : 6;
595#endif
596 };
597 u32 fb_div;
598 };
599 u32 ref_div;
600 bool enable_post_div;
601 bool enable_dithen;
602 u32 vco_mode;
603 u32 real_clock;
604 /* added for CI */
605 u32 post_divider;
606 u32 flags;
607};
608
609struct atom_mpll_param {
610 union {
611 struct {
612#ifdef __BIG_ENDIAN
613 u32 reserved : 8;
614 u32 clkfrac : 12;
615 u32 clkf : 12;
616#else
617 u32 clkf : 12;
618 u32 clkfrac : 12;
619 u32 reserved : 8;
620#endif
621 };
622 u32 fb_div;
623 };
624 u32 post_div;
625 u32 bwcntl;
626 u32 dll_speed;
627 u32 vco_mode;
628 u32 yclk_sel;
629 u32 qdr;
630 u32 half_rate;
631};
632
633#define MEM_TYPE_GDDR5 0x50
634#define MEM_TYPE_GDDR4 0x40
635#define MEM_TYPE_GDDR3 0x30
636#define MEM_TYPE_DDR2 0x20
637#define MEM_TYPE_GDDR1 0x10
638#define MEM_TYPE_DDR3 0xb0
639#define MEM_TYPE_MASK 0xf0
640
641struct atom_memory_info {
642 u8 mem_vendor;
643 u8 mem_type;
644};
645
646#define MAX_AC_TIMING_ENTRIES 16
647
648struct atom_memory_clock_range_table
649{
650 u8 num_entries;
651 u8 rsv[3];
652 u32 mclk[MAX_AC_TIMING_ENTRIES];
653};
654
655#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
656#define VBIOS_MAX_AC_TIMING_ENTRIES 20
657
658struct atom_mc_reg_entry {
659 u32 mclk_max;
660 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
661};
662
663struct atom_mc_register_address {
664 u16 s1;
665 u8 pre_reg_data;
666};
667
668struct atom_mc_reg_table {
669 u8 last;
670 u8 num_entries;
671 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
672 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
673};
674
675#define MAX_VOLTAGE_ENTRIES 32
676
677struct atom_voltage_table_entry
678{
679 u16 value;
680 u32 smio_low;
681};
682
683struct atom_voltage_table
684{
685 u32 count;
686 u32 mask_low;
687 u32 phase_delay;
688 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
689};
690
691/* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
692#define USE_REAL_VBLANKSTART (1 << 30)
693#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
694
695extern void
696radeon_add_atom_connector(struct drm_device *dev,
697 uint32_t connector_id,
698 uint32_t supported_device,
699 int connector_type,
700 struct radeon_i2c_bus_rec *i2c_bus,
701 uint32_t igp_lane_info,
702 uint16_t connector_object_id,
703 struct radeon_hpd *hpd,
704 struct radeon_router *router);
705extern void
706radeon_add_legacy_connector(struct drm_device *dev,
707 uint32_t connector_id,
708 uint32_t supported_device,
709 int connector_type,
710 struct radeon_i2c_bus_rec *i2c_bus,
711 uint16_t connector_object_id,
712 struct radeon_hpd *hpd);
713extern uint32_t
714radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
715 uint8_t dac);
716extern void radeon_link_encoder_connector(struct drm_device *dev);
717
718extern enum radeon_tv_std
719radeon_combios_get_tv_info(struct radeon_device *rdev);
720extern enum radeon_tv_std
721radeon_atombios_get_tv_info(struct radeon_device *rdev);
722extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
723 u16 *vddc, u16 *vddci, u16 *mvdd);
724
725extern void
726radeon_combios_connected_scratch_regs(struct drm_connector *connector,
727 struct drm_encoder *encoder,
728 bool connected);
729extern void
730radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
731 struct drm_encoder *encoder,
732 bool connected);
733
734extern struct drm_connector *
735radeon_get_connector_for_encoder(struct drm_encoder *encoder);
736extern struct drm_connector *
737radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
738extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
739 u32 pixel_clock);
740
741extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
742extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
743extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
744extern int radeon_get_monitor_bpc(struct drm_connector *connector);
745
746extern struct edid *radeon_connector_edid(struct drm_connector *connector);
747
748extern void radeon_connector_hotplug(struct drm_connector *connector);
749extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
750 struct drm_display_mode *mode);
751extern void radeon_dp_set_link_config(struct drm_connector *connector,
752 const struct drm_display_mode *mode);
753extern void radeon_dp_link_train(struct drm_encoder *encoder,
754 struct drm_connector *connector);
755extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
756extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
757extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
758extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
759 struct drm_connector *connector);
760extern int radeon_dp_get_dp_link_config(struct drm_connector *connector,
761 const u8 *dpcd,
762 unsigned pix_clock,
763 unsigned *dp_lanes, unsigned *dp_rate);
764extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
765 u8 power_state);
766extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
767extern ssize_t
768radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
769
770extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
771extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
772extern void radeon_atom_encoder_init(struct radeon_device *rdev);
773extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
774extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
775 int action, uint8_t lane_num,
776 uint8_t lane_set);
777extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
778 int action, uint8_t lane_num,
779 uint8_t lane_set, int fe);
780extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder,
781 int fe);
782extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
783extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
784void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
785
786extern void radeon_i2c_init(struct radeon_device *rdev);
787extern void radeon_i2c_fini(struct radeon_device *rdev);
788extern void radeon_combios_i2c_init(struct radeon_device *rdev);
789extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
790extern void radeon_i2c_add(struct radeon_device *rdev,
791 struct radeon_i2c_bus_rec *rec,
792 const char *name);
793extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
794 struct radeon_i2c_bus_rec *i2c_bus);
795extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
796 struct radeon_i2c_bus_rec *rec,
797 const char *name);
798extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
799extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
800 u8 slave_addr,
801 u8 addr,
802 u8 *val);
803extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
804 u8 slave_addr,
805 u8 addr,
806 u8 val);
807extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
808extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
809extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
810
811extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
812 struct radeon_atom_ss *ss,
813 int id);
814extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
815 struct radeon_atom_ss *ss,
816 int id, u32 clock);
817extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
818 u8 id);
819
820extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
821 uint64_t freq,
822 uint32_t *dot_clock_p,
823 uint32_t *fb_div_p,
824 uint32_t *frac_fb_div_p,
825 uint32_t *ref_div_p,
826 uint32_t *post_div_p);
827
828extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
829 u32 freq,
830 u32 *dot_clock_p,
831 u32 *fb_div_p,
832 u32 *frac_fb_div_p,
833 u32 *ref_div_p,
834 u32 *post_div_p);
835
836extern void radeon_setup_encoder_clones(struct drm_device *dev);
837
838struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
839struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
840struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
841struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
842struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
843extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
844extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
845extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
846extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
847extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
848extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
849
850extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
851extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
852 struct drm_framebuffer *old_fb);
853extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
854 struct drm_framebuffer *fb,
855 int x, int y,
856 enum mode_set_atomic state);
857extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
858 struct drm_display_mode *mode,
859 struct drm_display_mode *adjusted_mode,
860 int x, int y,
861 struct drm_framebuffer *old_fb);
862extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
863
864extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
865 struct drm_framebuffer *old_fb);
866extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
867 struct drm_framebuffer *fb,
868 int x, int y,
869 enum mode_set_atomic state);
870extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
871 struct drm_framebuffer *fb,
872 int x, int y, int atomic);
873extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
874 struct drm_file *file_priv,
875 uint32_t handle,
876 uint32_t width,
877 uint32_t height,
878 int32_t hot_x,
879 int32_t hot_y);
880extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
881 int x, int y);
882extern void radeon_cursor_reset(struct drm_crtc *crtc);
883
884extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
885 unsigned int flags, int *vpos, int *hpos,
886 ktime_t *stime, ktime_t *etime,
887 const struct drm_display_mode *mode);
888
889extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
890extern struct edid *
891radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
892extern bool radeon_atom_get_clock_info(struct drm_device *dev);
893extern bool radeon_combios_get_clock_info(struct drm_device *dev);
894extern struct radeon_encoder_atom_dig *
895radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
896extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
897 struct radeon_encoder_int_tmds *tmds);
898extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
899 struct radeon_encoder_int_tmds *tmds);
900extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
901 struct radeon_encoder_int_tmds *tmds);
902extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
903 struct radeon_encoder_ext_tmds *tmds);
904extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
905 struct radeon_encoder_ext_tmds *tmds);
906extern struct radeon_encoder_primary_dac *
907radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
908extern struct radeon_encoder_tv_dac *
909radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
910extern struct radeon_encoder_lvds *
911radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
912extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
913extern struct radeon_encoder_tv_dac *
914radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
915extern struct radeon_encoder_primary_dac *
916radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
917extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
918extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
919extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
920extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
921extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
922extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
923extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
924extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
925extern void
926radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
927extern void
928radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
929extern void
930radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
931extern void
932radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
933extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
934 u16 blue, int regno);
935extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
936 u16 *blue, int regno);
937int radeon_framebuffer_init(struct drm_device *dev,
938 struct radeon_framebuffer *rfb,
939 const struct drm_mode_fb_cmd2 *mode_cmd,
940 struct drm_gem_object *obj);
941
942int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
943bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
944bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
945void radeon_atombios_init_crtc(struct drm_device *dev,
946 struct radeon_crtc *radeon_crtc);
947void radeon_legacy_init_crtc(struct drm_device *dev,
948 struct radeon_crtc *radeon_crtc);
949
950void radeon_get_clock_info(struct drm_device *dev);
951
952extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
953extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
954
955void radeon_enc_destroy(struct drm_encoder *encoder);
956void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
957void radeon_combios_asic_init(struct drm_device *dev);
958bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
959 const struct drm_display_mode *mode,
960 struct drm_display_mode *adjusted_mode);
961void radeon_panel_mode_fixup(struct drm_encoder *encoder,
962 struct drm_display_mode *adjusted_mode);
963void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
964
965/* legacy tv */
966void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
967 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
968 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
969void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
970 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
971 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
972void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
973 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
974 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
975void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
976 struct drm_display_mode *mode,
977 struct drm_display_mode *adjusted_mode);
978
979/* fmt blocks */
980void avivo_program_fmt(struct drm_encoder *encoder);
981void dce3_program_fmt(struct drm_encoder *encoder);
982void dce4_program_fmt(struct drm_encoder *encoder);
983void dce8_program_fmt(struct drm_encoder *encoder);
984
985/* fbdev layer */
986int radeon_fbdev_init(struct radeon_device *rdev);
987void radeon_fbdev_fini(struct radeon_device *rdev);
988void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
989bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
990void radeon_fbdev_restore_mode(struct radeon_device *rdev);
991
992void radeon_fb_output_poll_changed(struct radeon_device *rdev);
993
994void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
995
996void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector);
997void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector);
998
999void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
1000
1001int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
1002
1003/* mst */
1004int radeon_dp_mst_init(struct radeon_connector *radeon_connector);
1005int radeon_dp_mst_probe(struct radeon_connector *radeon_connector);
1006int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector);
1007int radeon_mst_debugfs_init(struct radeon_device *rdev);
1008void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode);
1009
1010void radeon_setup_mst_connector(struct drm_device *dev);
1011
1012int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
1013void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
1014#endif
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_crtc_helper.h>
38#include <linux/i2c.h>
39#include <linux/i2c-algo-bit.h>
40
41struct radeon_bo;
42struct radeon_device;
43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
49enum radeon_rmx_type {
50 RMX_OFF,
51 RMX_FULL,
52 RMX_CENTER,
53 RMX_ASPECT
54};
55
56enum radeon_tv_std {
57 TV_STD_NTSC,
58 TV_STD_PAL,
59 TV_STD_PAL_M,
60 TV_STD_PAL_60,
61 TV_STD_NTSC_J,
62 TV_STD_SCART_PAL,
63 TV_STD_SECAM,
64 TV_STD_PAL_CN,
65 TV_STD_PAL_N,
66};
67
68enum radeon_underscan_type {
69 UNDERSCAN_OFF,
70 UNDERSCAN_ON,
71 UNDERSCAN_AUTO,
72};
73
74enum radeon_hpd_id {
75 RADEON_HPD_1 = 0,
76 RADEON_HPD_2,
77 RADEON_HPD_3,
78 RADEON_HPD_4,
79 RADEON_HPD_5,
80 RADEON_HPD_6,
81 RADEON_HPD_NONE = 0xff,
82};
83
84#define RADEON_MAX_I2C_BUS 16
85
86/* radeon gpio-based i2c
87 * 1. "mask" reg and bits
88 * grabs the gpio pins for software use
89 * 0=not held 1=held
90 * 2. "a" reg and bits
91 * output pin value
92 * 0=low 1=high
93 * 3. "en" reg and bits
94 * sets the pin direction
95 * 0=input 1=output
96 * 4. "y" reg and bits
97 * input pin value
98 * 0=low 1=high
99 */
100struct radeon_i2c_bus_rec {
101 bool valid;
102 /* id used by atom */
103 uint8_t i2c_id;
104 /* id used by atom */
105 enum radeon_hpd_id hpd;
106 /* can be used with hw i2c engine */
107 bool hw_capable;
108 /* uses multi-media i2c engine */
109 bool mm_i2c;
110 /* regs and bits */
111 uint32_t mask_clk_reg;
112 uint32_t mask_data_reg;
113 uint32_t a_clk_reg;
114 uint32_t a_data_reg;
115 uint32_t en_clk_reg;
116 uint32_t en_data_reg;
117 uint32_t y_clk_reg;
118 uint32_t y_data_reg;
119 uint32_t mask_clk_mask;
120 uint32_t mask_data_mask;
121 uint32_t a_clk_mask;
122 uint32_t a_data_mask;
123 uint32_t en_clk_mask;
124 uint32_t en_data_mask;
125 uint32_t y_clk_mask;
126 uint32_t y_data_mask;
127};
128
129struct radeon_tmds_pll {
130 uint32_t freq;
131 uint32_t value;
132};
133
134#define RADEON_MAX_BIOS_CONNECTOR 16
135
136/* pll flags */
137#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
138#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
139#define RADEON_PLL_USE_REF_DIV (1 << 2)
140#define RADEON_PLL_LEGACY (1 << 3)
141#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
142#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
143#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
144#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
145#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
146#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
147#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
148#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
149#define RADEON_PLL_USE_POST_DIV (1 << 12)
150#define RADEON_PLL_IS_LCD (1 << 13)
151#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
152
153struct radeon_pll {
154 /* reference frequency */
155 uint32_t reference_freq;
156
157 /* fixed dividers */
158 uint32_t reference_div;
159 uint32_t post_div;
160
161 /* pll in/out limits */
162 uint32_t pll_in_min;
163 uint32_t pll_in_max;
164 uint32_t pll_out_min;
165 uint32_t pll_out_max;
166 uint32_t lcd_pll_out_min;
167 uint32_t lcd_pll_out_max;
168 uint32_t best_vco;
169
170 /* divider limits */
171 uint32_t min_ref_div;
172 uint32_t max_ref_div;
173 uint32_t min_post_div;
174 uint32_t max_post_div;
175 uint32_t min_feedback_div;
176 uint32_t max_feedback_div;
177 uint32_t min_frac_feedback_div;
178 uint32_t max_frac_feedback_div;
179
180 /* flags for the current clock */
181 uint32_t flags;
182
183 /* pll id */
184 uint32_t id;
185};
186
187struct radeon_i2c_chan {
188 struct i2c_adapter adapter;
189 struct drm_device *dev;
190 struct i2c_algo_bit_data bit;
191 struct radeon_i2c_bus_rec rec;
192 struct drm_dp_aux aux;
193 bool has_aux;
194};
195
196/* mostly for macs, but really any system without connector tables */
197enum radeon_connector_table {
198 CT_NONE = 0,
199 CT_GENERIC,
200 CT_IBOOK,
201 CT_POWERBOOK_EXTERNAL,
202 CT_POWERBOOK_INTERNAL,
203 CT_POWERBOOK_VGA,
204 CT_MINI_EXTERNAL,
205 CT_MINI_INTERNAL,
206 CT_IMAC_G5_ISIGHT,
207 CT_EMAC,
208 CT_RN50_POWER,
209 CT_MAC_X800,
210 CT_MAC_G5_9600,
211 CT_SAM440EP,
212 CT_MAC_G4_SILVER
213};
214
215enum radeon_dvo_chip {
216 DVO_SIL164,
217 DVO_SIL1178,
218};
219
220struct radeon_fbdev;
221
222struct radeon_afmt {
223 bool enabled;
224 int offset;
225 bool last_buffer_filled_status;
226 int id;
227 struct r600_audio_pin *pin;
228};
229
230struct radeon_mode_info {
231 struct atom_context *atom_context;
232 struct card_info *atom_card_info;
233 enum radeon_connector_table connector_table;
234 bool mode_config_initialized;
235 struct radeon_crtc *crtcs[6];
236 struct radeon_afmt *afmt[7];
237 /* DVI-I properties */
238 struct drm_property *coherent_mode_property;
239 /* DAC enable load detect */
240 struct drm_property *load_detect_property;
241 /* TV standard */
242 struct drm_property *tv_std_property;
243 /* legacy TMDS PLL detect */
244 struct drm_property *tmds_pll_property;
245 /* underscan */
246 struct drm_property *underscan_property;
247 struct drm_property *underscan_hborder_property;
248 struct drm_property *underscan_vborder_property;
249 /* audio */
250 struct drm_property *audio_property;
251 /* FMT dithering */
252 struct drm_property *dither_property;
253 /* hardcoded DFP edid from BIOS */
254 struct edid *bios_hardcoded_edid;
255 int bios_hardcoded_edid_size;
256
257 /* pointer to fbdev info structure */
258 struct radeon_fbdev *rfbdev;
259 /* firmware flags */
260 u16 firmware_flags;
261 /* pointer to backlight encoder */
262 struct radeon_encoder *bl_encoder;
263};
264
265#define RADEON_MAX_BL_LEVEL 0xFF
266
267#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
268
269struct radeon_backlight_privdata {
270 struct radeon_encoder *encoder;
271 uint8_t negative;
272};
273
274#endif
275
276#define MAX_H_CODE_TIMING_LEN 32
277#define MAX_V_CODE_TIMING_LEN 32
278
279/* need to store these as reading
280 back code tables is excessive */
281struct radeon_tv_regs {
282 uint32_t tv_uv_adr;
283 uint32_t timing_cntl;
284 uint32_t hrestart;
285 uint32_t vrestart;
286 uint32_t frestart;
287 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
288 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
289};
290
291struct radeon_atom_ss {
292 uint16_t percentage;
293 uint16_t percentage_divider;
294 uint8_t type;
295 uint16_t step;
296 uint8_t delay;
297 uint8_t range;
298 uint8_t refdiv;
299 /* asic_ss */
300 uint16_t rate;
301 uint16_t amount;
302};
303
304struct radeon_crtc {
305 struct drm_crtc base;
306 int crtc_id;
307 u16 lut_r[256], lut_g[256], lut_b[256];
308 bool enabled;
309 bool can_tile;
310 uint32_t crtc_offset;
311 struct drm_gem_object *cursor_bo;
312 uint64_t cursor_addr;
313 int cursor_width;
314 int cursor_height;
315 int max_cursor_width;
316 int max_cursor_height;
317 uint32_t legacy_display_base_addr;
318 uint32_t legacy_cursor_offset;
319 enum radeon_rmx_type rmx_type;
320 u8 h_border;
321 u8 v_border;
322 fixed20_12 vsc;
323 fixed20_12 hsc;
324 struct drm_display_mode native_mode;
325 int pll_id;
326 /* page flipping */
327 struct radeon_unpin_work *unpin_work;
328 int deferred_flip_completion;
329 /* pll sharing */
330 struct radeon_atom_ss ss;
331 bool ss_enabled;
332 u32 adjusted_clock;
333 int bpc;
334 u32 pll_reference_div;
335 u32 pll_post_div;
336 u32 pll_flags;
337 struct drm_encoder *encoder;
338 struct drm_connector *connector;
339 /* for dpm */
340 u32 line_time;
341 u32 wm_low;
342 u32 wm_high;
343 struct drm_display_mode hw_mode;
344};
345
346struct radeon_encoder_primary_dac {
347 /* legacy primary dac */
348 uint32_t ps2_pdac_adj;
349};
350
351struct radeon_encoder_lvds {
352 /* legacy lvds */
353 uint16_t panel_vcc_delay;
354 uint8_t panel_pwr_delay;
355 uint8_t panel_digon_delay;
356 uint8_t panel_blon_delay;
357 uint16_t panel_ref_divider;
358 uint8_t panel_post_divider;
359 uint16_t panel_fb_divider;
360 bool use_bios_dividers;
361 uint32_t lvds_gen_cntl;
362 /* panel mode */
363 struct drm_display_mode native_mode;
364 struct backlight_device *bl_dev;
365 int dpms_mode;
366 uint8_t backlight_level;
367};
368
369struct radeon_encoder_tv_dac {
370 /* legacy tv dac */
371 uint32_t ps2_tvdac_adj;
372 uint32_t ntsc_tvdac_adj;
373 uint32_t pal_tvdac_adj;
374
375 int h_pos;
376 int v_pos;
377 int h_size;
378 int supported_tv_stds;
379 bool tv_on;
380 enum radeon_tv_std tv_std;
381 struct radeon_tv_regs tv;
382};
383
384struct radeon_encoder_int_tmds {
385 /* legacy int tmds */
386 struct radeon_tmds_pll tmds_pll[4];
387};
388
389struct radeon_encoder_ext_tmds {
390 /* tmds over dvo */
391 struct radeon_i2c_chan *i2c_bus;
392 uint8_t slave_addr;
393 enum radeon_dvo_chip dvo_chip;
394};
395
396/* spread spectrum */
397struct radeon_encoder_atom_dig {
398 bool linkb;
399 /* atom dig */
400 bool coherent_mode;
401 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
402 /* atom lvds/edp */
403 uint32_t lcd_misc;
404 uint16_t panel_pwr_delay;
405 uint32_t lcd_ss_id;
406 /* panel mode */
407 struct drm_display_mode native_mode;
408 struct backlight_device *bl_dev;
409 int dpms_mode;
410 uint8_t backlight_level;
411 int panel_mode;
412 struct radeon_afmt *afmt;
413};
414
415struct radeon_encoder_atom_dac {
416 enum radeon_tv_std tv_std;
417};
418
419struct radeon_encoder {
420 struct drm_encoder base;
421 uint32_t encoder_enum;
422 uint32_t encoder_id;
423 uint32_t devices;
424 uint32_t active_device;
425 uint32_t flags;
426 uint32_t pixel_clock;
427 enum radeon_rmx_type rmx_type;
428 enum radeon_underscan_type underscan_type;
429 uint32_t underscan_hborder;
430 uint32_t underscan_vborder;
431 struct drm_display_mode native_mode;
432 void *enc_priv;
433 int audio_polling_active;
434 bool is_ext_encoder;
435 u16 caps;
436};
437
438struct radeon_connector_atom_dig {
439 uint32_t igp_lane_info;
440 /* displayport */
441 u8 dpcd[DP_RECEIVER_CAP_SIZE];
442 u8 dp_sink_type;
443 int dp_clock;
444 int dp_lane_count;
445 bool edp_on;
446};
447
448struct radeon_gpio_rec {
449 bool valid;
450 u8 id;
451 u32 reg;
452 u32 mask;
453};
454
455struct radeon_hpd {
456 enum radeon_hpd_id hpd;
457 u8 plugged_state;
458 struct radeon_gpio_rec gpio;
459};
460
461struct radeon_router {
462 u32 router_id;
463 struct radeon_i2c_bus_rec i2c_info;
464 u8 i2c_addr;
465 /* i2c mux */
466 bool ddc_valid;
467 u8 ddc_mux_type;
468 u8 ddc_mux_control_pin;
469 u8 ddc_mux_state;
470 /* clock/data mux */
471 bool cd_valid;
472 u8 cd_mux_type;
473 u8 cd_mux_control_pin;
474 u8 cd_mux_state;
475};
476
477enum radeon_connector_audio {
478 RADEON_AUDIO_DISABLE = 0,
479 RADEON_AUDIO_ENABLE = 1,
480 RADEON_AUDIO_AUTO = 2
481};
482
483enum radeon_connector_dither {
484 RADEON_FMT_DITHER_DISABLE = 0,
485 RADEON_FMT_DITHER_ENABLE = 1,
486};
487
488struct radeon_connector {
489 struct drm_connector base;
490 uint32_t connector_id;
491 uint32_t devices;
492 struct radeon_i2c_chan *ddc_bus;
493 /* some systems have an hdmi and vga port with a shared ddc line */
494 bool shared_ddc;
495 bool use_digital;
496 /* we need to mind the EDID between detect
497 and get modes due to analog/digital/tvencoder */
498 struct edid *edid;
499 void *con_priv;
500 bool dac_load_detect;
501 bool detected_by_load; /* if the connection status was determined by load */
502 uint16_t connector_object_id;
503 struct radeon_hpd hpd;
504 struct radeon_router router;
505 struct radeon_i2c_chan *router_bus;
506 enum radeon_connector_audio audio;
507 enum radeon_connector_dither dither;
508};
509
510struct radeon_framebuffer {
511 struct drm_framebuffer base;
512 struct drm_gem_object *obj;
513};
514
515#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
516 ((em) == ATOM_ENCODER_MODE_DP_MST))
517
518struct atom_clock_dividers {
519 u32 post_div;
520 union {
521 struct {
522#ifdef __BIG_ENDIAN
523 u32 reserved : 6;
524 u32 whole_fb_div : 12;
525 u32 frac_fb_div : 14;
526#else
527 u32 frac_fb_div : 14;
528 u32 whole_fb_div : 12;
529 u32 reserved : 6;
530#endif
531 };
532 u32 fb_div;
533 };
534 u32 ref_div;
535 bool enable_post_div;
536 bool enable_dithen;
537 u32 vco_mode;
538 u32 real_clock;
539 /* added for CI */
540 u32 post_divider;
541 u32 flags;
542};
543
544struct atom_mpll_param {
545 union {
546 struct {
547#ifdef __BIG_ENDIAN
548 u32 reserved : 8;
549 u32 clkfrac : 12;
550 u32 clkf : 12;
551#else
552 u32 clkf : 12;
553 u32 clkfrac : 12;
554 u32 reserved : 8;
555#endif
556 };
557 u32 fb_div;
558 };
559 u32 post_div;
560 u32 bwcntl;
561 u32 dll_speed;
562 u32 vco_mode;
563 u32 yclk_sel;
564 u32 qdr;
565 u32 half_rate;
566};
567
568#define MEM_TYPE_GDDR5 0x50
569#define MEM_TYPE_GDDR4 0x40
570#define MEM_TYPE_GDDR3 0x30
571#define MEM_TYPE_DDR2 0x20
572#define MEM_TYPE_GDDR1 0x10
573#define MEM_TYPE_DDR3 0xb0
574#define MEM_TYPE_MASK 0xf0
575
576struct atom_memory_info {
577 u8 mem_vendor;
578 u8 mem_type;
579};
580
581#define MAX_AC_TIMING_ENTRIES 16
582
583struct atom_memory_clock_range_table
584{
585 u8 num_entries;
586 u8 rsv[3];
587 u32 mclk[MAX_AC_TIMING_ENTRIES];
588};
589
590#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
591#define VBIOS_MAX_AC_TIMING_ENTRIES 20
592
593struct atom_mc_reg_entry {
594 u32 mclk_max;
595 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
596};
597
598struct atom_mc_register_address {
599 u16 s1;
600 u8 pre_reg_data;
601};
602
603struct atom_mc_reg_table {
604 u8 last;
605 u8 num_entries;
606 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
607 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
608};
609
610#define MAX_VOLTAGE_ENTRIES 32
611
612struct atom_voltage_table_entry
613{
614 u16 value;
615 u32 smio_low;
616};
617
618struct atom_voltage_table
619{
620 u32 count;
621 u32 mask_low;
622 u32 phase_delay;
623 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
624};
625
626
627extern void
628radeon_add_atom_connector(struct drm_device *dev,
629 uint32_t connector_id,
630 uint32_t supported_device,
631 int connector_type,
632 struct radeon_i2c_bus_rec *i2c_bus,
633 uint32_t igp_lane_info,
634 uint16_t connector_object_id,
635 struct radeon_hpd *hpd,
636 struct radeon_router *router);
637extern void
638radeon_add_legacy_connector(struct drm_device *dev,
639 uint32_t connector_id,
640 uint32_t supported_device,
641 int connector_type,
642 struct radeon_i2c_bus_rec *i2c_bus,
643 uint16_t connector_object_id,
644 struct radeon_hpd *hpd);
645extern uint32_t
646radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
647 uint8_t dac);
648extern void radeon_link_encoder_connector(struct drm_device *dev);
649
650extern enum radeon_tv_std
651radeon_combios_get_tv_info(struct radeon_device *rdev);
652extern enum radeon_tv_std
653radeon_atombios_get_tv_info(struct radeon_device *rdev);
654extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
655 u16 *vddc, u16 *vddci, u16 *mvdd);
656
657extern void
658radeon_combios_connected_scratch_regs(struct drm_connector *connector,
659 struct drm_encoder *encoder,
660 bool connected);
661extern void
662radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
663 struct drm_encoder *encoder,
664 bool connected);
665
666extern struct drm_connector *
667radeon_get_connector_for_encoder(struct drm_encoder *encoder);
668extern struct drm_connector *
669radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
670extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
671 u32 pixel_clock);
672
673extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
674extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
675extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
676extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
677extern int radeon_get_monitor_bpc(struct drm_connector *connector);
678
679extern void radeon_connector_hotplug(struct drm_connector *connector);
680extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
681 struct drm_display_mode *mode);
682extern void radeon_dp_set_link_config(struct drm_connector *connector,
683 const struct drm_display_mode *mode);
684extern void radeon_dp_link_train(struct drm_encoder *encoder,
685 struct drm_connector *connector);
686extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
687extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
688extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
689extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
690 struct drm_connector *connector);
691extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
692 u8 power_state);
693extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
694extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
695extern void radeon_atom_encoder_init(struct radeon_device *rdev);
696extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
697extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
698 int action, uint8_t lane_num,
699 uint8_t lane_set);
700extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
701extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
702void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
703
704extern void radeon_i2c_init(struct radeon_device *rdev);
705extern void radeon_i2c_fini(struct radeon_device *rdev);
706extern void radeon_combios_i2c_init(struct radeon_device *rdev);
707extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
708extern void radeon_i2c_add(struct radeon_device *rdev,
709 struct radeon_i2c_bus_rec *rec,
710 const char *name);
711extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
712 struct radeon_i2c_bus_rec *i2c_bus);
713extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
714 struct radeon_i2c_bus_rec *rec,
715 const char *name);
716extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
717extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
718 u8 slave_addr,
719 u8 addr,
720 u8 *val);
721extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
722 u8 slave_addr,
723 u8 addr,
724 u8 val);
725extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
726extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
727extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
728extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
729
730extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
731
732extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
733 struct radeon_atom_ss *ss,
734 int id);
735extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
736 struct radeon_atom_ss *ss,
737 int id, u32 clock);
738
739extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
740 uint64_t freq,
741 uint32_t *dot_clock_p,
742 uint32_t *fb_div_p,
743 uint32_t *frac_fb_div_p,
744 uint32_t *ref_div_p,
745 uint32_t *post_div_p);
746
747extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
748 u32 freq,
749 u32 *dot_clock_p,
750 u32 *fb_div_p,
751 u32 *frac_fb_div_p,
752 u32 *ref_div_p,
753 u32 *post_div_p);
754
755extern void radeon_setup_encoder_clones(struct drm_device *dev);
756
757struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
758struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
759struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
760struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
761struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
762extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
763extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
764extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
765extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
766extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
767
768extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
769extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
770 struct drm_framebuffer *old_fb);
771extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
772 struct drm_framebuffer *fb,
773 int x, int y,
774 enum mode_set_atomic state);
775extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
776 struct drm_display_mode *mode,
777 struct drm_display_mode *adjusted_mode,
778 int x, int y,
779 struct drm_framebuffer *old_fb);
780extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
781
782extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
783 struct drm_framebuffer *old_fb);
784extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
785 struct drm_framebuffer *fb,
786 int x, int y,
787 enum mode_set_atomic state);
788extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
789 struct drm_framebuffer *fb,
790 int x, int y, int atomic);
791extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
792 struct drm_file *file_priv,
793 uint32_t handle,
794 uint32_t width,
795 uint32_t height);
796extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
797 int x, int y);
798
799extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
800 unsigned int flags,
801 int *vpos, int *hpos, ktime_t *stime,
802 ktime_t *etime);
803
804extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
805extern struct edid *
806radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
807extern bool radeon_atom_get_clock_info(struct drm_device *dev);
808extern bool radeon_combios_get_clock_info(struct drm_device *dev);
809extern struct radeon_encoder_atom_dig *
810radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
811extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
812 struct radeon_encoder_int_tmds *tmds);
813extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
814 struct radeon_encoder_int_tmds *tmds);
815extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
816 struct radeon_encoder_int_tmds *tmds);
817extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
818 struct radeon_encoder_ext_tmds *tmds);
819extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
820 struct radeon_encoder_ext_tmds *tmds);
821extern struct radeon_encoder_primary_dac *
822radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
823extern struct radeon_encoder_tv_dac *
824radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
825extern struct radeon_encoder_lvds *
826radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
827extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
828extern struct radeon_encoder_tv_dac *
829radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
830extern struct radeon_encoder_primary_dac *
831radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
832extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
833extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
834extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
835extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
836extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
837extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
838extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
839extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
840extern void
841radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
842extern void
843radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
844extern void
845radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
846extern void
847radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
848extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
849 u16 blue, int regno);
850extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
851 u16 *blue, int regno);
852int radeon_framebuffer_init(struct drm_device *dev,
853 struct radeon_framebuffer *rfb,
854 struct drm_mode_fb_cmd2 *mode_cmd,
855 struct drm_gem_object *obj);
856
857int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
858bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
859bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
860void radeon_atombios_init_crtc(struct drm_device *dev,
861 struct radeon_crtc *radeon_crtc);
862void radeon_legacy_init_crtc(struct drm_device *dev,
863 struct radeon_crtc *radeon_crtc);
864
865void radeon_get_clock_info(struct drm_device *dev);
866
867extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
868extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
869
870void radeon_enc_destroy(struct drm_encoder *encoder);
871void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
872void radeon_combios_asic_init(struct drm_device *dev);
873bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
874 const struct drm_display_mode *mode,
875 struct drm_display_mode *adjusted_mode);
876void radeon_panel_mode_fixup(struct drm_encoder *encoder,
877 struct drm_display_mode *adjusted_mode);
878void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
879
880/* legacy tv */
881void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
882 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
883 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
884void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
885 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
886 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
887void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
888 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
889 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
890void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
891 struct drm_display_mode *mode,
892 struct drm_display_mode *adjusted_mode);
893
894/* fmt blocks */
895void avivo_program_fmt(struct drm_encoder *encoder);
896void dce3_program_fmt(struct drm_encoder *encoder);
897void dce4_program_fmt(struct drm_encoder *encoder);
898void dce8_program_fmt(struct drm_encoder *encoder);
899
900/* fbdev layer */
901int radeon_fbdev_init(struct radeon_device *rdev);
902void radeon_fbdev_fini(struct radeon_device *rdev);
903void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
904int radeon_fbdev_total_size(struct radeon_device *rdev);
905bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
906
907void radeon_fb_output_poll_changed(struct radeon_device *rdev);
908
909void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
910
911int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
912#endif