Loading...
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "adreno_gpu.h"
21#include "msm_gem.h"
22#include "msm_mmu.h"
23
24#define RB_SIZE SZ_32K
25#define RB_BLKSIZE 16
26
27int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
28{
29 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
30
31 switch (param) {
32 case MSM_PARAM_GPU_ID:
33 *value = adreno_gpu->info->revn;
34 return 0;
35 case MSM_PARAM_GMEM_SIZE:
36 *value = adreno_gpu->gmem;
37 return 0;
38 case MSM_PARAM_CHIP_ID:
39 *value = adreno_gpu->rev.patchid |
40 (adreno_gpu->rev.minor << 8) |
41 (adreno_gpu->rev.major << 16) |
42 (adreno_gpu->rev.core << 24);
43 return 0;
44 case MSM_PARAM_MAX_FREQ:
45 *value = adreno_gpu->base.fast_rate;
46 return 0;
47 case MSM_PARAM_TIMESTAMP:
48 if (adreno_gpu->funcs->get_timestamp)
49 return adreno_gpu->funcs->get_timestamp(gpu, value);
50 return -EINVAL;
51 default:
52 DBG("%s: invalid param: %u", gpu->name, param);
53 return -EINVAL;
54 }
55}
56
57#define rbmemptr(adreno_gpu, member) \
58 ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
59
60int adreno_hw_init(struct msm_gpu *gpu)
61{
62 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
63 int ret;
64
65 DBG("%s", gpu->name);
66
67 ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
68 if (ret) {
69 gpu->rb_iova = 0;
70 dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
71 return ret;
72 }
73
74 /* Setup REG_CP_RB_CNTL: */
75 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
76 /* size is log2(quad-words): */
77 AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
78 AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
79 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
80
81 /* Setup ringbuffer address: */
82 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
83
84 if (!adreno_is_a430(adreno_gpu))
85 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
86 rbmemptr(adreno_gpu, rptr));
87
88 return 0;
89}
90
91static uint32_t get_wptr(struct msm_ringbuffer *ring)
92{
93 return ring->cur - ring->start;
94}
95
96/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
97static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
98{
99 if (adreno_is_a430(adreno_gpu))
100 return adreno_gpu->memptrs->rptr = adreno_gpu_read(
101 adreno_gpu, REG_ADRENO_CP_RB_RPTR);
102 else
103 return adreno_gpu->memptrs->rptr;
104}
105
106uint32_t adreno_last_fence(struct msm_gpu *gpu)
107{
108 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
109 return adreno_gpu->memptrs->fence;
110}
111
112void adreno_recover(struct msm_gpu *gpu)
113{
114 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
115 struct drm_device *dev = gpu->dev;
116 int ret;
117
118 gpu->funcs->pm_suspend(gpu);
119
120 /* reset ringbuffer: */
121 gpu->rb->cur = gpu->rb->start;
122
123 /* reset completed fence seqno, just discard anything pending: */
124 adreno_gpu->memptrs->fence = gpu->submitted_fence;
125 adreno_gpu->memptrs->rptr = 0;
126 adreno_gpu->memptrs->wptr = 0;
127
128 gpu->funcs->pm_resume(gpu);
129 ret = gpu->funcs->hw_init(gpu);
130 if (ret) {
131 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
132 /* hmm, oh well? */
133 }
134}
135
136int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
137 struct msm_file_private *ctx)
138{
139 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
140 struct msm_drm_private *priv = gpu->dev->dev_private;
141 struct msm_ringbuffer *ring = gpu->rb;
142 unsigned i, ibs = 0;
143
144 for (i = 0; i < submit->nr_cmds; i++) {
145 switch (submit->cmd[i].type) {
146 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
147 /* ignore IB-targets */
148 break;
149 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
150 /* ignore if there has not been a ctx switch: */
151 if (priv->lastctx == ctx)
152 break;
153 case MSM_SUBMIT_CMD_BUF:
154 OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
155 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
156 OUT_RING(ring, submit->cmd[i].iova);
157 OUT_RING(ring, submit->cmd[i].size);
158 ibs++;
159 break;
160 }
161 }
162
163 /* on a320, at least, we seem to need to pad things out to an
164 * even number of qwords to avoid issue w/ CP hanging on wrap-
165 * around:
166 */
167 if (ibs % 2)
168 OUT_PKT2(ring);
169
170 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
171 OUT_RING(ring, submit->fence);
172
173 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
174 /* Flush HLSQ lazy updates to make sure there is nothing
175 * pending for indirect loads after the timestamp has
176 * passed:
177 */
178 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
179 OUT_RING(ring, HLSQ_FLUSH);
180
181 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
182 OUT_RING(ring, 0x00000000);
183 }
184
185 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
186 OUT_RING(ring, CACHE_FLUSH_TS);
187 OUT_RING(ring, rbmemptr(adreno_gpu, fence));
188 OUT_RING(ring, submit->fence);
189
190 /* we could maybe be clever and only CP_COND_EXEC the interrupt: */
191 OUT_PKT3(ring, CP_INTERRUPT, 1);
192 OUT_RING(ring, 0x80000000);
193
194 /* Workaround for missing irq issue on 8x16/a306. Unsure if the
195 * root cause is a platform issue or some a306 quirk, but this
196 * keeps things humming along:
197 */
198 if (adreno_is_a306(adreno_gpu)) {
199 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
200 OUT_RING(ring, 0x00000000);
201 OUT_PKT3(ring, CP_INTERRUPT, 1);
202 OUT_RING(ring, 0x80000000);
203 }
204
205#if 0
206 if (adreno_is_a3xx(adreno_gpu)) {
207 /* Dummy set-constant to trigger context rollover */
208 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
209 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
210 OUT_RING(ring, 0x00000000);
211 }
212#endif
213
214 gpu->funcs->flush(gpu);
215
216 return 0;
217}
218
219void adreno_flush(struct msm_gpu *gpu)
220{
221 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
222 uint32_t wptr = get_wptr(gpu->rb);
223
224 /* ensure writes to ringbuffer have hit system memory: */
225 mb();
226
227 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
228}
229
230void adreno_idle(struct msm_gpu *gpu)
231{
232 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
233 uint32_t wptr = get_wptr(gpu->rb);
234 int ret;
235
236 /* wait for CP to drain ringbuffer: */
237 ret = spin_until(get_rptr(adreno_gpu) == wptr);
238
239 if (ret)
240 DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
241
242 /* TODO maybe we need to reset GPU here to recover from hang? */
243}
244
245#ifdef CONFIG_DEBUG_FS
246void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
247{
248 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
249 int i;
250
251 seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
252 adreno_gpu->info->revn, adreno_gpu->rev.core,
253 adreno_gpu->rev.major, adreno_gpu->rev.minor,
254 adreno_gpu->rev.patchid);
255
256 seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence,
257 gpu->submitted_fence);
258 seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
259 seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
260 seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
261
262 gpu->funcs->pm_resume(gpu);
263
264 /* dump these out in a form that can be parsed by demsm: */
265 seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
266 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
267 uint32_t start = adreno_gpu->registers[i];
268 uint32_t end = adreno_gpu->registers[i+1];
269 uint32_t addr;
270
271 for (addr = start; addr <= end; addr++) {
272 uint32_t val = gpu_read(gpu, addr);
273 seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
274 }
275 }
276
277 gpu->funcs->pm_suspend(gpu);
278}
279#endif
280
281/* Dump common gpu status and scratch registers on any hang, to make
282 * the hangcheck logs more useful. The scratch registers seem always
283 * safe to read when GPU has hung (unlike some other regs, depending
284 * on how the GPU hung), and they are useful to match up to cmdstream
285 * dumps when debugging hangs:
286 */
287void adreno_dump_info(struct msm_gpu *gpu)
288{
289 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
290 int i;
291
292 printk("revision: %d (%d.%d.%d.%d)\n",
293 adreno_gpu->info->revn, adreno_gpu->rev.core,
294 adreno_gpu->rev.major, adreno_gpu->rev.minor,
295 adreno_gpu->rev.patchid);
296
297 printk("fence: %d/%d\n", adreno_gpu->memptrs->fence,
298 gpu->submitted_fence);
299 printk("rptr: %d\n", get_rptr(adreno_gpu));
300 printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
301 printk("rb wptr: %d\n", get_wptr(gpu->rb));
302
303 for (i = 0; i < 8; i++) {
304 printk("CP_SCRATCH_REG%d: %u\n", i,
305 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
306 }
307}
308
309/* would be nice to not have to duplicate the _show() stuff with printk(): */
310void adreno_dump(struct msm_gpu *gpu)
311{
312 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
313 int i;
314
315 /* dump these out in a form that can be parsed by demsm: */
316 printk("IO:region %s 00000000 00020000\n", gpu->name);
317 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
318 uint32_t start = adreno_gpu->registers[i];
319 uint32_t end = adreno_gpu->registers[i+1];
320 uint32_t addr;
321
322 for (addr = start; addr <= end; addr++) {
323 uint32_t val = gpu_read(gpu, addr);
324 printk("IO:R %08x %08x\n", addr<<2, val);
325 }
326 }
327}
328
329static uint32_t ring_freewords(struct msm_gpu *gpu)
330{
331 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
332 uint32_t size = gpu->rb->size / 4;
333 uint32_t wptr = get_wptr(gpu->rb);
334 uint32_t rptr = get_rptr(adreno_gpu);
335 return (rptr + (size - 1) - wptr) % size;
336}
337
338void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
339{
340 if (spin_until(ring_freewords(gpu) >= ndwords))
341 DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
342}
343
344static const char *iommu_ports[] = {
345 "gfx3d_user", "gfx3d_priv",
346 "gfx3d1_user", "gfx3d1_priv",
347};
348
349int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
350 struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
351{
352 struct adreno_platform_config *config = pdev->dev.platform_data;
353 struct msm_gpu *gpu = &adreno_gpu->base;
354 struct msm_mmu *mmu;
355 int ret;
356
357 adreno_gpu->funcs = funcs;
358 adreno_gpu->info = adreno_info(config->rev);
359 adreno_gpu->gmem = adreno_gpu->info->gmem;
360 adreno_gpu->revn = adreno_gpu->info->revn;
361 adreno_gpu->rev = config->rev;
362
363 gpu->fast_rate = config->fast_rate;
364 gpu->slow_rate = config->slow_rate;
365 gpu->bus_freq = config->bus_freq;
366#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
367 gpu->bus_scale_table = config->bus_scale_table;
368#endif
369
370 DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
371 gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
372
373 ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
374 adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
375 RB_SIZE);
376 if (ret)
377 return ret;
378
379 ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
380 if (ret) {
381 dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
382 adreno_gpu->info->pm4fw, ret);
383 return ret;
384 }
385
386 ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
387 if (ret) {
388 dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
389 adreno_gpu->info->pfpfw, ret);
390 return ret;
391 }
392
393 mmu = gpu->mmu;
394 if (mmu) {
395 ret = mmu->funcs->attach(mmu, iommu_ports,
396 ARRAY_SIZE(iommu_ports));
397 if (ret)
398 return ret;
399 }
400
401 mutex_lock(&drm->struct_mutex);
402 adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
403 MSM_BO_UNCACHED);
404 mutex_unlock(&drm->struct_mutex);
405 if (IS_ERR(adreno_gpu->memptrs_bo)) {
406 ret = PTR_ERR(adreno_gpu->memptrs_bo);
407 adreno_gpu->memptrs_bo = NULL;
408 dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
409 return ret;
410 }
411
412 adreno_gpu->memptrs = msm_gem_vaddr(adreno_gpu->memptrs_bo);
413 if (!adreno_gpu->memptrs) {
414 dev_err(drm->dev, "could not vmap memptrs\n");
415 return -ENOMEM;
416 }
417
418 ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
419 &adreno_gpu->memptrs_iova);
420 if (ret) {
421 dev_err(drm->dev, "could not map memptrs: %d\n", ret);
422 return ret;
423 }
424
425 return 0;
426}
427
428void adreno_gpu_cleanup(struct adreno_gpu *gpu)
429{
430 if (gpu->memptrs_bo) {
431 if (gpu->memptrs_iova)
432 msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
433 drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
434 }
435 release_firmware(gpu->pm4);
436 release_firmware(gpu->pfp);
437 msm_gpu_cleanup(&gpu->base);
438}
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "adreno_gpu.h"
19#include "msm_gem.h"
20#include "msm_mmu.h"
21
22struct adreno_info {
23 struct adreno_rev rev;
24 uint32_t revn;
25 const char *name;
26 const char *pm4fw, *pfpfw;
27 uint32_t gmem;
28};
29
30#define ANY_ID 0xff
31
32static const struct adreno_info gpulist[] = {
33 {
34 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
35 .revn = 305,
36 .name = "A305",
37 .pm4fw = "a300_pm4.fw",
38 .pfpfw = "a300_pfp.fw",
39 .gmem = SZ_256K,
40 }, {
41 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
42 .revn = 320,
43 .name = "A320",
44 .pm4fw = "a300_pm4.fw",
45 .pfpfw = "a300_pfp.fw",
46 .gmem = SZ_512K,
47 }, {
48 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
49 .revn = 330,
50 .name = "A330",
51 .pm4fw = "a330_pm4.fw",
52 .pfpfw = "a330_pfp.fw",
53 .gmem = SZ_1M,
54 },
55};
56
57MODULE_FIRMWARE("a300_pm4.fw");
58MODULE_FIRMWARE("a300_pfp.fw");
59MODULE_FIRMWARE("a330_pm4.fw");
60MODULE_FIRMWARE("a330_pfp.fw");
61
62#define RB_SIZE SZ_32K
63#define RB_BLKSIZE 16
64
65int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
66{
67 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
68
69 switch (param) {
70 case MSM_PARAM_GPU_ID:
71 *value = adreno_gpu->info->revn;
72 return 0;
73 case MSM_PARAM_GMEM_SIZE:
74 *value = adreno_gpu->gmem;
75 return 0;
76 case MSM_PARAM_CHIP_ID:
77 *value = adreno_gpu->rev.patchid |
78 (adreno_gpu->rev.minor << 8) |
79 (adreno_gpu->rev.major << 16) |
80 (adreno_gpu->rev.core << 24);
81 return 0;
82 default:
83 DBG("%s: invalid param: %u", gpu->name, param);
84 return -EINVAL;
85 }
86}
87
88#define rbmemptr(adreno_gpu, member) \
89 ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
90
91int adreno_hw_init(struct msm_gpu *gpu)
92{
93 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
94
95 DBG("%s", gpu->name);
96
97 /* Setup REG_CP_RB_CNTL: */
98 gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
99 /* size is log2(quad-words): */
100 AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
101 AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)));
102
103 /* Setup ringbuffer address: */
104 gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova);
105 gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(adreno_gpu, rptr));
106
107 /* Setup scratch/timestamp: */
108 gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(adreno_gpu, fence));
109
110 gpu_write(gpu, REG_AXXX_SCRATCH_UMSK, 0x1);
111
112 return 0;
113}
114
115static uint32_t get_wptr(struct msm_ringbuffer *ring)
116{
117 return ring->cur - ring->start;
118}
119
120uint32_t adreno_last_fence(struct msm_gpu *gpu)
121{
122 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
123 return adreno_gpu->memptrs->fence;
124}
125
126void adreno_recover(struct msm_gpu *gpu)
127{
128 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
129 struct drm_device *dev = gpu->dev;
130 int ret;
131
132 gpu->funcs->pm_suspend(gpu);
133
134 /* reset ringbuffer: */
135 gpu->rb->cur = gpu->rb->start;
136
137 /* reset completed fence seqno, just discard anything pending: */
138 adreno_gpu->memptrs->fence = gpu->submitted_fence;
139 adreno_gpu->memptrs->rptr = 0;
140 adreno_gpu->memptrs->wptr = 0;
141
142 gpu->funcs->pm_resume(gpu);
143 ret = gpu->funcs->hw_init(gpu);
144 if (ret) {
145 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
146 /* hmm, oh well? */
147 }
148}
149
150int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
151 struct msm_file_private *ctx)
152{
153 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
154 struct msm_drm_private *priv = gpu->dev->dev_private;
155 struct msm_ringbuffer *ring = gpu->rb;
156 unsigned i, ibs = 0;
157
158 for (i = 0; i < submit->nr_cmds; i++) {
159 switch (submit->cmd[i].type) {
160 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
161 /* ignore IB-targets */
162 break;
163 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
164 /* ignore if there has not been a ctx switch: */
165 if (priv->lastctx == ctx)
166 break;
167 case MSM_SUBMIT_CMD_BUF:
168 OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
169 OUT_RING(ring, submit->cmd[i].iova);
170 OUT_RING(ring, submit->cmd[i].size);
171 ibs++;
172 break;
173 }
174 }
175
176 /* on a320, at least, we seem to need to pad things out to an
177 * even number of qwords to avoid issue w/ CP hanging on wrap-
178 * around:
179 */
180 if (ibs % 2)
181 OUT_PKT2(ring);
182
183 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
184 OUT_RING(ring, submit->fence);
185
186 if (adreno_is_a3xx(adreno_gpu)) {
187 /* Flush HLSQ lazy updates to make sure there is nothing
188 * pending for indirect loads after the timestamp has
189 * passed:
190 */
191 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
192 OUT_RING(ring, HLSQ_FLUSH);
193
194 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
195 OUT_RING(ring, 0x00000000);
196 }
197
198 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
199 OUT_RING(ring, CACHE_FLUSH_TS);
200 OUT_RING(ring, rbmemptr(adreno_gpu, fence));
201 OUT_RING(ring, submit->fence);
202
203 /* we could maybe be clever and only CP_COND_EXEC the interrupt: */
204 OUT_PKT3(ring, CP_INTERRUPT, 1);
205 OUT_RING(ring, 0x80000000);
206
207#if 0
208 if (adreno_is_a3xx(adreno_gpu)) {
209 /* Dummy set-constant to trigger context rollover */
210 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
211 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
212 OUT_RING(ring, 0x00000000);
213 }
214#endif
215
216 gpu->funcs->flush(gpu);
217
218 return 0;
219}
220
221void adreno_flush(struct msm_gpu *gpu)
222{
223 uint32_t wptr = get_wptr(gpu->rb);
224
225 /* ensure writes to ringbuffer have hit system memory: */
226 mb();
227
228 gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr);
229}
230
231void adreno_idle(struct msm_gpu *gpu)
232{
233 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
234 uint32_t wptr = get_wptr(gpu->rb);
235
236 /* wait for CP to drain ringbuffer: */
237 if (spin_until(adreno_gpu->memptrs->rptr == wptr))
238 DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
239
240 /* TODO maybe we need to reset GPU here to recover from hang? */
241}
242
243#ifdef CONFIG_DEBUG_FS
244void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
245{
246 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
247
248 seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
249 adreno_gpu->info->revn, adreno_gpu->rev.core,
250 adreno_gpu->rev.major, adreno_gpu->rev.minor,
251 adreno_gpu->rev.patchid);
252
253 seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence,
254 gpu->submitted_fence);
255 seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr);
256 seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
257 seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
258}
259#endif
260
261/* would be nice to not have to duplicate the _show() stuff with printk(): */
262void adreno_dump(struct msm_gpu *gpu)
263{
264 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
265
266 printk("revision: %d (%d.%d.%d.%d)\n",
267 adreno_gpu->info->revn, adreno_gpu->rev.core,
268 adreno_gpu->rev.major, adreno_gpu->rev.minor,
269 adreno_gpu->rev.patchid);
270
271 printk("fence: %d/%d\n", adreno_gpu->memptrs->fence,
272 gpu->submitted_fence);
273 printk("rptr: %d\n", adreno_gpu->memptrs->rptr);
274 printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
275 printk("rb wptr: %d\n", get_wptr(gpu->rb));
276
277}
278
279static uint32_t ring_freewords(struct msm_gpu *gpu)
280{
281 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
282 uint32_t size = gpu->rb->size / 4;
283 uint32_t wptr = get_wptr(gpu->rb);
284 uint32_t rptr = adreno_gpu->memptrs->rptr;
285 return (rptr + (size - 1) - wptr) % size;
286}
287
288void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
289{
290 if (spin_until(ring_freewords(gpu) >= ndwords))
291 DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
292}
293
294static const char *iommu_ports[] = {
295 "gfx3d_user", "gfx3d_priv",
296 "gfx3d1_user", "gfx3d1_priv",
297};
298
299static inline bool _rev_match(uint8_t entry, uint8_t id)
300{
301 return (entry == ANY_ID) || (entry == id);
302}
303
304int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
305 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
306 struct adreno_rev rev)
307{
308 struct msm_mmu *mmu;
309 int i, ret;
310
311 /* identify gpu: */
312 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
313 const struct adreno_info *info = &gpulist[i];
314 if (_rev_match(info->rev.core, rev.core) &&
315 _rev_match(info->rev.major, rev.major) &&
316 _rev_match(info->rev.minor, rev.minor) &&
317 _rev_match(info->rev.patchid, rev.patchid)) {
318 gpu->info = info;
319 gpu->revn = info->revn;
320 break;
321 }
322 }
323
324 if (i == ARRAY_SIZE(gpulist)) {
325 dev_err(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
326 rev.core, rev.major, rev.minor, rev.patchid);
327 return -ENXIO;
328 }
329
330 DBG("Found GPU: %s (%u.%u.%u.%u)", gpu->info->name,
331 rev.core, rev.major, rev.minor, rev.patchid);
332
333 gpu->funcs = funcs;
334 gpu->gmem = gpu->info->gmem;
335 gpu->rev = rev;
336
337 ret = request_firmware(&gpu->pm4, gpu->info->pm4fw, drm->dev);
338 if (ret) {
339 dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
340 gpu->info->pm4fw, ret);
341 return ret;
342 }
343
344 ret = request_firmware(&gpu->pfp, gpu->info->pfpfw, drm->dev);
345 if (ret) {
346 dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
347 gpu->info->pfpfw, ret);
348 return ret;
349 }
350
351 ret = msm_gpu_init(drm, pdev, &gpu->base, &funcs->base,
352 gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
353 RB_SIZE);
354 if (ret)
355 return ret;
356
357 mmu = gpu->base.mmu;
358 if (mmu) {
359 ret = mmu->funcs->attach(mmu, iommu_ports,
360 ARRAY_SIZE(iommu_ports));
361 if (ret)
362 return ret;
363 }
364
365 gpu->memptrs_bo = msm_gem_new(drm, sizeof(*gpu->memptrs),
366 MSM_BO_UNCACHED);
367 if (IS_ERR(gpu->memptrs_bo)) {
368 ret = PTR_ERR(gpu->memptrs_bo);
369 gpu->memptrs_bo = NULL;
370 dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
371 return ret;
372 }
373
374 gpu->memptrs = msm_gem_vaddr_locked(gpu->memptrs_bo);
375 if (!gpu->memptrs) {
376 dev_err(drm->dev, "could not vmap memptrs\n");
377 return -ENOMEM;
378 }
379
380 ret = msm_gem_get_iova_locked(gpu->memptrs_bo, gpu->base.id,
381 &gpu->memptrs_iova);
382 if (ret) {
383 dev_err(drm->dev, "could not map memptrs: %d\n", ret);
384 return ret;
385 }
386
387 return 0;
388}
389
390void adreno_gpu_cleanup(struct adreno_gpu *gpu)
391{
392 if (gpu->memptrs_bo) {
393 if (gpu->memptrs_iova)
394 msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
395 drm_gem_object_unreference(gpu->memptrs_bo);
396 }
397 if (gpu->pm4)
398 release_firmware(gpu->pm4);
399 if (gpu->pfp)
400 release_firmware(gpu->pfp);
401 msm_gpu_cleanup(&gpu->base);
402}