1/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
   2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3 *
   4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6 * All Rights Reserved.
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a
   9 * copy of this software and associated documentation files (the "Software"),
  10 * to deal in the Software without restriction, including without limitation
  11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12 * and/or sell copies of the Software, and to permit persons to whom the
  13 * Software is furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice (including the next
  16 * paragraph) shall be included in all copies or substantial portions of the
  17 * Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25 * DEALINGS IN THE SOFTWARE.
  26 */
  27
  28/**
  29 * \file mga_dma.c
  30 * DMA support for MGA G200 / G400.
  31 *
  32 * \author Rickard E. (Rik) Faith <faith@valinux.com>
  33 * \author Jeff Hartmann <jhartmann@valinux.com>
  34 * \author Keith Whitwell <keith@tungstengraphics.com>
  35 * \author Gareth Hughes <gareth@valinux.com>
  36 */
  37
  38#include <drm/drmP.h>
  39#include <drm/mga_drm.h>
  40#include "mga_drv.h"
  41
  42#define MGA_DEFAULT_USEC_TIMEOUT	10000
  43#define MGA_FREELIST_DEBUG		0
  44
  45#define MINIMAL_CLEANUP 0
  46#define FULL_CLEANUP 1
  47static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
  48
  49/* ================================================================
  50 * Engine control
  51 */
  52
  53int mga_do_wait_for_idle(drm_mga_private_t *dev_priv)
  54{
  55	u32 status = 0;
  56	int i;
  57	DRM_DEBUG("\n");
  58
  59	for (i = 0; i < dev_priv->usec_timeout; i++) {
  60		status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
  61		if (status == MGA_ENDPRDMASTS) {
  62			MGA_WRITE8(MGA_CRTC_INDEX, 0);
  63			return 0;
  64		}
  65		DRM_UDELAY(1);
  66	}
  67
  68#if MGA_DMA_DEBUG
  69	DRM_ERROR("failed!\n");
  70	DRM_INFO("   status=0x%08x\n", status);
  71#endif
  72	return -EBUSY;
  73}
  74
  75static int mga_do_dma_reset(drm_mga_private_t *dev_priv)
  76{
  77	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  78	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
  79
  80	DRM_DEBUG("\n");
  81
  82	/* The primary DMA stream should look like new right about now.
  83	 */
  84	primary->tail = 0;
  85	primary->space = primary->size;
  86	primary->last_flush = 0;
  87
  88	sarea_priv->last_wrap = 0;
  89
  90	/* FIXME: Reset counters, buffer ages etc...
  91	 */
  92
  93	/* FIXME: What else do we need to reinitialize?  WARP stuff?
  94	 */
  95
  96	return 0;
  97}
  98
  99/* ================================================================
 100 * Primary DMA stream
 101 */
 102
 103void mga_do_dma_flush(drm_mga_private_t *dev_priv)
 104{
 105	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 106	u32 head, tail;
 107	u32 status = 0;
 108	int i;
 109	DMA_LOCALS;
 110	DRM_DEBUG("\n");
 111
 112	/* We need to wait so that we can do an safe flush */
 113	for (i = 0; i < dev_priv->usec_timeout; i++) {
 114		status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
 115		if (status == MGA_ENDPRDMASTS)
 116			break;
 117		DRM_UDELAY(1);
 118	}
 119
 120	if (primary->tail == primary->last_flush) {
 121		DRM_DEBUG("   bailing out...\n");
 122		return;
 123	}
 124
 125	tail = primary->tail + dev_priv->primary->offset;
 126
 127	/* We need to pad the stream between flushes, as the card
 128	 * actually (partially?) reads the first of these commands.
 129	 * See page 4-16 in the G400 manual, middle of the page or so.
 130	 */
 131	BEGIN_DMA(1);
 132
 133	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 134		  MGA_DMAPAD, 0x00000000,
 135		  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 136
 137	ADVANCE_DMA();
 138
 139	primary->last_flush = primary->tail;
 140
 141	head = MGA_READ(MGA_PRIMADDRESS);
 142
 143	if (head <= tail)
 144		primary->space = primary->size - primary->tail;
 145	else
 146		primary->space = head - tail;
 147
 148	DRM_DEBUG("   head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset));
 149	DRM_DEBUG("   tail = 0x%06lx\n", (unsigned long)(tail - dev_priv->primary->offset));
 150	DRM_DEBUG("  space = 0x%06x\n", primary->space);
 151
 152	mga_flush_write_combine();
 153	MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
 154
 155	DRM_DEBUG("done.\n");
 156}
 157
 158void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv)
 159{
 160	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 161	u32 head, tail;
 162	DMA_LOCALS;
 163	DRM_DEBUG("\n");
 164
 165	BEGIN_DMA_WRAP();
 166
 167	DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 168		  MGA_DMAPAD, 0x00000000,
 169		  MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 170
 171	ADVANCE_DMA();
 172
 173	tail = primary->tail + dev_priv->primary->offset;
 174
 175	primary->tail = 0;
 176	primary->last_flush = 0;
 177	primary->last_wrap++;
 178
 179	head = MGA_READ(MGA_PRIMADDRESS);
 180
 181	if (head == dev_priv->primary->offset)
 182		primary->space = primary->size;
 183	else
 184		primary->space = head - dev_priv->primary->offset;
 185
 186	DRM_DEBUG("   head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset));
 187	DRM_DEBUG("   tail = 0x%06x\n", primary->tail);
 188	DRM_DEBUG("   wrap = %d\n", primary->last_wrap);
 189	DRM_DEBUG("  space = 0x%06x\n", primary->space);
 190
 191	mga_flush_write_combine();
 192	MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
 193
 194	set_bit(0, &primary->wrapped);
 195	DRM_DEBUG("done.\n");
 196}
 197
 198void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv)
 199{
 200	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 201	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 202	u32 head = dev_priv->primary->offset;
 203	DRM_DEBUG("\n");
 204
 205	sarea_priv->last_wrap++;
 206	DRM_DEBUG("   wrap = %d\n", sarea_priv->last_wrap);
 207
 208	mga_flush_write_combine();
 209	MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
 210
 211	clear_bit(0, &primary->wrapped);
 212	DRM_DEBUG("done.\n");
 213}
 214
 215/* ================================================================
 216 * Freelist management
 217 */
 218
 219#define MGA_BUFFER_USED		(~0)
 220#define MGA_BUFFER_FREE		0
 221
 222#if MGA_FREELIST_DEBUG
 223static void mga_freelist_print(struct drm_device *dev)
 224{
 225	drm_mga_private_t *dev_priv = dev->dev_private;
 226	drm_mga_freelist_t *entry;
 227
 228	DRM_INFO("\n");
 229	DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
 230		 dev_priv->sarea_priv->last_dispatch,
 231		 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
 232				dev_priv->primary->offset));
 233	DRM_INFO("current freelist:\n");
 234
 235	for (entry = dev_priv->head->next; entry; entry = entry->next) {
 236		DRM_INFO("   %p   idx=%2d  age=0x%x 0x%06lx\n",
 237			 entry, entry->buf->idx, entry->age.head,
 238			 (unsigned long)(entry->age.head - dev_priv->primary->offset));
 239	}
 240	DRM_INFO("\n");
 241}
 242#endif
 243
 244static int mga_freelist_init(struct drm_device *dev, drm_mga_private_t *dev_priv)
 245{
 246	struct drm_device_dma *dma = dev->dma;
 247	struct drm_buf *buf;
 248	drm_mga_buf_priv_t *buf_priv;
 249	drm_mga_freelist_t *entry;
 250	int i;
 251	DRM_DEBUG("count=%d\n", dma->buf_count);
 252
 253	dev_priv->head = kzalloc(sizeof(drm_mga_freelist_t), GFP_KERNEL);
 254	if (dev_priv->head == NULL)
 255		return -ENOMEM;
 256
 257	SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
 258
 259	for (i = 0; i < dma->buf_count; i++) {
 260		buf = dma->buflist[i];
 261		buf_priv = buf->dev_private;
 262
 263		entry = kzalloc(sizeof(drm_mga_freelist_t), GFP_KERNEL);
 264		if (entry == NULL)
 265			return -ENOMEM;
 266
 267		entry->next = dev_priv->head->next;
 268		entry->prev = dev_priv->head;
 269		SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 270		entry->buf = buf;
 271
 272		if (dev_priv->head->next != NULL)
 273			dev_priv->head->next->prev = entry;
 274		if (entry->next == NULL)
 275			dev_priv->tail = entry;
 276
 277		buf_priv->list_entry = entry;
 278		buf_priv->discard = 0;
 279		buf_priv->dispatched = 0;
 280
 281		dev_priv->head->next = entry;
 282	}
 283
 284	return 0;
 285}
 286
 287static void mga_freelist_cleanup(struct drm_device *dev)
 288{
 289	drm_mga_private_t *dev_priv = dev->dev_private;
 290	drm_mga_freelist_t *entry;
 291	drm_mga_freelist_t *next;
 292	DRM_DEBUG("\n");
 293
 294	entry = dev_priv->head;
 295	while (entry) {
 296		next = entry->next;
 297		kfree(entry);
 298		entry = next;
 299	}
 300
 301	dev_priv->head = dev_priv->tail = NULL;
 302}
 303
 304#if 0
 305/* FIXME: Still needed?
 306 */
 307static void mga_freelist_reset(struct drm_device *dev)
 308{
 309	struct drm_device_dma *dma = dev->dma;
 310	struct drm_buf *buf;
 311	drm_mga_buf_priv_t *buf_priv;
 312	int i;
 313
 314	for (i = 0; i < dma->buf_count; i++) {
 315		buf = dma->buflist[i];
 316		buf_priv = buf->dev_private;
 317		SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
 318	}
 319}
 320#endif
 321
 322static struct drm_buf *mga_freelist_get(struct drm_device * dev)
 323{
 324	drm_mga_private_t *dev_priv = dev->dev_private;
 325	drm_mga_freelist_t *next;
 326	drm_mga_freelist_t *prev;
 327	drm_mga_freelist_t *tail = dev_priv->tail;
 328	u32 head, wrap;
 329	DRM_DEBUG("\n");
 330
 331	head = MGA_READ(MGA_PRIMADDRESS);
 332	wrap = dev_priv->sarea_priv->last_wrap;
 333
 334	DRM_DEBUG("   tail=0x%06lx %d\n",
 335		  tail->age.head ?
 336		  (unsigned long)(tail->age.head - dev_priv->primary->offset) : 0,
 337		  tail->age.wrap);
 338	DRM_DEBUG("   head=0x%06lx %d\n",
 339		  (unsigned long)(head - dev_priv->primary->offset), wrap);
 340
 341	if (TEST_AGE(&tail->age, head, wrap)) {
 342		prev = dev_priv->tail->prev;
 343		next = dev_priv->tail;
 344		prev->next = NULL;
 345		next->prev = next->next = NULL;
 346		dev_priv->tail = prev;
 347		SET_AGE(&next->age, MGA_BUFFER_USED, 0);
 348		return next->buf;
 349	}
 350
 351	DRM_DEBUG("returning NULL!\n");
 352	return NULL;
 353}
 354
 355int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf)
 356{
 357	drm_mga_private_t *dev_priv = dev->dev_private;
 358	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 359	drm_mga_freelist_t *head, *entry, *prev;
 360
 361	DRM_DEBUG("age=0x%06lx wrap=%d\n",
 362		  (unsigned long)(buf_priv->list_entry->age.head -
 363				  dev_priv->primary->offset),
 364		  buf_priv->list_entry->age.wrap);
 365
 366	entry = buf_priv->list_entry;
 367	head = dev_priv->head;
 368
 369	if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
 370		SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 371		prev = dev_priv->tail;
 372		prev->next = entry;
 373		entry->prev = prev;
 374		entry->next = NULL;
 375	} else {
 376		prev = head->next;
 377		head->next = entry;
 378		prev->prev = entry;
 379		entry->prev = head;
 380		entry->next = prev;
 381	}
 382
 383	return 0;
 384}
 385
 386/* ================================================================
 387 * DMA initialization, cleanup
 388 */
 389
 390int mga_driver_load(struct drm_device *dev, unsigned long flags)
 391{
 392	drm_mga_private_t *dev_priv;
 393	int ret;
 394
 395	dev_priv = kzalloc(sizeof(drm_mga_private_t), GFP_KERNEL);
 396	if (!dev_priv)
 397		return -ENOMEM;
 398
 399	dev->dev_private = (void *)dev_priv;
 400
 401	dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
 402	dev_priv->chipset = flags;
 403
 404	pci_set_master(dev->pdev);
 405
 406	dev_priv->mmio_base = pci_resource_start(dev->pdev, 1);
 407	dev_priv->mmio_size = pci_resource_len(dev->pdev, 1);
 408
 409	ret = drm_vblank_init(dev, 1);
 410
 411	if (ret) {
 412		(void) mga_driver_unload(dev);
 413		return ret;
 414	}
 415
 416	return 0;
 417}
 418
 419#if IS_ENABLED(CONFIG_AGP)
 420/**
 421 * Bootstrap the driver for AGP DMA.
 422 *
 423 * \todo
 424 * Investigate whether there is any benefit to storing the WARP microcode in
 425 * AGP memory.  If not, the microcode may as well always be put in PCI
 426 * memory.
 427 *
 428 * \todo
 429 * This routine needs to set dma_bs->agp_mode to the mode actually configured
 430 * in the hardware.  Looking just at the Linux AGP driver code, I don't see
 431 * an easy way to determine this.
 432 *
 433 * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
 434 */
 435static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
 436				    drm_mga_dma_bootstrap_t *dma_bs)
 437{
 438	drm_mga_private_t *const dev_priv =
 439	    (drm_mga_private_t *) dev->dev_private;
 440	unsigned int warp_size = MGA_WARP_UCODE_SIZE;
 441	int err;
 442	unsigned offset;
 443	const unsigned secondary_size = dma_bs->secondary_bin_count
 444	    * dma_bs->secondary_bin_size;
 445	const unsigned agp_size = (dma_bs->agp_size << 20);
 446	struct drm_buf_desc req;
 447	struct drm_agp_mode mode;
 448	struct drm_agp_info info;
 449	struct drm_agp_buffer agp_req;
 450	struct drm_agp_binding bind_req;
 451
 452	/* Acquire AGP. */
 453	err = drm_agp_acquire(dev);
 454	if (err) {
 455		DRM_ERROR("Unable to acquire AGP: %d\n", err);
 456		return err;
 457	}
 458
 459	err = drm_agp_info(dev, &info);
 460	if (err) {
 461		DRM_ERROR("Unable to get AGP info: %d\n", err);
 462		return err;
 463	}
 464
 465	mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
 466	err = drm_agp_enable(dev, mode);
 467	if (err) {
 468		DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
 469		return err;
 470	}
 471
 472	/* In addition to the usual AGP mode configuration, the G200 AGP cards
 473	 * need to have the AGP mode "manually" set.
 474	 */
 475
 476	if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
 477		if (mode.mode & 0x02)
 478			MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
 479		else
 480			MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
 481	}
 482
 483	/* Allocate and bind AGP memory. */
 484	agp_req.size = agp_size;
 485	agp_req.type = 0;
 486	err = drm_agp_alloc(dev, &agp_req);
 487	if (err) {
 488		dev_priv->agp_size = 0;
 489		DRM_ERROR("Unable to allocate %uMB AGP memory\n",
 490			  dma_bs->agp_size);
 491		return err;
 492	}
 493
 494	dev_priv->agp_size = agp_size;
 495	dev_priv->agp_handle = agp_req.handle;
 496
 497	bind_req.handle = agp_req.handle;
 498	bind_req.offset = 0;
 499	err = drm_agp_bind(dev, &bind_req);
 500	if (err) {
 501		DRM_ERROR("Unable to bind AGP memory: %d\n", err);
 502		return err;
 503	}
 504
 505	/* Make drm_legacy_addbufs happy by not trying to create a mapping for
 506	 * less than a page.
 507	 */
 508	if (warp_size < PAGE_SIZE)
 509		warp_size = PAGE_SIZE;
 510
 511	offset = 0;
 512	err = drm_legacy_addmap(dev, offset, warp_size,
 513				_DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
 514	if (err) {
 515		DRM_ERROR("Unable to map WARP microcode: %d\n", err);
 516		return err;
 517	}
 518
 519	offset += warp_size;
 520	err = drm_legacy_addmap(dev, offset, dma_bs->primary_size,
 521				_DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary);
 522	if (err) {
 523		DRM_ERROR("Unable to map primary DMA region: %d\n", err);
 524		return err;
 525	}
 526
 527	offset += dma_bs->primary_size;
 528	err = drm_legacy_addmap(dev, offset, secondary_size,
 529				_DRM_AGP, 0, &dev->agp_buffer_map);
 530	if (err) {
 531		DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
 532		return err;
 533	}
 534
 535	(void)memset(&req, 0, sizeof(req));
 536	req.count = dma_bs->secondary_bin_count;
 537	req.size = dma_bs->secondary_bin_size;
 538	req.flags = _DRM_AGP_BUFFER;
 539	req.agp_start = offset;
 540
 541	err = drm_legacy_addbufs_agp(dev, &req);
 542	if (err) {
 543		DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
 544		return err;
 545	}
 546
 547	{
 548		struct drm_map_list *_entry;
 549		unsigned long agp_token = 0;
 550
 551		list_for_each_entry(_entry, &dev->maplist, head) {
 552			if (_entry->map == dev->agp_buffer_map)
 553				agp_token = _entry->user_token;
 554		}
 555		if (!agp_token)
 556			return -EFAULT;
 557
 558		dev->agp_buffer_token = agp_token;
 559	}
 560
 561	offset += secondary_size;
 562	err = drm_legacy_addmap(dev, offset, agp_size - offset,
 563				_DRM_AGP, 0, &dev_priv->agp_textures);
 564	if (err) {
 565		DRM_ERROR("Unable to map AGP texture region %d\n", err);
 566		return err;
 567	}
 568
 569	drm_legacy_ioremap(dev_priv->warp, dev);
 570	drm_legacy_ioremap(dev_priv->primary, dev);
 571	drm_legacy_ioremap(dev->agp_buffer_map, dev);
 572
 573	if (!dev_priv->warp->handle ||
 574	    !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
 575		DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
 576			  dev_priv->warp->handle, dev_priv->primary->handle,
 577			  dev->agp_buffer_map->handle);
 578		return -ENOMEM;
 579	}
 580
 581	dev_priv->dma_access = MGA_PAGPXFER;
 582	dev_priv->wagp_enable = MGA_WAGP_ENABLE;
 583
 584	DRM_INFO("Initialized card for AGP DMA.\n");
 585	return 0;
 586}
 587#else
 588static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
 589				    drm_mga_dma_bootstrap_t *dma_bs)
 590{
 591	return -EINVAL;
 592}
 593#endif
 594
 595/**
 596 * Bootstrap the driver for PCI DMA.
 597 *
 598 * \todo
 599 * The algorithm for decreasing the size of the primary DMA buffer could be
 600 * better.  The size should be rounded up to the nearest page size, then
 601 * decrease the request size by a single page each pass through the loop.
 602 *
 603 * \todo
 604 * Determine whether the maximum address passed to drm_pci_alloc is correct.
 605 * The same goes for drm_legacy_addbufs_pci.
 606 *
 607 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
 608 */
 609static int mga_do_pci_dma_bootstrap(struct drm_device *dev,
 610				    drm_mga_dma_bootstrap_t *dma_bs)
 611{
 612	drm_mga_private_t *const dev_priv =
 613	    (drm_mga_private_t *) dev->dev_private;
 614	unsigned int warp_size = MGA_WARP_UCODE_SIZE;
 615	unsigned int primary_size;
 616	unsigned int bin_count;
 617	int err;
 618	struct drm_buf_desc req;
 619
 620	if (dev->dma == NULL) {
 621		DRM_ERROR("dev->dma is NULL\n");
 622		return -EFAULT;
 623	}
 624
 625	/* Make drm_legacy_addbufs happy by not trying to create a mapping for
 626	 * less than a page.
 627	 */
 628	if (warp_size < PAGE_SIZE)
 629		warp_size = PAGE_SIZE;
 630
 631	/* The proper alignment is 0x100 for this mapping */
 632	err = drm_legacy_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
 633				_DRM_READ_ONLY, &dev_priv->warp);
 634	if (err != 0) {
 635		DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
 636			  err);
 637		return err;
 638	}
 639
 640	/* Other than the bottom two bits being used to encode other
 641	 * information, there don't appear to be any restrictions on the
 642	 * alignment of the primary or secondary DMA buffers.
 643	 */
 644
 645	for (primary_size = dma_bs->primary_size; primary_size != 0;
 646	     primary_size >>= 1) {
 647		/* The proper alignment for this mapping is 0x04 */
 648		err = drm_legacy_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
 649					_DRM_READ_ONLY, &dev_priv->primary);
 650		if (!err)
 651			break;
 652	}
 653
 654	if (err != 0) {
 655		DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
 656		return -ENOMEM;
 657	}
 658
 659	if (dev_priv->primary->size != dma_bs->primary_size) {
 660		DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
 661			 dma_bs->primary_size,
 662			 (unsigned)dev_priv->primary->size);
 663		dma_bs->primary_size = dev_priv->primary->size;
 664	}
 665
 666	for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
 667	     bin_count--) {
 668		(void)memset(&req, 0, sizeof(req));
 669		req.count = bin_count;
 670		req.size = dma_bs->secondary_bin_size;
 671
 672		err = drm_legacy_addbufs_pci(dev, &req);
 673		if (!err)
 674			break;
 675	}
 676
 677	if (bin_count == 0) {
 678		DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
 679		return err;
 680	}
 681
 682	if (bin_count != dma_bs->secondary_bin_count) {
 683		DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
 684			 "to %u.\n", dma_bs->secondary_bin_count, bin_count);
 685
 686		dma_bs->secondary_bin_count = bin_count;
 687	}
 688
 689	dev_priv->dma_access = 0;
 690	dev_priv->wagp_enable = 0;
 691
 692	dma_bs->agp_mode = 0;
 693
 694	DRM_INFO("Initialized card for PCI DMA.\n");
 695	return 0;
 696}
 697
 698static int mga_do_dma_bootstrap(struct drm_device *dev,
 699				drm_mga_dma_bootstrap_t *dma_bs)
 700{
 701	const int is_agp = (dma_bs->agp_mode != 0) && drm_pci_device_is_agp(dev);
 702	int err;
 703	drm_mga_private_t *const dev_priv =
 704	    (drm_mga_private_t *) dev->dev_private;
 705
 706	dev_priv->used_new_dma_init = 1;
 707
 708	/* The first steps are the same for both PCI and AGP based DMA.  Map
 709	 * the cards MMIO registers and map a status page.
 710	 */
 711	err = drm_legacy_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
 712				_DRM_REGISTERS, _DRM_READ_ONLY,
 713				&dev_priv->mmio);
 714	if (err) {
 715		DRM_ERROR("Unable to map MMIO region: %d\n", err);
 716		return err;
 717	}
 718
 719	err = drm_legacy_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
 720				_DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
 721			 &dev_priv->status);
 722	if (err) {
 723		DRM_ERROR("Unable to map status region: %d\n", err);
 724		return err;
 725	}
 726
 727	/* The DMA initialization procedure is slightly different for PCI and
 728	 * AGP cards.  AGP cards just allocate a large block of AGP memory and
 729	 * carve off portions of it for internal uses.  The remaining memory
 730	 * is returned to user-mode to be used for AGP textures.
 731	 */
 732	if (is_agp)
 733		err = mga_do_agp_dma_bootstrap(dev, dma_bs);
 734
 735	/* If we attempted to initialize the card for AGP DMA but failed,
 736	 * clean-up any mess that may have been created.
 737	 */
 738
 739	if (err)
 740		mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
 741
 742	/* Not only do we want to try and initialized PCI cards for PCI DMA,
 743	 * but we also try to initialized AGP cards that could not be
 744	 * initialized for AGP DMA.  This covers the case where we have an AGP
 745	 * card in a system with an unsupported AGP chipset.  In that case the
 746	 * card will be detected as AGP, but we won't be able to allocate any
 747	 * AGP memory, etc.
 748	 */
 749
 750	if (!is_agp || err)
 751		err = mga_do_pci_dma_bootstrap(dev, dma_bs);
 752
 753	return err;
 754}
 755
 756int mga_dma_bootstrap(struct drm_device *dev, void *data,
 757		      struct drm_file *file_priv)
 758{
 759	drm_mga_dma_bootstrap_t *bootstrap = data;
 760	int err;
 761	static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
 762	const drm_mga_private_t *const dev_priv =
 763		(drm_mga_private_t *) dev->dev_private;
 764
 765	err = mga_do_dma_bootstrap(dev, bootstrap);
 766	if (err) {
 767		mga_do_cleanup_dma(dev, FULL_CLEANUP);
 768		return err;
 769	}
 770
 771	if (dev_priv->agp_textures != NULL) {
 772		bootstrap->texture_handle = dev_priv->agp_textures->offset;
 773		bootstrap->texture_size = dev_priv->agp_textures->size;
 774	} else {
 775		bootstrap->texture_handle = 0;
 776		bootstrap->texture_size = 0;
 777	}
 778
 779	bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
 780
 781	return err;
 782}
 783
 784static int mga_do_init_dma(struct drm_device *dev, drm_mga_init_t *init)
 785{
 786	drm_mga_private_t *dev_priv;
 787	int ret;
 788	DRM_DEBUG("\n");
 789
 790	dev_priv = dev->dev_private;
 791
 792	if (init->sgram)
 793		dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
 794	else
 795		dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
 796	dev_priv->maccess = init->maccess;
 797
 798	dev_priv->fb_cpp = init->fb_cpp;
 799	dev_priv->front_offset = init->front_offset;
 800	dev_priv->front_pitch = init->front_pitch;
 801	dev_priv->back_offset = init->back_offset;
 802	dev_priv->back_pitch = init->back_pitch;
 803
 804	dev_priv->depth_cpp = init->depth_cpp;
 805	dev_priv->depth_offset = init->depth_offset;
 806	dev_priv->depth_pitch = init->depth_pitch;
 807
 808	/* FIXME: Need to support AGP textures...
 809	 */
 810	dev_priv->texture_offset = init->texture_offset[0];
 811	dev_priv->texture_size = init->texture_size[0];
 812
 813	dev_priv->sarea = drm_legacy_getsarea(dev);
 814	if (!dev_priv->sarea) {
 815		DRM_ERROR("failed to find sarea!\n");
 816		return -EINVAL;
 817	}
 818
 819	if (!dev_priv->used_new_dma_init) {
 820
 821		dev_priv->dma_access = MGA_PAGPXFER;
 822		dev_priv->wagp_enable = MGA_WAGP_ENABLE;
 823
 824		dev_priv->status = drm_legacy_findmap(dev, init->status_offset);
 825		if (!dev_priv->status) {
 826			DRM_ERROR("failed to find status page!\n");
 827			return -EINVAL;
 828		}
 829		dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset);
 830		if (!dev_priv->mmio) {
 831			DRM_ERROR("failed to find mmio region!\n");
 832			return -EINVAL;
 833		}
 834		dev_priv->warp = drm_legacy_findmap(dev, init->warp_offset);
 835		if (!dev_priv->warp) {
 836			DRM_ERROR("failed to find warp microcode region!\n");
 837			return -EINVAL;
 838		}
 839		dev_priv->primary = drm_legacy_findmap(dev, init->primary_offset);
 840		if (!dev_priv->primary) {
 841			DRM_ERROR("failed to find primary dma region!\n");
 842			return -EINVAL;
 843		}
 844		dev->agp_buffer_token = init->buffers_offset;
 845		dev->agp_buffer_map =
 846		    drm_legacy_findmap(dev, init->buffers_offset);
 847		if (!dev->agp_buffer_map) {
 848			DRM_ERROR("failed to find dma buffer region!\n");
 849			return -EINVAL;
 850		}
 851
 852		drm_legacy_ioremap(dev_priv->warp, dev);
 853		drm_legacy_ioremap(dev_priv->primary, dev);
 854		drm_legacy_ioremap(dev->agp_buffer_map, dev);
 855	}
 856
 857	dev_priv->sarea_priv =
 858	    (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 859				 init->sarea_priv_offset);
 860
 861	if (!dev_priv->warp->handle ||
 862	    !dev_priv->primary->handle ||
 863	    ((dev_priv->dma_access != 0) &&
 864	     ((dev->agp_buffer_map == NULL) ||
 865	      (dev->agp_buffer_map->handle == NULL)))) {
 866		DRM_ERROR("failed to ioremap agp regions!\n");
 867		return -ENOMEM;
 868	}
 869
 870	ret = mga_warp_install_microcode(dev_priv);
 871	if (ret < 0) {
 872		DRM_ERROR("failed to install WARP ucode!: %d\n", ret);
 873		return ret;
 874	}
 875
 876	ret = mga_warp_init(dev_priv);
 877	if (ret < 0) {
 878		DRM_ERROR("failed to init WARP engine!: %d\n", ret);
 879		return ret;
 880	}
 881
 882	dev_priv->prim.status = (u32 *) dev_priv->status->handle;
 883
 884	mga_do_wait_for_idle(dev_priv);
 885
 886	/* Init the primary DMA registers.
 887	 */
 888	MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
 889#if 0
 890	MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 |	/* Soft trap, SECEND, SETUPEND */
 891		  MGA_PRIMPTREN1);	/* DWGSYNC */
 892#endif
 893
 894	dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
 895	dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
 896			      + dev_priv->primary->size);
 897	dev_priv->prim.size = dev_priv->primary->size;
 898
 899	dev_priv->prim.tail = 0;
 900	dev_priv->prim.space = dev_priv->prim.size;
 901	dev_priv->prim.wrapped = 0;
 902
 903	dev_priv->prim.last_flush = 0;
 904	dev_priv->prim.last_wrap = 0;
 905
 906	dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
 907
 908	dev_priv->prim.status[0] = dev_priv->primary->offset;
 909	dev_priv->prim.status[1] = 0;
 910
 911	dev_priv->sarea_priv->last_wrap = 0;
 912	dev_priv->sarea_priv->last_frame.head = 0;
 913	dev_priv->sarea_priv->last_frame.wrap = 0;
 914
 915	if (mga_freelist_init(dev, dev_priv) < 0) {
 916		DRM_ERROR("could not initialize freelist\n");
 917		return -ENOMEM;
 918	}
 919
 920	return 0;
 921}
 922
 923static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
 924{
 925	int err = 0;
 926	DRM_DEBUG("\n");
 927
 928	/* Make sure interrupts are disabled here because the uninstall ioctl
 929	 * may not have been called from userspace and after dev_private
 930	 * is freed, it's too late.
 931	 */
 932	if (dev->irq_enabled)
 933		drm_irq_uninstall(dev);
 934
 935	if (dev->dev_private) {
 936		drm_mga_private_t *dev_priv = dev->dev_private;
 937
 938		if ((dev_priv->warp != NULL)
 939		    && (dev_priv->warp->type != _DRM_CONSISTENT))
 940			drm_legacy_ioremapfree(dev_priv->warp, dev);
 941
 942		if ((dev_priv->primary != NULL)
 943		    && (dev_priv->primary->type != _DRM_CONSISTENT))
 944			drm_legacy_ioremapfree(dev_priv->primary, dev);
 945
 946		if (dev->agp_buffer_map != NULL)
 947			drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
 948
 949		if (dev_priv->used_new_dma_init) {
 950#if IS_ENABLED(CONFIG_AGP)
 951			if (dev_priv->agp_handle != 0) {
 952				struct drm_agp_binding unbind_req;
 953				struct drm_agp_buffer free_req;
 954
 955				unbind_req.handle = dev_priv->agp_handle;
 956				drm_agp_unbind(dev, &unbind_req);
 957
 958				free_req.handle = dev_priv->agp_handle;
 959				drm_agp_free(dev, &free_req);
 960
 961				dev_priv->agp_textures = NULL;
 962				dev_priv->agp_size = 0;
 963				dev_priv->agp_handle = 0;
 964			}
 965
 966			if ((dev->agp != NULL) && dev->agp->acquired)
 967				err = drm_agp_release(dev);
 968#endif
 969		}
 970
 971		dev_priv->warp = NULL;
 972		dev_priv->primary = NULL;
 973		dev_priv->sarea = NULL;
 974		dev_priv->sarea_priv = NULL;
 975		dev->agp_buffer_map = NULL;
 976
 977		if (full_cleanup) {
 978			dev_priv->mmio = NULL;
 979			dev_priv->status = NULL;
 980			dev_priv->used_new_dma_init = 0;
 981		}
 982
 983		memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
 984		dev_priv->warp_pipe = 0;
 985		memset(dev_priv->warp_pipe_phys, 0,
 986		       sizeof(dev_priv->warp_pipe_phys));
 987
 988		if (dev_priv->head != NULL)
 989			mga_freelist_cleanup(dev);
 990	}
 991
 992	return err;
 993}
 994
 995int mga_dma_init(struct drm_device *dev, void *data,
 996		 struct drm_file *file_priv)
 997{
 998	drm_mga_init_t *init = data;
 999	int err;
1000
1001	LOCK_TEST_WITH_RETURN(dev, file_priv);
1002
1003	switch (init->func) {
1004	case MGA_INIT_DMA:
1005		err = mga_do_init_dma(dev, init);
1006		if (err)
1007			(void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
1008		return err;
1009	case MGA_CLEANUP_DMA:
1010		return mga_do_cleanup_dma(dev, FULL_CLEANUP);
1011	}
1012
1013	return -EINVAL;
1014}
1015
1016/* ================================================================
1017 * Primary DMA stream management
1018 */
1019
1020int mga_dma_flush(struct drm_device *dev, void *data,
1021		  struct drm_file *file_priv)
1022{
1023	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1024	struct drm_lock *lock = data;
1025
1026	LOCK_TEST_WITH_RETURN(dev, file_priv);
1027
1028	DRM_DEBUG("%s%s%s\n",
1029		  (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1030		  (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1031		  (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1032
1033	WRAP_WAIT_WITH_RETURN(dev_priv);
1034
1035	if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL))
1036		mga_do_dma_flush(dev_priv);
1037
1038	if (lock->flags & _DRM_LOCK_QUIESCENT) {
1039#if MGA_DMA_DEBUG
1040		int ret = mga_do_wait_for_idle(dev_priv);
1041		if (ret < 0)
1042			DRM_INFO("-EBUSY\n");
1043		return ret;
1044#else
1045		return mga_do_wait_for_idle(dev_priv);
1046#endif
1047	} else {
1048		return 0;
1049	}
1050}
1051
1052int mga_dma_reset(struct drm_device *dev, void *data,
1053		  struct drm_file *file_priv)
1054{
1055	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1056
1057	LOCK_TEST_WITH_RETURN(dev, file_priv);
1058
1059	return mga_do_dma_reset(dev_priv);
1060}
1061
1062/* ================================================================
1063 * DMA buffer management
1064 */
1065
1066static int mga_dma_get_buffers(struct drm_device *dev,
1067			       struct drm_file *file_priv, struct drm_dma *d)
1068{
1069	struct drm_buf *buf;
1070	int i;
1071
1072	for (i = d->granted_count; i < d->request_count; i++) {
1073		buf = mga_freelist_get(dev);
1074		if (!buf)
1075			return -EAGAIN;
1076
1077		buf->file_priv = file_priv;
1078
1079		if (copy_to_user(&d->request_indices[i],
1080				     &buf->idx, sizeof(buf->idx)))
1081			return -EFAULT;
1082		if (copy_to_user(&d->request_sizes[i],
1083				     &buf->total, sizeof(buf->total)))
1084			return -EFAULT;
1085
1086		d->granted_count++;
1087	}
1088	return 0;
1089}
1090
1091int mga_dma_buffers(struct drm_device *dev, void *data,
1092		    struct drm_file *file_priv)
1093{
1094	struct drm_device_dma *dma = dev->dma;
1095	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1096	struct drm_dma *d = data;
1097	int ret = 0;
1098
1099	LOCK_TEST_WITH_RETURN(dev, file_priv);
1100
1101	/* Please don't send us buffers.
1102	 */
1103	if (d->send_count != 0) {
1104		DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1105			  DRM_CURRENTPID, d->send_count);
1106		return -EINVAL;
1107	}
1108
1109	/* We'll send you buffers.
1110	 */
1111	if (d->request_count < 0 || d->request_count > dma->buf_count) {
1112		DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1113			  DRM_CURRENTPID, d->request_count, dma->buf_count);
1114		return -EINVAL;
1115	}
1116
1117	WRAP_TEST_WITH_RETURN(dev_priv);
1118
1119	d->granted_count = 0;
1120
1121	if (d->request_count)
1122		ret = mga_dma_get_buffers(dev, file_priv, d);
1123
1124	return ret;
1125}
1126
1127/**
1128 * Called just before the module is unloaded.
1129 */
1130int mga_driver_unload(struct drm_device *dev)
1131{
1132	kfree(dev->dev_private);
1133	dev->dev_private = NULL;
1134
1135	return 0;
1136}
1137
1138/**
1139 * Called when the last opener of the device is closed.
1140 */
1141void mga_driver_lastclose(struct drm_device *dev)
1142{
1143	mga_do_cleanup_dma(dev, FULL_CLEANUP);
1144}
1145
1146int mga_driver_dma_quiescent(struct drm_device *dev)
1147{
1148	drm_mga_private_t *dev_priv = dev->dev_private;
1149	return mga_do_wait_for_idle(dev_priv);
1150}