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1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/interrupt.h>
14#include <linux/of.h>
15#include <linux/mfd/stmpe.h>
16#include <linux/seq_file.h>
17
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_RE, REG_FE, REG_IE };
23
24#define CACHE_NR_REGS 3
25/* No variant has more than 24 GPIOs */
26#define CACHE_NR_BANKS (24 / 8)
27
28struct stmpe_gpio {
29 struct gpio_chip chip;
30 struct stmpe *stmpe;
31 struct device *dev;
32 struct mutex irq_lock;
33 u32 norequest_mask;
34 /* Caches of interrupt control registers for bus_lock */
35 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
36 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
37};
38
39static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
40{
41 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
42 struct stmpe *stmpe = stmpe_gpio->stmpe;
43 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
44 u8 mask = 1 << (offset % 8);
45 int ret;
46
47 ret = stmpe_reg_read(stmpe, reg);
48 if (ret < 0)
49 return ret;
50
51 return !!(ret & mask);
52}
53
54static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
55{
56 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
57 struct stmpe *stmpe = stmpe_gpio->stmpe;
58 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
59 u8 reg = stmpe->regs[which] - (offset / 8);
60 u8 mask = 1 << (offset % 8);
61
62 /*
63 * Some variants have single register for gpio set/clear functionality.
64 * For them we need to write 0 to clear and 1 to set.
65 */
66 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
67 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
68 else
69 stmpe_reg_write(stmpe, reg, mask);
70}
71
72static int stmpe_gpio_direction_output(struct gpio_chip *chip,
73 unsigned offset, int val)
74{
75 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
76 struct stmpe *stmpe = stmpe_gpio->stmpe;
77 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
78 u8 mask = 1 << (offset % 8);
79
80 stmpe_gpio_set(chip, offset, val);
81
82 return stmpe_set_bits(stmpe, reg, mask, mask);
83}
84
85static int stmpe_gpio_direction_input(struct gpio_chip *chip,
86 unsigned offset)
87{
88 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
89 struct stmpe *stmpe = stmpe_gpio->stmpe;
90 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
91 u8 mask = 1 << (offset % 8);
92
93 return stmpe_set_bits(stmpe, reg, mask, 0);
94}
95
96static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
97{
98 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
99 struct stmpe *stmpe = stmpe_gpio->stmpe;
100
101 if (stmpe_gpio->norequest_mask & (1 << offset))
102 return -EINVAL;
103
104 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
105}
106
107static struct gpio_chip template_chip = {
108 .label = "stmpe",
109 .owner = THIS_MODULE,
110 .direction_input = stmpe_gpio_direction_input,
111 .get = stmpe_gpio_get,
112 .direction_output = stmpe_gpio_direction_output,
113 .set = stmpe_gpio_set,
114 .request = stmpe_gpio_request,
115 .can_sleep = true,
116};
117
118static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
119{
120 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
121 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
122 int offset = d->hwirq;
123 int regoffset = offset / 8;
124 int mask = 1 << (offset % 8);
125
126 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
127 return -EINVAL;
128
129 /* STMPE801 doesn't have RE and FE registers */
130 if (stmpe_gpio->stmpe->partnum == STMPE801)
131 return 0;
132
133 if (type & IRQ_TYPE_EDGE_RISING)
134 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
135 else
136 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
137
138 if (type & IRQ_TYPE_EDGE_FALLING)
139 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
140 else
141 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
142
143 return 0;
144}
145
146static void stmpe_gpio_irq_lock(struct irq_data *d)
147{
148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
149 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
150
151 mutex_lock(&stmpe_gpio->irq_lock);
152}
153
154static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
155{
156 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
157 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
158 struct stmpe *stmpe = stmpe_gpio->stmpe;
159 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
160 static const u8 regmap[] = {
161 [REG_RE] = STMPE_IDX_GPRER_LSB,
162 [REG_FE] = STMPE_IDX_GPFER_LSB,
163 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
164 };
165 int i, j;
166
167 for (i = 0; i < CACHE_NR_REGS; i++) {
168 /* STMPE801 doesn't have RE and FE registers */
169 if ((stmpe->partnum == STMPE801) &&
170 (i != REG_IE))
171 continue;
172
173 for (j = 0; j < num_banks; j++) {
174 u8 old = stmpe_gpio->oldregs[i][j];
175 u8 new = stmpe_gpio->regs[i][j];
176
177 if (new == old)
178 continue;
179
180 stmpe_gpio->oldregs[i][j] = new;
181 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
182 }
183 }
184
185 mutex_unlock(&stmpe_gpio->irq_lock);
186}
187
188static void stmpe_gpio_irq_mask(struct irq_data *d)
189{
190 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
191 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
192 int offset = d->hwirq;
193 int regoffset = offset / 8;
194 int mask = 1 << (offset % 8);
195
196 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
197}
198
199static void stmpe_gpio_irq_unmask(struct irq_data *d)
200{
201 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
202 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
203 int offset = d->hwirq;
204 int regoffset = offset / 8;
205 int mask = 1 << (offset % 8);
206
207 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
208}
209
210static void stmpe_dbg_show_one(struct seq_file *s,
211 struct gpio_chip *gc,
212 unsigned offset, unsigned gpio)
213{
214 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
215 struct stmpe *stmpe = stmpe_gpio->stmpe;
216 const char *label = gpiochip_is_requested(gc, offset);
217 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
218 bool val = !!stmpe_gpio_get(gc, offset);
219 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
220 u8 mask = 1 << (offset % 8);
221 int ret;
222 u8 dir;
223
224 ret = stmpe_reg_read(stmpe, dir_reg);
225 if (ret < 0)
226 return;
227 dir = !!(ret & mask);
228
229 if (dir) {
230 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
231 gpio, label ?: "(none)",
232 val ? "hi" : "lo");
233 } else {
234 u8 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_MSB] + num_banks - 1 - (offset / 8);
235 u8 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB] - (offset / 8);
236 u8 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB] - (offset / 8);
237 u8 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB] - (offset / 8);
238 bool edge_det;
239 bool rise;
240 bool fall;
241 bool irqen;
242
243 ret = stmpe_reg_read(stmpe, edge_det_reg);
244 if (ret < 0)
245 return;
246 edge_det = !!(ret & mask);
247 ret = stmpe_reg_read(stmpe, rise_reg);
248 if (ret < 0)
249 return;
250 rise = !!(ret & mask);
251 ret = stmpe_reg_read(stmpe, fall_reg);
252 if (ret < 0)
253 return;
254 fall = !!(ret & mask);
255 ret = stmpe_reg_read(stmpe, irqen_reg);
256 if (ret < 0)
257 return;
258 irqen = !!(ret & mask);
259
260 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s %s%s%s",
261 gpio, label ?: "(none)",
262 val ? "hi" : "lo",
263 edge_det ? "edge-asserted" : "edge-inactive",
264 irqen ? "IRQ-enabled" : "",
265 rise ? " rising-edge-detection" : "",
266 fall ? " falling-edge-detection" : "");
267 }
268}
269
270static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
271{
272 unsigned i;
273 unsigned gpio = gc->base;
274
275 for (i = 0; i < gc->ngpio; i++, gpio++) {
276 stmpe_dbg_show_one(s, gc, i, gpio);
277 seq_printf(s, "\n");
278 }
279}
280
281static struct irq_chip stmpe_gpio_irq_chip = {
282 .name = "stmpe-gpio",
283 .irq_bus_lock = stmpe_gpio_irq_lock,
284 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
285 .irq_mask = stmpe_gpio_irq_mask,
286 .irq_unmask = stmpe_gpio_irq_unmask,
287 .irq_set_type = stmpe_gpio_irq_set_type,
288};
289
290static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
291{
292 struct stmpe_gpio *stmpe_gpio = dev;
293 struct stmpe *stmpe = stmpe_gpio->stmpe;
294 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
295 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
296 u8 status[num_banks];
297 int ret;
298 int i;
299
300 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
301 if (ret < 0)
302 return IRQ_NONE;
303
304 for (i = 0; i < num_banks; i++) {
305 int bank = num_banks - i - 1;
306 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
307 unsigned int stat = status[i];
308
309 stat &= enabled;
310 if (!stat)
311 continue;
312
313 while (stat) {
314 int bit = __ffs(stat);
315 int line = bank * 8 + bit;
316 int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
317 line);
318
319 handle_nested_irq(child_irq);
320 stat &= ~(1 << bit);
321 }
322
323 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
324
325 /* Edge detect register is not present on 801 */
326 if (stmpe->partnum != STMPE801)
327 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
328 + i, status[i]);
329 }
330
331 return IRQ_HANDLED;
332}
333
334static int stmpe_gpio_probe(struct platform_device *pdev)
335{
336 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
337 struct device_node *np = pdev->dev.of_node;
338 struct stmpe_gpio *stmpe_gpio;
339 int ret;
340 int irq = 0;
341
342 irq = platform_get_irq(pdev, 0);
343
344 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
345 if (!stmpe_gpio)
346 return -ENOMEM;
347
348 mutex_init(&stmpe_gpio->irq_lock);
349
350 stmpe_gpio->dev = &pdev->dev;
351 stmpe_gpio->stmpe = stmpe;
352 stmpe_gpio->chip = template_chip;
353 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
354 stmpe_gpio->chip.parent = &pdev->dev;
355 stmpe_gpio->chip.of_node = np;
356 stmpe_gpio->chip.base = -1;
357
358 if (IS_ENABLED(CONFIG_DEBUG_FS))
359 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
360
361 of_property_read_u32(np, "st,norequest-mask",
362 &stmpe_gpio->norequest_mask);
363
364 if (irq < 0)
365 dev_info(&pdev->dev,
366 "device configured in no-irq mode: "
367 "irqs are not available\n");
368
369 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
370 if (ret)
371 goto out_free;
372
373 ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
374 if (ret) {
375 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
376 goto out_disable;
377 }
378
379 if (irq > 0) {
380 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
381 stmpe_gpio_irq, IRQF_ONESHOT,
382 "stmpe-gpio", stmpe_gpio);
383 if (ret) {
384 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
385 goto out_disable;
386 }
387 ret = gpiochip_irqchip_add(&stmpe_gpio->chip,
388 &stmpe_gpio_irq_chip,
389 0,
390 handle_simple_irq,
391 IRQ_TYPE_NONE);
392 if (ret) {
393 dev_err(&pdev->dev,
394 "could not connect irqchip to gpiochip\n");
395 goto out_disable;
396 }
397
398 gpiochip_set_chained_irqchip(&stmpe_gpio->chip,
399 &stmpe_gpio_irq_chip,
400 irq,
401 NULL);
402 }
403
404 platform_set_drvdata(pdev, stmpe_gpio);
405
406 return 0;
407
408out_disable:
409 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
410 gpiochip_remove(&stmpe_gpio->chip);
411out_free:
412 kfree(stmpe_gpio);
413 return ret;
414}
415
416static int stmpe_gpio_remove(struct platform_device *pdev)
417{
418 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
419 struct stmpe *stmpe = stmpe_gpio->stmpe;
420
421 gpiochip_remove(&stmpe_gpio->chip);
422 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
423 kfree(stmpe_gpio);
424
425 return 0;
426}
427
428static struct platform_driver stmpe_gpio_driver = {
429 .driver.name = "stmpe-gpio",
430 .driver.owner = THIS_MODULE,
431 .probe = stmpe_gpio_probe,
432 .remove = stmpe_gpio_remove,
433};
434
435static int __init stmpe_gpio_init(void)
436{
437 return platform_driver_register(&stmpe_gpio_driver);
438}
439subsys_initcall(stmpe_gpio_init);
440
441static void __exit stmpe_gpio_exit(void)
442{
443 platform_driver_unregister(&stmpe_gpio_driver);
444}
445module_exit(stmpe_gpio_exit);
446
447MODULE_LICENSE("GPL v2");
448MODULE_DESCRIPTION("STMPExxxx GPIO driver");
449MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/interrupt.h>
16#include <linux/of.h>
17#include <linux/mfd/stmpe.h>
18
19/*
20 * These registers are modified under the irq bus lock and cached to avoid
21 * unnecessary writes in bus_sync_unlock.
22 */
23enum { REG_RE, REG_FE, REG_IE };
24
25#define CACHE_NR_REGS 3
26#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
27
28struct stmpe_gpio {
29 struct gpio_chip chip;
30 struct stmpe *stmpe;
31 struct device *dev;
32 struct mutex irq_lock;
33 struct irq_domain *domain;
34
35 int irq_base;
36 unsigned norequest_mask;
37
38 /* Caches of interrupt control registers for bus_lock */
39 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
40 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
41};
42
43static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
44{
45 return container_of(chip, struct stmpe_gpio, chip);
46}
47
48static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
49{
50 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
51 struct stmpe *stmpe = stmpe_gpio->stmpe;
52 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
53 u8 mask = 1 << (offset % 8);
54 int ret;
55
56 ret = stmpe_reg_read(stmpe, reg);
57 if (ret < 0)
58 return ret;
59
60 return !!(ret & mask);
61}
62
63static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
64{
65 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
66 struct stmpe *stmpe = stmpe_gpio->stmpe;
67 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
68 u8 reg = stmpe->regs[which] - (offset / 8);
69 u8 mask = 1 << (offset % 8);
70
71 /*
72 * Some variants have single register for gpio set/clear functionality.
73 * For them we need to write 0 to clear and 1 to set.
74 */
75 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
76 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
77 else
78 stmpe_reg_write(stmpe, reg, mask);
79}
80
81static int stmpe_gpio_direction_output(struct gpio_chip *chip,
82 unsigned offset, int val)
83{
84 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
85 struct stmpe *stmpe = stmpe_gpio->stmpe;
86 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
87 u8 mask = 1 << (offset % 8);
88
89 stmpe_gpio_set(chip, offset, val);
90
91 return stmpe_set_bits(stmpe, reg, mask, mask);
92}
93
94static int stmpe_gpio_direction_input(struct gpio_chip *chip,
95 unsigned offset)
96{
97 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
98 struct stmpe *stmpe = stmpe_gpio->stmpe;
99 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
100 u8 mask = 1 << (offset % 8);
101
102 return stmpe_set_bits(stmpe, reg, mask, 0);
103}
104
105static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
106{
107 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
108
109 return irq_create_mapping(stmpe_gpio->domain, offset);
110}
111
112static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
113{
114 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
115 struct stmpe *stmpe = stmpe_gpio->stmpe;
116
117 if (stmpe_gpio->norequest_mask & (1 << offset))
118 return -EINVAL;
119
120 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
121}
122
123static struct gpio_chip template_chip = {
124 .label = "stmpe",
125 .owner = THIS_MODULE,
126 .direction_input = stmpe_gpio_direction_input,
127 .get = stmpe_gpio_get,
128 .direction_output = stmpe_gpio_direction_output,
129 .set = stmpe_gpio_set,
130 .to_irq = stmpe_gpio_to_irq,
131 .request = stmpe_gpio_request,
132 .can_sleep = true,
133};
134
135static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
136{
137 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
138 int offset = d->hwirq;
139 int regoffset = offset / 8;
140 int mask = 1 << (offset % 8);
141
142 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
143 return -EINVAL;
144
145 /* STMPE801 doesn't have RE and FE registers */
146 if (stmpe_gpio->stmpe->partnum == STMPE801)
147 return 0;
148
149 if (type == IRQ_TYPE_EDGE_RISING)
150 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
151 else
152 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
153
154 if (type == IRQ_TYPE_EDGE_FALLING)
155 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
156 else
157 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
158
159 return 0;
160}
161
162static void stmpe_gpio_irq_lock(struct irq_data *d)
163{
164 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
165
166 mutex_lock(&stmpe_gpio->irq_lock);
167}
168
169static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
170{
171 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
172 struct stmpe *stmpe = stmpe_gpio->stmpe;
173 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
174 static const u8 regmap[] = {
175 [REG_RE] = STMPE_IDX_GPRER_LSB,
176 [REG_FE] = STMPE_IDX_GPFER_LSB,
177 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
178 };
179 int i, j;
180
181 for (i = 0; i < CACHE_NR_REGS; i++) {
182 /* STMPE801 doesn't have RE and FE registers */
183 if ((stmpe->partnum == STMPE801) &&
184 (i != REG_IE))
185 continue;
186
187 for (j = 0; j < num_banks; j++) {
188 u8 old = stmpe_gpio->oldregs[i][j];
189 u8 new = stmpe_gpio->regs[i][j];
190
191 if (new == old)
192 continue;
193
194 stmpe_gpio->oldregs[i][j] = new;
195 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
196 }
197 }
198
199 mutex_unlock(&stmpe_gpio->irq_lock);
200}
201
202static void stmpe_gpio_irq_mask(struct irq_data *d)
203{
204 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
205 int offset = d->hwirq;
206 int regoffset = offset / 8;
207 int mask = 1 << (offset % 8);
208
209 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
210}
211
212static void stmpe_gpio_irq_unmask(struct irq_data *d)
213{
214 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
215 int offset = d->hwirq;
216 int regoffset = offset / 8;
217 int mask = 1 << (offset % 8);
218
219 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
220}
221
222static struct irq_chip stmpe_gpio_irq_chip = {
223 .name = "stmpe-gpio",
224 .irq_bus_lock = stmpe_gpio_irq_lock,
225 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
226 .irq_mask = stmpe_gpio_irq_mask,
227 .irq_unmask = stmpe_gpio_irq_unmask,
228 .irq_set_type = stmpe_gpio_irq_set_type,
229};
230
231static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
232{
233 struct stmpe_gpio *stmpe_gpio = dev;
234 struct stmpe *stmpe = stmpe_gpio->stmpe;
235 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
236 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
237 u8 status[num_banks];
238 int ret;
239 int i;
240
241 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
242 if (ret < 0)
243 return IRQ_NONE;
244
245 for (i = 0; i < num_banks; i++) {
246 int bank = num_banks - i - 1;
247 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
248 unsigned int stat = status[i];
249
250 stat &= enabled;
251 if (!stat)
252 continue;
253
254 while (stat) {
255 int bit = __ffs(stat);
256 int line = bank * 8 + bit;
257 int child_irq = irq_find_mapping(stmpe_gpio->domain,
258 line);
259
260 handle_nested_irq(child_irq);
261 stat &= ~(1 << bit);
262 }
263
264 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
265
266 /* Edge detect register is not present on 801 */
267 if (stmpe->partnum != STMPE801)
268 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
269 + i, status[i]);
270 }
271
272 return IRQ_HANDLED;
273}
274
275static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq,
276 irq_hw_number_t hwirq)
277{
278 struct stmpe_gpio *stmpe_gpio = d->host_data;
279
280 if (!stmpe_gpio)
281 return -EINVAL;
282
283 irq_set_chip_data(irq, stmpe_gpio);
284 irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
285 handle_simple_irq);
286 irq_set_nested_thread(irq, 1);
287#ifdef CONFIG_ARM
288 set_irq_flags(irq, IRQF_VALID);
289#else
290 irq_set_noprobe(irq);
291#endif
292
293 return 0;
294}
295
296static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
297{
298#ifdef CONFIG_ARM
299 set_irq_flags(irq, 0);
300#endif
301 irq_set_chip_and_handler(irq, NULL, NULL);
302 irq_set_chip_data(irq, NULL);
303}
304
305static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
306 .unmap = stmpe_gpio_irq_unmap,
307 .map = stmpe_gpio_irq_map,
308 .xlate = irq_domain_xlate_twocell,
309};
310
311static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
312 struct device_node *np)
313{
314 int base = 0;
315
316 if (!np)
317 base = stmpe_gpio->irq_base;
318
319 stmpe_gpio->domain = irq_domain_add_simple(np,
320 stmpe_gpio->chip.ngpio, base,
321 &stmpe_gpio_irq_simple_ops, stmpe_gpio);
322 if (!stmpe_gpio->domain) {
323 dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
324 return -ENOSYS;
325 }
326
327 return 0;
328}
329
330static int stmpe_gpio_probe(struct platform_device *pdev)
331{
332 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
333 struct device_node *np = pdev->dev.of_node;
334 struct stmpe_gpio_platform_data *pdata;
335 struct stmpe_gpio *stmpe_gpio;
336 int ret;
337 int irq = 0;
338
339 pdata = stmpe->pdata->gpio;
340
341 irq = platform_get_irq(pdev, 0);
342
343 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
344 if (!stmpe_gpio)
345 return -ENOMEM;
346
347 mutex_init(&stmpe_gpio->irq_lock);
348
349 stmpe_gpio->dev = &pdev->dev;
350 stmpe_gpio->stmpe = stmpe;
351 stmpe_gpio->chip = template_chip;
352 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
353 stmpe_gpio->chip.dev = &pdev->dev;
354#ifdef CONFIG_OF
355 stmpe_gpio->chip.of_node = np;
356#endif
357 stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
358
359 if (pdata)
360 stmpe_gpio->norequest_mask = pdata->norequest_mask;
361 else if (np)
362 of_property_read_u32(np, "st,norequest-mask",
363 &stmpe_gpio->norequest_mask);
364
365 if (irq >= 0)
366 stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
367 else
368 dev_info(&pdev->dev,
369 "device configured in no-irq mode; "
370 "irqs are not available\n");
371
372 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
373 if (ret)
374 goto out_free;
375
376 if (irq >= 0) {
377 ret = stmpe_gpio_irq_init(stmpe_gpio, np);
378 if (ret)
379 goto out_disable;
380
381 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
382 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
383 if (ret) {
384 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
385 goto out_disable;
386 }
387 }
388
389 ret = gpiochip_add(&stmpe_gpio->chip);
390 if (ret) {
391 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
392 goto out_freeirq;
393 }
394
395 if (pdata && pdata->setup)
396 pdata->setup(stmpe, stmpe_gpio->chip.base);
397
398 platform_set_drvdata(pdev, stmpe_gpio);
399
400 return 0;
401
402out_freeirq:
403 if (irq >= 0)
404 free_irq(irq, stmpe_gpio);
405out_disable:
406 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
407out_free:
408 kfree(stmpe_gpio);
409 return ret;
410}
411
412static int stmpe_gpio_remove(struct platform_device *pdev)
413{
414 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
415 struct stmpe *stmpe = stmpe_gpio->stmpe;
416 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
417 int irq = platform_get_irq(pdev, 0);
418 int ret;
419
420 if (pdata && pdata->remove)
421 pdata->remove(stmpe, stmpe_gpio->chip.base);
422
423 ret = gpiochip_remove(&stmpe_gpio->chip);
424 if (ret < 0) {
425 dev_err(stmpe_gpio->dev,
426 "unable to remove gpiochip: %d\n", ret);
427 return ret;
428 }
429
430 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
431
432 if (irq >= 0)
433 free_irq(irq, stmpe_gpio);
434
435 kfree(stmpe_gpio);
436
437 return 0;
438}
439
440static struct platform_driver stmpe_gpio_driver = {
441 .driver.name = "stmpe-gpio",
442 .driver.owner = THIS_MODULE,
443 .probe = stmpe_gpio_probe,
444 .remove = stmpe_gpio_remove,
445};
446
447static int __init stmpe_gpio_init(void)
448{
449 return platform_driver_register(&stmpe_gpio_driver);
450}
451subsys_initcall(stmpe_gpio_init);
452
453static void __exit stmpe_gpio_exit(void)
454{
455 platform_driver_unregister(&stmpe_gpio_driver);
456}
457module_exit(stmpe_gpio_exit);
458
459MODULE_LICENSE("GPL v2");
460MODULE_DESCRIPTION("STMPExxxx GPIO driver");
461MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");