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1/* smp.c: Sparc64 SMP support.
2 *
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/export.h>
7#include <linux/kernel.h>
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <linux/pagemap.h>
11#include <linux/threads.h>
12#include <linux/smp.h>
13#include <linux/interrupt.h>
14#include <linux/kernel_stat.h>
15#include <linux/delay.h>
16#include <linux/init.h>
17#include <linux/spinlock.h>
18#include <linux/fs.h>
19#include <linux/seq_file.h>
20#include <linux/cache.h>
21#include <linux/jiffies.h>
22#include <linux/profile.h>
23#include <linux/bootmem.h>
24#include <linux/vmalloc.h>
25#include <linux/ftrace.h>
26#include <linux/cpu.h>
27#include <linux/slab.h>
28#include <linux/kgdb.h>
29
30#include <asm/head.h>
31#include <asm/ptrace.h>
32#include <linux/atomic.h>
33#include <asm/tlbflush.h>
34#include <asm/mmu_context.h>
35#include <asm/cpudata.h>
36#include <asm/hvtramp.h>
37#include <asm/io.h>
38#include <asm/timer.h>
39#include <asm/setup.h>
40
41#include <asm/irq.h>
42#include <asm/irq_regs.h>
43#include <asm/page.h>
44#include <asm/pgtable.h>
45#include <asm/oplib.h>
46#include <asm/uaccess.h>
47#include <asm/starfire.h>
48#include <asm/tlb.h>
49#include <asm/sections.h>
50#include <asm/prom.h>
51#include <asm/mdesc.h>
52#include <asm/ldc.h>
53#include <asm/hypervisor.h>
54#include <asm/pcr.h>
55
56#include "cpumap.h"
57#include "kernel.h"
58
59DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
60cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
61 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
62
63cpumask_t cpu_core_sib_map[NR_CPUS] __read_mostly = {
64 [0 ... NR_CPUS-1] = CPU_MASK_NONE };
65
66EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
67EXPORT_SYMBOL(cpu_core_map);
68EXPORT_SYMBOL(cpu_core_sib_map);
69
70static cpumask_t smp_commenced_mask;
71
72void smp_info(struct seq_file *m)
73{
74 int i;
75
76 seq_printf(m, "State:\n");
77 for_each_online_cpu(i)
78 seq_printf(m, "CPU%d:\t\tonline\n", i);
79}
80
81void smp_bogo(struct seq_file *m)
82{
83 int i;
84
85 for_each_online_cpu(i)
86 seq_printf(m,
87 "Cpu%dClkTck\t: %016lx\n",
88 i, cpu_data(i).clock_tick);
89}
90
91extern void setup_sparc64_timer(void);
92
93static volatile unsigned long callin_flag = 0;
94
95void smp_callin(void)
96{
97 int cpuid = hard_smp_processor_id();
98
99 __local_per_cpu_offset = __per_cpu_offset(cpuid);
100
101 if (tlb_type == hypervisor)
102 sun4v_ktsb_register();
103
104 __flush_tlb_all();
105
106 setup_sparc64_timer();
107
108 if (cheetah_pcache_forced_on)
109 cheetah_enable_pcache();
110
111 callin_flag = 1;
112 __asm__ __volatile__("membar #Sync\n\t"
113 "flush %%g6" : : : "memory");
114
115 /* Clear this or we will die instantly when we
116 * schedule back to this idler...
117 */
118 current_thread_info()->new_child = 0;
119
120 /* Attach to the address space of init_task. */
121 atomic_inc(&init_mm.mm_count);
122 current->active_mm = &init_mm;
123
124 /* inform the notifiers about the new cpu */
125 notify_cpu_starting(cpuid);
126
127 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
128 rmb();
129
130 set_cpu_online(cpuid, true);
131
132 /* idle thread is expected to have preempt disabled */
133 preempt_disable();
134
135 local_irq_enable();
136
137 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
138}
139
140void cpu_panic(void)
141{
142 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
143 panic("SMP bolixed\n");
144}
145
146/* This tick register synchronization scheme is taken entirely from
147 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
148 *
149 * The only change I've made is to rework it so that the master
150 * initiates the synchonization instead of the slave. -DaveM
151 */
152
153#define MASTER 0
154#define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
155
156#define NUM_ROUNDS 64 /* magic value */
157#define NUM_ITERS 5 /* likewise */
158
159static DEFINE_RAW_SPINLOCK(itc_sync_lock);
160static unsigned long go[SLAVE + 1];
161
162#define DEBUG_TICK_SYNC 0
163
164static inline long get_delta (long *rt, long *master)
165{
166 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
167 unsigned long tcenter, t0, t1, tm;
168 unsigned long i;
169
170 for (i = 0; i < NUM_ITERS; i++) {
171 t0 = tick_ops->get_tick();
172 go[MASTER] = 1;
173 membar_safe("#StoreLoad");
174 while (!(tm = go[SLAVE]))
175 rmb();
176 go[SLAVE] = 0;
177 wmb();
178 t1 = tick_ops->get_tick();
179
180 if (t1 - t0 < best_t1 - best_t0)
181 best_t0 = t0, best_t1 = t1, best_tm = tm;
182 }
183
184 *rt = best_t1 - best_t0;
185 *master = best_tm - best_t0;
186
187 /* average best_t0 and best_t1 without overflow: */
188 tcenter = (best_t0/2 + best_t1/2);
189 if (best_t0 % 2 + best_t1 % 2 == 2)
190 tcenter++;
191 return tcenter - best_tm;
192}
193
194void smp_synchronize_tick_client(void)
195{
196 long i, delta, adj, adjust_latency = 0, done = 0;
197 unsigned long flags, rt, master_time_stamp;
198#if DEBUG_TICK_SYNC
199 struct {
200 long rt; /* roundtrip time */
201 long master; /* master's timestamp */
202 long diff; /* difference between midpoint and master's timestamp */
203 long lat; /* estimate of itc adjustment latency */
204 } t[NUM_ROUNDS];
205#endif
206
207 go[MASTER] = 1;
208
209 while (go[MASTER])
210 rmb();
211
212 local_irq_save(flags);
213 {
214 for (i = 0; i < NUM_ROUNDS; i++) {
215 delta = get_delta(&rt, &master_time_stamp);
216 if (delta == 0)
217 done = 1; /* let's lock on to this... */
218
219 if (!done) {
220 if (i > 0) {
221 adjust_latency += -delta;
222 adj = -delta + adjust_latency/4;
223 } else
224 adj = -delta;
225
226 tick_ops->add_tick(adj);
227 }
228#if DEBUG_TICK_SYNC
229 t[i].rt = rt;
230 t[i].master = master_time_stamp;
231 t[i].diff = delta;
232 t[i].lat = adjust_latency/4;
233#endif
234 }
235 }
236 local_irq_restore(flags);
237
238#if DEBUG_TICK_SYNC
239 for (i = 0; i < NUM_ROUNDS; i++)
240 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
241 t[i].rt, t[i].master, t[i].diff, t[i].lat);
242#endif
243
244 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
245 "(last diff %ld cycles, maxerr %lu cycles)\n",
246 smp_processor_id(), delta, rt);
247}
248
249static void smp_start_sync_tick_client(int cpu);
250
251static void smp_synchronize_one_tick(int cpu)
252{
253 unsigned long flags, i;
254
255 go[MASTER] = 0;
256
257 smp_start_sync_tick_client(cpu);
258
259 /* wait for client to be ready */
260 while (!go[MASTER])
261 rmb();
262
263 /* now let the client proceed into his loop */
264 go[MASTER] = 0;
265 membar_safe("#StoreLoad");
266
267 raw_spin_lock_irqsave(&itc_sync_lock, flags);
268 {
269 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
270 while (!go[MASTER])
271 rmb();
272 go[MASTER] = 0;
273 wmb();
274 go[SLAVE] = tick_ops->get_tick();
275 membar_safe("#StoreLoad");
276 }
277 }
278 raw_spin_unlock_irqrestore(&itc_sync_lock, flags);
279}
280
281#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
282static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg,
283 void **descrp)
284{
285 extern unsigned long sparc64_ttable_tl0;
286 extern unsigned long kern_locked_tte_data;
287 struct hvtramp_descr *hdesc;
288 unsigned long trampoline_ra;
289 struct trap_per_cpu *tb;
290 u64 tte_vaddr, tte_data;
291 unsigned long hv_err;
292 int i;
293
294 hdesc = kzalloc(sizeof(*hdesc) +
295 (sizeof(struct hvtramp_mapping) *
296 num_kernel_image_mappings - 1),
297 GFP_KERNEL);
298 if (!hdesc) {
299 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
300 "hvtramp_descr.\n");
301 return;
302 }
303 *descrp = hdesc;
304
305 hdesc->cpu = cpu;
306 hdesc->num_mappings = num_kernel_image_mappings;
307
308 tb = &trap_block[cpu];
309
310 hdesc->fault_info_va = (unsigned long) &tb->fault_info;
311 hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
312
313 hdesc->thread_reg = thread_reg;
314
315 tte_vaddr = (unsigned long) KERNBASE;
316 tte_data = kern_locked_tte_data;
317
318 for (i = 0; i < hdesc->num_mappings; i++) {
319 hdesc->maps[i].vaddr = tte_vaddr;
320 hdesc->maps[i].tte = tte_data;
321 tte_vaddr += 0x400000;
322 tte_data += 0x400000;
323 }
324
325 trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
326
327 hv_err = sun4v_cpu_start(cpu, trampoline_ra,
328 kimage_addr_to_ra(&sparc64_ttable_tl0),
329 __pa(hdesc));
330 if (hv_err)
331 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
332 "gives error %lu\n", hv_err);
333}
334#endif
335
336extern unsigned long sparc64_cpu_startup;
337
338/* The OBP cpu startup callback truncates the 3rd arg cookie to
339 * 32-bits (I think) so to be safe we have it read the pointer
340 * contained here so we work on >4GB machines. -DaveM
341 */
342static struct thread_info *cpu_new_thread = NULL;
343
344static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
345{
346 unsigned long entry =
347 (unsigned long)(&sparc64_cpu_startup);
348 unsigned long cookie =
349 (unsigned long)(&cpu_new_thread);
350 void *descr = NULL;
351 int timeout, ret;
352
353 callin_flag = 0;
354 cpu_new_thread = task_thread_info(idle);
355
356 if (tlb_type == hypervisor) {
357#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
358 if (ldom_domaining_enabled)
359 ldom_startcpu_cpuid(cpu,
360 (unsigned long) cpu_new_thread,
361 &descr);
362 else
363#endif
364 prom_startcpu_cpuid(cpu, entry, cookie);
365 } else {
366 struct device_node *dp = of_find_node_by_cpuid(cpu);
367
368 prom_startcpu(dp->phandle, entry, cookie);
369 }
370
371 for (timeout = 0; timeout < 50000; timeout++) {
372 if (callin_flag)
373 break;
374 udelay(100);
375 }
376
377 if (callin_flag) {
378 ret = 0;
379 } else {
380 printk("Processor %d is stuck.\n", cpu);
381 ret = -ENODEV;
382 }
383 cpu_new_thread = NULL;
384
385 kfree(descr);
386
387 return ret;
388}
389
390static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
391{
392 u64 result, target;
393 int stuck, tmp;
394
395 if (this_is_starfire) {
396 /* map to real upaid */
397 cpu = (((cpu & 0x3c) << 1) |
398 ((cpu & 0x40) >> 4) |
399 (cpu & 0x3));
400 }
401
402 target = (cpu << 14) | 0x70;
403again:
404 /* Ok, this is the real Spitfire Errata #54.
405 * One must read back from a UDB internal register
406 * after writes to the UDB interrupt dispatch, but
407 * before the membar Sync for that write.
408 * So we use the high UDB control register (ASI 0x7f,
409 * ADDR 0x20) for the dummy read. -DaveM
410 */
411 tmp = 0x40;
412 __asm__ __volatile__(
413 "wrpr %1, %2, %%pstate\n\t"
414 "stxa %4, [%0] %3\n\t"
415 "stxa %5, [%0+%8] %3\n\t"
416 "add %0, %8, %0\n\t"
417 "stxa %6, [%0+%8] %3\n\t"
418 "membar #Sync\n\t"
419 "stxa %%g0, [%7] %3\n\t"
420 "membar #Sync\n\t"
421 "mov 0x20, %%g1\n\t"
422 "ldxa [%%g1] 0x7f, %%g0\n\t"
423 "membar #Sync"
424 : "=r" (tmp)
425 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
426 "r" (data0), "r" (data1), "r" (data2), "r" (target),
427 "r" (0x10), "0" (tmp)
428 : "g1");
429
430 /* NOTE: PSTATE_IE is still clear. */
431 stuck = 100000;
432 do {
433 __asm__ __volatile__("ldxa [%%g0] %1, %0"
434 : "=r" (result)
435 : "i" (ASI_INTR_DISPATCH_STAT));
436 if (result == 0) {
437 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
438 : : "r" (pstate));
439 return;
440 }
441 stuck -= 1;
442 if (stuck == 0)
443 break;
444 } while (result & 0x1);
445 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
446 : : "r" (pstate));
447 if (stuck == 0) {
448 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
449 smp_processor_id(), result);
450 } else {
451 udelay(2);
452 goto again;
453 }
454}
455
456static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
457{
458 u64 *mondo, data0, data1, data2;
459 u16 *cpu_list;
460 u64 pstate;
461 int i;
462
463 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
464 cpu_list = __va(tb->cpu_list_pa);
465 mondo = __va(tb->cpu_mondo_block_pa);
466 data0 = mondo[0];
467 data1 = mondo[1];
468 data2 = mondo[2];
469 for (i = 0; i < cnt; i++)
470 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
471}
472
473/* Cheetah now allows to send the whole 64-bytes of data in the interrupt
474 * packet, but we have no use for that. However we do take advantage of
475 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
476 */
477static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
478{
479 int nack_busy_id, is_jbus, need_more;
480 u64 *mondo, pstate, ver, busy_mask;
481 u16 *cpu_list;
482
483 cpu_list = __va(tb->cpu_list_pa);
484 mondo = __va(tb->cpu_mondo_block_pa);
485
486 /* Unfortunately, someone at Sun had the brilliant idea to make the
487 * busy/nack fields hard-coded by ITID number for this Ultra-III
488 * derivative processor.
489 */
490 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
491 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
492 (ver >> 32) == __SERRANO_ID);
493
494 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
495
496retry:
497 need_more = 0;
498 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
499 : : "r" (pstate), "i" (PSTATE_IE));
500
501 /* Setup the dispatch data registers. */
502 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
503 "stxa %1, [%4] %6\n\t"
504 "stxa %2, [%5] %6\n\t"
505 "membar #Sync\n\t"
506 : /* no outputs */
507 : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
508 "r" (0x40), "r" (0x50), "r" (0x60),
509 "i" (ASI_INTR_W));
510
511 nack_busy_id = 0;
512 busy_mask = 0;
513 {
514 int i;
515
516 for (i = 0; i < cnt; i++) {
517 u64 target, nr;
518
519 nr = cpu_list[i];
520 if (nr == 0xffff)
521 continue;
522
523 target = (nr << 14) | 0x70;
524 if (is_jbus) {
525 busy_mask |= (0x1UL << (nr * 2));
526 } else {
527 target |= (nack_busy_id << 24);
528 busy_mask |= (0x1UL <<
529 (nack_busy_id * 2));
530 }
531 __asm__ __volatile__(
532 "stxa %%g0, [%0] %1\n\t"
533 "membar #Sync\n\t"
534 : /* no outputs */
535 : "r" (target), "i" (ASI_INTR_W));
536 nack_busy_id++;
537 if (nack_busy_id == 32) {
538 need_more = 1;
539 break;
540 }
541 }
542 }
543
544 /* Now, poll for completion. */
545 {
546 u64 dispatch_stat, nack_mask;
547 long stuck;
548
549 stuck = 100000 * nack_busy_id;
550 nack_mask = busy_mask << 1;
551 do {
552 __asm__ __volatile__("ldxa [%%g0] %1, %0"
553 : "=r" (dispatch_stat)
554 : "i" (ASI_INTR_DISPATCH_STAT));
555 if (!(dispatch_stat & (busy_mask | nack_mask))) {
556 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
557 : : "r" (pstate));
558 if (unlikely(need_more)) {
559 int i, this_cnt = 0;
560 for (i = 0; i < cnt; i++) {
561 if (cpu_list[i] == 0xffff)
562 continue;
563 cpu_list[i] = 0xffff;
564 this_cnt++;
565 if (this_cnt == 32)
566 break;
567 }
568 goto retry;
569 }
570 return;
571 }
572 if (!--stuck)
573 break;
574 } while (dispatch_stat & busy_mask);
575
576 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
577 : : "r" (pstate));
578
579 if (dispatch_stat & busy_mask) {
580 /* Busy bits will not clear, continue instead
581 * of freezing up on this cpu.
582 */
583 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
584 smp_processor_id(), dispatch_stat);
585 } else {
586 int i, this_busy_nack = 0;
587
588 /* Delay some random time with interrupts enabled
589 * to prevent deadlock.
590 */
591 udelay(2 * nack_busy_id);
592
593 /* Clear out the mask bits for cpus which did not
594 * NACK us.
595 */
596 for (i = 0; i < cnt; i++) {
597 u64 check_mask, nr;
598
599 nr = cpu_list[i];
600 if (nr == 0xffff)
601 continue;
602
603 if (is_jbus)
604 check_mask = (0x2UL << (2*nr));
605 else
606 check_mask = (0x2UL <<
607 this_busy_nack);
608 if ((dispatch_stat & check_mask) == 0)
609 cpu_list[i] = 0xffff;
610 this_busy_nack += 2;
611 if (this_busy_nack == 64)
612 break;
613 }
614
615 goto retry;
616 }
617 }
618}
619
620/* Multi-cpu list version. */
621static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
622{
623 int retries, this_cpu, prev_sent, i, saw_cpu_error;
624 unsigned long status;
625 u16 *cpu_list;
626
627 this_cpu = smp_processor_id();
628
629 cpu_list = __va(tb->cpu_list_pa);
630
631 saw_cpu_error = 0;
632 retries = 0;
633 prev_sent = 0;
634 do {
635 int forward_progress, n_sent;
636
637 status = sun4v_cpu_mondo_send(cnt,
638 tb->cpu_list_pa,
639 tb->cpu_mondo_block_pa);
640
641 /* HV_EOK means all cpus received the xcall, we're done. */
642 if (likely(status == HV_EOK))
643 break;
644
645 /* First, see if we made any forward progress.
646 *
647 * The hypervisor indicates successful sends by setting
648 * cpu list entries to the value 0xffff.
649 */
650 n_sent = 0;
651 for (i = 0; i < cnt; i++) {
652 if (likely(cpu_list[i] == 0xffff))
653 n_sent++;
654 }
655
656 forward_progress = 0;
657 if (n_sent > prev_sent)
658 forward_progress = 1;
659
660 prev_sent = n_sent;
661
662 /* If we get a HV_ECPUERROR, then one or more of the cpus
663 * in the list are in error state. Use the cpu_state()
664 * hypervisor call to find out which cpus are in error state.
665 */
666 if (unlikely(status == HV_ECPUERROR)) {
667 for (i = 0; i < cnt; i++) {
668 long err;
669 u16 cpu;
670
671 cpu = cpu_list[i];
672 if (cpu == 0xffff)
673 continue;
674
675 err = sun4v_cpu_state(cpu);
676 if (err == HV_CPU_STATE_ERROR) {
677 saw_cpu_error = (cpu + 1);
678 cpu_list[i] = 0xffff;
679 }
680 }
681 } else if (unlikely(status != HV_EWOULDBLOCK))
682 goto fatal_mondo_error;
683
684 /* Don't bother rewriting the CPU list, just leave the
685 * 0xffff and non-0xffff entries in there and the
686 * hypervisor will do the right thing.
687 *
688 * Only advance timeout state if we didn't make any
689 * forward progress.
690 */
691 if (unlikely(!forward_progress)) {
692 if (unlikely(++retries > 10000))
693 goto fatal_mondo_timeout;
694
695 /* Delay a little bit to let other cpus catch up
696 * on their cpu mondo queue work.
697 */
698 udelay(2 * cnt);
699 }
700 } while (1);
701
702 if (unlikely(saw_cpu_error))
703 goto fatal_mondo_cpu_error;
704
705 return;
706
707fatal_mondo_cpu_error:
708 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
709 "(including %d) were in error state\n",
710 this_cpu, saw_cpu_error - 1);
711 return;
712
713fatal_mondo_timeout:
714 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
715 " progress after %d retries.\n",
716 this_cpu, retries);
717 goto dump_cpu_list_and_out;
718
719fatal_mondo_error:
720 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
721 this_cpu, status);
722 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
723 "mondo_block_pa(%lx)\n",
724 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
725
726dump_cpu_list_and_out:
727 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
728 for (i = 0; i < cnt; i++)
729 printk("%u ", cpu_list[i]);
730 printk("]\n");
731}
732
733static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
734
735static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
736{
737 struct trap_per_cpu *tb;
738 int this_cpu, i, cnt;
739 unsigned long flags;
740 u16 *cpu_list;
741 u64 *mondo;
742
743 /* We have to do this whole thing with interrupts fully disabled.
744 * Otherwise if we send an xcall from interrupt context it will
745 * corrupt both our mondo block and cpu list state.
746 *
747 * One consequence of this is that we cannot use timeout mechanisms
748 * that depend upon interrupts being delivered locally. So, for
749 * example, we cannot sample jiffies and expect it to advance.
750 *
751 * Fortunately, udelay() uses %stick/%tick so we can use that.
752 */
753 local_irq_save(flags);
754
755 this_cpu = smp_processor_id();
756 tb = &trap_block[this_cpu];
757
758 mondo = __va(tb->cpu_mondo_block_pa);
759 mondo[0] = data0;
760 mondo[1] = data1;
761 mondo[2] = data2;
762 wmb();
763
764 cpu_list = __va(tb->cpu_list_pa);
765
766 /* Setup the initial cpu list. */
767 cnt = 0;
768 for_each_cpu(i, mask) {
769 if (i == this_cpu || !cpu_online(i))
770 continue;
771 cpu_list[cnt++] = i;
772 }
773
774 if (cnt)
775 xcall_deliver_impl(tb, cnt);
776
777 local_irq_restore(flags);
778}
779
780/* Send cross call to all processors mentioned in MASK_P
781 * except self. Really, there are only two cases currently,
782 * "cpu_online_mask" and "mm_cpumask(mm)".
783 */
784static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
785{
786 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
787
788 xcall_deliver(data0, data1, data2, mask);
789}
790
791/* Send cross call to all processors except self. */
792static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
793{
794 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
795}
796
797extern unsigned long xcall_sync_tick;
798
799static void smp_start_sync_tick_client(int cpu)
800{
801 xcall_deliver((u64) &xcall_sync_tick, 0, 0,
802 cpumask_of(cpu));
803}
804
805extern unsigned long xcall_call_function;
806
807void arch_send_call_function_ipi_mask(const struct cpumask *mask)
808{
809 xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
810}
811
812extern unsigned long xcall_call_function_single;
813
814void arch_send_call_function_single_ipi(int cpu)
815{
816 xcall_deliver((u64) &xcall_call_function_single, 0, 0,
817 cpumask_of(cpu));
818}
819
820void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
821{
822 clear_softint(1 << irq);
823 irq_enter();
824 generic_smp_call_function_interrupt();
825 irq_exit();
826}
827
828void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
829{
830 clear_softint(1 << irq);
831 irq_enter();
832 generic_smp_call_function_single_interrupt();
833 irq_exit();
834}
835
836static void tsb_sync(void *info)
837{
838 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
839 struct mm_struct *mm = info;
840
841 /* It is not valid to test "current->active_mm == mm" here.
842 *
843 * The value of "current" is not changed atomically with
844 * switch_mm(). But that's OK, we just need to check the
845 * current cpu's trap block PGD physical address.
846 */
847 if (tp->pgd_paddr == __pa(mm->pgd))
848 tsb_context_switch(mm);
849}
850
851void smp_tsb_sync(struct mm_struct *mm)
852{
853 smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
854}
855
856extern unsigned long xcall_flush_tlb_mm;
857extern unsigned long xcall_flush_tlb_page;
858extern unsigned long xcall_flush_tlb_kernel_range;
859extern unsigned long xcall_fetch_glob_regs;
860extern unsigned long xcall_fetch_glob_pmu;
861extern unsigned long xcall_fetch_glob_pmu_n4;
862extern unsigned long xcall_receive_signal;
863extern unsigned long xcall_new_mmu_context_version;
864#ifdef CONFIG_KGDB
865extern unsigned long xcall_kgdb_capture;
866#endif
867
868#ifdef DCACHE_ALIASING_POSSIBLE
869extern unsigned long xcall_flush_dcache_page_cheetah;
870#endif
871extern unsigned long xcall_flush_dcache_page_spitfire;
872
873static inline void __local_flush_dcache_page(struct page *page)
874{
875#ifdef DCACHE_ALIASING_POSSIBLE
876 __flush_dcache_page(page_address(page),
877 ((tlb_type == spitfire) &&
878 page_mapping(page) != NULL));
879#else
880 if (page_mapping(page) != NULL &&
881 tlb_type == spitfire)
882 __flush_icache_page(__pa(page_address(page)));
883#endif
884}
885
886void smp_flush_dcache_page_impl(struct page *page, int cpu)
887{
888 int this_cpu;
889
890 if (tlb_type == hypervisor)
891 return;
892
893#ifdef CONFIG_DEBUG_DCFLUSH
894 atomic_inc(&dcpage_flushes);
895#endif
896
897 this_cpu = get_cpu();
898
899 if (cpu == this_cpu) {
900 __local_flush_dcache_page(page);
901 } else if (cpu_online(cpu)) {
902 void *pg_addr = page_address(page);
903 u64 data0 = 0;
904
905 if (tlb_type == spitfire) {
906 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
907 if (page_mapping(page) != NULL)
908 data0 |= ((u64)1 << 32);
909 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
910#ifdef DCACHE_ALIASING_POSSIBLE
911 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
912#endif
913 }
914 if (data0) {
915 xcall_deliver(data0, __pa(pg_addr),
916 (u64) pg_addr, cpumask_of(cpu));
917#ifdef CONFIG_DEBUG_DCFLUSH
918 atomic_inc(&dcpage_flushes_xcall);
919#endif
920 }
921 }
922
923 put_cpu();
924}
925
926void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
927{
928 void *pg_addr;
929 u64 data0;
930
931 if (tlb_type == hypervisor)
932 return;
933
934 preempt_disable();
935
936#ifdef CONFIG_DEBUG_DCFLUSH
937 atomic_inc(&dcpage_flushes);
938#endif
939 data0 = 0;
940 pg_addr = page_address(page);
941 if (tlb_type == spitfire) {
942 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
943 if (page_mapping(page) != NULL)
944 data0 |= ((u64)1 << 32);
945 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
946#ifdef DCACHE_ALIASING_POSSIBLE
947 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
948#endif
949 }
950 if (data0) {
951 xcall_deliver(data0, __pa(pg_addr),
952 (u64) pg_addr, cpu_online_mask);
953#ifdef CONFIG_DEBUG_DCFLUSH
954 atomic_inc(&dcpage_flushes_xcall);
955#endif
956 }
957 __local_flush_dcache_page(page);
958
959 preempt_enable();
960}
961
962void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
963{
964 struct mm_struct *mm;
965 unsigned long flags;
966
967 clear_softint(1 << irq);
968
969 /* See if we need to allocate a new TLB context because
970 * the version of the one we are using is now out of date.
971 */
972 mm = current->active_mm;
973 if (unlikely(!mm || (mm == &init_mm)))
974 return;
975
976 spin_lock_irqsave(&mm->context.lock, flags);
977
978 if (unlikely(!CTX_VALID(mm->context)))
979 get_new_mmu_context(mm);
980
981 spin_unlock_irqrestore(&mm->context.lock, flags);
982
983 load_secondary_context(mm);
984 __flush_tlb_mm(CTX_HWBITS(mm->context),
985 SECONDARY_CONTEXT);
986}
987
988void smp_new_mmu_context_version(void)
989{
990 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
991}
992
993#ifdef CONFIG_KGDB
994void kgdb_roundup_cpus(unsigned long flags)
995{
996 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
997}
998#endif
999
1000void smp_fetch_global_regs(void)
1001{
1002 smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1003}
1004
1005void smp_fetch_global_pmu(void)
1006{
1007 if (tlb_type == hypervisor &&
1008 sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
1009 smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
1010 else
1011 smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
1012}
1013
1014/* We know that the window frames of the user have been flushed
1015 * to the stack before we get here because all callers of us
1016 * are flush_tlb_*() routines, and these run after flush_cache_*()
1017 * which performs the flushw.
1018 *
1019 * The SMP TLB coherency scheme we use works as follows:
1020 *
1021 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1022 * space has (potentially) executed on, this is the heuristic
1023 * we use to avoid doing cross calls.
1024 *
1025 * Also, for flushing from kswapd and also for clones, we
1026 * use cpu_vm_mask as the list of cpus to make run the TLB.
1027 *
1028 * 2) TLB context numbers are shared globally across all processors
1029 * in the system, this allows us to play several games to avoid
1030 * cross calls.
1031 *
1032 * One invariant is that when a cpu switches to a process, and
1033 * that processes tsk->active_mm->cpu_vm_mask does not have the
1034 * current cpu's bit set, that tlb context is flushed locally.
1035 *
1036 * If the address space is non-shared (ie. mm->count == 1) we avoid
1037 * cross calls when we want to flush the currently running process's
1038 * tlb state. This is done by clearing all cpu bits except the current
1039 * processor's in current->mm->cpu_vm_mask and performing the
1040 * flush locally only. This will force any subsequent cpus which run
1041 * this task to flush the context from the local tlb if the process
1042 * migrates to another cpu (again).
1043 *
1044 * 3) For shared address spaces (threads) and swapping we bite the
1045 * bullet for most cases and perform the cross call (but only to
1046 * the cpus listed in cpu_vm_mask).
1047 *
1048 * The performance gain from "optimizing" away the cross call for threads is
1049 * questionable (in theory the big win for threads is the massive sharing of
1050 * address space state across processors).
1051 */
1052
1053/* This currently is only used by the hugetlb arch pre-fault
1054 * hook on UltraSPARC-III+ and later when changing the pagesize
1055 * bits of the context register for an address space.
1056 */
1057void smp_flush_tlb_mm(struct mm_struct *mm)
1058{
1059 u32 ctx = CTX_HWBITS(mm->context);
1060 int cpu = get_cpu();
1061
1062 if (atomic_read(&mm->mm_users) == 1) {
1063 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1064 goto local_flush_and_out;
1065 }
1066
1067 smp_cross_call_masked(&xcall_flush_tlb_mm,
1068 ctx, 0, 0,
1069 mm_cpumask(mm));
1070
1071local_flush_and_out:
1072 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1073
1074 put_cpu();
1075}
1076
1077struct tlb_pending_info {
1078 unsigned long ctx;
1079 unsigned long nr;
1080 unsigned long *vaddrs;
1081};
1082
1083static void tlb_pending_func(void *info)
1084{
1085 struct tlb_pending_info *t = info;
1086
1087 __flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
1088}
1089
1090void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1091{
1092 u32 ctx = CTX_HWBITS(mm->context);
1093 struct tlb_pending_info info;
1094 int cpu = get_cpu();
1095
1096 info.ctx = ctx;
1097 info.nr = nr;
1098 info.vaddrs = vaddrs;
1099
1100 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1101 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1102 else
1103 smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
1104 &info, 1);
1105
1106 __flush_tlb_pending(ctx, nr, vaddrs);
1107
1108 put_cpu();
1109}
1110
1111void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
1112{
1113 unsigned long context = CTX_HWBITS(mm->context);
1114 int cpu = get_cpu();
1115
1116 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1117 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1118 else
1119 smp_cross_call_masked(&xcall_flush_tlb_page,
1120 context, vaddr, 0,
1121 mm_cpumask(mm));
1122 __flush_tlb_page(context, vaddr);
1123
1124 put_cpu();
1125}
1126
1127void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1128{
1129 start &= PAGE_MASK;
1130 end = PAGE_ALIGN(end);
1131 if (start != end) {
1132 smp_cross_call(&xcall_flush_tlb_kernel_range,
1133 0, start, end);
1134
1135 __flush_tlb_kernel_range(start, end);
1136 }
1137}
1138
1139/* CPU capture. */
1140/* #define CAPTURE_DEBUG */
1141extern unsigned long xcall_capture;
1142
1143static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1144static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1145static unsigned long penguins_are_doing_time;
1146
1147void smp_capture(void)
1148{
1149 int result = atomic_add_return(1, &smp_capture_depth);
1150
1151 if (result == 1) {
1152 int ncpus = num_online_cpus();
1153
1154#ifdef CAPTURE_DEBUG
1155 printk("CPU[%d]: Sending penguins to jail...",
1156 smp_processor_id());
1157#endif
1158 penguins_are_doing_time = 1;
1159 atomic_inc(&smp_capture_registry);
1160 smp_cross_call(&xcall_capture, 0, 0, 0);
1161 while (atomic_read(&smp_capture_registry) != ncpus)
1162 rmb();
1163#ifdef CAPTURE_DEBUG
1164 printk("done\n");
1165#endif
1166 }
1167}
1168
1169void smp_release(void)
1170{
1171 if (atomic_dec_and_test(&smp_capture_depth)) {
1172#ifdef CAPTURE_DEBUG
1173 printk("CPU[%d]: Giving pardon to "
1174 "imprisoned penguins\n",
1175 smp_processor_id());
1176#endif
1177 penguins_are_doing_time = 0;
1178 membar_safe("#StoreLoad");
1179 atomic_dec(&smp_capture_registry);
1180 }
1181}
1182
1183/* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1184 * set, so they can service tlb flush xcalls...
1185 */
1186extern void prom_world(int);
1187
1188void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
1189{
1190 clear_softint(1 << irq);
1191
1192 preempt_disable();
1193
1194 __asm__ __volatile__("flushw");
1195 prom_world(1);
1196 atomic_inc(&smp_capture_registry);
1197 membar_safe("#StoreLoad");
1198 while (penguins_are_doing_time)
1199 rmb();
1200 atomic_dec(&smp_capture_registry);
1201 prom_world(0);
1202
1203 preempt_enable();
1204}
1205
1206/* /proc/profile writes can call this, don't __init it please. */
1207int setup_profiling_timer(unsigned int multiplier)
1208{
1209 return -EINVAL;
1210}
1211
1212void __init smp_prepare_cpus(unsigned int max_cpus)
1213{
1214}
1215
1216void smp_prepare_boot_cpu(void)
1217{
1218}
1219
1220void __init smp_setup_processor_id(void)
1221{
1222 if (tlb_type == spitfire)
1223 xcall_deliver_impl = spitfire_xcall_deliver;
1224 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1225 xcall_deliver_impl = cheetah_xcall_deliver;
1226 else
1227 xcall_deliver_impl = hypervisor_xcall_deliver;
1228}
1229
1230void smp_fill_in_sib_core_maps(void)
1231{
1232 unsigned int i;
1233
1234 for_each_present_cpu(i) {
1235 unsigned int j;
1236
1237 cpumask_clear(&cpu_core_map[i]);
1238 if (cpu_data(i).core_id == 0) {
1239 cpumask_set_cpu(i, &cpu_core_map[i]);
1240 continue;
1241 }
1242
1243 for_each_present_cpu(j) {
1244 if (cpu_data(i).core_id ==
1245 cpu_data(j).core_id)
1246 cpumask_set_cpu(j, &cpu_core_map[i]);
1247 }
1248 }
1249
1250 for_each_present_cpu(i) {
1251 unsigned int j;
1252
1253 for_each_present_cpu(j) {
1254 if (cpu_data(i).sock_id == cpu_data(j).sock_id)
1255 cpumask_set_cpu(j, &cpu_core_sib_map[i]);
1256 }
1257 }
1258
1259 for_each_present_cpu(i) {
1260 unsigned int j;
1261
1262 cpumask_clear(&per_cpu(cpu_sibling_map, i));
1263 if (cpu_data(i).proc_id == -1) {
1264 cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
1265 continue;
1266 }
1267
1268 for_each_present_cpu(j) {
1269 if (cpu_data(i).proc_id ==
1270 cpu_data(j).proc_id)
1271 cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
1272 }
1273 }
1274}
1275
1276int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1277{
1278 int ret = smp_boot_one_cpu(cpu, tidle);
1279
1280 if (!ret) {
1281 cpumask_set_cpu(cpu, &smp_commenced_mask);
1282 while (!cpu_online(cpu))
1283 mb();
1284 if (!cpu_online(cpu)) {
1285 ret = -ENODEV;
1286 } else {
1287 /* On SUN4V, writes to %tick and %stick are
1288 * not allowed.
1289 */
1290 if (tlb_type != hypervisor)
1291 smp_synchronize_one_tick(cpu);
1292 }
1293 }
1294 return ret;
1295}
1296
1297#ifdef CONFIG_HOTPLUG_CPU
1298void cpu_play_dead(void)
1299{
1300 int cpu = smp_processor_id();
1301 unsigned long pstate;
1302
1303 idle_task_exit();
1304
1305 if (tlb_type == hypervisor) {
1306 struct trap_per_cpu *tb = &trap_block[cpu];
1307
1308 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1309 tb->cpu_mondo_pa, 0);
1310 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1311 tb->dev_mondo_pa, 0);
1312 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1313 tb->resum_mondo_pa, 0);
1314 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1315 tb->nonresum_mondo_pa, 0);
1316 }
1317
1318 cpumask_clear_cpu(cpu, &smp_commenced_mask);
1319 membar_safe("#Sync");
1320
1321 local_irq_disable();
1322
1323 __asm__ __volatile__(
1324 "rdpr %%pstate, %0\n\t"
1325 "wrpr %0, %1, %%pstate"
1326 : "=r" (pstate)
1327 : "i" (PSTATE_IE));
1328
1329 while (1)
1330 barrier();
1331}
1332
1333int __cpu_disable(void)
1334{
1335 int cpu = smp_processor_id();
1336 cpuinfo_sparc *c;
1337 int i;
1338
1339 for_each_cpu(i, &cpu_core_map[cpu])
1340 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
1341 cpumask_clear(&cpu_core_map[cpu]);
1342
1343 for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
1344 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
1345 cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
1346
1347 c = &cpu_data(cpu);
1348
1349 c->core_id = 0;
1350 c->proc_id = -1;
1351
1352 smp_wmb();
1353
1354 /* Make sure no interrupts point to this cpu. */
1355 fixup_irqs();
1356
1357 local_irq_enable();
1358 mdelay(1);
1359 local_irq_disable();
1360
1361 set_cpu_online(cpu, false);
1362
1363 cpu_map_rebuild();
1364
1365 return 0;
1366}
1367
1368void __cpu_die(unsigned int cpu)
1369{
1370 int i;
1371
1372 for (i = 0; i < 100; i++) {
1373 smp_rmb();
1374 if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
1375 break;
1376 msleep(100);
1377 }
1378 if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
1379 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1380 } else {
1381#if defined(CONFIG_SUN_LDOMS)
1382 unsigned long hv_err;
1383 int limit = 100;
1384
1385 do {
1386 hv_err = sun4v_cpu_stop(cpu);
1387 if (hv_err == HV_EOK) {
1388 set_cpu_present(cpu, false);
1389 break;
1390 }
1391 } while (--limit > 0);
1392 if (limit <= 0) {
1393 printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1394 hv_err);
1395 }
1396#endif
1397 }
1398}
1399#endif
1400
1401void __init smp_cpus_done(unsigned int max_cpus)
1402{
1403}
1404
1405void smp_send_reschedule(int cpu)
1406{
1407 if (cpu == smp_processor_id()) {
1408 WARN_ON_ONCE(preemptible());
1409 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
1410 } else {
1411 xcall_deliver((u64) &xcall_receive_signal,
1412 0, 0, cpumask_of(cpu));
1413 }
1414}
1415
1416void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
1417{
1418 clear_softint(1 << irq);
1419 scheduler_ipi();
1420}
1421
1422static void stop_this_cpu(void *dummy)
1423{
1424 prom_stopself();
1425}
1426
1427void smp_send_stop(void)
1428{
1429 int cpu;
1430
1431 if (tlb_type == hypervisor) {
1432 for_each_online_cpu(cpu) {
1433 if (cpu == smp_processor_id())
1434 continue;
1435#ifdef CONFIG_SUN_LDOMS
1436 if (ldom_domaining_enabled) {
1437 unsigned long hv_err;
1438 hv_err = sun4v_cpu_stop(cpu);
1439 if (hv_err)
1440 printk(KERN_ERR "sun4v_cpu_stop() "
1441 "failed err=%lu\n", hv_err);
1442 } else
1443#endif
1444 prom_stopcpu_cpuid(cpu);
1445 }
1446 } else
1447 smp_call_function(stop_this_cpu, NULL, 0);
1448}
1449
1450/**
1451 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1452 * @cpu: cpu to allocate for
1453 * @size: size allocation in bytes
1454 * @align: alignment
1455 *
1456 * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper
1457 * does the right thing for NUMA regardless of the current
1458 * configuration.
1459 *
1460 * RETURNS:
1461 * Pointer to the allocated area on success, NULL on failure.
1462 */
1463static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size,
1464 size_t align)
1465{
1466 const unsigned long goal = __pa(MAX_DMA_ADDRESS);
1467#ifdef CONFIG_NEED_MULTIPLE_NODES
1468 int node = cpu_to_node(cpu);
1469 void *ptr;
1470
1471 if (!node_online(node) || !NODE_DATA(node)) {
1472 ptr = __alloc_bootmem(size, align, goal);
1473 pr_info("cpu %d has no node %d or node-local memory\n",
1474 cpu, node);
1475 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1476 cpu, size, __pa(ptr));
1477 } else {
1478 ptr = __alloc_bootmem_node(NODE_DATA(node),
1479 size, align, goal);
1480 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1481 "%016lx\n", cpu, size, node, __pa(ptr));
1482 }
1483 return ptr;
1484#else
1485 return __alloc_bootmem(size, align, goal);
1486#endif
1487}
1488
1489static void __init pcpu_free_bootmem(void *ptr, size_t size)
1490{
1491 free_bootmem(__pa(ptr), size);
1492}
1493
1494static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1495{
1496 if (cpu_to_node(from) == cpu_to_node(to))
1497 return LOCAL_DISTANCE;
1498 else
1499 return REMOTE_DISTANCE;
1500}
1501
1502static void __init pcpu_populate_pte(unsigned long addr)
1503{
1504 pgd_t *pgd = pgd_offset_k(addr);
1505 pud_t *pud;
1506 pmd_t *pmd;
1507
1508 if (pgd_none(*pgd)) {
1509 pud_t *new;
1510
1511 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1512 pgd_populate(&init_mm, pgd, new);
1513 }
1514
1515 pud = pud_offset(pgd, addr);
1516 if (pud_none(*pud)) {
1517 pmd_t *new;
1518
1519 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1520 pud_populate(&init_mm, pud, new);
1521 }
1522
1523 pmd = pmd_offset(pud, addr);
1524 if (!pmd_present(*pmd)) {
1525 pte_t *new;
1526
1527 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1528 pmd_populate_kernel(&init_mm, pmd, new);
1529 }
1530}
1531
1532void __init setup_per_cpu_areas(void)
1533{
1534 unsigned long delta;
1535 unsigned int cpu;
1536 int rc = -EINVAL;
1537
1538 if (pcpu_chosen_fc != PCPU_FC_PAGE) {
1539 rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
1540 PERCPU_DYNAMIC_RESERVE, 4 << 20,
1541 pcpu_cpu_distance,
1542 pcpu_alloc_bootmem,
1543 pcpu_free_bootmem);
1544 if (rc)
1545 pr_warning("PERCPU: %s allocator failed (%d), "
1546 "falling back to page size\n",
1547 pcpu_fc_names[pcpu_chosen_fc], rc);
1548 }
1549 if (rc < 0)
1550 rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
1551 pcpu_alloc_bootmem,
1552 pcpu_free_bootmem,
1553 pcpu_populate_pte);
1554 if (rc < 0)
1555 panic("cannot initialize percpu area (err=%d)", rc);
1556
1557 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1558 for_each_possible_cpu(cpu)
1559 __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1560
1561 /* Setup %g5 for the boot cpu. */
1562 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1563
1564 of_fill_in_cpu_data();
1565 if (tlb_type == hypervisor)
1566 mdesc_fill_in_cpu_data(cpu_all_mask);
1567}
1/* smp.c: Sparc64 SMP support.
2 *
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/export.h>
7#include <linux/kernel.h>
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <linux/pagemap.h>
11#include <linux/threads.h>
12#include <linux/smp.h>
13#include <linux/interrupt.h>
14#include <linux/kernel_stat.h>
15#include <linux/delay.h>
16#include <linux/init.h>
17#include <linux/spinlock.h>
18#include <linux/fs.h>
19#include <linux/seq_file.h>
20#include <linux/cache.h>
21#include <linux/jiffies.h>
22#include <linux/profile.h>
23#include <linux/bootmem.h>
24#include <linux/vmalloc.h>
25#include <linux/ftrace.h>
26#include <linux/cpu.h>
27#include <linux/slab.h>
28
29#include <asm/head.h>
30#include <asm/ptrace.h>
31#include <linux/atomic.h>
32#include <asm/tlbflush.h>
33#include <asm/mmu_context.h>
34#include <asm/cpudata.h>
35#include <asm/hvtramp.h>
36#include <asm/io.h>
37#include <asm/timer.h>
38
39#include <asm/irq.h>
40#include <asm/irq_regs.h>
41#include <asm/page.h>
42#include <asm/pgtable.h>
43#include <asm/oplib.h>
44#include <asm/uaccess.h>
45#include <asm/starfire.h>
46#include <asm/tlb.h>
47#include <asm/sections.h>
48#include <asm/prom.h>
49#include <asm/mdesc.h>
50#include <asm/ldc.h>
51#include <asm/hypervisor.h>
52#include <asm/pcr.h>
53
54#include "cpumap.h"
55
56DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
57cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
58 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
59
60EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
61EXPORT_SYMBOL(cpu_core_map);
62
63static cpumask_t smp_commenced_mask;
64
65void smp_info(struct seq_file *m)
66{
67 int i;
68
69 seq_printf(m, "State:\n");
70 for_each_online_cpu(i)
71 seq_printf(m, "CPU%d:\t\tonline\n", i);
72}
73
74void smp_bogo(struct seq_file *m)
75{
76 int i;
77
78 for_each_online_cpu(i)
79 seq_printf(m,
80 "Cpu%dClkTck\t: %016lx\n",
81 i, cpu_data(i).clock_tick);
82}
83
84extern void setup_sparc64_timer(void);
85
86static volatile unsigned long callin_flag = 0;
87
88void smp_callin(void)
89{
90 int cpuid = hard_smp_processor_id();
91
92 __local_per_cpu_offset = __per_cpu_offset(cpuid);
93
94 if (tlb_type == hypervisor)
95 sun4v_ktsb_register();
96
97 __flush_tlb_all();
98
99 setup_sparc64_timer();
100
101 if (cheetah_pcache_forced_on)
102 cheetah_enable_pcache();
103
104 callin_flag = 1;
105 __asm__ __volatile__("membar #Sync\n\t"
106 "flush %%g6" : : : "memory");
107
108 /* Clear this or we will die instantly when we
109 * schedule back to this idler...
110 */
111 current_thread_info()->new_child = 0;
112
113 /* Attach to the address space of init_task. */
114 atomic_inc(&init_mm.mm_count);
115 current->active_mm = &init_mm;
116
117 /* inform the notifiers about the new cpu */
118 notify_cpu_starting(cpuid);
119
120 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
121 rmb();
122
123 set_cpu_online(cpuid, true);
124
125 /* idle thread is expected to have preempt disabled */
126 preempt_disable();
127
128 local_irq_enable();
129
130 cpu_startup_entry(CPUHP_ONLINE);
131}
132
133void cpu_panic(void)
134{
135 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
136 panic("SMP bolixed\n");
137}
138
139/* This tick register synchronization scheme is taken entirely from
140 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
141 *
142 * The only change I've made is to rework it so that the master
143 * initiates the synchonization instead of the slave. -DaveM
144 */
145
146#define MASTER 0
147#define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
148
149#define NUM_ROUNDS 64 /* magic value */
150#define NUM_ITERS 5 /* likewise */
151
152static DEFINE_RAW_SPINLOCK(itc_sync_lock);
153static unsigned long go[SLAVE + 1];
154
155#define DEBUG_TICK_SYNC 0
156
157static inline long get_delta (long *rt, long *master)
158{
159 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
160 unsigned long tcenter, t0, t1, tm;
161 unsigned long i;
162
163 for (i = 0; i < NUM_ITERS; i++) {
164 t0 = tick_ops->get_tick();
165 go[MASTER] = 1;
166 membar_safe("#StoreLoad");
167 while (!(tm = go[SLAVE]))
168 rmb();
169 go[SLAVE] = 0;
170 wmb();
171 t1 = tick_ops->get_tick();
172
173 if (t1 - t0 < best_t1 - best_t0)
174 best_t0 = t0, best_t1 = t1, best_tm = tm;
175 }
176
177 *rt = best_t1 - best_t0;
178 *master = best_tm - best_t0;
179
180 /* average best_t0 and best_t1 without overflow: */
181 tcenter = (best_t0/2 + best_t1/2);
182 if (best_t0 % 2 + best_t1 % 2 == 2)
183 tcenter++;
184 return tcenter - best_tm;
185}
186
187void smp_synchronize_tick_client(void)
188{
189 long i, delta, adj, adjust_latency = 0, done = 0;
190 unsigned long flags, rt, master_time_stamp;
191#if DEBUG_TICK_SYNC
192 struct {
193 long rt; /* roundtrip time */
194 long master; /* master's timestamp */
195 long diff; /* difference between midpoint and master's timestamp */
196 long lat; /* estimate of itc adjustment latency */
197 } t[NUM_ROUNDS];
198#endif
199
200 go[MASTER] = 1;
201
202 while (go[MASTER])
203 rmb();
204
205 local_irq_save(flags);
206 {
207 for (i = 0; i < NUM_ROUNDS; i++) {
208 delta = get_delta(&rt, &master_time_stamp);
209 if (delta == 0)
210 done = 1; /* let's lock on to this... */
211
212 if (!done) {
213 if (i > 0) {
214 adjust_latency += -delta;
215 adj = -delta + adjust_latency/4;
216 } else
217 adj = -delta;
218
219 tick_ops->add_tick(adj);
220 }
221#if DEBUG_TICK_SYNC
222 t[i].rt = rt;
223 t[i].master = master_time_stamp;
224 t[i].diff = delta;
225 t[i].lat = adjust_latency/4;
226#endif
227 }
228 }
229 local_irq_restore(flags);
230
231#if DEBUG_TICK_SYNC
232 for (i = 0; i < NUM_ROUNDS; i++)
233 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
234 t[i].rt, t[i].master, t[i].diff, t[i].lat);
235#endif
236
237 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
238 "(last diff %ld cycles, maxerr %lu cycles)\n",
239 smp_processor_id(), delta, rt);
240}
241
242static void smp_start_sync_tick_client(int cpu);
243
244static void smp_synchronize_one_tick(int cpu)
245{
246 unsigned long flags, i;
247
248 go[MASTER] = 0;
249
250 smp_start_sync_tick_client(cpu);
251
252 /* wait for client to be ready */
253 while (!go[MASTER])
254 rmb();
255
256 /* now let the client proceed into his loop */
257 go[MASTER] = 0;
258 membar_safe("#StoreLoad");
259
260 raw_spin_lock_irqsave(&itc_sync_lock, flags);
261 {
262 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
263 while (!go[MASTER])
264 rmb();
265 go[MASTER] = 0;
266 wmb();
267 go[SLAVE] = tick_ops->get_tick();
268 membar_safe("#StoreLoad");
269 }
270 }
271 raw_spin_unlock_irqrestore(&itc_sync_lock, flags);
272}
273
274#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
275/* XXX Put this in some common place. XXX */
276static unsigned long kimage_addr_to_ra(void *p)
277{
278 unsigned long val = (unsigned long) p;
279
280 return kern_base + (val - KERNBASE);
281}
282
283static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg,
284 void **descrp)
285{
286 extern unsigned long sparc64_ttable_tl0;
287 extern unsigned long kern_locked_tte_data;
288 struct hvtramp_descr *hdesc;
289 unsigned long trampoline_ra;
290 struct trap_per_cpu *tb;
291 u64 tte_vaddr, tte_data;
292 unsigned long hv_err;
293 int i;
294
295 hdesc = kzalloc(sizeof(*hdesc) +
296 (sizeof(struct hvtramp_mapping) *
297 num_kernel_image_mappings - 1),
298 GFP_KERNEL);
299 if (!hdesc) {
300 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
301 "hvtramp_descr.\n");
302 return;
303 }
304 *descrp = hdesc;
305
306 hdesc->cpu = cpu;
307 hdesc->num_mappings = num_kernel_image_mappings;
308
309 tb = &trap_block[cpu];
310
311 hdesc->fault_info_va = (unsigned long) &tb->fault_info;
312 hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
313
314 hdesc->thread_reg = thread_reg;
315
316 tte_vaddr = (unsigned long) KERNBASE;
317 tte_data = kern_locked_tte_data;
318
319 for (i = 0; i < hdesc->num_mappings; i++) {
320 hdesc->maps[i].vaddr = tte_vaddr;
321 hdesc->maps[i].tte = tte_data;
322 tte_vaddr += 0x400000;
323 tte_data += 0x400000;
324 }
325
326 trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
327
328 hv_err = sun4v_cpu_start(cpu, trampoline_ra,
329 kimage_addr_to_ra(&sparc64_ttable_tl0),
330 __pa(hdesc));
331 if (hv_err)
332 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
333 "gives error %lu\n", hv_err);
334}
335#endif
336
337extern unsigned long sparc64_cpu_startup;
338
339/* The OBP cpu startup callback truncates the 3rd arg cookie to
340 * 32-bits (I think) so to be safe we have it read the pointer
341 * contained here so we work on >4GB machines. -DaveM
342 */
343static struct thread_info *cpu_new_thread = NULL;
344
345static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
346{
347 unsigned long entry =
348 (unsigned long)(&sparc64_cpu_startup);
349 unsigned long cookie =
350 (unsigned long)(&cpu_new_thread);
351 void *descr = NULL;
352 int timeout, ret;
353
354 callin_flag = 0;
355 cpu_new_thread = task_thread_info(idle);
356
357 if (tlb_type == hypervisor) {
358#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
359 if (ldom_domaining_enabled)
360 ldom_startcpu_cpuid(cpu,
361 (unsigned long) cpu_new_thread,
362 &descr);
363 else
364#endif
365 prom_startcpu_cpuid(cpu, entry, cookie);
366 } else {
367 struct device_node *dp = of_find_node_by_cpuid(cpu);
368
369 prom_startcpu(dp->phandle, entry, cookie);
370 }
371
372 for (timeout = 0; timeout < 50000; timeout++) {
373 if (callin_flag)
374 break;
375 udelay(100);
376 }
377
378 if (callin_flag) {
379 ret = 0;
380 } else {
381 printk("Processor %d is stuck.\n", cpu);
382 ret = -ENODEV;
383 }
384 cpu_new_thread = NULL;
385
386 kfree(descr);
387
388 return ret;
389}
390
391static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
392{
393 u64 result, target;
394 int stuck, tmp;
395
396 if (this_is_starfire) {
397 /* map to real upaid */
398 cpu = (((cpu & 0x3c) << 1) |
399 ((cpu & 0x40) >> 4) |
400 (cpu & 0x3));
401 }
402
403 target = (cpu << 14) | 0x70;
404again:
405 /* Ok, this is the real Spitfire Errata #54.
406 * One must read back from a UDB internal register
407 * after writes to the UDB interrupt dispatch, but
408 * before the membar Sync for that write.
409 * So we use the high UDB control register (ASI 0x7f,
410 * ADDR 0x20) for the dummy read. -DaveM
411 */
412 tmp = 0x40;
413 __asm__ __volatile__(
414 "wrpr %1, %2, %%pstate\n\t"
415 "stxa %4, [%0] %3\n\t"
416 "stxa %5, [%0+%8] %3\n\t"
417 "add %0, %8, %0\n\t"
418 "stxa %6, [%0+%8] %3\n\t"
419 "membar #Sync\n\t"
420 "stxa %%g0, [%7] %3\n\t"
421 "membar #Sync\n\t"
422 "mov 0x20, %%g1\n\t"
423 "ldxa [%%g1] 0x7f, %%g0\n\t"
424 "membar #Sync"
425 : "=r" (tmp)
426 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
427 "r" (data0), "r" (data1), "r" (data2), "r" (target),
428 "r" (0x10), "0" (tmp)
429 : "g1");
430
431 /* NOTE: PSTATE_IE is still clear. */
432 stuck = 100000;
433 do {
434 __asm__ __volatile__("ldxa [%%g0] %1, %0"
435 : "=r" (result)
436 : "i" (ASI_INTR_DISPATCH_STAT));
437 if (result == 0) {
438 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
439 : : "r" (pstate));
440 return;
441 }
442 stuck -= 1;
443 if (stuck == 0)
444 break;
445 } while (result & 0x1);
446 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
447 : : "r" (pstate));
448 if (stuck == 0) {
449 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
450 smp_processor_id(), result);
451 } else {
452 udelay(2);
453 goto again;
454 }
455}
456
457static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
458{
459 u64 *mondo, data0, data1, data2;
460 u16 *cpu_list;
461 u64 pstate;
462 int i;
463
464 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
465 cpu_list = __va(tb->cpu_list_pa);
466 mondo = __va(tb->cpu_mondo_block_pa);
467 data0 = mondo[0];
468 data1 = mondo[1];
469 data2 = mondo[2];
470 for (i = 0; i < cnt; i++)
471 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
472}
473
474/* Cheetah now allows to send the whole 64-bytes of data in the interrupt
475 * packet, but we have no use for that. However we do take advantage of
476 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
477 */
478static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
479{
480 int nack_busy_id, is_jbus, need_more;
481 u64 *mondo, pstate, ver, busy_mask;
482 u16 *cpu_list;
483
484 cpu_list = __va(tb->cpu_list_pa);
485 mondo = __va(tb->cpu_mondo_block_pa);
486
487 /* Unfortunately, someone at Sun had the brilliant idea to make the
488 * busy/nack fields hard-coded by ITID number for this Ultra-III
489 * derivative processor.
490 */
491 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
492 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
493 (ver >> 32) == __SERRANO_ID);
494
495 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
496
497retry:
498 need_more = 0;
499 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
500 : : "r" (pstate), "i" (PSTATE_IE));
501
502 /* Setup the dispatch data registers. */
503 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
504 "stxa %1, [%4] %6\n\t"
505 "stxa %2, [%5] %6\n\t"
506 "membar #Sync\n\t"
507 : /* no outputs */
508 : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
509 "r" (0x40), "r" (0x50), "r" (0x60),
510 "i" (ASI_INTR_W));
511
512 nack_busy_id = 0;
513 busy_mask = 0;
514 {
515 int i;
516
517 for (i = 0; i < cnt; i++) {
518 u64 target, nr;
519
520 nr = cpu_list[i];
521 if (nr == 0xffff)
522 continue;
523
524 target = (nr << 14) | 0x70;
525 if (is_jbus) {
526 busy_mask |= (0x1UL << (nr * 2));
527 } else {
528 target |= (nack_busy_id << 24);
529 busy_mask |= (0x1UL <<
530 (nack_busy_id * 2));
531 }
532 __asm__ __volatile__(
533 "stxa %%g0, [%0] %1\n\t"
534 "membar #Sync\n\t"
535 : /* no outputs */
536 : "r" (target), "i" (ASI_INTR_W));
537 nack_busy_id++;
538 if (nack_busy_id == 32) {
539 need_more = 1;
540 break;
541 }
542 }
543 }
544
545 /* Now, poll for completion. */
546 {
547 u64 dispatch_stat, nack_mask;
548 long stuck;
549
550 stuck = 100000 * nack_busy_id;
551 nack_mask = busy_mask << 1;
552 do {
553 __asm__ __volatile__("ldxa [%%g0] %1, %0"
554 : "=r" (dispatch_stat)
555 : "i" (ASI_INTR_DISPATCH_STAT));
556 if (!(dispatch_stat & (busy_mask | nack_mask))) {
557 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
558 : : "r" (pstate));
559 if (unlikely(need_more)) {
560 int i, this_cnt = 0;
561 for (i = 0; i < cnt; i++) {
562 if (cpu_list[i] == 0xffff)
563 continue;
564 cpu_list[i] = 0xffff;
565 this_cnt++;
566 if (this_cnt == 32)
567 break;
568 }
569 goto retry;
570 }
571 return;
572 }
573 if (!--stuck)
574 break;
575 } while (dispatch_stat & busy_mask);
576
577 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
578 : : "r" (pstate));
579
580 if (dispatch_stat & busy_mask) {
581 /* Busy bits will not clear, continue instead
582 * of freezing up on this cpu.
583 */
584 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
585 smp_processor_id(), dispatch_stat);
586 } else {
587 int i, this_busy_nack = 0;
588
589 /* Delay some random time with interrupts enabled
590 * to prevent deadlock.
591 */
592 udelay(2 * nack_busy_id);
593
594 /* Clear out the mask bits for cpus which did not
595 * NACK us.
596 */
597 for (i = 0; i < cnt; i++) {
598 u64 check_mask, nr;
599
600 nr = cpu_list[i];
601 if (nr == 0xffff)
602 continue;
603
604 if (is_jbus)
605 check_mask = (0x2UL << (2*nr));
606 else
607 check_mask = (0x2UL <<
608 this_busy_nack);
609 if ((dispatch_stat & check_mask) == 0)
610 cpu_list[i] = 0xffff;
611 this_busy_nack += 2;
612 if (this_busy_nack == 64)
613 break;
614 }
615
616 goto retry;
617 }
618 }
619}
620
621/* Multi-cpu list version. */
622static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
623{
624 int retries, this_cpu, prev_sent, i, saw_cpu_error;
625 unsigned long status;
626 u16 *cpu_list;
627
628 this_cpu = smp_processor_id();
629
630 cpu_list = __va(tb->cpu_list_pa);
631
632 saw_cpu_error = 0;
633 retries = 0;
634 prev_sent = 0;
635 do {
636 int forward_progress, n_sent;
637
638 status = sun4v_cpu_mondo_send(cnt,
639 tb->cpu_list_pa,
640 tb->cpu_mondo_block_pa);
641
642 /* HV_EOK means all cpus received the xcall, we're done. */
643 if (likely(status == HV_EOK))
644 break;
645
646 /* First, see if we made any forward progress.
647 *
648 * The hypervisor indicates successful sends by setting
649 * cpu list entries to the value 0xffff.
650 */
651 n_sent = 0;
652 for (i = 0; i < cnt; i++) {
653 if (likely(cpu_list[i] == 0xffff))
654 n_sent++;
655 }
656
657 forward_progress = 0;
658 if (n_sent > prev_sent)
659 forward_progress = 1;
660
661 prev_sent = n_sent;
662
663 /* If we get a HV_ECPUERROR, then one or more of the cpus
664 * in the list are in error state. Use the cpu_state()
665 * hypervisor call to find out which cpus are in error state.
666 */
667 if (unlikely(status == HV_ECPUERROR)) {
668 for (i = 0; i < cnt; i++) {
669 long err;
670 u16 cpu;
671
672 cpu = cpu_list[i];
673 if (cpu == 0xffff)
674 continue;
675
676 err = sun4v_cpu_state(cpu);
677 if (err == HV_CPU_STATE_ERROR) {
678 saw_cpu_error = (cpu + 1);
679 cpu_list[i] = 0xffff;
680 }
681 }
682 } else if (unlikely(status != HV_EWOULDBLOCK))
683 goto fatal_mondo_error;
684
685 /* Don't bother rewriting the CPU list, just leave the
686 * 0xffff and non-0xffff entries in there and the
687 * hypervisor will do the right thing.
688 *
689 * Only advance timeout state if we didn't make any
690 * forward progress.
691 */
692 if (unlikely(!forward_progress)) {
693 if (unlikely(++retries > 10000))
694 goto fatal_mondo_timeout;
695
696 /* Delay a little bit to let other cpus catch up
697 * on their cpu mondo queue work.
698 */
699 udelay(2 * cnt);
700 }
701 } while (1);
702
703 if (unlikely(saw_cpu_error))
704 goto fatal_mondo_cpu_error;
705
706 return;
707
708fatal_mondo_cpu_error:
709 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
710 "(including %d) were in error state\n",
711 this_cpu, saw_cpu_error - 1);
712 return;
713
714fatal_mondo_timeout:
715 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
716 " progress after %d retries.\n",
717 this_cpu, retries);
718 goto dump_cpu_list_and_out;
719
720fatal_mondo_error:
721 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
722 this_cpu, status);
723 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
724 "mondo_block_pa(%lx)\n",
725 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
726
727dump_cpu_list_and_out:
728 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
729 for (i = 0; i < cnt; i++)
730 printk("%u ", cpu_list[i]);
731 printk("]\n");
732}
733
734static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
735
736static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
737{
738 struct trap_per_cpu *tb;
739 int this_cpu, i, cnt;
740 unsigned long flags;
741 u16 *cpu_list;
742 u64 *mondo;
743
744 /* We have to do this whole thing with interrupts fully disabled.
745 * Otherwise if we send an xcall from interrupt context it will
746 * corrupt both our mondo block and cpu list state.
747 *
748 * One consequence of this is that we cannot use timeout mechanisms
749 * that depend upon interrupts being delivered locally. So, for
750 * example, we cannot sample jiffies and expect it to advance.
751 *
752 * Fortunately, udelay() uses %stick/%tick so we can use that.
753 */
754 local_irq_save(flags);
755
756 this_cpu = smp_processor_id();
757 tb = &trap_block[this_cpu];
758
759 mondo = __va(tb->cpu_mondo_block_pa);
760 mondo[0] = data0;
761 mondo[1] = data1;
762 mondo[2] = data2;
763 wmb();
764
765 cpu_list = __va(tb->cpu_list_pa);
766
767 /* Setup the initial cpu list. */
768 cnt = 0;
769 for_each_cpu(i, mask) {
770 if (i == this_cpu || !cpu_online(i))
771 continue;
772 cpu_list[cnt++] = i;
773 }
774
775 if (cnt)
776 xcall_deliver_impl(tb, cnt);
777
778 local_irq_restore(flags);
779}
780
781/* Send cross call to all processors mentioned in MASK_P
782 * except self. Really, there are only two cases currently,
783 * "cpu_online_mask" and "mm_cpumask(mm)".
784 */
785static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
786{
787 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
788
789 xcall_deliver(data0, data1, data2, mask);
790}
791
792/* Send cross call to all processors except self. */
793static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
794{
795 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
796}
797
798extern unsigned long xcall_sync_tick;
799
800static void smp_start_sync_tick_client(int cpu)
801{
802 xcall_deliver((u64) &xcall_sync_tick, 0, 0,
803 cpumask_of(cpu));
804}
805
806extern unsigned long xcall_call_function;
807
808void arch_send_call_function_ipi_mask(const struct cpumask *mask)
809{
810 xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
811}
812
813extern unsigned long xcall_call_function_single;
814
815void arch_send_call_function_single_ipi(int cpu)
816{
817 xcall_deliver((u64) &xcall_call_function_single, 0, 0,
818 cpumask_of(cpu));
819}
820
821void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
822{
823 clear_softint(1 << irq);
824 generic_smp_call_function_interrupt();
825}
826
827void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
828{
829 clear_softint(1 << irq);
830 generic_smp_call_function_single_interrupt();
831}
832
833static void tsb_sync(void *info)
834{
835 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
836 struct mm_struct *mm = info;
837
838 /* It is not valid to test "current->active_mm == mm" here.
839 *
840 * The value of "current" is not changed atomically with
841 * switch_mm(). But that's OK, we just need to check the
842 * current cpu's trap block PGD physical address.
843 */
844 if (tp->pgd_paddr == __pa(mm->pgd))
845 tsb_context_switch(mm);
846}
847
848void smp_tsb_sync(struct mm_struct *mm)
849{
850 smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
851}
852
853extern unsigned long xcall_flush_tlb_mm;
854extern unsigned long xcall_flush_tlb_page;
855extern unsigned long xcall_flush_tlb_kernel_range;
856extern unsigned long xcall_fetch_glob_regs;
857extern unsigned long xcall_fetch_glob_pmu;
858extern unsigned long xcall_fetch_glob_pmu_n4;
859extern unsigned long xcall_receive_signal;
860extern unsigned long xcall_new_mmu_context_version;
861#ifdef CONFIG_KGDB
862extern unsigned long xcall_kgdb_capture;
863#endif
864
865#ifdef DCACHE_ALIASING_POSSIBLE
866extern unsigned long xcall_flush_dcache_page_cheetah;
867#endif
868extern unsigned long xcall_flush_dcache_page_spitfire;
869
870#ifdef CONFIG_DEBUG_DCFLUSH
871extern atomic_t dcpage_flushes;
872extern atomic_t dcpage_flushes_xcall;
873#endif
874
875static inline void __local_flush_dcache_page(struct page *page)
876{
877#ifdef DCACHE_ALIASING_POSSIBLE
878 __flush_dcache_page(page_address(page),
879 ((tlb_type == spitfire) &&
880 page_mapping(page) != NULL));
881#else
882 if (page_mapping(page) != NULL &&
883 tlb_type == spitfire)
884 __flush_icache_page(__pa(page_address(page)));
885#endif
886}
887
888void smp_flush_dcache_page_impl(struct page *page, int cpu)
889{
890 int this_cpu;
891
892 if (tlb_type == hypervisor)
893 return;
894
895#ifdef CONFIG_DEBUG_DCFLUSH
896 atomic_inc(&dcpage_flushes);
897#endif
898
899 this_cpu = get_cpu();
900
901 if (cpu == this_cpu) {
902 __local_flush_dcache_page(page);
903 } else if (cpu_online(cpu)) {
904 void *pg_addr = page_address(page);
905 u64 data0 = 0;
906
907 if (tlb_type == spitfire) {
908 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
909 if (page_mapping(page) != NULL)
910 data0 |= ((u64)1 << 32);
911 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
912#ifdef DCACHE_ALIASING_POSSIBLE
913 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
914#endif
915 }
916 if (data0) {
917 xcall_deliver(data0, __pa(pg_addr),
918 (u64) pg_addr, cpumask_of(cpu));
919#ifdef CONFIG_DEBUG_DCFLUSH
920 atomic_inc(&dcpage_flushes_xcall);
921#endif
922 }
923 }
924
925 put_cpu();
926}
927
928void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
929{
930 void *pg_addr;
931 u64 data0;
932
933 if (tlb_type == hypervisor)
934 return;
935
936 preempt_disable();
937
938#ifdef CONFIG_DEBUG_DCFLUSH
939 atomic_inc(&dcpage_flushes);
940#endif
941 data0 = 0;
942 pg_addr = page_address(page);
943 if (tlb_type == spitfire) {
944 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
945 if (page_mapping(page) != NULL)
946 data0 |= ((u64)1 << 32);
947 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
948#ifdef DCACHE_ALIASING_POSSIBLE
949 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
950#endif
951 }
952 if (data0) {
953 xcall_deliver(data0, __pa(pg_addr),
954 (u64) pg_addr, cpu_online_mask);
955#ifdef CONFIG_DEBUG_DCFLUSH
956 atomic_inc(&dcpage_flushes_xcall);
957#endif
958 }
959 __local_flush_dcache_page(page);
960
961 preempt_enable();
962}
963
964void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
965{
966 struct mm_struct *mm;
967 unsigned long flags;
968
969 clear_softint(1 << irq);
970
971 /* See if we need to allocate a new TLB context because
972 * the version of the one we are using is now out of date.
973 */
974 mm = current->active_mm;
975 if (unlikely(!mm || (mm == &init_mm)))
976 return;
977
978 spin_lock_irqsave(&mm->context.lock, flags);
979
980 if (unlikely(!CTX_VALID(mm->context)))
981 get_new_mmu_context(mm);
982
983 spin_unlock_irqrestore(&mm->context.lock, flags);
984
985 load_secondary_context(mm);
986 __flush_tlb_mm(CTX_HWBITS(mm->context),
987 SECONDARY_CONTEXT);
988}
989
990void smp_new_mmu_context_version(void)
991{
992 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
993}
994
995#ifdef CONFIG_KGDB
996void kgdb_roundup_cpus(unsigned long flags)
997{
998 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
999}
1000#endif
1001
1002void smp_fetch_global_regs(void)
1003{
1004 smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1005}
1006
1007void smp_fetch_global_pmu(void)
1008{
1009 if (tlb_type == hypervisor &&
1010 sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
1011 smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
1012 else
1013 smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
1014}
1015
1016/* We know that the window frames of the user have been flushed
1017 * to the stack before we get here because all callers of us
1018 * are flush_tlb_*() routines, and these run after flush_cache_*()
1019 * which performs the flushw.
1020 *
1021 * The SMP TLB coherency scheme we use works as follows:
1022 *
1023 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1024 * space has (potentially) executed on, this is the heuristic
1025 * we use to avoid doing cross calls.
1026 *
1027 * Also, for flushing from kswapd and also for clones, we
1028 * use cpu_vm_mask as the list of cpus to make run the TLB.
1029 *
1030 * 2) TLB context numbers are shared globally across all processors
1031 * in the system, this allows us to play several games to avoid
1032 * cross calls.
1033 *
1034 * One invariant is that when a cpu switches to a process, and
1035 * that processes tsk->active_mm->cpu_vm_mask does not have the
1036 * current cpu's bit set, that tlb context is flushed locally.
1037 *
1038 * If the address space is non-shared (ie. mm->count == 1) we avoid
1039 * cross calls when we want to flush the currently running process's
1040 * tlb state. This is done by clearing all cpu bits except the current
1041 * processor's in current->mm->cpu_vm_mask and performing the
1042 * flush locally only. This will force any subsequent cpus which run
1043 * this task to flush the context from the local tlb if the process
1044 * migrates to another cpu (again).
1045 *
1046 * 3) For shared address spaces (threads) and swapping we bite the
1047 * bullet for most cases and perform the cross call (but only to
1048 * the cpus listed in cpu_vm_mask).
1049 *
1050 * The performance gain from "optimizing" away the cross call for threads is
1051 * questionable (in theory the big win for threads is the massive sharing of
1052 * address space state across processors).
1053 */
1054
1055/* This currently is only used by the hugetlb arch pre-fault
1056 * hook on UltraSPARC-III+ and later when changing the pagesize
1057 * bits of the context register for an address space.
1058 */
1059void smp_flush_tlb_mm(struct mm_struct *mm)
1060{
1061 u32 ctx = CTX_HWBITS(mm->context);
1062 int cpu = get_cpu();
1063
1064 if (atomic_read(&mm->mm_users) == 1) {
1065 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1066 goto local_flush_and_out;
1067 }
1068
1069 smp_cross_call_masked(&xcall_flush_tlb_mm,
1070 ctx, 0, 0,
1071 mm_cpumask(mm));
1072
1073local_flush_and_out:
1074 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1075
1076 put_cpu();
1077}
1078
1079struct tlb_pending_info {
1080 unsigned long ctx;
1081 unsigned long nr;
1082 unsigned long *vaddrs;
1083};
1084
1085static void tlb_pending_func(void *info)
1086{
1087 struct tlb_pending_info *t = info;
1088
1089 __flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
1090}
1091
1092void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1093{
1094 u32 ctx = CTX_HWBITS(mm->context);
1095 struct tlb_pending_info info;
1096 int cpu = get_cpu();
1097
1098 info.ctx = ctx;
1099 info.nr = nr;
1100 info.vaddrs = vaddrs;
1101
1102 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1103 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1104 else
1105 smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
1106 &info, 1);
1107
1108 __flush_tlb_pending(ctx, nr, vaddrs);
1109
1110 put_cpu();
1111}
1112
1113void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
1114{
1115 unsigned long context = CTX_HWBITS(mm->context);
1116 int cpu = get_cpu();
1117
1118 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1119 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1120 else
1121 smp_cross_call_masked(&xcall_flush_tlb_page,
1122 context, vaddr, 0,
1123 mm_cpumask(mm));
1124 __flush_tlb_page(context, vaddr);
1125
1126 put_cpu();
1127}
1128
1129void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1130{
1131 start &= PAGE_MASK;
1132 end = PAGE_ALIGN(end);
1133 if (start != end) {
1134 smp_cross_call(&xcall_flush_tlb_kernel_range,
1135 0, start, end);
1136
1137 __flush_tlb_kernel_range(start, end);
1138 }
1139}
1140
1141/* CPU capture. */
1142/* #define CAPTURE_DEBUG */
1143extern unsigned long xcall_capture;
1144
1145static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1146static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1147static unsigned long penguins_are_doing_time;
1148
1149void smp_capture(void)
1150{
1151 int result = atomic_add_ret(1, &smp_capture_depth);
1152
1153 if (result == 1) {
1154 int ncpus = num_online_cpus();
1155
1156#ifdef CAPTURE_DEBUG
1157 printk("CPU[%d]: Sending penguins to jail...",
1158 smp_processor_id());
1159#endif
1160 penguins_are_doing_time = 1;
1161 atomic_inc(&smp_capture_registry);
1162 smp_cross_call(&xcall_capture, 0, 0, 0);
1163 while (atomic_read(&smp_capture_registry) != ncpus)
1164 rmb();
1165#ifdef CAPTURE_DEBUG
1166 printk("done\n");
1167#endif
1168 }
1169}
1170
1171void smp_release(void)
1172{
1173 if (atomic_dec_and_test(&smp_capture_depth)) {
1174#ifdef CAPTURE_DEBUG
1175 printk("CPU[%d]: Giving pardon to "
1176 "imprisoned penguins\n",
1177 smp_processor_id());
1178#endif
1179 penguins_are_doing_time = 0;
1180 membar_safe("#StoreLoad");
1181 atomic_dec(&smp_capture_registry);
1182 }
1183}
1184
1185/* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1186 * set, so they can service tlb flush xcalls...
1187 */
1188extern void prom_world(int);
1189
1190void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
1191{
1192 clear_softint(1 << irq);
1193
1194 preempt_disable();
1195
1196 __asm__ __volatile__("flushw");
1197 prom_world(1);
1198 atomic_inc(&smp_capture_registry);
1199 membar_safe("#StoreLoad");
1200 while (penguins_are_doing_time)
1201 rmb();
1202 atomic_dec(&smp_capture_registry);
1203 prom_world(0);
1204
1205 preempt_enable();
1206}
1207
1208/* /proc/profile writes can call this, don't __init it please. */
1209int setup_profiling_timer(unsigned int multiplier)
1210{
1211 return -EINVAL;
1212}
1213
1214void __init smp_prepare_cpus(unsigned int max_cpus)
1215{
1216}
1217
1218void smp_prepare_boot_cpu(void)
1219{
1220}
1221
1222void __init smp_setup_processor_id(void)
1223{
1224 if (tlb_type == spitfire)
1225 xcall_deliver_impl = spitfire_xcall_deliver;
1226 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1227 xcall_deliver_impl = cheetah_xcall_deliver;
1228 else
1229 xcall_deliver_impl = hypervisor_xcall_deliver;
1230}
1231
1232void smp_fill_in_sib_core_maps(void)
1233{
1234 unsigned int i;
1235
1236 for_each_present_cpu(i) {
1237 unsigned int j;
1238
1239 cpumask_clear(&cpu_core_map[i]);
1240 if (cpu_data(i).core_id == 0) {
1241 cpumask_set_cpu(i, &cpu_core_map[i]);
1242 continue;
1243 }
1244
1245 for_each_present_cpu(j) {
1246 if (cpu_data(i).core_id ==
1247 cpu_data(j).core_id)
1248 cpumask_set_cpu(j, &cpu_core_map[i]);
1249 }
1250 }
1251
1252 for_each_present_cpu(i) {
1253 unsigned int j;
1254
1255 cpumask_clear(&per_cpu(cpu_sibling_map, i));
1256 if (cpu_data(i).proc_id == -1) {
1257 cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
1258 continue;
1259 }
1260
1261 for_each_present_cpu(j) {
1262 if (cpu_data(i).proc_id ==
1263 cpu_data(j).proc_id)
1264 cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
1265 }
1266 }
1267}
1268
1269int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1270{
1271 int ret = smp_boot_one_cpu(cpu, tidle);
1272
1273 if (!ret) {
1274 cpumask_set_cpu(cpu, &smp_commenced_mask);
1275 while (!cpu_online(cpu))
1276 mb();
1277 if (!cpu_online(cpu)) {
1278 ret = -ENODEV;
1279 } else {
1280 /* On SUN4V, writes to %tick and %stick are
1281 * not allowed.
1282 */
1283 if (tlb_type != hypervisor)
1284 smp_synchronize_one_tick(cpu);
1285 }
1286 }
1287 return ret;
1288}
1289
1290#ifdef CONFIG_HOTPLUG_CPU
1291void cpu_play_dead(void)
1292{
1293 int cpu = smp_processor_id();
1294 unsigned long pstate;
1295
1296 idle_task_exit();
1297
1298 if (tlb_type == hypervisor) {
1299 struct trap_per_cpu *tb = &trap_block[cpu];
1300
1301 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1302 tb->cpu_mondo_pa, 0);
1303 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1304 tb->dev_mondo_pa, 0);
1305 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1306 tb->resum_mondo_pa, 0);
1307 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1308 tb->nonresum_mondo_pa, 0);
1309 }
1310
1311 cpumask_clear_cpu(cpu, &smp_commenced_mask);
1312 membar_safe("#Sync");
1313
1314 local_irq_disable();
1315
1316 __asm__ __volatile__(
1317 "rdpr %%pstate, %0\n\t"
1318 "wrpr %0, %1, %%pstate"
1319 : "=r" (pstate)
1320 : "i" (PSTATE_IE));
1321
1322 while (1)
1323 barrier();
1324}
1325
1326int __cpu_disable(void)
1327{
1328 int cpu = smp_processor_id();
1329 cpuinfo_sparc *c;
1330 int i;
1331
1332 for_each_cpu(i, &cpu_core_map[cpu])
1333 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
1334 cpumask_clear(&cpu_core_map[cpu]);
1335
1336 for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
1337 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
1338 cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
1339
1340 c = &cpu_data(cpu);
1341
1342 c->core_id = 0;
1343 c->proc_id = -1;
1344
1345 smp_wmb();
1346
1347 /* Make sure no interrupts point to this cpu. */
1348 fixup_irqs();
1349
1350 local_irq_enable();
1351 mdelay(1);
1352 local_irq_disable();
1353
1354 set_cpu_online(cpu, false);
1355
1356 cpu_map_rebuild();
1357
1358 return 0;
1359}
1360
1361void __cpu_die(unsigned int cpu)
1362{
1363 int i;
1364
1365 for (i = 0; i < 100; i++) {
1366 smp_rmb();
1367 if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
1368 break;
1369 msleep(100);
1370 }
1371 if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
1372 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1373 } else {
1374#if defined(CONFIG_SUN_LDOMS)
1375 unsigned long hv_err;
1376 int limit = 100;
1377
1378 do {
1379 hv_err = sun4v_cpu_stop(cpu);
1380 if (hv_err == HV_EOK) {
1381 set_cpu_present(cpu, false);
1382 break;
1383 }
1384 } while (--limit > 0);
1385 if (limit <= 0) {
1386 printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1387 hv_err);
1388 }
1389#endif
1390 }
1391}
1392#endif
1393
1394void __init smp_cpus_done(unsigned int max_cpus)
1395{
1396 pcr_arch_init();
1397}
1398
1399void smp_send_reschedule(int cpu)
1400{
1401 if (cpu == smp_processor_id()) {
1402 WARN_ON_ONCE(preemptible());
1403 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
1404 } else {
1405 xcall_deliver((u64) &xcall_receive_signal,
1406 0, 0, cpumask_of(cpu));
1407 }
1408}
1409
1410void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
1411{
1412 clear_softint(1 << irq);
1413 scheduler_ipi();
1414}
1415
1416/* This is a nop because we capture all other cpus
1417 * anyways when making the PROM active.
1418 */
1419void smp_send_stop(void)
1420{
1421}
1422
1423/**
1424 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1425 * @cpu: cpu to allocate for
1426 * @size: size allocation in bytes
1427 * @align: alignment
1428 *
1429 * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper
1430 * does the right thing for NUMA regardless of the current
1431 * configuration.
1432 *
1433 * RETURNS:
1434 * Pointer to the allocated area on success, NULL on failure.
1435 */
1436static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size,
1437 size_t align)
1438{
1439 const unsigned long goal = __pa(MAX_DMA_ADDRESS);
1440#ifdef CONFIG_NEED_MULTIPLE_NODES
1441 int node = cpu_to_node(cpu);
1442 void *ptr;
1443
1444 if (!node_online(node) || !NODE_DATA(node)) {
1445 ptr = __alloc_bootmem(size, align, goal);
1446 pr_info("cpu %d has no node %d or node-local memory\n",
1447 cpu, node);
1448 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1449 cpu, size, __pa(ptr));
1450 } else {
1451 ptr = __alloc_bootmem_node(NODE_DATA(node),
1452 size, align, goal);
1453 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1454 "%016lx\n", cpu, size, node, __pa(ptr));
1455 }
1456 return ptr;
1457#else
1458 return __alloc_bootmem(size, align, goal);
1459#endif
1460}
1461
1462static void __init pcpu_free_bootmem(void *ptr, size_t size)
1463{
1464 free_bootmem(__pa(ptr), size);
1465}
1466
1467static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1468{
1469 if (cpu_to_node(from) == cpu_to_node(to))
1470 return LOCAL_DISTANCE;
1471 else
1472 return REMOTE_DISTANCE;
1473}
1474
1475static void __init pcpu_populate_pte(unsigned long addr)
1476{
1477 pgd_t *pgd = pgd_offset_k(addr);
1478 pud_t *pud;
1479 pmd_t *pmd;
1480
1481 pud = pud_offset(pgd, addr);
1482 if (pud_none(*pud)) {
1483 pmd_t *new;
1484
1485 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1486 pud_populate(&init_mm, pud, new);
1487 }
1488
1489 pmd = pmd_offset(pud, addr);
1490 if (!pmd_present(*pmd)) {
1491 pte_t *new;
1492
1493 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1494 pmd_populate_kernel(&init_mm, pmd, new);
1495 }
1496}
1497
1498void __init setup_per_cpu_areas(void)
1499{
1500 unsigned long delta;
1501 unsigned int cpu;
1502 int rc = -EINVAL;
1503
1504 if (pcpu_chosen_fc != PCPU_FC_PAGE) {
1505 rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
1506 PERCPU_DYNAMIC_RESERVE, 4 << 20,
1507 pcpu_cpu_distance,
1508 pcpu_alloc_bootmem,
1509 pcpu_free_bootmem);
1510 if (rc)
1511 pr_warning("PERCPU: %s allocator failed (%d), "
1512 "falling back to page size\n",
1513 pcpu_fc_names[pcpu_chosen_fc], rc);
1514 }
1515 if (rc < 0)
1516 rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
1517 pcpu_alloc_bootmem,
1518 pcpu_free_bootmem,
1519 pcpu_populate_pte);
1520 if (rc < 0)
1521 panic("cannot initialize percpu area (err=%d)", rc);
1522
1523 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1524 for_each_possible_cpu(cpu)
1525 __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1526
1527 /* Setup %g5 for the boot cpu. */
1528 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1529
1530 of_fill_in_cpu_data();
1531 if (tlb_type == hypervisor)
1532 mdesc_fill_in_cpu_data(cpu_all_mask);
1533}