1/*
 2 * arch/arm/mach-at91/at91x40_time.c
 3 *
 4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
 5 *
 6 * This program is free software; you can redistribute it and/or modify
 7 * it under the terms of the GNU General Public License as published by
 8 * the Free Software Foundation; either version 2 of the License, or
 9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/time.h>
26#include <linux/io.h>
27#include <mach/hardware.h>
28#include <mach/at91x40.h>
29#include <asm/mach/time.h>
30
31#include "at91_tc.h"
32
33#define at91_tc_read(field) \
34	__raw_readl(AT91_IO_P2V(AT91_TC) + field)
35
36#define at91_tc_write(field, value) \
37	__raw_writel(value, AT91_IO_P2V(AT91_TC) + field)
38
39/*
40 *	3 counter/timer units present.
41 */
42#define	AT91_TC_CLK0BASE	0
43#define	AT91_TC_CLK1BASE	0x40
44#define	AT91_TC_CLK2BASE	0x80
45
46static u32 at91x40_gettimeoffset(void)
47{
48	return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 /
49		(AT91X40_MASTER_CLOCK / 128)) * 1000;
50}
51
52static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
53{
54	at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
55	timer_tick();
56	return IRQ_HANDLED;
57}
58
59static struct irqaction at91x40_timer_irq = {
60	.name		= "at91_tick",
61	.flags		= IRQF_TIMER,
62	.handler	= at91x40_timer_interrupt
63};
64
65void __init at91x40_timer_init(void)
66{
67	unsigned int v;
68
69	arch_gettimeoffset = at91x40_gettimeoffset;
70
71	at91_tc_write(AT91_TC_BCR, 0);
72	v = at91_tc_read(AT91_TC_BMR);
73	v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
74	at91_tc_write(AT91_TC_BMR, v);
75
76	at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
77	at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
78	at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
79	at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
80	at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
81
82	setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
83
84	at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
85}