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1/*
2 * arch/arm/mach-at91/at91sam9261.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/clk/at91_pmc.h>
15
16#include <asm/proc-fns.h>
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/system_misc.h>
21#include <mach/cpu.h>
22#include <mach/at91sam9261.h>
23#include <mach/hardware.h>
24
25#include "at91_aic.h"
26#include "at91_rstc.h"
27#include "soc.h"
28#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32#if defined(CONFIG_OLD_CLK_AT91)
33#include "clock.h"
34
35/* --------------------------------------------------------------------
36 * Clocks
37 * -------------------------------------------------------------------- */
38
39/*
40 * The peripheral clocks.
41 */
42static struct clk pioA_clk = {
43 .name = "pioA_clk",
44 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk pioB_clk = {
48 .name = "pioB_clk",
49 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk pioC_clk = {
53 .name = "pioC_clk",
54 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk usart0_clk = {
58 .name = "usart0_clk",
59 .pmc_mask = 1 << AT91SAM9261_ID_US0,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk usart1_clk = {
63 .name = "usart1_clk",
64 .pmc_mask = 1 << AT91SAM9261_ID_US1,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk usart2_clk = {
68 .name = "usart2_clk",
69 .pmc_mask = 1 << AT91SAM9261_ID_US2,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk mmc_clk = {
73 .name = "mci_clk",
74 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk udc_clk = {
78 .name = "udc_clk",
79 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk twi_clk = {
83 .name = "twi_clk",
84 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk spi0_clk = {
88 .name = "spi0_clk",
89 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk spi1_clk = {
93 .name = "spi1_clk",
94 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk ssc0_clk = {
98 .name = "ssc0_clk",
99 .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk ssc1_clk = {
103 .name = "ssc1_clk",
104 .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk ssc2_clk = {
108 .name = "ssc2_clk",
109 .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk tc0_clk = {
113 .name = "tc0_clk",
114 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk tc1_clk = {
118 .name = "tc1_clk",
119 .pmc_mask = 1 << AT91SAM9261_ID_TC1,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk tc2_clk = {
123 .name = "tc2_clk",
124 .pmc_mask = 1 << AT91SAM9261_ID_TC2,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk ohci_clk = {
128 .name = "ohci_clk",
129 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk lcdc_clk = {
133 .name = "lcdc_clk",
134 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137
138/* HClocks */
139static struct clk hck0 = {
140 .name = "hck0",
141 .pmc_mask = AT91_PMC_HCK0,
142 .type = CLK_TYPE_SYSTEM,
143 .id = 0,
144};
145static struct clk hck1 = {
146 .name = "hck1",
147 .pmc_mask = AT91_PMC_HCK1,
148 .type = CLK_TYPE_SYSTEM,
149 .id = 1,
150};
151
152static struct clk *periph_clocks[] __initdata = {
153 &pioA_clk,
154 &pioB_clk,
155 &pioC_clk,
156 &usart0_clk,
157 &usart1_clk,
158 &usart2_clk,
159 &mmc_clk,
160 &udc_clk,
161 &twi_clk,
162 &spi0_clk,
163 &spi1_clk,
164 &ssc0_clk,
165 &ssc1_clk,
166 &ssc2_clk,
167 &tc0_clk,
168 &tc1_clk,
169 &tc2_clk,
170 &ohci_clk,
171 &lcdc_clk,
172 // irq0 .. irq2
173};
174
175static struct clk_lookup periph_clocks_lookups[] = {
176 CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
177 CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
178 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
179 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
180 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
181 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
182 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
183 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
184 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
185 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
186 CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
187 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
188 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
189 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
190 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
191 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
192 CLKDEV_CON_ID("pioA", &pioA_clk),
193 CLKDEV_CON_ID("pioB", &pioB_clk),
194 CLKDEV_CON_ID("pioC", &pioC_clk),
195 /* more lookup table for DT entries */
196 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
197 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
198 CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
199 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
200 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
201 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
202 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
203 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &hck0),
204 CLKDEV_CON_DEV_ID("hclk", "600000.fb", &hck1),
205 CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
206 CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
207 CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
208 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
209 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
210 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
211 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
212};
213
214static struct clk_lookup usart_clocks_lookups[] = {
215 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
216 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
217 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
218 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
219};
220
221/*
222 * The four programmable clocks.
223 * You must configure pin multiplexing to bring these signals out.
224 */
225static struct clk pck0 = {
226 .name = "pck0",
227 .pmc_mask = AT91_PMC_PCK0,
228 .type = CLK_TYPE_PROGRAMMABLE,
229 .id = 0,
230};
231static struct clk pck1 = {
232 .name = "pck1",
233 .pmc_mask = AT91_PMC_PCK1,
234 .type = CLK_TYPE_PROGRAMMABLE,
235 .id = 1,
236};
237static struct clk pck2 = {
238 .name = "pck2",
239 .pmc_mask = AT91_PMC_PCK2,
240 .type = CLK_TYPE_PROGRAMMABLE,
241 .id = 2,
242};
243static struct clk pck3 = {
244 .name = "pck3",
245 .pmc_mask = AT91_PMC_PCK3,
246 .type = CLK_TYPE_PROGRAMMABLE,
247 .id = 3,
248};
249
250static void __init at91sam9261_register_clocks(void)
251{
252 int i;
253
254 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
255 clk_register(periph_clocks[i]);
256
257 clkdev_add_table(periph_clocks_lookups,
258 ARRAY_SIZE(periph_clocks_lookups));
259 clkdev_add_table(usart_clocks_lookups,
260 ARRAY_SIZE(usart_clocks_lookups));
261
262 clk_register(&pck0);
263 clk_register(&pck1);
264 clk_register(&pck2);
265 clk_register(&pck3);
266
267 clk_register(&hck0);
268 clk_register(&hck1);
269}
270#else
271#define at91sam9261_register_clocks NULL
272#endif
273/* --------------------------------------------------------------------
274 * GPIO
275 * -------------------------------------------------------------------- */
276
277static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
278 {
279 .id = AT91SAM9261_ID_PIOA,
280 .regbase = AT91SAM9261_BASE_PIOA,
281 }, {
282 .id = AT91SAM9261_ID_PIOB,
283 .regbase = AT91SAM9261_BASE_PIOB,
284 }, {
285 .id = AT91SAM9261_ID_PIOC,
286 .regbase = AT91SAM9261_BASE_PIOC,
287 }
288};
289
290/* --------------------------------------------------------------------
291 * AT91SAM9261 processor initialization
292 * -------------------------------------------------------------------- */
293
294static void __init at91sam9261_map_io(void)
295{
296 if (cpu_is_at91sam9g10())
297 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
298 else
299 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
300}
301
302static void __init at91sam9261_ioremap_registers(void)
303{
304 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
305 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
306 at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
307 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
308 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
309 at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
310 at91_pm_set_standby(at91sam9_sdram_standby);
311}
312
313static void __init at91sam9261_initialize(void)
314{
315 arm_pm_idle = at91sam9_idle;
316 arm_pm_restart = at91sam9_alt_restart;
317
318 at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
319
320 /* Register GPIO subsystem */
321 at91_gpio_init(at91sam9261_gpio, 3);
322}
323
324/* --------------------------------------------------------------------
325 * Interrupt initialization
326 * -------------------------------------------------------------------- */
327
328/*
329 * The default interrupt priority levels (0 = lowest, 7 = highest).
330 */
331static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
332 7, /* Advanced Interrupt Controller */
333 7, /* System Peripherals */
334 1, /* Parallel IO Controller A */
335 1, /* Parallel IO Controller B */
336 1, /* Parallel IO Controller C */
337 0,
338 5, /* USART 0 */
339 5, /* USART 1 */
340 5, /* USART 2 */
341 0, /* Multimedia Card Interface */
342 2, /* USB Device Port */
343 6, /* Two-Wire Interface */
344 5, /* Serial Peripheral Interface 0 */
345 5, /* Serial Peripheral Interface 1 */
346 4, /* Serial Synchronous Controller 0 */
347 4, /* Serial Synchronous Controller 1 */
348 4, /* Serial Synchronous Controller 2 */
349 0, /* Timer Counter 0 */
350 0, /* Timer Counter 1 */
351 0, /* Timer Counter 2 */
352 2, /* USB Host port */
353 3, /* LCD Controller */
354 0,
355 0,
356 0,
357 0,
358 0,
359 0,
360 0,
361 0, /* Advanced Interrupt Controller */
362 0, /* Advanced Interrupt Controller */
363 0, /* Advanced Interrupt Controller */
364};
365
366AT91_SOC_START(at91sam9261)
367 .map_io = at91sam9261_map_io,
368 .default_irq_priority = at91sam9261_default_irq_priority,
369 .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
370 | (1 << AT91SAM9261_ID_IRQ2),
371 .ioremap_registers = at91sam9261_ioremap_registers,
372 .register_clocks = at91sam9261_register_clocks,
373 .init = at91sam9261_initialize,
374AT91_SOC_END